Wafer structure and layout generation method

Abstract

The application relates to the technical field of wafer packaging and testing, in particular to a wafer structure and a layout generation method. The wafer structure comprises a chip die, a rewiring layer and a protective layer which are sequentially stacked; a plurality of original pads are arranged on the chip die; a plurality of array-arranged top pads are arranged on the surface of the rewiring layer close to the protective layer; a window is arranged on the protective layer to expose the top pads so that a probe card can contact the top pads during electrical testing; the top pads are divided into at least a power / ground pad partition, a test-dedicated pad partition and a functional pad partition according to functional attributes, and an isolation belt is arranged between adjacent partitions. The application realizes accurate alignment, cross-zone electrical isolation and signal stability during probe testing, thereby significantly improving the reliability and reproducibility of wafer-level testing.

Description

Technical Field

[0001] This application relates to the field of wafer packaging and testing technology, and more specifically, to a wafer structure and layout generation method. Background Technology

[0002] In advanced packaging processes, wafer-level packaging commonly employs fan-in redistribution layer (RDL) technology. This technology rearranges the high-density, irregularly arranged original pads on the die into a regular array of top-layer pads via metal interconnects and dielectric layers (such as polyimide, PI) to accommodate subsequent wire bonding or flip-chip processes. A typical mass production flow includes: wafer testing (CP) at the raw wafer stage, where a large number of internal networks can be directly accessed; followed by the redistribution layer process, which "rises" critical signals to the top-layer pads; and finally, final product testing (FT) after packaging. Some engineering verifications also include retesting before and after the high-temperature operating life to assess long-term reliability.

[0003] However, the introduction of redistribution layers brings new testing challenges: their metal traces, vias, and dielectric layers introduce additional interconnect resistance, parasitic coupling, and leakage paths, leading to interface malfunctions or electrical parameter degradation. More importantly, when customer package pin resources are fully utilized and no additional test pins can be added, problems exposed in the post-packaging FT stage are difficult to trace back and locate. If wafer testing is added in the wafer stage after the redistribution layer, a probe reach structure that is alignable, partitionable, isolated, and reproducible is required; otherwise, false failures and misjudgments can easily occur due to probe misreach, cross-region coupling, unstable contact, or contamination diffusion, severely affecting test accuracy and yield control. Summary of the Invention

[0004] The purpose of this application is to provide a wafer structure and layout generation method, which achieves precise alignment, cross-region electrical isolation and signal stability during probe testing by functionally partitioning the top-level pads and setting isolation bands, thereby significantly improving the reliability and reproducibility of wafer-level testing.

[0005] This application is implemented as follows: In a first aspect, this application provides a wafer structure including a die, a redistribution layer, and a protective layer stacked sequentially; the die has a plurality of original pads; the redistribution layer has a plurality of arrayed top-layer pads on its surface near the protective layer; the protective layer has windows exposing the top-layer pads for contact with probe cards during power supply testing; the top-layer pads are divided into at least a power / ground pad partition, a test-specific pad partition, and a functional pad partition according to their functional attributes, and an isolation band is provided between adjacent partitions.

[0006] As an optional implementation, the functional pad partition includes at least one debug interface sub-region and at least one general-purpose I / O sub-region.

[0007] As an optional implementation, the debug interface sub-area includes a JTAG interface sub-area, which includes at least top-level pads corresponding to the test clock signal and the test mode selection signal, respectively.

[0008] As an optional implementation, the redistribution layer includes a first metal layer; the isolation band includes island-shaped containment areas disposed in the first metal layer, wherein the vertical projection of the island-shaped containment areas is located between any two adjacent partitions among the power / ground pad partition, the test pad partition, and the functional pad partition.

[0009] As an optional implementation, the redistribution layer includes a first metal layer; the first metal layer is provided with signal lines and vias electrically connected to the original pads; the isolation strip includes a ground shielding structure disposed in the first metal layer, the ground shielding structure being arranged on both sides of the signal lines and coplanar with the signal traces while maintaining a preset process spacing; and / or, the ground shielding structure is arranged around the vias to form an enclosed shielding structure.

[0010] As an optional implementation, the redistribution layer includes a second metal layer not used for signal interconnection; the isolation strip includes a ground grid layer disposed in the second metal layer and covering the die; the ground grid layer is electrically connected to the ground grid of the die or to the ground shield structure via ground vias.

[0011] As an alternative implementation, the grounding grid layer is connected to the top pad for grounding in the power / ground pad partition via metal vias to provide a low-impedance grounding path for wafer-level testing.

[0012] As an optional implementation, the physical boundaries of different partitions have a preset spacing to form the isolation zone.

[0013] As an optional implementation, at least one alignment mark is provided on the chip die. The alignment mark is located outside the window area of ​​the redistribution layer and is configured for optical alignment by the probe card. The geometry or layout of the alignment mark is asymmetrical to prevent misinstallation or reverse contact of the probe card.

[0014] As an optional implementation, the side length of the window is 60-70 μm.

[0015] Secondly, this application provides a layout generation method, including: Obtain the electrical network information and functional purpose identifier of the original pads on the chip die. The functional purpose identifier includes at least one of signal protocol type, power type, or test role. Based on the target package pin layout rules and probe contact window constraints, the original pads are mapped to the top layer of the redistribution layer through a redistribution process to form an array of top-level pads. Based on the functional purpose identifier, the top-level pad set is divided into at least a power / ground pad partition, a test-specific pad partition, and a functional pad partition; Based on the distribution of the top-level pads within each partition, the partition boundary of each partition is generated. Isolation zones are generated between different partitions using layout design rules; The output includes layout data containing the top-level pads, partition boundaries, isolation bands, and interconnects. This layout data conforms to the design rule check requirements of the target manufacturing process and is used for wafer manufacturing and packaging.

[0016] As an optional implementation, generating the partition boundary of each partition based on the distribution position of the top-level pads within each partition includes: Based on the automated script, geometric analysis or spatial clustering is performed on the coordinate data of the top-level pad on the wafer plane to generate candidate partition boundaries; The candidate partition boundaries are then manually verified and corrected according to process constraints or testing requirements to determine the final partition boundaries.

[0017] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: Set a physical distance of not less than the preset minimum value between the partition boundaries of any two adjacent partitions.

[0018] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: Multiple island-shaped containment areas are formed in the first metal layer of the redistribution layer, which prohibit the placement of any electronic components or circuit connections. The vertical projection of the island-shaped containment areas is located between any two adjacent partitions among the power / ground pad partition, the test pad partition, and the functional pad partition.

[0019] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: A ground shielding structure is formed in the first metal layer of the redistribution layer; wherein the ground shielding structure is arranged on both sides of the signal line in the first metal layer; and / or, the ground shielding structure is arranged on the outer periphery of the via in the first metal layer to form an enclosed shielding structure.

[0020] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: A ground grid layer is formed in a second metal layer of the redistribution layer that is not used for signal interconnection; the ground grid layer covers the die and is electrically connected to the ground grid on the die.

[0021] The beneficial effects of this application include: The wafer structure and layout generation method provided in this application effectively suppresses parasitic coupling, leakage current, and crosstalk introduced by metal traces, vias, and dielectric layers in the RDL structure by clearly partitioning the pads according to functional attributes on the top layer of the redistribution layer and setting isolation bands between each partition. At the same time, the partition layout combined with the protective layer window design provides a stable contact window for the probe card that can be aligned and reproduced, avoiding problems such as cross-regional accidental contact, unstable contact, and contamination diffusion. Thus, interface anomalies or electrical parameter degradation caused by the RDL process can be captured with high precision and high reliability in the wafer testing stage before packaging, significantly improving test accuracy, failure location capability, and overall yield control level. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the overall layout of the top-level pad array and its distribution in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the VSS family, VDD family, and their package wire bonding relationships in embodiments of this application; Figure 3 This is a cross-sectional schematic diagram of the wafer structure according to an embodiment of this application; Figure 4 This is one of the structural schematic diagrams of the ground protection shielding structure in the embodiments of this application; Figure 5 This is a second schematic diagram of the protective shielding structure according to an embodiment of this application; Figure 6 This is one of the structural schematic diagrams of the grounding grid layer in the embodiments of this application; Figure 7 This is a second schematic diagram of the grounding grid layer structure in an embodiment of this application; Figure 8 This is a schematic diagram of the alignment marks of the wafer structure in an embodiment of this application.

[0024] Icons: 100 - Chip die; 101 - Original pad; 102 - Top pad; 103 - Window; 104 - First dielectric layer; 105 - First metal layer; 106 - Second dielectric layer; 107 - Second metal layer; 108 - Protective layer; 109 - Ground shielding structure; 110 - Grounding grid layer; 111 - Alignment mark. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0027] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] In actual testing, the metal traces, vias, and dielectric layers of the redistribution layer introduce additional interconnect resistance, parasitic coupling, and leakage paths, leading to interface malfunctions or deterioration of electrical parameters. More importantly, when customer package pin resources are fully utilized and no additional test pins can be added, problems exposed in the post-packaging FT stage are difficult to trace back and locate. If wafer testing is added in the wafer stage after the redistribution layer, a probe reach structure that can be aligned, partitioned, isolated, and reproducible is required. Otherwise, false failures and misjudgments can easily occur due to probe misreach, cross-region coupling, unstable contact, or contamination diffusion, seriously affecting test accuracy and yield control.

[0030] To address the aforementioned technical problems, this application provides a wafer structure.

[0031] The wafer structure of this application embodiment includes a chip die 100, a redistribution layer, and a protective layer 108 stacked sequentially. The chip die 100 has a plurality of original pads 101. The redistribution layer has a plurality of top pads 102 arranged in an array on the surface near the protective layer 108. The protective layer 108 has windows 103 that expose the top pads 102 so that the probe card can contact them during power supply testing. The top pads 102 are divided into at least three partitions according to their functional attributes: a power / ground pad partition, a test-specific pad partition, and a functional pad partition, and isolation bands are provided between the different partitions.

[0032] The specific structure of the rewiring layer can be configured by those skilled in the art as needed, and no special limitations are made here.

[0033] For example, refer to Figure 3 As shown, a first dielectric layer 104, a first metal layer 105, a second dielectric layer 106, a second metal layer 107, and a protective layer 108 for top protection are stacked on the chip die 100. Alternatively, a first dielectric layer 104, a first metal layer 105, a second dielectric layer 106, a second metal layer 107, a third dielectric layer, a third metal layer, and a protective layer 108 for top protection are stacked on the chip die 100. The metal layers can be made of metals such as copper or aluminum. The dielectric layer and the protective layer 108 can both be made of materials such as polyimide, silicon dioxide, or silicon nitride.

[0034] The working principle of this application embodiment is as follows: by clearly dividing the pads on the top layer of the redistribution layer according to their functional attributes, namely: power / ground pad partition, test-specific pad partition and functional pad partition, and setting physical and electrical isolation bands (such as no-distribution zones, ground shielding structure 109, etc.) between each partition, a highly reliable and low-interference probe testing environment is constructed in the wafer stage after the redistribution layer; during operation, the probe card accurately contacts the top layer pad 102 of the corresponding partition through the opening on the protective layer 108.

[0035] For example, refer to Figure 1 As shown, the power / ground pad partitioning includes a continuous arrangement of VSS and VDD pad families located on the left side of the top-level pad array 102. The VSS pad family includes VSS_SHIELD, VSS_CMP, VSS_VREF, VSS_ANA, and a general-purpose VSS pad arranged sequentially, used to connect signals such as shield ground, reference voltage ground, analog ground, and digital common ground. The VDD pad family includes VDDIO_ANA, VDDIO_VREF, VDDIO_PMB, and VDDIO pads arranged sequentially, used to provide I / O power for different functional modules. Furthermore, one or more additional VSS pads can be distributed in other non-signal-dense areas of the layout, such as corners or edges, to enhance the ground return path, reduce power supply impedance, and provide redundant ground contacts for probe testing. Figure 2 This diagram illustrates the wire bonding relationship between the VSS and VDD pad families, which are partitioned into power / ground pads.

[0036] For example, a dedicated test pad partition includes six Flash Test pads for reserving access during the CP phase Flash testing. For example, a functional pad partition may include 20 top-level pads 102, each corresponding to a plurality of package pins.

[0037] The size of window 103 is not specifically limited here, and those skilled in the art can set it as needed. For example, the side length of window 103 is 60-70μm.

[0038] It should be noted that the typical size of the window 103 exposing a single top-layer pad 102 is preferably 70μm×70μm, in order to facilitate subsequent packaging wire bonding and improve the consistency of manufacturing and testing; when the available area of ​​the top layer is insufficient or the array density needs to be increased, the window 103 can be reduced to about 60μm×60μm.

[0039] It should be noted that parameters such as the top layer pad pitch 102, probe card type, probe tip material, contact force and allowable alignment error can be determined by the probe card specifications, machine capabilities and process design rules used. The embodiments of this application do not limit their specific values.

[0040] In this embodiment, 35 top-level pads 102 are formed through window 103, accessible in the wafer stage after the redistribution layer. The purpose of the partitioning design described above in this embodiment is to achieve reproducible testable access organized by functional domain in the wafer CP stage after RDL, and to provide a partition boundary basis for isolation band design. The isolation bands between partitions effectively suppress crosstalk, leakage current, and probe mis-touch risks, ensuring test signal integrity and contact reproducibility. This allows interconnect defects or parameter degradation introduced by the RDL process to be accurately captured and located before packaging, significantly improving the effectiveness of wafer-level testing and yield control capabilities.

[0041] It should be noted that the top-level pad 102 on the redistribution layer has more than 30 pads. The specific number is determined by the number of pads retained after RDL and the CP feature acquisition requirements. Therefore, those skilled in the art can set it as needed.

[0042] Compared with the prior art, the embodiments of this application have the following beneficial effects: It provides a mass-producible structure for post-RDL wafer CP. Through the top-level accessible top-level pad array and its arrayed alignment rules, anomalies that were originally exposed in the post-packaging FT can be moved to the post-RDL wafer stage for retesting and positioning, shortening the process-test-failure mode closed-loop cycle. The structured layout of partitions and isolation zones enhances test stability and anti-interference capabilities: the partition boundaries and isolation zone mechanism together reduce the risk of cross-zone coupling and false access, the explicit no-wiring zone reduces the risk of wire / wiring structure spillover, and the ground shield and ground grid improve interconnection anti-interference and consistency. The pads are set up as independent areas, supporting extended testing capabilities during the CP phase without occupying package pins: such as power / ground pad partitions, test-specific pad partitions, and functional pad partitions. They provide dedicated access points for the CP phase without increasing package pins, reducing interference and misjudgments to other functional areas.

[0043] As an optional implementation, the functional pad partition includes at least one debug interface sub-region and at least one general-purpose I / O sub-region. The debug interface sub-region includes a JTAG interface sub-region, which includes at least a top-level pad 102 corresponding to the test clock signal and the test mode selection signal, respectively.

[0044] It should be noted that, in this embodiment of the application, by further dividing the functional pad partition into a debug interface sub-area (such as a JTAG interface sub-area) and a general I / O sub-area, fine-grained management of the physical layout of test signals and conventional functional signals is achieved. Among them, the JTAG interface sub-area is specifically arranged to centrally arrange the key signal pads for boundary scan testing (such as TCK test clock, TMS test mode selection, etc.), which not only facilitates the accurate positioning and stable contact of the probe card, but also, in conjunction with the surrounding ground shielding structure 109 or isolation strip, effectively suppresses crosstalk between high-speed test signals and adjacent general I / O. This design improves the accessibility, signal integrity and retest consistency of the debug interface in the wafer-level testing stage without adding additional package pins, thereby supporting more efficient fault diagnosis and parameter verification.

[0045] As an optional implementation, the redistribution layer includes a first metal layer 105; the isolation band includes an island-shaped containment area disposed in the first metal layer 105, the vertical projection of the island-shaped containment area being located between any two adjacent partitions among the power / ground pad partition, the test dedicated pad partition and the functional pad partition.

[0046] The island-shaped no-disk area has a polygonal structure, including but not limited to rectangles, L-shapes, U-shapes, or irregular polygons automatically generated based on the distribution of pads in adjacent partitions. Its boundary is formed by connecting multiple line segments end to end to form a closed area, and it ensures that it maintains a minimum spacing of not less than the minimum specified by the process with the metal patterns in the partitions on both sides.

[0047] It should be noted that, in this embodiment, an island-shaped exclusion zone is set as an isolation band in the first metal layer 105 of the redistribution layer. In vertical projection, it is located between any two adjacent partitions among the power / ground pad partition, the test dedicated pad partition, and the functional pad partition. By prohibiting the placement of any metal traces, vias, or devices in this area, a physical and electrical geometric isolation barrier is formed. This design effectively avoids the risk of cross-wires that may occur during subsequent packaging wire bonding due to the compression of pad spacing after RDL rearrangement. On the other hand, it significantly reduces signal crosstalk caused by adjacent trace coupling or electric field interference when the probe contacts a certain pad, thereby improving the contact stability and retest consistency of wafer-level testing, and providing key manufacturability and testability guarantees for high-density, high-reliability packaging.

[0048] As an optional implementation, the redistribution layer includes a first metal layer 105; the first metal layer 105 is provided with signal lines and vias electrically connected to the original pads 101; the isolation strip includes a ground shielding structure 109 disposed in the first metal layer 105, as shown in the figure. Figure 5 As shown, the grounding shielding structure 109 is arranged on both sides of the signal line, and is coplanar with the signal trace while maintaining a preset process spacing; refer to Figure 4As shown, the grounding shielding structure 109 is arranged on the outer periphery of the via, forming an enclosed shielding structure.

[0049] For example, refer to Figure 4 , Figure 5 As shown, the physical spacing between adjacent ground shielding structures 109 is 0.01 inches, and the allowable deviation during actual processing is no more than ±2μm.

[0050] The preset process spacing can be set according to specific circumstances. For example, the preset process spacing is 10μm.

[0051] It should be noted that in the first metal layer 105 of the redistribution layer in this application embodiment, a ground shielding structure 109 is provided on both sides of the signal line, which is coplanar and maintains a preset process spacing. An enclosed ground shielding structure 109 is arranged around the via, and a local electromagnetic shielding environment is formed by using grounded metal patterns. This design effectively suppresses crosstalk, capacitive coupling and electromagnetic radiation between RDL metal traces and vias by constructing a low impedance ground reference around the high-frequency or sensitive signal path, while avoiding parameter drift or misjudgment caused by interference from nearby signals during probe testing.

[0052] Reference Figure 6 , Figure 7 As shown, in one optional implementation, the redistribution layer includes a second metal layer 107 not used for signal interconnection; the isolation strip includes a ground grid layer 110 disposed in the second metal layer 107 and covering the die 100; the ground grid layer 110 is electrically connected to the ground grid of the die 100 or to the ground shielding structure 109 through ground vias.

[0053] For example, refer to Figure 6 , Figure 7 As shown, the intersecting horizontal and vertical metal strips form a grounding grid layer 110, wherein the metal strips are 0.02 inches in size, and the allowable deviation during actual processing is no more than ±3μm.

[0054] It should be noted that, in this embodiment of the application, a second metal layer 107 not used for signal interconnection is introduced in the redistribution layer, and a ground grid layer 110 covering the area of ​​the die 100 is formed on it. The ground grid layer 110 is electrically connected to the ground network inside the die 100 and the ground shielding structure 109 in the first metal layer 105 through ground vias, thereby constructing a distributed low-impedance reference ground plane in the RDL structure. As a shielding layer, the ground grid layer 110 can effectively absorb and discharge high-frequency noise, suppress electromagnetic coupling and radiation interference between different functional areas, and provide a stable grounding loop for probe testing. Combined with the lower ground shielding structure, a multi-level shielding system with vertical and horizontal coordination is formed, which significantly improves the signal integrity, anti-interference capability and reproducibility of test results in wafer-level testing.

[0055] As an alternative implementation, the ground grid layer 110 is connected to the top pad 102 for grounding in the power / ground pad partition via a metal via, providing a low-impedance grounding path for wafer-level testing.

[0056] It should be noted that, in this embodiment of the application, by electrically connecting the ground grid layer 110 in the second metal layer 107 to the top-level ground pad 102 (such as the pad identified as VSS_SHIELD or VSS) in the power / ground pad partition via a metal via, a low-impedance and continuous grounding path is constructed from the chip internal ground network, the ground shielding structure 109, the ground grid layer 110, and the top-level ground pad. This design ensures that during wafer-level testing, the probe can quickly access the global reference ground through the top-level ground pad, effectively dissipating high-frequency noise, stabilizing the test potential, and avoiding signal distortion, parameter drift, or false failures caused by excessively high ground path impedance, thereby significantly improving test accuracy, repeatability, and the ability to detect defects introduced by the RDL process.

[0057] As an optional implementation, the physical boundaries of different zones have a preset spacing to form an isolation zone.

[0058] It should be noted that, in this application embodiment, by defining clear physical boundaries for power / ground pad partitions, test-specific pad partitions, and functional pad partitions in the layout design, and ensuring a preset distance between any two adjacent partitions, an effective physical spacing isolation zone is formed in space. This preset distance not only meets manufacturing rule requirements, but also physically blocks cross-area mis-reaching caused by probe point offset during testing from the layout level, limits mutual interference of signal return paths, and suppresses capacitive / inductive coupling between different functional areas. At the same time, the gaps between partitions also reduce the risk of contaminants or metal residues spreading between pad groups during probe contact, significantly improving the electrical stability, contact reliability, and result reproducibility of wafer-level testing.

[0059] Reference Figure 8 As shown, as an optional implementation, at least one alignment mark 111 is provided on the chip die 100. The alignment mark 111 is located outside the window area of ​​the redistribution layer and is configured for optical alignment by the probe card. The geometry or layout of the alignment mark 111 is asymmetrical to prevent the probe card from being misinstalled or making reverse contact.

[0060] It should be noted that, in this embodiment of the application, at least one alignment mark 111 is provided on the chip die 100 outside the area of ​​the redistribution layer window 103. Its geometry or layout adopts an asymmetrical design (such as an L-shape, a notched cross, or a directional pattern). This ensures that the mark can still be clearly identified by the optical system of the CP test equipment after the redistribution layer and the protective layer 108 are covered, for high-precision probe card alignment. At the same time, the asymmetrical feature achieves a foolproof function, effectively preventing mis-contact caused by the probe card being rotated 180° or installed in reverse. The alignment mark 111 only occupies the chip dicing area or non-functional area, does not occupy package pin resources, and does not require the addition of on-chip test circuits or functional modules. Without increasing cost and area, it significantly improves the alignment accuracy, operational safety, and automation reliability of wafer-level testing.

[0061] This application embodiment also provides a wafer alignment and probe reach method based on functional partitioning: First, the CP test equipment identifies the asymmetric alignment mark 111 set on the die chip outside the redistribution layer window area to complete the wafer attitude correction and high-precision optical alignment, effectively preventing probe card misinstallation or reverse contact; then, the equipment performs probe reach and electrical tests according to the predefined pad partitioning layout (including power / ground pad partitions, JTAG and other interface sub-areas in the test-dedicated pad partitions, and functional pad partitions, etc.) in an optimized partitioning order. This order can be a test order from left to right or from top to bottom, or it can prioritize testing key areas (such as JTAG debugging interfaces) to accelerate failure location, or it can perform block parallel testing according to the arrangement of the physical probe groups of the probe card, thereby significantly improving test efficiency and retest consistency while ensuring contact accuracy.

[0062] Secondly, this application provides a layout generation method, including: Obtain the electrical network information and functional purpose identifier of the original pad 101 on the bare chip 100. The functional purpose identifier includes at least one of signal protocol type, power type or test role. Based on the target package pin arrangement rules and the constraints of the probe contact window 103, the original pad 101 is mapped to the top layer of the redistribution layer through the redistribution process to form an array of top-layer pads 102. Based on the functional purpose identifier, the top-level pad 102 set is divided into at least a power / ground pad partition, a test-specific pad partition, and a functional pad partition. Based on the distribution of the top-level pads 102 within each partition, the partition boundary of each partition is generated. Isolation zones are generated between different partitions using layout design rules; The output includes layout data of the top-level pad 102, partition boundaries, isolation band structure and interconnects. The layout data meets the design rule check requirements of the target manufacturing process and is used for wafer manufacturing and packaging.

[0063] This application provides a layout generation method for wafer-level testing. Its core lies in using functional purpose identifiers as a driving force. The original pads 101 are mapped to a regular array of top-level pads 102 through a rewiring process. Physical partitioning is then performed according to at least three attributes: power / ground, test-specific, and functional signals. Boundaries are automatically generated based on the pad distribution of each partition, and isolation bands conforming to process rules are embedded between partitions. This method constructs an alignable, isolating, and retestable RDL layout architecture from the layout source. It not only meets the engineering constraints of package pin arrangement and probe contact windows 103, but also effectively suppresses cross-region crosstalk, reduces the risk of probe mis-touch, and ensures the integrity of the ground return path through functional partitioning and isolation design. Therefore, without adding new package pins, it significantly improves the accuracy of wafer testing after RDL, the failure location capability, and the manufacturing yield.

[0064] As an optional implementation, generating the partition boundary of each partition based on the distribution position of the top-level pads 102 within each partition includes: Based on the automated script, geometric analysis or spatial clustering is performed on the coordinate data of the top-level pad 102 on the wafer plane to generate candidate partition boundaries; The candidate boundaries are then manually verified, and the candidate partition boundaries are corrected according to process constraints or testing requirements to determine the final partition boundaries.

[0065] This application embodiment generates partition boundaries by combining automation and manual intervention: First, an automated script is used to perform geometric analysis or spatial clustering on the coordinate data of the top-level pad 102 on the wafer plane to quickly generate candidate partition boundaries that conform to the pad distribution characteristics; then, the layout engineer verifies and corrects the candidate boundaries based on actual process constraints (such as metal density, minimum line width spacing, and wire bonding area restrictions) and testing requirements (such as probe card contact window 103 and alignment mark 111 avoidance), thereby determining the final partition boundaries that take into account manufacturing feasibility, testing reliability, and layout efficiency.

[0066] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: Set a physical distance of not less than the preset minimum value between the partition boundaries of any two adjacent partitions.

[0067] This application embodiment forms an isolation zone that meets process requirements at the layout level by setting a physical distance of not less than a preset minimum value between the partition boundaries of any two adjacent functional partitions. This preset minimum value is limited by the design rules of the target manufacturing process.

[0068] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: Multiple island-shaped containment areas are formed in the first metal layer 105 of the redistribution layer to prevent the placement of any electronic components or circuit connections. The vertical projection of the island-shaped containment areas is located between any two adjacent partitions among the power / ground pad partition, the test pad partition, and the functional pad partition.

[0069] In this embodiment, multiple island-shaped no-distribution zones are formed in the first metal layer 105 of the redistribution layer. These zones prohibit the placement of any metal traces, vias, or active components, and their vertical projection is precisely located between any two adjacent zones among the power / ground pad zone, the test dedicated pad zone, and the functional pad zone. By constructing such passive, connectionless, physically isolated "islands" in the critical boundary areas, the lateral coupling paths and leakage channels between different functional signals are effectively blocked. At the same time, it provides a clear, non-interference boundary for probe contact, avoiding electric field disturbances or contamination diffusion caused by adjacent wiring. This design not only meets the spacing and density requirements of process design rules, but also significantly improves the electrical isolation, contact reliability, and result reproducibility of wafer-level testing.

[0070] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: A ground shielding structure 109 is formed in the first metal layer 105 of the redistribution layer; wherein the ground shielding structure 109 is arranged on both sides of the signal line in the first metal layer 105; the ground shielding structure 109 is arranged on the outer periphery of the via in the first metal layer 105 to form an enclosed shielding structure.

[0071] In this embodiment, a ground shielding structure 109 is provided in the first metal layer 105 of the redistribution layer. This structure is arranged on both sides of the signal lines and around the vias to form an enclosed layout, utilizing grounded metal patterns to construct a local electromagnetic shielding environment. The ground shielding structure 109 maintains a preset process spacing with adjacent signal lines and vias, and is connected to the system reference ground network through grounded vias, thereby effectively absorbing high-frequency noise, suppressing crosstalk between signals, and reducing electromagnetic coupling between vias. During wafer-level testing, this design significantly improves the integrity and stability of sensitive signals, reduces the risk of parameter drift or misjudgment caused by parasitic effects introduced by RDL interconnects, and eliminates the need for additional package pins, thus balancing testability, manufacturability, and electrical performance.

[0072] As an optional implementation, generating isolation bands between different partitions through layout design rules includes: A ground grid layer 110 is formed in a second metal layer 107 of the redistribution layer that is not used for signal interconnection; the ground grid layer 110 covers the die 100 and is electrically connected to the ground grid on the die 100.

[0073] This application embodiment enhances the electromagnetic isolation between different functional regions within the chip by forming a ground grid layer 110 on the second metal layer 107, which is not involved in signal interconnection in the redistribution layer. Specifically, the ground grid layer 110 covers the entire chip die 100 and is electrically connected to the ground grid on the chip, forming a continuous, low-impedance ground plane. This approach in this application embodiment helps absorb and disperse high-frequency noise, reduces electromagnetic interference between different circuit blocks, and thus improves the overall performance and stability of the chip.

[0074] Thirdly, embodiments of this application also provide a layout generation system, including the following functional modules: The pad / network information acquisition module is used to acquire the electrical network information and functional purpose identifier of the original pad 101 on the chip die 100. The functional purpose identifier includes at least one of signal protocol type, power type or test role. Based on the target package pin layout rules and the constraints of the probe contact window 103, the original pad 101 is mapped to the top layer of the redistribution layer through a redistribution process to form an array of top layer pads 102. The pad classification and partitioning determination module is used to divide the top-level pad set 102 into at least a power / ground pad partition, a test-specific pad partition, and a functional pad partition according to the functional purpose identifier. The array layout generation module is used to generate the partition boundary of each partition based on the distribution position of the top-level pad 102 in each partition; and supports automated script generation of candidate boundaries and acceptance of manual verification and correction. The isolation zone construction module is used to generate isolation zones between different partitions based on layout design rules; The layout data output module is used to integrate the partition boundaries, isolation zones, and interconnect wiring to generate layout data and manufacturing data that conform to the target process design rules.

[0075] The rules and parameters storage module is used to store and call process design rules, minimum spacing parameters, grid density tables, and test interface protocol definitions.

[0076] This layout generation system contains the same structure and beneficial effects as the layout generation method in the foregoing embodiments. The structure and beneficial effects of the layout generation method have been described in detail in the foregoing embodiments and will not be repeated here.

[0077] In addition, this application embodiment also provides a storage medium storing instructions, which, when executed by a processor, implement the above-described layout generation method.

[0078] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A wafer structure, characterized in that, The device includes a die, a redistribution layer, and a protective layer stacked sequentially. The die has multiple original pads. The redistribution layer has multiple arrayed top-level pads on its surface near the protective layer. The protective layer has windows that expose the top-level pads for probe card contact during power supply testing. The top-level pads are divided into at least three functional areas: power / ground pads, test-specific pads, and functional pads, with isolation bands between adjacent areas.

2. The wafer structure according to claim 1, characterized in that, The redistribution layer includes a first metal layer; the isolation band includes an island-shaped exclusion zone disposed in the first metal layer, wherein the vertical projection of the island-shaped exclusion zone is located between any two adjacent partitions among the power / ground pad partition, the test pad partition, and the functional pad partition.

3. The wafer structure according to claim 1, characterized in that, The redistribution layer includes a first metal layer; the first metal layer is provided with signal lines and vias that are electrically connected to the original pads; the isolation strip includes a ground shielding structure provided in the first metal layer, the ground shielding structure is arranged on both sides of the signal lines, and is coplanar with the signal traces and maintains a preset process spacing. And / or, the grounding shielding structure is arranged around the periphery of the via to form an enclosed shielding structure.

4. The wafer structure according to claim 3, characterized in that, The redistribution layer includes a second metal layer not used for signal interconnection; the isolation strip includes a ground grid layer disposed in the second metal layer and covering the die; the ground grid layer is electrically connected to the ground grid of the die or to the ground shielding structure via ground vias.

5. The wafer structure according to claim 1, characterized in that, At least one alignment mark is provided on the chip die. The alignment mark is located outside the window area of ​​the redistribution layer and is configured for optical alignment by the probe card. The geometry or layout of the alignment mark is asymmetrical to prevent misinstallation or reverse contact of the probe card.

6. A method for generating a map layout, characterized in that, include: Obtain the electrical network information and functional purpose identifier of the original pads on the chip die. The functional purpose identifier includes at least one of signal protocol type, power type, or test role. Based on the target package pin layout rules and probe contact window constraints, the original pads are mapped to the top layer of the redistribution layer through a redistribution process to form an array of top-level pads. Based on the functional purpose identifier, the top-level pad set is divided into at least a power / ground pad partition, a test-specific pad partition, and a functional pad partition; Based on the distribution of the top-level pads within each partition, the partition boundary of each partition is generated. Isolation zones are generated between different partitions using layout design rules; The output includes layout data containing the top-level pads, partition boundaries, isolation bands, and interconnects. This layout data conforms to the design rule check requirements of the target manufacturing process and is used for wafer manufacturing and packaging.

7. The layout generation method according to claim 6, characterized in that, The step of generating the partition boundary for each partition based on the distribution location of the top-level pads within each partition includes: Based on the automated script, geometric analysis or spatial clustering is performed on the coordinate data of the top-level pad on the wafer plane to generate candidate partition boundaries; The candidate partition boundaries are then manually verified and corrected according to process constraints or testing requirements to determine the final partition boundaries.

8. The layout generation method according to claim 6, characterized in that, The generation of isolation zones between different partitions through layout design rules includes: Multiple island-shaped containment areas are formed in the first metal layer of the redistribution layer, which prohibit the placement of any electronic components or circuit connections. The vertical projection of the island-shaped containment areas is located between any two adjacent partitions among the power / ground pad partition, the test pad partition, and the functional pad partition.

9. The layout generation method according to claim 6, characterized in that, The generation of isolation zones between different partitions through layout design rules includes: A ground shielding structure is formed in the first metal layer of the redistribution layer; wherein the ground shielding structure is arranged on both sides of the signal line in the first metal layer; and / or, the ground shielding structure is arranged on the outer periphery of the via in the first metal layer to form an enclosed shielding structure.

10. The layout generation method according to claim 6, characterized in that, The generation of isolation zones between different partitions through layout design rules includes: A ground grid layer is formed in a second metal layer of the redistribution layer that is not used for signal interconnection; the ground grid layer covers the die and is electrically connected to the ground grid on the die.

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