Apparatus and method for host data implicit placement without host intervention
By using an implicit data placement table and processing circuitry, the latency problem caused by host interrupt injection for ID placement in memory devices is solved, achieving efficient data storage and performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SK HYNIX NAND PRODUCT SOLUTIONS CORP
- Filing Date
- 2024-12-02
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies require host interrupts to the device to inject a placement ID when performing data placement in memory, resulting in consistent latency and performance degradation for write streaming workloads.
By using data placement tables and processing circuitry, write requests are implicitly routed to specific subsets of memory, eliminating the need for host interrupt-based ID injection and enabling data storage based on system characteristics.
It improves the overall write performance and data placement efficiency of memory devices, avoids latency in the write stream, and is suitable for computing and storage workloads.
Smart Images
Figure CN122439152A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to apparatus and methods for placing data within a memory. Background Technology
[0002] According to this disclosure, an apparatus and method are provided for performing implicit data placement by directing write requests to a subset of memory based on specific system characteristics. The apparatus includes memory, which may include blocks of memory having pages or superpages. The apparatus and method disclosed herein may employ a data placement table or a suitable mapping structure to associate mapped system characteristics with corresponding placement identifiers (IDs). This implicit data placement using a data placement table enables the device to provide flexible data placement (FDP) capabilities for storage workloads without additional latency. FDP is a non-volatile fast memory (NVMe) mechanism that allows a host to store data in a physical subset of memory within a device communicatively coupled to the host. Typically, for a given workload, FDP requires the host to interrupt device operation to inject a placement ID, thereby causing the device to store data at an available memory address associated with the injected placement ID. This form of data placement can cause consistent latency and limitations for workloads using large write flows, thus degrading the overall performance of the device. The apparatus and method disclosed herein eliminate the need for host-interrupted placement ID injection by implicitly routing write requests to a specific subset of memory using locally stored data placement IDs.
[0003] The device may include processing circuitry configured to receive write requests from a host and determine one or more system characteristics based on information indicating system characteristics from the write request. The processing circuitry is also configured to determine whether one or more of the system characteristics from the write request match any of the mapped system characteristics in a data placement table. When a match is determined, the processing circuitry determines the location (e.g., memory address) in memory where the data of the write request is stored, based on the corresponding placement ID of the matching mapped system characteristic and regardless of the destination address. Finally, the processing circuitry stores the data at the determined location within memory. The device and method provided herein improve overall write performance and data placement through the processing circuitry of a device (e.g., a solid-state drive (SSD) device).
[0004] In some embodiments, the device (e.g., a storage device) is provided with a memory and processing circuitry communicatively coupled to each other. In some embodiments, the processing circuitry receives a write request indicating that data is to be stored at an associated destination address within the memory. In some embodiments, the write request received by the processing circuitry includes information indicating one or more system characteristics—information to be used by the processing circuitry in conjunction with a data placement table—and a destination memory address corresponding to the memory address of the memory where the data is stored. Attached Figure Description
[0005] The following description includes a discussion of the figures, which are illustrations given in an exemplary manner through implementations of embodiments of this disclosure. The figures should be understood by way of example, not by way of limitation. As used herein, references to one or more “embodiments” are to be understood as describing a particular feature, structure, and / or characteristic included in at least one implementation. Therefore, expressions such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.
[0006] Figure 1 A schematic diagram of a system including a host and a device having processing circuitry and memory, according to some embodiments of the present disclosure, is shown; Figure 2 Another schematic diagram illustrating a system including a host and devices according to some embodiments of the present disclosure is shown; Figure 3 Additional schematic diagrams of a system having multiple hosts and devices according to some embodiments of the present disclosure are shown; Figure 4 Flowcharts illustrating illustrative steps for performing implicit data placement according to some embodiments of the present disclosure are shown; and Figure 5 A flowchart illustrating the steps of a sub-process for performing implicit data placement on data associated with unmapped system characteristics, according to some embodiments of the present disclosure, is shown. Detailed Implementation
[0007] According to this disclosure, systems and methods are provided for implicitly placing data within the memory of a device (e.g., an SSD device) using a data placement table. The device (e.g., an SSD device) may include multiple memory dies (e.g., NAND memory dies), and the device is configured to perform garbage collection while receiving I / O (e.g., write requests) from multiple tenants and / or hosts. If a first host has a higher write request rate or volume than other hosts communicatively coupled to the device, the device may be required to perform background garbage collection on memory addresses storing data from hosts with slower write request rates or smaller write request volumes. This garbage collection needs to be increased to accommodate I / O (e.g., write requests) from the first host. This causes write amplification by repeatedly copying data to accommodate data from the first host, and write amplification can lead to performance and durability issues with the device's memory dies.
[0008] In some examples of systems with devices communicatively coupled to a host, the host may include multiple virtual machines or applications unaware that other virtual machines or applications can access the device's memory. A data placement table on the device is used to determine the appropriate placement identifier (ID) of the memory where the data for a corresponding write request is stored, enabling the device to perform implicit data placement by directing write requests to a subset of memory based on specific system characteristics. An example system characteristic that can be determined from a write request is a commit queue ID. In such an example, each virtual machine or application may correspond to a unique commit queue ID to indicate the virtual machine or application from which the write request was sent. Processing circuitry receives the write request and uses the data placement table to determine the placement ID of other memory where similar write requests have already been stored. In some embodiments, implicit data placement performed by the device's processing circuitry can be used to store and compute workloads without latency in the write request path of a host with multiple virtual machines or applications.
[0009] The features of this disclosure described herein are in the context of a device having processing circuitry and memory (e.g., an SSD device). However, the principles of this disclosure can be applied to any other suitable environment in which implicit data placement is performed by directing write requests to a subset of memory based on specific system characteristics. The device may include memory and processing circuitry, and the processing circuitry and memory are communicatively coupled to each other via a network bus or interface. In some embodiments, the processing circuitry receives a write request, determines a placement ID of the memory where data associated with the write request is stored based on at least one system characteristic, and causes the data to be stored at a location in the memory according to the determined placement ID. In some embodiments, the request is sent from a host to the device via a network bus or interface.
[0010] In particular, this disclosure provides apparatus and methods for performing implicit data placement to allow devices (e.g., SSD devices) to provide data placement with improved performance and without additional latency in the I / O path (e.g., write request path). This enables FDP placement mode to be implemented in both compute workload applications and storage workload applications.
[0011] In some embodiments, the processor of the processing circuit may be a highly parallelized processor capable of rapidly processing high-bandwidth incoming data (e.g., by processing simultaneously with initiating a write request or instruction before completing a previously received write request or instruction).
[0012] In some embodiments, the memory of the device disclosed herein may include any of the following memory densities: single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), five-level cell (PLC), and any suitable memory density with each memory cell greater than five bits.
[0013] In some embodiments, the systems and methods disclosed herein may refer to storage device systems (e.g., SSD storage systems) that include storage devices, such as solid-state drive devices, that are communicatively coupled to a host (e.g., a host device) via a network bus or interface.
[0014] An SSD is a data storage device that uses integrated circuit components as memory to persistently store data. SSDs have no moving mechanical components, a feature that distinguishes them from traditional electromechanical disks, such as hard disk drives (HDDs) or floppy disks, which consist of spinning disks and removable read / write heads. Compared to HDDs, SSDs are typically more resistant to physical shock, operate quietly, have shorter access times, and lower latency.
[0015] refer to Figure 1-5 This will allow for a better understanding of the subject matter of this disclosure.
[0016] Figure 1A schematic diagram of a system 100 according to some embodiments of the present disclosure is shown. The system 100 includes a host 108 and a device 102 having processing circuitry 104, input / output (I / O) circuitry 105, and memory 106. In some embodiments, device 102 may be a storage device, such as a solid-state storage device (e.g., an SSD device). In some embodiments, processing circuitry 104 may include a processor or any suitable processing unit. In some embodiments, memory 106 may be non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, in addition to or instead of an SSD, device 102 may also include a hard disk drive (HDD) device. In some embodiments, I / O circuitry 105 includes temporary memory (e.g., a cache or any suitable volatile memory) to store write requests (e.g., write request 110) received via port 107.
[0017] In some embodiments, processing circuitry 104 is configured to receive write requests (e.g., write request 110) from host 108, wherein each write request 110 includes information indicating system characteristics and a destination address in memory 106 where data is stored. In some embodiments, system characteristics may include any one or more of physical functions, virtual functions, namespace IDs, commit queue IDs, write operation lengths (or sizes), and port IDs (e.g., in embodiments with multiple ports such as port 107). Processing circuitry 104 determines the system characteristics associated with write request 110 based on the information indicating system characteristics. Write request 110 indicates to processing circuitry 104 that the corresponding data for write request 110 should be stored at a memory address in memory 106. In some embodiments, processing circuitry 104 stores the corresponding data for write request 110 based on system characteristics (e.g., physical functions, virtual functions, namespace IDs, commit queue IDs, write operation lengths (or sizes), and port IDs). Processing circuitry 104 may refer to a data placement table that maps system characteristics, each mapping system characteristic having a corresponding placement identifier (ID). In some embodiments, a data placement table is temporarily stored and accessed in processing circuitry 104. In some embodiments, the data placement table may be stored in memory 106. In some embodiments, write requests 110 are transmitted to processing circuitry 104 via I / O circuitry 105 on a network bus or interface. In some embodiments, write requests 110 are transmitted from an external source (e.g., a host 110 communicatively coupled to device 102 via port 107). Processing circuitry 104 may receive write requests (e.g., write request 110) from both internal and external sources of device 102. In some embodiments, I / O circuitry 105 includes volatile memory configured to temporarily store any incomplete write requests (e.g., request 110) to be processed by processing circuitry 104. In some embodiments, the device may receive any of NVMe write requests, Fast Peripheral Component Interconnect (PCIe) write requests, and write requests for any other suitable interface protocol.
[0018] Additionally, device 102 includes memory 106. In some embodiments, memory 106 includes any one or more of the following: non-volatile memory, such as phase-change memory (PCM), PCM and switching (PCMS), ferroelectric random access memory (FeRAM) or ferroelectric transistor random access memory (FeTRAM), memristor, spin-torque random access memory (STT-RAM) and magnetoresistive random access memory (MRAM), any other suitable memory or any combination thereof. In some embodiments, memory 106 has a memory density that is (a) single-cell (SLC) memory density, (b) multi-cell (MLC) memory density, (c) three-cell (TLC) memory density, (d) four-cell (QLC) memory density, (e) five-cell (PLC) memory density, or (f) any of the following: greater than 5 bits per memory cell. In some embodiments, processing circuitry 104 is communicatively coupled to memory 106 to store and access data in memory blocks or pages. In some embodiments, a data bus interface is used to transmit write / read commands or data.
[0019] In some embodiments, device 102 further includes volatile memory, which may include any one or more volatile memories, such as static random access memory (SRAM). In some embodiments, the volatile memory is configured to temporarily store data (e.g., write request 110) during operations performed by processing circuitry 104. In some embodiments, each of processing circuitry 104 and I / O circuitry 105 is communicatively coupled to the volatile memory to store and access write request 110 data in the volatile memory. In some embodiments, a data bus interface is used to transfer write request 110 data from the volatile memory to processing circuitry 104. In some embodiments, the volatile memory is communicatively coupled to memory 106, which is configured to serve as a cache or temporary memory for memory 106. In some embodiments, a data bus interface between memory 106 and the volatile memory provides a network bus for accessing memory 106 or writing data to memory 106.
[0020] In some embodiments, the processor or processing unit of processing circuitry 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor, also referred to herein as processing circuitry 104, may include any suitable software, hardware, or both for controlling memory 106 and processing circuitry 104. In some embodiments, device 102 may further include a multi-core processor. Memory 106 may also include hardware elements for non-transitory storage of instructions, commands, or requests.
[0021] Processing circuitry 104 is configured to perform implicit data placement by receiving write requests (e.g., write request 110) from host 108 and determining one or more system characteristics based on information indicating system characteristics included in each write request 110, and then directing the write requests to a subset of memory 106 based on specific system characteristics. Write request 110 may originate from host 108 and includes data to be stored in memory 106 and a destination address indicating the memory address of memory 106 where the data is stored. Processing circuitry 104 determines whether any one or more system characteristics match mapped system characteristics of a data placement table. The data placement table includes at least one mapped system characteristic, each corresponding to a corresponding placement identifier (ID). In some embodiments, a placement ID refers to the memory address of a specific subset of memory within one or more memory dies of memory 106. For example, each placement ID may point to a corresponding memory address of a memory block or page of a corresponding memory die (e.g., NAND memory). If none of the determined system characteristics matches a mapped system characteristic in the data placement table, the processing circuit 104 maps the determined system characteristics to available placement IDs and stores the system characteristic-placement ID pair in the data placement table for processing subsequent write requests. In some embodiments, the available placement ID may correspond to a memory block or page that has not yet been written to, or contain stale or invalid data that can be overwritten or cleared. In some embodiments, the data placement table may be initialized with an initial mapped system characteristic corresponding to the respective placement ID, rather than initializing the mapping of system characteristics to placement IDs in real time when a write request (e.g., write request 110) is received and processed. Furthermore, the data placement table may include a configured default placement ID, which is used when the processing circuitry determines that one or more system characteristics of a write request (e.g., write request 110) do not match any of the mapped system characteristics in the data placement table.
[0022] When one or more determined system characteristics match the mapping characteristics of a data placement table, processing circuitry 104 then determines the location (e.g., a memory address) of the data in memory 106 where write request 110 is stored, based on one or more placement IDs corresponding to the matching mapping system characteristics of the data placement table, regardless of the destination address included in write request 110. In some embodiments, when more than one placement ID is determined based on the matching system characteristics, processing circuitry 104 may randomly select one of the placement IDs to store the data in write request 110. In other embodiments, processing circuitry 104 determines a placement ID corresponding to a matching mapping system characteristic. Once processing circuitry 104 has determined the location in memory where the data is stored, it stores the data at that location (e.g., the memory address corresponding to the determined placement ID). In some embodiments, write request 110 may be one of multiple write requests (e.g., a write request stream). In such an embodiment, the processing circuit 104 can determine that each write request 110 in the write request stream includes data indicating the same system characteristics that match the same mapping system characteristics, and therefore the corresponding data for each write request is sequentially stored by the processing circuit 104 in a subset of the memory 106 associated with the same placement ID.
[0023] In some embodiments, device 102 may be a storage device (e.g., an SSD device) that may include one or more packages of memory dies (e.g., memory 106), wherein each die includes a storage cell. In some embodiments, the storage cells are organized into pages or superpages such that pages and superpages are organized into blocks, each page or superpage having a corresponding placement ID. In some embodiments, each storage cell may store one or more bits of information.
[0024] For clarity and brevity, and not as a limitation, this disclosure is provided in the context described below: implicit data placement is performed without intervention from the host and without regard to the corresponding destination address of each write request 110. Processing circuitry 104 stores data associated with write requests (e.g., write request 110) received from host 108 using a data placement table that maps system characteristics to corresponding placement IDs, regardless of the destination address of each corresponding write request. The process of performing implicit data placement by directing write requests to subsets of memory based on specific system characteristics can be configured by any suitable software, hardware, or both for implementing such features and functionality. As disclosed, implicit data placement can be implemented at least partially in, for example, device 102 (e.g., as part of processing circuitry 104 or any other suitable device). For example, for a solid-state storage device (e.g., device 102), implicit data placement can be implemented in processing circuitry 104. Implicit data placement using data placement tables and system features enables device 102 to provide data placement capabilities without additional latency from host 108 in the I / O path of write requests (e.g., write request 110). This allows FDP placement mode to be used for both compute workloads and storage workloads (e.g., write request 110).
[0025] Figure 2 Another schematic diagram of a system 200 including a host 108 and a device 102 according to some embodiments of the present disclosure is shown. The host 108 includes I / O circuitry 204 and four virtual machines 202 (e.g., virtual machines 1-4), such that the I / O circuitry 204 is communicatively coupled to each of the virtual machines 202. The host 108 is configured to transmit a write request 110 from one of the virtual machines 202 via the I / O circuitry 204. The system 200 also includes a device 102, which includes a port 107, I / O circuitry 105, processing circuitry 104, and memory 106, similar to... Figure 1The device 102 is described above. Processing circuitry 104 includes at least one processor 206. In some embodiments, processing circuitry 104 includes a data placement table 208 used to map one or more system features to corresponding placement IDs. In some embodiments, the data placement table may be stored in memory 106, where processing circuitry 104 can still access the data placement table 208. In some embodiments, data placement table 208 may be implemented in firmware such as a device transport layer of device 102. In such embodiments, the transport layer is configured to receive I / O (e.g., write request 110 and other appropriate commands) from virtual machine 202, determine the corresponding placement ID 212 of memory 106 accessible to the I / O, and inject the determined placement ID 212 into the I / O. Furthermore, data placement table 208 may be implemented in hardware, software, or any combination thereof.
[0026] Memory 106 includes memory dies 210 (e.g., dies 1, dies 2, dies 3, and dies 4). Furthermore, memory 106 may be partitioned by a plurality of placement IDs 212 (e.g., PIDs 1-N). In some embodiments, any available placement ID 212 may be used in a data placement table, and the available placement ID 212 is mapped to one or more corresponding system characteristics. In some embodiments, memory 106 may include any suitable number of memory dies 210 and any suitable number of placement IDs 212 to store data associated with write requests received from host 108. In some embodiments, memory 106 includes any one or more of the following non-volatile memories: such as phase-change memory (PCM), PCM and switching (PCMS), ferroelectric random access memory (FeRAM) or ferroelectric transistor random access memory (FeTRAM), memristors, spin-torque random access memory (STT-RAM) and magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, memory 106 has a memory density that is (a) a single-cell (SLC) memory density, (b) a multi-cell (MLC) memory density, (c) a three-cell (TLC) memory density, (d) a four-cell (QLC) memory density, (e) a five-cell (PLC) memory density, or (f) any of the following: greater than 5 bits per memory cell. In some embodiments, processing circuitry 104 is communicatively coupled to memory 106 to store and access data in memory blocks or pages.
[0027] Host 108 may include a corresponding commit queue between each virtual machine 202 and I / O circuit 204 to temporarily store write requests 110 between the respective virtual machine and I / O circuit 204, each commit queue having a unique commit queue ID. In some embodiments, the commit queue ID of the commit queue storing the write request may be one of one or more system characteristics included in the write request. In some embodiments, the write request (e.g., write request 110) may include information indicating one or more other system characteristics, including any one or more of the physical function associated with the respective virtual machine 202, the virtual function associated with the respective virtual machine 202, the namespace ID corresponding to the source memory address of the data associated with the write request 110, the write operation length (or size) of the write request 110, and the port ID of the device 102 receiving the write request.
[0028] Figure 3 Additional schematic diagrams of a system 300 having multiple hosts (e.g., host 108 and host 302) and device 102 according to some embodiments of the present disclosure are shown. Device 102 includes two ports (e.g., port 107 and port 303). Port 107 is coupled to host 108, and port 303 is coupled to host 302. I / O circuitry 105 is configured to receive write requests (e.g., write requests 110 and 304) from host 108 and host 302, respectively, via port 107 and port 303. Similar to... Figure 1 Device 102 in the diagram may be a storage device, such as a solid-state storage device (e.g., an SSD device). In some embodiments, processing circuitry 104 may include a processor or any suitable processing unit. In some embodiments, memory 106 may be non-volatile memory. In some embodiments, I / O circuitry 105 includes temporary memory (e.g., a cache or any suitable volatile memory) to store write requests (e.g., write request 110 and write request 304) received via ports 107 and 303.
[0029] Processing circuitry 104 is configured to receive write requests (e.g., write request 110 and write request 304) from hosts 108 and 302, wherein each write request includes information indicating system characteristics and a destination address in memory 106 where data is stored. In some embodiments, system characteristics may include any one or more of physical functions, virtual functions, namespace IDs, commit queue IDs, write operation lengths (or sizes), and port IDs. Processing circuitry 104 determines the system characteristics associated with the write request (e.g., write request 110 and write request 303) based on the information indicating system characteristics. The received write request indicates to processing circuitry 104 that the corresponding data for the write request (e.g., write request 110 or write request 304) should be stored at a memory address in memory 106. In some embodiments, processing circuitry 104 stores the corresponding data for the write request based on system characteristics (e.g., physical functions, virtual functions, namespace IDs, commit queue IDs, write operation lengths (or sizes), and port IDs). Processing circuitry 104 may refer to a data placement table that maps system characteristics, each mapping system characteristic having a corresponding placement identifier (ID).
[0030] In some embodiments, write requests (write request 110 and write request 304) are transmitted from one or more external sources (e.g., host 110 communicatively coupled to device 102 via port 107 and host 302 communicatively coupled to device 102 via port 303). Processing circuitry 104 can receive write requests (e.g., write request 110 and write request 304) from both internal and external sources of device 102. In some embodiments, I / O circuitry 105 includes volatile memory configured to temporarily store any unfinished write requests to be processed by processing circuitry 104. In some embodiments, device 102 may include more than two ports. In some embodiments, I / O circuitry 105 may be communicatively coupled to more than two hosts. In some embodiments, host 108 and host 302 may each be implemented as a virtual machine on a single host. In some embodiments, host 108 and host 302 may each be an application running on a single host.
[0031] In addition, such as Figure 1As shown, device 102 includes memory 106. In some embodiments, processing circuitry 104 is communicatively coupled to memory 106 to store and access data in memory blocks or pages. In some embodiments, a data bus interface is used to transmit write / read instructions or data. In some embodiments, device 102 also includes volatile memory, which may include any one or more volatile memories, such as static random access memory (SRAM). In some embodiments, the volatile memory is configured to temporarily store data (e.g., write request 110 and write request 304) during operations performed by processing circuitry 104. In some embodiments, a data bus interface between memory 106 and the volatile memory provides a network bus for accessing memory 106 or writing data to memory 106.
[0032] Processing circuitry 104 is configured to perform implicit data placement by receiving write requests (e.g., write request 110 and write request 304) from hosts 108 and 302 and determining one or more system characteristics based on information indicating system characteristics included in each write request, thereby directing write requests to a subset of memory 106 based on specific system characteristics. Each of write requests 110 and 304 may include data to be stored in memory 106 and a destination address indicating the memory address of memory 106 where the data is stored. In some embodiments, write request 304 may be one of a write stream of write requests from host 302. In such embodiments, each write stream including write request 304 may include one or more system characteristics that cause the corresponding data for each write request to be stored at a placement ID in memory 106, which corresponds to a mapped system characteristic in a data location table that matches one or more system characteristics of the write request.
[0033] When one or more system characteristics are determined to match the mapping characteristics of the data placement table, the processing circuit 104 then determines the location (e.g., memory address) of the data in memory 106 where write request 110 is stored based on one or more placement IDs corresponding to the matching mapping system characteristics of the data placement table, without considering the destination address included in the write request (e.g., write request 110 and write request 302).
[0034] In some embodiments, device 102 may be a storage device (e.g., an SSD device) that may include one or more memory die packages (e.g., memory 106), wherein each die includes a storage cell. In some embodiments, the storage cells are organized into pages or superpages such that pages and superpages are organized into blocks, each page or superpage having a corresponding placement ID. In some embodiments, each storage cell may store one or more bits of information.
[0035] Figure 4 A flowchart illustrating the illustrative steps of a process 400 for performing implicit data placement according to some embodiments of the present disclosure is shown. In some embodiments, the system, device, processing circuitry, I / O circuitry, memory, port, host, and write request referred to may be implemented as system 100, device 102, processing circuitry 104, I / O circuitry 105, memory 106, port 107, host 108, and write request 110, respectively. In some embodiments, process 400 may be modified, for example, by rearranging, changing, adding, and / or removing steps.
[0036] At step 402, the processing circuitry receives a write request from the host, wherein the write request includes information indicating one or more system characteristics and a destination address where data is stored. In some embodiments, the destination address is a memory address of memory within the device. The write request may initially be received by I / O circuitry via a port of the device. In some embodiments, the write request is transmitted to the processing circuitry via I / O circuitry on a network bus or interface. The I / O circuitry may include temporary storage devices or caches to store incomplete write requests received from the host before each write request is processed by the processing circuitry. At step 404, once the processing circuitry receives the write request from the host, it determines one or more system characteristics based on the information included in the write request.
[0037] In step 404, the processing circuitry determines one or more system characteristics based on information indicating one or more system characteristics. In some embodiments, system characteristics may include any one or more of physical functions, virtual functions, namespace IDs, commit queue IDs, write operation lengths (or sizes), and port IDs (e.g., in embodiments of devices with more than one port). A write request indicates to the processing circuitry that the corresponding data for the write request should be stored at a memory address. However, the processing circuitry stores the corresponding data for the write request based on system characteristics (e.g., physical functions, virtual functions, namespace IDs, commit queue IDs, write operation lengths (or sizes), and port IDs). As shown in step 406, the processing circuitry may refer to a data placement table that maps system characteristics, each mapping system characteristic having a corresponding placement ID.
[0038] In step 406, the processing circuitry determines whether any one or more system characteristics match a mapping system characteristic of the data placement table, where each corresponding mapping system characteristic corresponds to a corresponding placement identifier (ID). In some embodiments, the processing circuitry compares each of the one or more system characteristics with each mapping system characteristic of the data placement table to determine if a match exists. In some embodiments, the processing circuitry may use any suitable method to compare each of the system characteristics of the write request and each of the mapping system characteristics of the data placement table. In some embodiments, the data placement table may be implemented as a lookup table or a suitable data structure to compare each of the system characteristics of the write request and each of the mapping system characteristics of the data placement table. If the processing circuitry determines that no at least one mapping system characteristic matches one or more system characteristics, process 400 continues to sub-process A, as follows. Figure 5 As shown in the diagram. When the processing circuitry determines that at least one mapped system characteristic in the data placement table matches one or more system characteristics determined from the information in the write request, process 400 proceeds to step 408, which involves determining the location in memory where the data is stored.
[0039] In step 408, the processing circuitry determines the location (e.g., memory address) in memory where data is stored, based on one or more placement IDs corresponding to the matching mapping system characteristics of the data placement table, regardless of the destination address. In some embodiments, when more than one placement ID is determined based on the matching system characteristics, the processing circuitry randomly selects one of the placement IDs to store the write request data therein. In other embodiments, the processing circuitry determines a placement ID corresponding to a plurality of matching mapping system characteristics. In some embodiments, the determined location where data is stored is based on the next available memory address offset from the base memory address associated with the placement ID. Once the processing circuitry has determined the location (e.g., memory address) in memory where data is stored, in step 410, the processing circuitry stores the data at that location (e.g., the memory address corresponding to the determined placement ID).
[0040] In step 410, the processing circuit stores the data at the determined location. In some embodiments, the processing circuit performs a write operation to store the data requested for writing at the determined location.
[0041] Figure 5A flowchart illustrating the steps of a sub-process 500 for performing implicit data placement on data associated with unmapped system characteristics, according to some embodiments of the present disclosure, is shown. In some embodiments, the system, device, processing circuitry, I / O circuitry, memory, port, host, and write request referred to may be implemented as system 100, device 102, processing circuitry 104, I / O circuitry 105, memory 106, port 107, host 108, and write request 110, respectively. In some embodiments, sub-process 500 may be modified by, for example, rearranging, changing, adding, and / or removing steps.
[0042] In step 502, the processing circuitry maps one or more system characteristics to available placement IDs. In some embodiments, an available placement ID may correspond to a memory block or page that has not yet been written to or contains stale or invalid data that may be overwritten or erased. In some embodiments, each memory block includes information indicating whether each memory block is available (e.g., valid bits). Therefore, the placement table is updated using the new mapped system characteristics associated with the available placement IDs. The updated placement table is then used for subsequent write requests received from the host. While updating the placement table requires additional processing time and cost, any write request that includes corresponding data received from the host with one or more system characteristics that match the new mapped system characteristics will be written to the location in memory based on the corresponding placement ID of the matching mapped system characteristic.
[0043] In step 504, the processing circuitry stores the data in memory at a location based on the Available Placement ID. In some embodiments, the Available Placement ID points to a base memory address where the data is stored. In some embodiments, once the data is stored in memory based on the Available Placement ID, the processing circuitry updates the data associated with the Available Placement ID, indicating that the Available Placement ID can be written. Updating this data by the processing circuitry may include setting valid bits associated with the memory block corresponding to the Available Placement ID. In some embodiments, the processing circuitry may update the valid bits associated with the memory block, corresponding to the Available Placement ID, based on the age of the data stored in the memory block or other characteristics of the data indicating data validity.
[0044] Unless otherwise expressly specified, the terms “an embodiment,” “an embodiment,” “multiple embodiments,” “the embodiment,” “the embodiment,” “one or more embodiments,” “some embodiments,” and “an embodiment” mean “one or more (but not all) embodiments.”
[0045] Unless otherwise expressly specified, the terms “including,” “comprising,” “having,” and their variations mean “including but not limited to.”
[0046] Unless otherwise expressly specified, the list of items does not imply that any or all items are mutually exclusive.
[0047] Unless otherwise expressly stated, the terms “a,” “an,” and “the” mean “one or more.”
[0048] Unless otherwise explicitly stated, devices communicating with each other do not need to communicate continuously. Furthermore, devices communicating with each other may communicate directly or indirectly through one or more intermediaries.
[0049] The description of an embodiment having several communicating components does not imply a requirement for all such components. Instead, a wide variety of optional components are described to illustrate a broad range of possible embodiments. Furthermore, while process steps, method steps, algorithms, etc., may be described in sequential order, such processes, methods, and algorithms may be configured to operate in an alternating order. In other words, any order or sequence of steps that can be described does not necessarily indicate a requirement to perform the steps in that order. The steps of the process described herein can be performed in any actual order. Moreover, some steps may be performed simultaneously.
[0050] When a single device or article of art is described herein, it will be apparent that more than one device / article of art (whether or not they cooperate) may be used in place of the single device / article of art. Similarly, in cases where more than one device or article of art (whether or not they cooperate) is described herein, it will be apparent that a single device / article of art may be used in place of the more than one device or article of art, or that a different number of devices / articles of art may be used in place of the number of devices or programs shown. The functionality and / or features of a device may alternatively be embodied by one or more other devices that are not explicitly described as having such functionality / features. Therefore, other embodiments do not need to include the device itself.
[0051] The figures may illustrate specific events occurring in a specific order, as shown by at least certain operations. In alternative embodiments, specific operations may be performed, modified, or removed in a different order. Furthermore, steps may be added to the above logic, still conforming to the described embodiments. Additionally, the operations described herein may occur sequentially, or specific operations may be processed in parallel. Furthermore, operations may be performed by a single processing unit or distributed processing units.
[0052] The foregoing description of various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible in accordance with the above teachings.
Claims
1. A method for storing data on a device including a memory, the method comprising: Receive a write request from the host, the write request including information indicating one or more system characteristics and the destination address where the data is stored; The one or more system characteristics are determined based on information indicating the one or more system characteristics; Determine whether any one of the one or more system characteristics matches a mapping system characteristic of the data placement table, wherein each corresponding mapping system characteristic corresponds to a corresponding placement identifier ID; The location of the data in memory is determined based on one or more placement IDs corresponding to the characteristics of the mapping system that match the data placement table, regardless of the destination address; and Processing circuitry is used to store the data at the specified location.
2. The method according to claim 1, further comprising: In response to determining that any one of the one or more system characteristics does not match the mapping system characteristics of the data placement table: Map the one or more system characteristics to available placement IDs; and Data is stored in memory at a location based on the available placement ID.
3. The method according to claim 2, further comprising: Available placement IDs are determined based on unused placement IDs and obsolete placement IDs, where each corresponding placement ID in the unused placement IDs and obsolete placement IDs is associated with a corresponding available location in the memory.
4. The method of claim 1, wherein the information indicating one or more system characteristics includes any one or more of the following: Physical function Virtual functions Namespace ID, Submit queue ID, Write operation length, and Port ID.
5. The method of claim 1, wherein the host is a first host associated with a first port, and wherein receiving a write request from the host includes receiving a write request from one of a plurality of ports, each of which is associated with a corresponding host, wherein each of the plurality of ports is associated with a corresponding port ID.
6. An apparatus comprising: Memory; and Processing circuitry, used for: Receive a write request from the host, the write request including information indicating one or more system characteristics and the destination address where the data is stored; The one or more system characteristics are determined based on information indicating the one or more system characteristics; Determine whether any one of the one or more system characteristics matches a mapping system characteristic of the data placement table, wherein each corresponding mapping system characteristic corresponds to a corresponding placement identifier ID; The location of the data stored in memory is determined based on one or more placement IDs corresponding to the matching mapping system characteristics of the data placement table, regardless of the destination address; and Store the data at the location stated.
7. The device according to claim 6, wherein the processing circuitry is further used for: In response to a determination that any of the one or more system characteristics does not match the mapping system characteristics of the data placement table: Map the one or more system characteristics to available placement IDs; and Data is stored in memory at a location based on the available placement ID.
8. The device of claim 7, wherein the processing circuitry further determines the available placement ID based on unused placement IDs and obsolete placement IDs, wherein, Each of the unused placement IDs and obsolete placement IDs is associated with a corresponding available location in the memory.
9. The device of claim 6, wherein the information indicating one or more system characteristics includes any one or more of the following: Physical function Virtual functions Namespace ID, Submit queue ID, Write operation length, and Port ID.
10. The device of claim 6, wherein the host is a first host associated with the first port, and wherein, in order to receive a write request from the host, the processing circuitry receives a write request from one of a plurality of ports, each of the plurality of ports being associated with a corresponding host, wherein each of the plurality of ports is associated with a corresponding port ID.
11. A non-transitory computer-readable medium having non-transitory computer-readable instructions encoded thereon, wherein when executed by processing circuitry, the computer-readable instructions cause the processing circuitry to: Receive a write request from the host, the write request including information indicating one or more system characteristics and the destination address where the data is stored; One or more system characteristics are determined based on information indicating one or more system characteristics; Determine whether any one of the one or more system characteristics matches a mapping system characteristic of the data placement table, wherein each corresponding mapping system characteristic corresponds to a corresponding placement identifier ID; The location of the data stored in memory is determined based on one or more placement IDs corresponding to the matching mapping system characteristics of the data placement table, regardless of the destination address; and Store the data at the location stated.
12. The non-transitory computer-readable medium of claim 11, wherein the processing circuitry is further configured to: In response to determining that any one of the one or more system characteristics does not match the mapping system characteristics of the data placement table: Map the one or more system characteristics to available placement IDs; and Data is stored in memory at a location based on the available placement ID.
13. The non-transitory computer-readable medium of claim 12, wherein the processing circuitry is further configured to: Available placement IDs are determined based on unused placement IDs and obsolete placement IDs, where each corresponding placement ID in the unused placement IDs and obsolete placement IDs is associated with a corresponding available location in the memory.
14. The non-transitory computer-readable medium of claim 11, wherein the information indicating one or more system characteristics includes any one or more of the following: Physical function Virtual functions Namespace ID, Submit queue ID, Write operation length, and Port ID.
15. The non-transitory computer-readable medium of claim 11, wherein the host is a first host associated with the first port, and wherein, in order to receive a write request from the host, the processing circuitry receives a write request from one of a plurality of ports, each of the plurality of ports being associated with a corresponding host, wherein each of the plurality of ports is associated with a corresponding port ID.