A high-sensitivity fixed-beam damage system based on EQR-SiPM and quartz rod

Abstract

This invention belongs to the field of high-energy physics particle detection technology, specifically a high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod. It includes: one end of a quartz rod inserted into the cavity of the SiPM cassette, with its end face optically coupled to the photosensitive surface of the EQR-SiPM integrated on the SiPM circuit board; on the SiPM circuit board: the output of a voltage amplifier circuit is connected to the signal input of the SiPM signal processing system via an SMA interface and a coaxial cable, and the signal output is connected to the central control OPI via a control network; an attenuator is also connected in series between the output of the voltage amplifier circuit and the analog input of the SiPM signal processing system. This invention utilizes its high photon detection efficiency and the high light transmittance of the quartz rod to identify femto-Coulomb-level weak beam losses, featuring high sensitivity, nanosecond-level time resolution, resistance to magnetic field interference, wide dynamic range, and a small, compact structure.

Description

Technical Field

[0001] This invention belongs to the field of high-energy physics particle detection technology, specifically a high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod. Background Technology

[0002] Accelerator beam loss monitoring (BLM) is a key technology for ensuring the safe operation of accelerators. Currently, accelerator beam loss monitoring mainly uses ionization chambers or traditional photomultiplier tubes (PMTs) in conjunction with scintillators / fibers.

[0003] Existing detectors have the following drawbacks:

[0004] (1) Sensitivity limitations: Traditional detectors have low signal-to-noise ratios under extremely weak beam loss (on the order of tens of fecoulombs fC), making it difficult to capture losses in the state where the beam is "not visible". For example, commercially available detectors can only detect beam loss on the order of hundreds of fecoulombs and cannot detect lower beam loss.

[0005] (2) Size and installation limitations: PMTs are large in size and sensitive to magnetic fields, making them difficult to install in confined spaces such as accelerator undulators. PMTs require high-voltage power supplies and have a large overall size, making them unsuitable for flexible installation and use in small spaces.

[0006] (3) Insufficient dynamic range: Commercial fixed beam loss probes are prone to saturation under high intensity radiation, and have a narrow linear response range, making it impossible to accurately measure both weak and strong signals.

[0007] Therefore, developing a beam loss probe that is highly sensitive, miniaturized, resistant to magnetic field interference, and has a wide dynamic range is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0008] The purpose of this invention is to provide a high-sensitivity fixed beam loss system based on an EQR-SiPM and a quartz rod. The probe of this invention operates based on the Cherenkov radiation principle. When high-energy charged particles (such as electrons and protons) in the accelerator experience beam loss and strike the quartz rod, if the particle velocity exceeds the speed of light in the quartz medium, Cherenkov light will be generated along the particle trajectory. This light signal undergoes multiple reflections and total internal reflections within the quartz rod, eventually exiting from the end of the rod, passing through the optical coupling gap, and entering the photosensitive surface of the EQR-SiPM. The EQR-SiPM converts the weak light signal into an electrical pulse signal, which is amplified and shaped by the circuit before being output to the back-end signal processing system via an SMA interface. The signal processing system then performs pulse acquisition and beam loss intensity calculation.

[0009] The technical solution adopted by the present invention to achieve the above objectives is: a high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod, comprising: a SiPM cassette, a quartz rod, a SiPM circuit board (CGN product), an external linear regulated power supply, a SiPM signal processing system, a central control OPI, and an attenuator;

[0010] One end of the quartz rod is inserted into the cavity of the SiPM cassette, and the end face is optically coupled to the photosensitive surface of the EQR-SiPM integrated on the SiPM circuit board.

[0011] The SiPM circuit board is equipped with: a bias circuit, an EQR-SiPM, a transimpedance amplifier circuit, and a voltage amplifier circuit.

[0012] The input terminal of the bias circuit is connected to the output terminal of an external linear regulated power supply via a low-noise coaxial cable, and the output terminal of the bias circuit is connected to the bias input terminal of the EQR-SiPM. The signal output terminal of the EQR-SiPM is connected to the input terminal of the transimpedance amplifier circuit via a DC blocking capacitor, and the output terminal of the transimpedance amplifier circuit is connected to the input terminal of the voltage amplifier circuit. The output terminal of the voltage amplifier circuit is connected to the signal input terminal of the SiPM signal processing system via an SMA interface and a coaxial cable.

[0013] The signal output terminal of the SiPM signal processing system is connected to the central control OPI via a control network.

[0014] An attenuator is connected in series between the output of the linear regulated power supply and the analog input of the SiPM signal processing system.

[0015] The SiPM dark box is a square shell with one end open and the other end closed, forming the receiving cavity inside; after encapsulation, the open side is fixed with a cover plate and screws to maintain the darkroom environment.

[0016] The SiPM cassette has a lightweight resin shell.

[0017] The outer wall of the SiPM cassette has a threaded interface for fixing the probe to the undulator mounting position.

[0018] The bias circuit is a two-stage RC low-pass filter circuit;

[0019] The first-stage RC filter circuit consists of a 50Ω resistor R1 and a 100nF capacitor C1, and its cutoff frequency is: The resistor R1 serves as a current-limiting and noise-reducing resistor, used to limit the surge current during power-on or abnormal events to protect the EQR-SiPM; the capacitor C1 serves as a first-stage decoupling capacitor, used to guide the high-frequency components in the power supply to ground and provide local energy storage for the EQR-SiPM to compensate for instantaneous voltage drops; the resistor R1 and capacitor C1 work together to filter out the mid-to-high frequency noise in the power supply.

[0020] The second-stage RC filter circuit consists of a 1Ω resistor R2 and a 10nF capacitor C2, and its cutoff frequency is: The resistor R2 serves as an isolation resistor, used to isolate the pre-stage filter capacitor from the post-stage load, preventing LC oscillation caused by parasitic inductance; the capacitor C2 serves as a second-stage high-frequency bypass capacitor, used to filter out high-frequency noise, including digital circuit crosstalk and radio frequency interference; the resistor R2 and capacitor C2 together form a second-stage low-pass filter.

[0021] The output of the first-stage RC filter circuit is connected to the input of the second-stage RC filter circuit. The two RC filter circuits are connected in series, which attenuates noise above the set value and allows the bias voltage to pass through almost without loss in the DC to 30kHz frequency band.

[0022] The EQR-SiPM integrates a plurality of independent detection pixel units, which are connected in parallel. Each pixel unit consists of an avalanche photodiode operating in Geiger mode and a quenching resistor connected in series with the avalanche photodiode, wherein:

[0023] In each pixel unit, the cathode of the avalanche photodiode is connected to the bias input pin of the EQR-SiPM, one end of the quenching resistor is connected to the anode of the same avalanche photodiode, and the other end of the quenching resistor is connected to the signal output pin of the EQR-SiPM.

[0024] The bias input pins of all pixel units are connected together as the bias input terminal of the EQR-SiPM, which is used to connect to the output terminal of the bias circuit.

[0025] All pixel units share the same signal output pin, which serves as the signal output terminal of the EQR-SiPM and is connected to the input terminal of the transimpedance amplifier circuit via a DC blocking capacitor.

[0026] During operation, a reverse bias voltage higher than the breakdown voltage of the avalanche photodiode is applied to put it in an overbiased state. When a single photon hits a pixel unit, an avalanche chain reaction is generated to form a current pulse. Subsequently, the quenching resistor reduces the voltage across the avalanche photodiode to below the breakdown voltage to forcibly stop the avalanche and complete the reset within tens of nanoseconds. The output currents of each pixel unit are directly superimposed, and the total output current is proportional to the number of pixel units that are triggered at the same time.

[0027] The quartz rod is made of fused silica with a purity ≥ 99.9997%, and both ends of the quartz rod are cold-polished, with a temperature resistance ≥ The coefficient of thermal expansion is Thermal conductivity is ;

[0028] A light coupling layer is provided between the end face of the quartz rod and the photosensitive surface of the EQR-SiPM;

[0029] The optical coupling layer is formed by filling a refractive index matching material, which is a refractive index matching gel or optical coupling adhesive with a refractive index between 1.46 and 1.54, matching the refractive index of the quartz rod. The thickness of the optical coupling layer is 0.1 mm to 0.5 mm, which is used to eliminate the air gap between the end face of the quartz rod and the photosensitive surface of the SiPM, reduce Fresnel reflection loss, and improve the collection efficiency of Cherenkov light.

[0030] A method for monitoring beam loss based on a high-sensitivity fixed beam loss system using EQR-SiPM and a quartz rod includes the following steps:

[0031] Step S1: Use a quartz rod to receive high-energy charged particles. When the particle speed exceeds the speed of light in the quartz medium, Cherenkov light is generated along the particle trajectory. The Cherenkov light is transmitted to the exit end face of the quartz rod after multiple total internal reflections.

[0032] Step S2: The optical signal is incident on the EQR-SiPM and converted into a current pulse. After being amplified by transimpedance and voltage on the SiPM circuit board, the voltage pulse is output to the SiPM signal processing system.

[0033] Step S3: The SiPM signal processing system acquires voltage pulses, performs baseline correction and integration calculations, and converts them into charge quantities according to calibration coefficients;

[0034] Step S4: Compare the converted charge with a preset threshold. If the charge exceeds the threshold, trigger the interlock, output the TTL interlock signal, and simultaneously perform waveform latching to extract and save the waveform data before and after the trigger point from the circular buffer.

[0035] Step S5: After the interlock is triggered, the system enters the interlock state, prohibits repeated latching, and waits for a reset command; if a reset command is received, the interlock flag and TTL output are cleared and monitoring is resumed; if no reset command is received and subsequent pulses still exceed the threshold, the interlock output is maintained and the interlock count is updated but the new waveform is not latched again.

[0036] Step S6: Perform data conversion and EPICS integration on the processing results, and transmit the converted data to the central control OPI for display and alarm through the control network.

[0037] Step S3 includes the following steps:

[0038] Step 3-1: The voltage pulse is sampled by the SiPM signal processing system at a sampling rate of 1 GS / s, with a sampling interval of... ,in, This represents the time interval between two adjacent sampling points, used to ensure that the waveform has a time resolution of 1 nanosecond.

[0039] Step S3-2: Take the average voltage of the M sampling points before triggering as the baseline. This eliminates the DC offset introduced by the bias circuit and EQR-SiPM, allowing the integral calculation to be based on the actual signal change.

[0040] Step S3-3: Calculate the integral value using the trapezoidal rule:

[0041]

[0042] in, This is the voltage-time integral value, where i is the sampling point index, ranging from 0 to... , Let N be the voltage value at the i-th sampling point, and N be the total number of sampling points within the integration length. The baseline voltage average value. The sampling interval;

[0043] Step S3-4: Convert the integral value into charge quantity according to the calibration coefficient k. The calibration coefficient k is obtained by laboratory calibration and is used to convert the voltage-time integral value into charge in femtocoulombs or picocoulombs, thereby reflecting the beam loss intensity.

[0044] Step S3-5: Preset charge threshold and count rate threshold ,in, It includes multiple threshold levels of 50fC, 100fC, and 1-100pC to distinguish different levels of beam loss; It includes count rate limits of 1kHz and 10kHz to prevent pulse accumulation; it adopts a dual threshold judgment logic: if the integral value Q exceeds the high threshold, the interlock is immediately triggered and a TTL interlock signal is output; if it only exceeds the low threshold, a warning is recorded and the interlock is not triggered.

[0045] Steps 3-6: Use an FPGA parallel comparator to compare the integral value Q with a preset threshold. Compare the pulse counts per unit time with... The comparison process is such that if any condition exceeds the threshold, an interlocking trigger signal is output. The parallel processing method of the FPGA is used to ensure that the comparison delay is less than 500ns, which meets the real-time interlocking requirements.

[0046] In step S4, the waveform latching process includes the following steps:

[0047] Step 4-1: Preset trigger delay (Delay) and integration length (Integration Length);

[0048] The Delay is used to control the interval time from when the trigger condition is met to when the waveform recording actually begins, and its adjustable range is -500ns to +500ns.

[0049] The Integration Length is used to control the duration of the recorded waveform after triggering, and its adjustable range is 50ns~1000ns to ensure complete capture of the pulse waveform;

[0050] Step 4-2: When the rising edge of the interlock trigger signal arrives, the FPGA extracts data from the cyclic FIFO: before extracting the trigger point. One sampling point is used as pre-trigger data, and after the trigger point Each sampling point is used as post-trigger data; among which, the pre-trigger data is used to analyze the state before the beam loss event, and the post-trigger data is used to analyze the complete process of the event;

[0051] Step 4-3: Package the extracted data into waveform records, which include: timestamp, channel number, integral value, rising edge width, and original waveform data array;

[0052] Step 4-4: Store the waveform record in the onboard memory or transfer it to the host memory via DMA. At the same time, generate an interlock event record, which contains the index address of the latched data for EPICS IOC to read.

[0053] Steps 4-5: After the interlock is triggered, a latch prohibition time of 100ms is entered. During this prohibition time, if a new interlock event occurs, only the interlock counter is updated, and no new waveform latch record is generated, so as to avoid generating multiple latch data for the same event.

[0054] In steps S4 and S5, an FPGA finite state machine is used to implement interlocking latching and reset control. The state machine includes the following 8 states: WAIT, DELAY, INTEGRAL, COMPARE, LATCH, CLEAR, IDLE, and RESET. The specific transition process between each state is as follows:

[0055] a) In WAIT state, continuously detect whether the input signal exceeds the trigger level. If a rising edge is detected, record the current timestamp and jump to DELAY.

[0056] b) In the DELAY state, wait for the set delay count. If the Delay is negative, read back the historical data from the loop FIFO as the pre-trigger part. After the delay ends, jump to INTEGRAL.

[0057] c) In INTEGRAL state, the acquired waveform segment is integrated in real time, and the rising edge width is calculated at the same time. After the integration length is completed, the program jumps to COMPARE.

[0058] d) In COMPARE state, compare the integration result with the preset threshold. If the threshold is exceeded, the interlock flag is set and the process jumps to LATCH; otherwise, the process jumps to CLEAR.

[0059] e) In LATCH state, waveform latching is performed, TTL interlock signal is output, and after latching is completed, it jumps to CLEAR;

[0060] f) In CLEAR state, reset the internal integral accumulator, baseline register, and trigger flag. If there is a latch completion flag, notify EPICS IOC and jump to IDLE.

[0061] g) In IDLE state, wait for the set time and then return to WAIT;

[0062] h) In RESET state, triggered by an external reset command, all interlock flags, latch buffer pointers, and internal state machine counters are cleared, TTL interlock output signals are canceled, and the system automatically returns to WAIT upon completion.

[0063] Step S6 includes the following steps:

[0064] Step S6-1: Time-to-location conversion, used to determine the location of beam loss, i.e.:

[0065]

[0066] in, For the first The location of beam loss corresponding to each sampling point For effective transmission speed, For the first The time corresponding to each sampling point For reference only;

[0067] Step S6-2: Voltage to charge density conversion, used to obtain the space charge distribution along the beam direction, expressed as:

[0068]

[0069] in, For the first The charge density at each location For the first The processed voltage values ​​of each sampling point For system sensitivity;

[0070] Step S6-3: Extract the minimum value of the waveform The absolute value of the charge is used to estimate the amount of charge. :

[0071]

[0072] in, Peak sensitivity represents the peak voltage generated per unit charge;

[0073] Step S6-4: The total charge of the waveform is calculated as follows:

[0074]

[0075] in, The sampling time interval;

[0076] Step S6-5: Encapsulate the real-time charge quantity, count rate, rising edge width, position information, latched waveform data, and interlock status as process variables, and transmit them to the central control OPI through the control network; the central control OPI performs real-time waveform display, beam loss intensity display, interlock alarm, and historical record.

[0077] The present invention has the following beneficial effects and advantages:

[0078] 1. This invention uses a high-purity fused silica rod to efficiently collect Cherenkov light, combined with the EQR-SiPM's high photon detection efficiency of up to 47.8%, and low-noise transimpedance amplification and voltage amplification circuits, which can stably identify extremely weak beam loss signals on the order of tens of femtocoulombs (fC), solving the problem of low signal-to-noise ratio and inability to provide early warning under weak beam conditions in traditional detectors.

[0079] 2. The fast quenching mechanism and compact circuit design of the EQR-SiPM operating in Geiger mode of this invention enable the output pulse to have a nanosecond-level rise time and an extremely narrow pulse width (≤100ns), with a short recovery time, meeting the real-time protection requirements of high-energy accelerators for fast response.

[0080] 3. This invention adopts a lightweight resin dark box and PCB integrated design, with an overall volume much smaller than traditional PMT modules; the outer wall of the dark box is provided with a standard threaded interface, which can be easily installed in narrow spaces such as oscillators; the quartz rod is directly optically coupled to the SiPM, eliminating the need for a complex optical lens system and further simplifying the structure.

[0081] 4. The EQR-SiPM of this invention is based on semiconductor technology and is not sensitive to magnetic fields. It can work stably in strong magnetic field regions such as undulators and diodes, overcoming the defect of traditional PMTs that cannot be deployed due to magnetic field sensitivity.

[0082] 5. By combining a voltage amplifier with the large dynamic range characteristics of SiPM itself, this invention can simultaneously detect femtocoulometric weak signals and nanocoulometric strong signals, with a wide linear response range, thus meeting the needs of both weak signal detection and strong signal unsaturation.

[0083] 6. This invention uses an FPGA finite state machine to implement the integral algorithm, threshold interlock judgment, waveform latching and reset control, with a parallel processing delay of less than 500ns; it supports software / hardware reset and publishes process variables to the central control OPI through EPICS, realizing real-time monitoring of bundle loss events, interlock alarm and historical data playback functions. Attached Figure Description

[0084] Figure 1 A schematic diagram of the system structure connection of the present invention;

[0085] Figure 2 This is a schematic diagram of the probe structure of the present invention; wherein, a is a side view of the probe of the present invention, and b is a top view of the probe of the present invention;

[0086] Figure 3 This is a three-dimensional structural diagram of the SiPM probe of the present invention;

[0087] Figure 4 This is the SiPM circuit diagram of the present invention;

[0088] Figure 5 This is a system hardware architecture diagram of the present invention;

[0089] Figure 6 This is a flowchart of the signal processing of the present invention;

[0090] Figure 7 This is a flowchart of the state machine of the present invention;

[0091] Figure 8 The SiPM fixed beam loss probe of the present invention exhibits response under different charge levels;

[0092] Figure 9 This is a comparison chart of the sensitivity of the SiPM fixed beam loss probe of this invention and that of a traditional PMT. Detailed Implementation

[0093] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0094] This embodiment provides a complete installation, debugging, and operation process for a high-sensitivity fixed beam loss probe based on EQR-SiPM and a quartz rod on a free-electron laser undulator.

[0095] (a) Fabrication of a fixed beam loss probe

[0096] like Figure 1 As shown in the diagram, the system structure connection diagram of the present invention illustrates the overall connection relationship of SiPM dark box 1, quartz rod 2, SiPM circuit board 3, external linear regulated power supply 4, SiPM signal processing system 5, central control OPI 6 and attenuator 7.

[0097] like Figure 2 As shown, the probe side view ( Figure 2 (a) and top view ( Figure 2 Figure b) shows the shape of the dark box and its mounting threaded interface. Figure 3 This is a schematic diagram of the three-dimensional structure of the SIPM probe. Figure 4 This is the SIPM circuit diagram. Specific parameters are as follows:

[0098] Quartz rod 2: Made of high-purity fused silica (purity ≥99.9997%), 6mm in diameter and 50mm in length, with both ends cold-polished.

[0099] EQR-SiPM: Adopting the CGN EQR11-3030D-S model, it has a photosensitive area of ​​3×3mm², 22,500 microcells, and a peak photon detection efficiency of 47.8% (@420nm). Its internal structure integrates multiple parallel-connected pixel units. Each pixel unit consists of an avalanche photodiode operating in Geiger mode and a series quenching resistor. The cathodes of all pixel units are connected together to form the bias input terminal, and the ends of all quenching resistors are connected together to form the signal output terminal.

[0100] Optical coupling layer: A refractive index matching gel with a refractive index of 1.46 to 1.50 and a thickness of 0.2 mm is filled between the end face of the quartz rod and the photosensitive surface of the EQR-SiPM. This layer is used to eliminate air gaps and reduce Fresnel reflection loss.

[0101] SiPM Dark Box 1: Made of black ABS resin, this square-shaped shell is open at one end and closed at the other, forming an internal cavity. The outer wall has a threaded mounting interface, and the inner surface is coated with a light-absorbing coating, providing electromagnetic shielding. After encapsulation, the opening is secured with a cover plate and screws to maintain the darkroom environment.

[0102] SiPM circuit board 3: such as Figure 5 The diagram shown is the SIPM circuit diagram of this invention. The bias circuit is a two-stage RC low-pass filter circuit: the first stage has R1=50Ω, C1=100nF, and a cutoff frequency of approximately 31.8kHz; the second stage has R2=1Ω, C2=10nF, and a cutoff frequency of approximately 15.9MHz; the two stages are connected in series, providing at least -40dB / dec attenuation for noise above 30kHz. The circuit board integrates a transimpedance amplifier circuit and a voltage amplifier circuit, outputting a maximum 2V voltage pulse via an SMA interface.

[0103] External linear regulated power supply 4: Adjustable range linear power supply, output 32VDC, ripple ≤10mVpp, connected to the probe power input terminal via a low-noise coaxial cable.

[0104] Attenuator 7: Connected in series between the power output terminal and the power input terminal of the SiPM circuit board.

[0105] (ii) On-site installation of the oscillator with a sipm fixed beam loss probe

[0106] In this embodiment, the probe is installed at the entrance of the free-electron laser undulator (upstream of the beam loss point). The installation steps are as follows:

[0107] Secure the probe housing to the inlet of the free-electron laser undulator (upstream of the beam loss point) via its external threaded interface, exposing the quartz rod to the accelerator beam environment. The installation steps are as follows:

[0108] 1. Fix the outer wall of the probe box to the oscillator entrance inside the tunnel.

[0109] 2. Connect a 50Ω low-loss coaxial cable (15 m in length) to the SMA output interface of the probe, and connect the other end of the cable to the analog input front end of the tunnel external beam loss acquisition system.

[0110] 3. Connect the DC output line (twisted pair shielded cable) of the external linear power supply to the power input SMA interface of the probe. Note the polarity: the center conductor is connected to the positive terminal and the shielding layer is grounded (length 15 m).

[0111] 4. All cables should be laid along the cable trays of the support frame and secured with cable ties to prevent pulling on the probe.

[0112] (III) Beam Loss Acquisition System

[0113] The beam loss acquisition system is based on a PXIe chassis, with the NI-PXIe-5764 high-speed digitizer (4 channels, 1 GS / s, 14-bit resolution) at its core. The system also includes a PXIe controller (running a real-time operating system) and EPICS IOC software. The overall signal transmission and conversion process is as follows: Figure 5 The system hardware architecture diagram shown is as follows:

[0114] Beam loss physical process → optical signal: When a high-energy charged particle hits a quartz rod and its speed exceeds the speed of light in the medium, Cherenkov light (wavelength 320-900nm) is generated.

[0115] Optical signal → weak current pulse: Light passes through the optical coupling layer and is incident on the EQR-SiPM. The internal micro-units undergo avalanche breakdown, outputting a current pulse.

[0116] Weak current pulse → Standard voltage pulse: Connect to the analog input of NI-PXIe-5764 via a 50Ω coaxial cable.

[0117] Coaxial cable transmission → waveform acquisition and synchronous triggering → FPGA processing algorithm → EPICS packaging → control network upload → central control room monitoring.

[0118] The specific hardware architecture and signal flow transmission method are as follows:

[0119] The system of this invention is used to implement a high-sensitivity fixed beam loss monitoring method based on EQR-SiPM and a quartz rod, such as... Figure 5 As shown, it includes the following steps:

[0120] Step S1: Use quartz rod 2 to receive high-energy charged particles. When the particle speed exceeds the speed of light in the quartz medium, Cherenkov light is generated along the particle trajectory. The Cherenkov light is transmitted to the exit end face of the quartz rod after multiple total internal reflections in the quartz rod 2.

[0121] Step S2: The optical signal is incident on the EQR-SiPM and converted into a current pulse. After being amplified by transimpedance and voltage on the SiPM circuit board 3, the voltage pulse is output to the SiPM signal processing system 5.

[0122] Step S3: The SiPM signal processing system 5 acquires voltage pulses, performs baseline correction and integration calculation, and converts them into charge quantities according to calibration coefficients;

[0123] Step S4: Compare the converted charge with a preset threshold. If the charge exceeds the threshold, trigger the interlock, output the TTL interlock signal, and simultaneously perform waveform latching to extract and save the waveform data before and after the trigger point from the circular buffer.

[0124] Step S5: After the interlock is triggered, the system enters the interlock state, prohibits repeated latching, and waits for a reset command; if a reset command is received, the interlock flag and TTL output are cleared and monitoring is resumed; if no reset command is received and subsequent pulses still exceed the threshold, the interlock output is maintained and the interlock count is updated but the new waveform is not latched again.

[0125] Step S6: Perform data conversion and EPICS integration on the processing results, and transmit the converted data to the central control OPI for display and alarm through the control network.

[0126] (iv) Signal processing method of this embodiment

[0127] like Figure 6 The diagram shown is a flowchart of the signal processing of this invention.

[0128] (4.1) Integral algorithm and threshold interlock judgment

[0129] Integration algorithm: For each triggered pulse waveform, numerical integration is used to calculate the area of ​​the pulse. This area is proportional to the total charge generated by the Cherenkov light, thus reflecting the energy loss of the beam.

[0130] Algorithm steps: The integral value and the threshold comparator run in parallel, and the output interlock trigger signal is generated.

[0131] 1. Waveform data point sequence: V[0], V[1], ..., V[N-1], sampling interval at a sampling rate of 1GS / s ( )collection.

[0132] 2. Baseline Correction: The average of the M points before triggering is taken as the baseline. .

[0133] 3. Integral calculation (trapezoidal method):

[0134]

[0135] 4. Convert to charge: Q = k * Integral, where k is a coefficient of 0.22 obtained by laboratory calibration (unit: pC / (V·ns)).

[0136] Threshold interlocking judgment:

[0137] Energy threshold: Preset charge threshold (e.g., multi-level thresholds of 50fC, 100fC, and 1-100pC) are used to distinguish different levels of beam loss;

[0138] Count rate threshold: The upper limit of pulse count per unit time (preset). (e.g., 1 kHz, 10 kHz) are used to prevent pulse buildup;

[0139] Judgment logic: A dual threshold judgment logic is adopted. If the integral value Q exceeds the high threshold, the interlock is immediately triggered and a TTL interlock signal is output. If it only exceeds the low threshold, a warning is recorded and the interlock is not triggered.

[0140] (4.2) Latching algorithm during interlocking

[0141] When the interlocking conditions are met, the current trigger waveform and the data of a period of time before and after it need to be saved for post-fault analysis.

[0142] Latching process:

[0143] 1. The rising edge of the interlock trigger signal arrives.

[0144] 2. Retrieve data from the circular buffer (or FIFO): before the trigger point Each sampling point (e.g., 500 ns), after the trigger point Each sampling point (e.g., 2000 ns).

[0145] 3. Pack the latched data packets into waveform records, including: timestamp (ns precision), channel number, integral value (charge amount), rising edge width, and raw waveform data (array).

[0146] 4. Record the waveform and store it in the onboard memory or transfer it to the host memory via DMA.

[0147] 5. Simultaneously generate an interlock event record containing the index address of the latched data for EPICS IOC to read.

[0148] Anti-overlap and multiple latching: After interlocking is triggered, a latching prohibition time (e.g., 100 ms) is entered to prevent multiple latching records from being generated for the same event. If a new interlocking event occurs within the prohibition time, only the counter is updated, and the new waveform is not latched.

[0149] (4.3) FPGA Algorithm State Machine Control Method

[0150] like Figure 7 The FPGA algorithm state machine flowchart is shown below, with the specific implementation as follows:

[0151] FPGA state machine control: The state machine includes 8 states: WAIT, DELAY, INTEGRAL, COMPARE, LATCH, CLEAR, IDLE, and RESET. The transition process for each state is as follows: Figure 8 As shown, the processing delay is <500ns.

[0152] State definition:

[0153] State 0 - WAIT: Waiting for the trigger condition (rising edge exceeds threshold), continuously monitoring input signals.

[0154] State 1 - DELAY: The trigger condition has been met, and the trigger delay is being executed (if Delay is positive) or the pre-trigger data is being retrieved from the FIFO (if Delay is negative).

[0155] Status 2 - INTEGRAL: Data is being collected within the integration length, while real-time baseline calculation and trapezoidal integral accumulation are being performed simultaneously.

[0156] State 3 - COMPARE: Integration complete. Compare the integrated value with the preset threshold. If the value exceeds the threshold, proceed to LATCH; otherwise, proceed to IDLE.

[0157] State 4 - LATCH: The interlocking condition is met, and waveform latching (writing to memory) is performed. At the same time, a TTL interlocking signal is output.

[0158] Status 5 - CLEAR: Clears the current processing flags and prepares to process the next pulse.

[0159] State 6 - IDLE: Single pulse processing completed, no interlock or interlock has been processed, return to WAIT.

[0160] Status 7 - RESET: Interlock reset status (accepts external reset commands).

[0161] The detailed explanations of each state are as follows:

[0162] WAIT: Continuously monitors whether the input signal exceeds the trigger level. If a rising edge is detected, the current timestamp is recorded, written to the pending queue, and the process jumps to DELAY.

[0163] DELAY: Wait for the set delay count (based on the system clock). If Delay is negative, historical data is read back from the loop FIFO as the pre-trigger portion. At the end of the delay, jump to INTEGRAL.

[0164] INTEGRAL: Performs real-time integration on the acquired waveform segment: for each sample point, accumulate (V[i] - V_base) × Ts. Optionally, the rising edge width (10% → 90%) is also calculated. After the integration length is complete, jump to COMPARE.

[0165] COMPARE: Compares the integration result with a preset threshold (Q_th). If the threshold is exceeded, the interlock flag is set, and the process jumps to LATCH; otherwise, it jumps to CLEAR.

[0166] LATCH: Checks for any pending latch operations (to prevent re-entry). Packs the raw waveform data, integral value, timestamp, rising edge, etc., and writes them to onboard memory or DMA buffer. Outputs a TTL interlock signal (lasting at least 1 μs or cleared by an external reset). After latching is complete, jumps to CLEAR.

[0167] CLEAR: Resets the internal integral accumulator, baseline register, and trigger flag. If a latch completion flag is present, it notifies the EPICS IOC that new data is available. Jumps to IDLE.

[0168] IDLE: Wait a short time (e.g., 10 ns) to ensure the next pulse can be correctly detected. Return to WAIT.

[0169] RESET: Triggered by an external reset command (from EPICS or a manual button). Clears all interlock flags, latch buffer pointers, and internal state machine counters. Cancels TTL interlock output signals. Automatically returns to WAIT upon completion.

[0170] (4.4) Interlock Reset Function

[0171] Reset function: Supports software reset (EPICS process variable write reset command) and hardware reset (external TTL signal). Upon reset, the TTL interlock output is immediately pulled low, the interlock flag is cleared, the latch buffer pointer is cleared (without deleting existing data), the reset event is recorded, the EPICS IOC updates the reset status PV and clears the alarm PV.

[0172] 1. Software Reset: Write the reset command for the PYDM button on the upper interface through the EPICS process variable (PV), such as BLM_Interlock_Reset = 1.

[0173] 2. Hardware Reset: An external TTL reset signal is connected to the digital input port of the board (e.g., from a control room button or machine protection system).

[0174] Reset operation content

[0175] When the reset command is valid, perform the following operations:

[0176] Clear interlock output: Immediately pull the TTL interlock output pin low to stop sending interlock signals to the machine protection system.

[0177] Clear the interlock flags in the state machine: force the state machine to enter the RESET state, and then return to WAIT.

[0178] Clear the latch buffer pointer: but do not delete existing latch waveform data (historical data is retained for analysis).

[0179] Record reset events: Record the reset time and reset source (software / hardware) in the log.

[0180] The probe begins normal monitoring. If beam loss persists and the integral value exceeds the threshold, the interlock will be triggered again in the next pulse processing cycle. The EPICS IOC updates the reset status PV (e.g., BLM_Reset_Status = OK) and clears the alarm PV.

[0181] All algorithms are implemented inside the FPGA, with a processing latency of less than 500ns, meeting the real-time protection requirements of the accelerator.

[0182] (v) Data transformation and EPICS integration

[0183] Perform time-location conversion:

[0184]

[0185] in, For the first The location of beam loss corresponding to each sampling point For effective transmission speed, For the first The time corresponding to each sampling point For reference only;

[0186] Voltage-charge density conversion:

[0187]

[0188] in, For the first The charge density at each location For the first The processed voltage values ​​of each sampling point For system sensitivity;

[0189] Peak estimated charge:

[0190]

[0191] in, Peak sensitivity represents the peak voltage generated per unit charge;

[0192] Total charge:

[0193]

[0194] in, The sampling time interval;

[0195] Real-time charge quantity, count rate, rise edge width, position information, latched waveform data, and interlock status are encapsulated as process variables and transmitted to the central control OPI6 via the control network to realize real-time waveform display, beam loss intensity display, interlock alarm, and historical records.

[0196] (vi) System configuration and algorithm deployment

[0197] Deploy the configuration file on the PXIe controller and set the following key parameters:

[0198] Sampling rate: 1 GS / s;

[0199] Triggering method: rising edge self-triggered, trigger level 10mV;

[0200] Trigger delay: -10ns;

[0201] Integration length: 800 ns;

[0202] Calibration coefficient: k = 0.22 pC / (V·ns);

[0203] Interlocking threshold: Adjustable according to beam conditions (e.g., 50fC, 100fC, 1pC, 10pC, 100pC, etc.).

[0204] The FPGA internal state machine is based on:

[0205] The WAIT-DELAY-INTEGRAL-COMPARE-LATCH-CLEAR-IDLE-RESET deployment updates synchronously every clock cycle (1ns).

[0206] (vii) System debugging and interlocking testing

[0207] 1) Power supply check: Turn on the linear power supply and measure the voltage at the power input terminal of the probe. It is 32.0±0.1V, and the static power consumption is about 5mW.

[0208] 2) Signal baseline test: Under no beam current conditions, the output waveform of the probe is collected, and the peak-to-peak noise floor is less than 10mV.

[0209] 3) Interlock Function Test: A beam loss signal (amplitude > 100mV, pulse width 10ns) is generated by inserting the target chip before the undulator. Observe the TTL interlock output of the board change from high level (3.3V) to low level (0V), and simultaneously check that the latched waveform is successfully stored in the onboard memory and uploaded via DMA. Write a reset command via EPICSPV; the TTL output immediately returns to low level, and the state machine returns to WAIT.

[0210] 4) EPICSIOC Startup: All process variables (PVs) are registered to the control network, including real-time charge, count rate, rise edge width, position information, latched waveform data, interlock status, and reset control.

[0211] 5) Central Control Room Monitoring: Operators can view real-time waveforms and heat maps through the PyDM interface. When the beam loss exceeds the threshold, the interface displays a red alarm, and the TTL interlock signal simultaneously generates an alarm.

[0212] 6) Post-event analysis: After an interlocking event occurs, the system automatically saves the latch waveform (timestamp accurate to 1ns), and the operator can remotely replay and analyze the location of the loss.

[0213] 7) Fault recovery: After the fault is cleared, the operator sends a reset command through the central control room reset button (EPICSPV), the system clears the interlock flag and resumes monitoring.

[0214] (viii) Long-term operational results

[0215] The fixed beam loss probe in this embodiment showed stable performance after 6 months of continuous operation. Figure 8 As shown, the response of the SiPM fixed beam loss probe under different charge levels demonstrates that the probe possesses extremely high unit density, capable of identifying minute beam loss signals on the order of tens of femtocoulombs (fC), and exhibits high response sensitivity. It also features a fast rise time, narrow pulse width, and short recovery time, achieving nanosecond-level temporal resolution. Simplified packaging technology results in a compact and cost-effective structure, facilitating integration and installation in confined spaces such as undulators. Furthermore, the probe is insensitive to magnetic field environments, possesses excellent radiation resistance, and maintains extremely high photon detection efficiency while preserving a compact structure.

[0216] like Figure 9 As shown in the figure, the sensitivity comparison between the SiPM fixed beam loss probe and the traditional PMT shows that, under the same beam current conditions, the SiPM probe can detect weak losses (<100 fC) that the PMT cannot identify, providing an earlier warning capability for accelerator protection.

[0217] In summary, this embodiment successfully applied a high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod to a free-electron laser undulator. Through the Cherenkov radiation principle, a two-stage RC filter low-noise bias circuit, a high-detection-efficiency EQR-SiPM, and an integral interlocking latching algorithm controlled by an FPGA state machine, reliable identification of femto-Coolie-level weak beam loss and nanosecond-level rapid response were achieved. The system has advantages such as compact structure, resistance to magnetic field interference, and wide dynamic range. Furthermore, continuous operation has verified its stable performance, enabling it to provide earlier beam loss warnings for the accelerator and significantly improving beam safety protection capabilities.

[0218] Those skilled in the art will understand that the above description is merely a preferred embodiment of the present invention, and the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. This is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0219] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if these modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include these modifications and modifications.

Claims

1. A high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod, characterized in that, Includes: SiPM dark box (1), quartz rod (2), SiPM circuit board (3), external linear regulated power supply (4), SiPM signal processing system (5), central control OPI (6), and attenuator (7); One end of the quartz rod (2) is inserted into the cavity of the SiPM box (1) and the end face is optically coupled to the photosensitive surface of the EQR-SiPM integrated on the SiPM circuit board (3). The SiPM circuit board (3) is provided with: a bias circuit, an EQR-SiPM, a transimpedance amplifier circuit and a voltage amplifier circuit; The input terminal of the bias circuit is connected to the output terminal of the external linear regulated power supply (4) via a low-noise coaxial cable, and the output terminal of the bias circuit is connected to the bias input terminal of the EQR-SiPM. The signal output terminal of the EQR-SiPM is connected to the input terminal of the transimpedance amplifier circuit via a DC blocking capacitor, and the output terminal of the transimpedance amplifier circuit is connected to the input terminal of the voltage amplifier circuit. The output terminal of the voltage amplifier circuit is connected to the signal input terminal of the SiPM signal processing system (5) via an SMA interface and a coaxial cable. The signal output terminal of the SiPM signal processing system (5) is connected to the central control OPI (6) through the control network. An attenuator (7) is connected in series between the output of the voltage amplifier circuit and the analog input of the SiPM signal processing system (5).

2. The high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 1, characterized in that, The SiPM dark box (1) is a square shell with one end open and the other end closed, and the cavity inside is formed. After the encapsulation is completed, the opening is fixed with a cover plate and screws to maintain the dark room environment. The SiPM cassette (1) has a lightweight resin shell. The outer wall of the SiPM cassette (1) is provided with a mounting thread interface for fixing the probe to the oscillator mounting position.

3. The high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 1, characterized in that, The bias circuit is a two-stage RC low-pass filter circuit; The first-stage RC filter circuit consists of a 50Ω resistor R1 and a 100nF capacitor C1, and its cutoff frequency is: The resistor R1 serves as a current-limiting and noise-reducing resistor, used to limit the surge current during power-on or abnormal events to protect the EQR-SiPM; the capacitor C1 serves as a first-stage decoupling capacitor, used to guide the high-frequency components in the power supply to ground and provide local energy storage for the EQR-SiPM to compensate for instantaneous voltage drops; the resistor R1 and capacitor C1 work together to filter out the mid-to-high frequency noise in the power supply. The second-stage RC filter circuit consists of a 1Ω resistor R2 and a 10nF capacitor C2, and its cutoff frequency is: The resistor R2 serves as an isolation resistor, used to isolate the pre-stage filter capacitor from the post-stage load, preventing LC oscillation caused by parasitic inductance; the capacitor C2 serves as a second-stage high-frequency bypass capacitor, used to filter out high-frequency noise, including digital circuit crosstalk and radio frequency interference; the resistor R2 and capacitor C2 together form a second-stage low-pass filter. The output of the first-stage RC filter circuit is connected to the input of the second-stage RC filter circuit. The two RC filter circuits are connected in series, which attenuates noise above the set value and allows the bias voltage to pass through almost without loss in the DC to 30kHz frequency band.

4. The high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 1, characterized in that, The EQR-SiPM integrates a plurality of independent detection pixel units, which are connected in parallel. Each pixel unit consists of an avalanche photodiode operating in Geiger mode and a quenching resistor connected in series with the avalanche photodiode, wherein: In each pixel unit, the cathode of the avalanche photodiode is connected to the bias input pin of the EQR-SiPM, one end of the quenching resistor is connected to the anode of the same avalanche photodiode, and the other end of the quenching resistor is connected to the signal output pin of the EQR-SiPM. The bias input pins of all pixel units are connected together as the bias input terminal of the EQR-SiPM, which is used to connect to the output terminal of the bias circuit. All pixel units share the same signal output pin, which serves as the signal output terminal of the EQR-SiPM and is connected to the input terminal of the transimpedance amplifier circuit via a DC blocking capacitor. During operation, a reverse bias voltage higher than the breakdown voltage of the avalanche photodiode is applied to put it in an overbiased state. When a single photon hits a pixel unit, an avalanche chain reaction is generated to form a current pulse. Subsequently, the quenching resistor reduces the voltage across the avalanche photodiode to below the breakdown voltage to forcibly stop the avalanche and complete the reset within tens of nanoseconds. The output currents of each pixel unit are directly superimposed, and the total output current is proportional to the number of pixel units that are triggered at the same time.

5. A high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 1, characterized in that, The quartz rod (2) is made of fused quartz with a purity ≥ 99.9997%. Both ends of the quartz rod (2) are cold-polished and have a temperature resistance ≥ The coefficient of thermal expansion is Thermal conductivity is ; A light coupling layer is provided between the end face of the quartz rod (2) and the photosensitive surface of the EQR-SiPM; The optical coupling layer is formed by filling a refractive index matching material, which is a refractive index matching gel or optical coupling adhesive with a refractive index between 1.46 and 1.54, matching the refractive index of the quartz rod. The thickness of the optical coupling layer is 0.1 mm to 0.5 mm, which is used to eliminate the air gap between the end face of the quartz rod and the photosensitive surface of the SiPM, reduce Fresnel reflection loss, and improve the collection efficiency of Cherenkov light.

6. A high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to any one of claims 1-5, characterized in that, Its beam loss monitoring method includes the following steps: Step S1: Use a quartz rod (2) to receive high-energy charged particles. When the particle speed exceeds the speed of light in the quartz medium, Cherenkov light is generated along the particle trajectory. The Cherenkov light is transmitted to the exit end face of the quartz rod after multiple total internal reflections in the quartz rod (2). Step S2: The optical signal is incident on the EQR-SiPM and converted into a current pulse. After being amplified by transimpedance and voltage on the SiPM circuit board (3), the voltage pulse is output to the SiPM signal processing system (5). Step S3: The SiPM signal processing system (5) acquires voltage pulses, performs baseline correction and integration calculation, and converts them into charge quantities according to calibration coefficients; Step S4: Compare the converted charge with a preset threshold. If the charge exceeds the threshold, trigger the interlock, output the TTL interlock signal, and simultaneously perform waveform latching to extract and save the waveform data before and after the trigger point from the circular buffer. Step S5: After the interlock is triggered, the system enters the interlock state, prohibits repeated latching, and waits for a reset command; if a reset command is received, the interlock flag and TTL output are cleared and monitoring is resumed; if no reset command is received and subsequent pulses still exceed the threshold, the interlock output is maintained and the interlock count is updated but the new waveform is not latched again. Step S6: Perform data conversion and EPICS integration on the processing results, and transmit the converted data to the central control OPI (6) for display and alarm through the control network.

7. A high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 6, characterized in that, Step S3 includes the following steps: Step 3-1: The voltage pulse is sampled by the SiPM signal processing system (5) at a sampling rate of 1 GS / s, with a sampling interval of... ,in, This represents the time interval between two adjacent sampling points, used to ensure that the waveform has a time resolution of 1 nanosecond. Step S3-2: Take the average voltage of the M sampling points before triggering as the baseline. This eliminates the DC offset introduced by the bias circuit and EQR-SiPM, allowing the integral calculation to be based on the actual signal change. Step S3-3: Calculate the integral value using the trapezoidal rule: ； in, This is the voltage-time integral value, where i is the sampling point index, ranging from 0 to... , Let N be the voltage value at the i-th sampling point, and N be the total number of sampling points within the integration length. The baseline voltage average value. The sampling interval; Step S3-4: Convert the integral value into charge quantity according to the calibration coefficient k. The calibration coefficient k is obtained by laboratory calibration and is used to convert the voltage-time integral value into charge in femtocoulombs or picocoulombs, thereby reflecting the beam loss intensity. Step S3-5: Preset charge threshold and count rate threshold ,in, It includes multiple threshold levels of 50fC, 100fC, and 1-100pC to distinguish different levels of beam loss; It includes count rate limits of 1kHz and 10kHz to prevent pulse accumulation; it adopts a dual threshold judgment logic: if the integral value Q exceeds the high threshold, the interlock is immediately triggered and a TTL interlock signal is output; if it only exceeds the low threshold, a warning is recorded and the interlock is not triggered. Steps 3-6: Use an FPGA parallel comparator to compare the integral value Q with a preset threshold. Compare the pulse counts per unit time with... The comparison process is such that if any condition exceeds the threshold, an interlocking trigger signal is output. The parallel processing method of the FPGA is used to ensure that the comparison delay is less than 500ns, which meets the real-time interlocking requirements.

8. A high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 6, characterized in that, In step S4, the waveform latching process includes the following steps: Step 4-1: Preset trigger delay (Delay) and integration length (Integration Length); The Delay is used to control the interval time from when the trigger condition is met to when the waveform recording actually begins, and its adjustable range is -500ns to +500ns. The Integration Length is used to control the duration of the recorded waveform after triggering, and its adjustable range is 50ns~1000ns to ensure complete capture of the pulse waveform; Step 4-2: When the rising edge of the interlock trigger signal arrives, the FPGA extracts data from the cyclic FIFO: before extracting the trigger point. One sampling point is used as pre-trigger data, and after the trigger point Each sampling point is used as post-trigger data; among which, the pre-trigger data is used to analyze the state before the beam loss event, and the post-trigger data is used to analyze the complete process of the event; Step 4-3: Package the extracted data into waveform records, which include: timestamp, channel number, integral value, rising edge width, and original waveform data array; Step 4-4: Store the waveform record in the onboard memory or transfer it to the host memory via DMA. At the same time, generate an interlock event record, which contains the index address of the latched data for EPICS IOC to read. Steps 4-5: After the interlock is triggered, a latch prohibition time of 100ms is entered. During this prohibition time, if a new interlock event occurs, only the interlock counter is updated, and no new waveform latch record is generated, so as to avoid generating multiple latch data for the same event.

9. A high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 6, characterized in that, In steps S4 and S5, an FPGA finite state machine is used to implement interlocking latching and reset control. The state machine includes the following 8 states: WAIT, DELAY, INTEGRAL, COMPARE, LATCH, CLEAR, IDLE, and RESET. The specific transition process between each state is as follows: a) In WAIT state, continuously detect whether the input signal exceeds the trigger level. If a rising edge is detected, record the current timestamp and jump to DELAY. b) In the DELAY state, wait for the set delay count. If the Delay is negative, read back the historical data from the loop FIFO as the pre-trigger part. After the delay ends, jump to INTEGRAL. c) In INTEGRAL state, the acquired waveform segment is integrated in real time, and the rising edge width is calculated at the same time. After the integration length is completed, the program jumps to COMPARE. d) In COMPARE state, compare the integration result with the preset threshold. If the threshold is exceeded, the interlock flag is set and the process jumps to LATCH; otherwise, the process jumps to CLEAR. e) In LATCH state, waveform latching is performed, TTL interlock signal is output, and after latching is completed, it jumps to CLEAR; f) In CLEAR state, reset the internal integral accumulator, baseline register, and trigger flag. If there is a latch completion flag, notify EPICS IOC and jump to IDLE. g) In IDLE state, wait for the set time and then return to WAIT; h) In RESET state, triggered by an external reset command, all interlock flags, latch buffer pointers, and internal state machine counters are cleared, TTL interlock output signals are canceled, and the system automatically returns to WAIT upon completion.

10. A high-sensitivity fixed beam loss system based on EQR-SiPM and a quartz rod according to claim 6, characterized in that, Step S6 includes the following steps: Step S6-1: Time-to-location conversion, used to determine the location of beam loss, i.e.: ； in, For the first The location of beam loss corresponding to each sampling point For effective transmission speed, For the first The time corresponding to each sampling point For reference only; Step S6-2: Voltage to charge density conversion, used to obtain the space charge distribution along the beam direction, expressed as: ； in, For the first The charge density at each location For the first The processed voltage values ​​of each sampling point For system sensitivity; Step S6-3: Extract the minimum value of the waveform The absolute value of the charge is used to estimate the amount of charge. : ； in, Peak sensitivity represents the peak voltage generated per unit charge; Step S6-4: The total charge of the waveform is calculated as follows: ； in, The sampling time interval; Step S6-5: Encapsulate the real-time charge quantity, count rate, rising edge width, position information, latched waveform data and interlock status as process variables, and transmit them to the central control OPI (6) through the control network; the central control OPI (6) performs real-time waveform display, beam loss intensity display, interlock alarm and historical record.

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