Dynamic voltage regulation and power balancing control method and system in integrated circuits

Abstract

The application discloses a dynamic voltage regulation and power balance control method and system in an integrated circuit, and particularly relates to the technical field of integrated circuit power management, which measures the timing margin, load change slope and voltage undershoot amplitude of a key path in real time, calculates a timing robustness quantitative value, calculates a leading compensation pulse and sends the same before load jumping, dynamically switches PID coefficients to suppress nonlinear oscillation, stretches a clock or freezes a pipeline when the timing robustness quantitative value is lower than a first threshold value, inserts idle instructions to cut off positive feedback when the product of a current change rate and a temperature gradient is higher than a second threshold value, decouples and isolates a calculation core from peripheral logic, and calibrates the first and second threshold values, so that the application suppresses voltage transients through the leading compensation pulse, reduces timing violation risks, blocks metastable state propagation and positive feedback cycles through clock stretching or pipeline freezing and forced idle instructions, and improves adaptive capacity through voltage domain decoupling and isolation and stable state feedback calibration of threshold values.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit power management technology, and more specifically, to a method and system for dynamic voltage regulation and power consumption balance control in integrated circuits. Background Technology

[0002] Dynamic voltage and frequency regulation is a fundamental technology in the field of integrated circuit power management. Its principle is to dynamically adjust the supply voltage and operating frequency based on the real-time load of the processor or system, thereby reducing dynamic power consumption while ensuring performance. This technology has been widely applied in mobile terminals, data centers, artificial intelligence accelerator chips, and various embedded systems.

[0003] In practical engineering, a common implementation is closed-loop adaptive voltage regulation. This scheme utilizes on-chip sensors or critical path replication circuits to monitor voltage, temperature, and process angles in real time, and feeds the detected signals back to the voltage regulator, which adjusts the output voltage to maintain timing margin. For loads with relatively gradual changes, such as office applications or video playback scenarios, the above mechanism can achieve good energy efficiency benefits. However, as integrated circuit technology continues to evolve towards the nanoscale, and tasks such as artificial intelligence inference and graphics rendering exhibit typical pulsed load characteristics, with load current change rates reaching hundreds of amperes per microsecond, the load can jump from idle to full load within microseconds. Under such severe transient conditions, the response speed of existing closed-loop regulation schemes is relatively limited.

[0004] When the load switching rate exceeds the response bandwidth of the feedback loop, the voltage regulator often intervenes to compensate only after voltage undershoot or overshoot has occurred. Instantaneous voltage dips can still compress or even eliminate the timing margin of the critical path. Insufficient timing margin can lead to downstream triggers entering a metastable state, resulting in intermittent calculation errors. Furthermore, voltage dips, current increases, and temperature rises can form a mutually reinforcing chain reaction, further deteriorating system stability. Therefore, this invention proposes a dynamic voltage regulation and power consumption balance control method and system for integrated circuits to address the aforementioned problems. Summary of the Invention

[0005] To achieve the above objectives, the present invention provides the following technical solution: A method for dynamic voltage regulation and power consumption balance control in integrated circuits includes the following steps: The timing margin, load change slope, and voltage undershoot magnitude of the critical path in the integrated circuit are measured in real time, and the current timing robustness quantization value is calculated based on the timing margin, load change slope, and voltage undershoot magnitude. Based on the load change slope and timing robustness quantization value, the amplitude and duration of the lead compensation pulse are calculated, and the lead compensation pulse is sent to the voltage regulator before the load jumps or at the synchronization moment. After sending the lead compensation pulse, the proportional-integral-derivative coefficients of the voltage regulator are dynamically switched according to the amplitude and rate of load change in order to suppress the nonlinear oscillation of the voltage regulator at the boundary between discontinuous conduction mode and continuous conduction mode. After dynamically switching the proportional-integral-derivative coefficients, when the timing robustness quantization value is lower than the preset first threshold, the clock is stretched to high level or the data pipeline is frozen to prevent metastability from propagating to downstream logic; then the current change rate and temperature gradient are monitored, and when the product of the current change rate and temperature gradient exceeds the preset second threshold, a forced idle instruction for one or more clock cycles is inserted to cut off the positive feedback loop between voltage-current-temperature-voltage. The computationally intensive core and peripheral logic are configured in independent voltage domains. The voltage domains are electrically decoupled and isolated by asynchronous level conversion circuits and capacitor isolation barriers. The stable operating state of each decoupled and isolated voltage domain is fed back to calibrate the first and second thresholds.

[0006] In a preferred embodiment, the current time-series robustness quantization value is calculated through the following steps: When the timing margin is greater than zero, the product value is obtained by multiplying the timing margin by the absolute value of the load change slope. The quotient is obtained by squaring the voltage undershoot amplitude and dividing it by the ratio of the timing margin to a preset fixed reference voltage. Determine if the sum of the product and the quotient is greater than zero: If the value is greater than zero, the product value is added to the quotient value and the natural logarithm is taken. Then, the product is multiplied by the product of the absolute value of the load change slope and the absolute value of the voltage undershoot amplitude to obtain the intermediate value. Then, the intermediate value is multiplied by the sign value of the load change slope. The sign value is positive one when the load change slope is positive, negative one when the load change slope is negative, and zero when the load change slope is zero to obtain the current timing robustness quantization value. If it equals zero, then set the current time series robustness quantization value to zero; When the timing margin is zero or negative, the absolute value of the voltage undershoot amplitude is multiplied by the absolute value of the load change slope, and then added to the absolute value of the timing margin to obtain a temporary value. Divide the temporary value by the preset fixed reference voltage, and then multiply it by the square root of the product of the absolute value of the load change slope and the absolute value of the voltage undershoot amplitude to obtain the current timing robustness quantization value.

[0007] The amplitude and duration of the lead compensation pulse also depend on the difference between the current operating temperature and the nominal temperature of the integrated circuit: When the current operating temperature is higher than the nominal temperature, the amplitude increases by an increment proportional to the difference, and the duration is extended by a duration proportional to the square of the difference.

[0008] In a preferred embodiment, when dynamically switching the proportional-integral-derivative coefficients, a lookup table is pre-stored. The lookup table is indexed by the magnitude and rate of load change, and each set of indexes corresponds to a set of pre-calibrated proportional coefficients, integral coefficients, and derivative coefficients. When the magnitude and rate of the current load change are detected to fall into a certain index range, the control parameters of the voltage regulator are immediately switched to that set of coefficients.

[0009] In a preferred embodiment, the timing and number of forced idle commands are determined through the following steps: Continuously sample the rate of change of current and the temperature gradient, and calculate the instantaneous product of the rate of change of current and the temperature gradient at each sampling moment; Arrange the values ​​of the instantaneous product within the most recent four sampling periods into a sequence, and calculate the amplitude of the discrete Fourier transform fundamental frequency component of the sequence; When the moving average is greater than zero, the amplitude is divided by the moving average of the instantaneous product. The moving average is the arithmetic mean of the instantaneous products in the most recent four sampling periods to obtain the ratio. When the ratio exceeds the second threshold twice in a row, a forced idle instruction for one clock cycle is inserted. If the ratio is still higher than the second threshold in the following two sampling periods, a forced idle instruction for two more clock cycles is inserted. When the moving average is less than or equal to zero, the ratio is not calculated and no forced idle command is inserted.

[0010] In a preferred embodiment, the duration of the high-level clock stretch is equal to the length of the entire time window during which the timing robustness quantization value is below a first threshold, and within this time window, the freeze signal of the data pipeline is determined by the sign of the difference between the timing margin and the voltage undershoot amplitude; when the difference is positive, only the clock is stretched, and when the difference is negative, the data pipeline is frozen simultaneously.

[0011] In a preferred embodiment, the asynchronous level shifting circuit includes a pair of back-to-back metal-oxide-semiconductor field-effect transistors and a capacitor isolation gate, with the two sides of the capacitor isolation gate connected to the voltage domain of the computationally intensive core and the voltage domain of the peripheral logic, respectively, and the ground planes on both sides being independent of each other.

[0012] In a preferred embodiment, the first threshold and the second threshold employ an adaptive calibration method: Within each calibration cycle, the number of times metastability propagation was successfully prevented and the number of times positive feedback loops were interrupted are counted. Successful prevention of metastability propagation means that after stretching the clock or freezing the data pipeline, the flip-flop output of the downstream logic stabilizes to a valid logic level within one clock cycle after the clock edge, without level indeterminacy or oscillation. Interruption of positive feedback loops means that after inserting a forced idle instruction, the product of the current rate of change and the temperature gradient is lower than the last sampled value before the forced idle instruction was inserted in each of the following two sampling cycles. If the total number of times the time-order robustness quantization value is below the first threshold is greater than zero, and the proportion of the number of times metastable propagation is successfully prevented to the total number of times the time-order robustness quantization value is below the first threshold is less than 95%, then the first threshold is lowered. If the total number of times the product of the current change rate and the temperature gradient exceeds the second threshold is greater than zero, and the proportion of the number of times the positive feedback loop is cut off to the total number of times the product of the current change rate and the temperature gradient exceeds the second threshold is less than 90%, then the second threshold is raised.

[0013] When the stable operating states of each voltage domain after decoupling and isolation are fed back to calibrate the first and second thresholds, the stable operating states include the actual peak-to-peak voltage fluctuations, minimum timing margin, and longest load transient recovery time of each voltage domain. The calibration uses proportional-integral regulation. When the minimum timing margin is greater than zero, the deviation between the actual peak-to-peak value of the voltage fluctuation and the preset target peak-to-peak value of the voltage fluctuation is multiplied by a first coefficient to obtain a first adjustment amount. The deviation between the reciprocal of the minimum timing margin and the reciprocal of the preset minimum timing margin target value is multiplied by a second coefficient to obtain a second adjustment amount. The first adjustment amount is added to the first threshold, and the second adjustment amount is added to the second threshold. When the minimum time margin is equal to zero or the minimum time margin is negative, both the first adjustment and the second adjustment are set to zero, while the first threshold and the second threshold remain unchanged.

[0014] In a preferred embodiment, the dynamic voltage regulation and power consumption balance control system in the integrated circuit includes: The sensing quantization module is used to measure the timing margin, load change slope, and voltage undershoot magnitude of the critical path in the integrated circuit in real time, and calculate the current timing robustness quantization value based on the timing margin, load change slope, and voltage undershoot magnitude. The feedforward compensation module is used to calculate the amplitude and duration of the lead compensation pulse based on the load change slope and timing robustness quantization value, and send the lead compensation pulse to the voltage regulator before the load jumps or at the synchronization moment. The gain adjustment module is used to dynamically switch the proportional-integral-derivative coefficients of the voltage regulator according to the amplitude and rate of load change after sending the lead compensation pulse, so as to suppress the nonlinear oscillation of the voltage regulator at the boundary between discontinuous conduction mode and continuous conduction mode. The protection and blocking module is used to stretch the clock high level or freeze the data pipeline to prevent metastability from propagating to downstream logic when the timing robustness quantization value is lower than the preset first threshold after dynamically switching the proportional-integral-derivative coefficients. It also monitors the current change rate and temperature gradient. When the product of the current change rate and temperature gradient exceeds the preset second threshold, it inserts a forced idle instruction for one or more clock cycles to cut off the positive feedback loop between voltage-current-temperature-voltage. The isolation calibration module is used to configure the computationally intensive core and peripheral logic in independent voltage domains. It uses asynchronous level conversion circuits and capacitor isolation barriers to electrically decouple and isolate each voltage domain, and feeds back the stable operating state of each decoupled and isolated voltage domain for calibration of the first and second thresholds.

[0015] The technical effects and advantages of this invention are as follows: This invention significantly improves the transient response capability of voltage regulators to drastic load jumps by calculating timing robustness quantization values ​​in real time and sending advance compensation pulses, effectively suppressing voltage undershoot and overshoot amplitudes. This invention measures the timing margin, load change slope, and voltage undershoot amplitude of the critical path in real time to calculate the current timing robustness quantization value, which comprehensively reflects the timing margin and load trend. Based on the load change slope and timing robustness quantization value, the amplitude and duration of the advance compensation pulse are calculated and sent before or at the moment of load jump, enabling the voltage regulator to respond in advance and significantly reducing the voltage undershoot peak. Subsequently, the proportional-integral-derivative coefficients are dynamically switched according to the load change amplitude and rate to suppress nonlinear oscillations at the boundary between intermittent and continuous conduction modes. This invention proactively pushes compensation commands within the same time window as the load jump, significantly improving power supply quality and reducing the risk of timing violations caused by voltage transients.

[0016] This invention achieves proactive protection against metastable state propagation and timely blocking of positive feedback loops by comparing the timing robustness quantization value with a preset threshold and monitoring the product of the current rate of change and the temperature gradient, significantly improving the system's stable operation under transient abnormal conditions. After dynamically switching the proportional-integral-derivative (PID) coefficients, this invention continuously monitors the timing robustness quantization value. Once this value falls below the first threshold, it immediately stretches the clock high level or freezes the data pipeline to prevent metastable state propagation. Stretching the clock increases register setup time, and freezing the pipeline prevents metastable signals from propagating downwards, reducing the soft error rate to an extremely low level. Simultaneously, it monitors the current rate of change and the temperature gradient. When their product exceeds the second threshold, it indicates that a positive feedback chain has begun to form. At this point, a forced idle instruction is inserted to actively reduce the current rate of change and power density, cutting off the voltage-current-temperature-voltage positive feedback loop. The forced idle instruction can significantly suppress the temperature rise rate of local hot spots on the chip, avoiding frequency reduction or shutdown caused by thermal runaway, and narrowing the system performance jitter to a low range.

[0017] This invention significantly improves the system's anti-interference capability and adaptive adjustment accuracy by configuring the computationally intensive core and peripheral logic in independent voltage domains and electrically decoupling them. Simultaneously, it utilizes the stable operating state after decoupling and isolation to calibrate the first and second thresholds. The invention configures the core and peripheral logic in independent voltage domains, achieving electrical decoupling and isolation through asynchronous level conversion circuits and capacitive isolation barriers. The two ground planes are independent of each other, preventing large voltage fluctuations on the core side from being transmitted to the peripheral logic domain, resulting in significant coupling attenuation. Furthermore, the stable operating state of each voltage domain after decoupling and isolation is used to calibrate the first and second thresholds. The stable state of the peripheral logic domain accurately reflects the chip's reference timing and voltage behavior under conditions unaffected by core transients, allowing the first and second thresholds to adaptively follow process angles, temperature, and aging drift. The feedback calibration is entirely automatic during chip operation, and after long-term operation, the threshold offset is controlled within a small range, effectively extending the chip's lifespan and energy efficiency optimization window. Attached Figure Description

[0018] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings; Figure 1 This is a schematic diagram of the dynamic voltage regulation and power consumption balance control method in the integrated circuit of the present invention.

[0019] Figure 2 This is a schematic diagram of the dynamic voltage regulation and power consumption balance control system in the integrated circuit of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Reference Figure 1 - Figure 2 The following examples were obtained: Example 1: A method for dynamic voltage regulation and power consumption balance control in integrated circuits, comprising the following steps: The timing margin, load change slope, and voltage undershoot magnitude of the critical path in the integrated circuit are measured in real time, and the current timing robustness quantization value is calculated based on the timing margin, load change slope, and voltage undershoot magnitude. Based on the load change slope and timing robustness quantization value, the amplitude and duration of the lead compensation pulse are calculated, and the lead compensation pulse is sent to the voltage regulator before the load jumps or at the synchronization moment. After sending the lead compensation pulse, the proportional-integral-derivative coefficients of the voltage regulator are dynamically switched according to the amplitude and rate of load change in order to suppress the nonlinear oscillation of the voltage regulator at the boundary between discontinuous conduction mode and continuous conduction mode. After dynamically switching the proportional-integral-derivative coefficients, when the timing robustness quantization value is lower than the preset first threshold, the clock is stretched to high level or the data pipeline is frozen to prevent metastability from propagating to downstream logic; then the current change rate and temperature gradient are monitored, and when the product of the current change rate and temperature gradient exceeds the preset second threshold, a forced idle instruction for one or more clock cycles is inserted to cut off the positive feedback loop between voltage-current-temperature-voltage. The computationally intensive core and peripheral logic are configured in independent voltage domains. The voltage domains are electrically decoupled and isolated by asynchronous level conversion circuits and capacitor isolation barriers. The stable operating state of each decoupled and isolated voltage domain is fed back to calibrate the first and second thresholds.

[0022] In integrated circuits, the critical path refers to the signal propagation path with the longest delay from the output of a flip-flop in a sequential logic circuit through combinational logic to the input of the next flip-flop. The timing margin of this path directly determines whether the chip can operate stably at the target frequency. Timing margin is the difference between the maximum signal propagation delay allowed by the timing constraints of the critical path and the actual measured signal propagation delay. A positive difference indicates a timing margin, a zero difference indicates that the timing requirements are met, and a negative difference indicates a timing violation. When measuring the timing margin of the critical path, an on-chip configurable delay chain ring oscillator or time-to-digital converter is used for real-time sampling. The sampling frequency is set according to the chip's highest operating frequency, typically two to four times the chip's clock frequency. For example, for a processor with a 2 GHz clock frequency, the sampling frequency is set to 4 GHz to 8 GHz.

[0023] The load change slope is the change in load current per unit time, estimated by monitoring the output inductor current or the gate drive signal of the on-chip power transistor. Its absolute value is used to prevent sign interference in subsequent multiplication operations. The preset fixed reference voltage is between 1% and 5% of the chip's nominal operating voltage, with a typical value of 0.05 volts. This value comes from the lower limit of the voltage margin recommended in the device manual. The voltage undershoot is defined as the peak downward offset of the voltage relative to the nominal value. It is obtained by acquiring the power supply network node voltage through an analog-to-digital converter, with an acquisition accuracy of at least 8 bits and a range covering ±20% of the nominal voltage.

[0024] When the timing margin is greater than zero, first multiply the timing margin by the absolute value of the load change slope to obtain the product. For example, if the timing margin is 50 picoseconds and the load change slope is 100 amperes per microsecond, the product is 5000 picoseconds·amperes per microsecond. Then, square the voltage undershoot amplitude and divide it by the ratio of the timing margin to a preset fixed reference voltage to obtain the quotient. For example, if the voltage undershoot amplitude is 0.03 volts, its square is 0.0009 volts squared. Dividing the timing margin of 50 picoseconds by the fixed reference voltage of 0.05 volts gives a ratio of 1000 picoseconds per volt. The quotient is 0.0009 divided by 1000, which is 9e-7 volts squared·volts per picosecond.

[0025] To determine if the sum of the product and quotient is greater than zero, if it is, add the product and quotient together, take the natural logarithm, and then multiply this sum by the product of the absolute value of the load change slope and the absolute value of the voltage undershoot amplitude. This yields an intermediate value. Finally, multiply this intermediate value by the sign of the load change slope to obtain the current timing robustness quantization value. The sign value is positive one for a positive load change slope, negative one for a negative load change slope, and zero for zero. For example, if the load rise slope is 100 amperes per microsecond and the sign is positive one, the quantization value is positive, indicating sufficient timing robustness. If the load fall slope is -80 amperes per microsecond and the sign is negative one, the quantization value is negative, indicating a need to pay attention to overshoot risk.

[0026] If the sum of the product and the quotient is zero, the current timing robustness quantization value is directly set to zero. This occurs when both the timing margin and the voltage undershoot are extremely small, for example, when the timing margin is 0.1 picoseconds and the voltage undershoot is 0.001 volts. Since the natural logarithm is undefined, it is manually set to zero.

[0027] When the timing margin is zero or negative, the absolute value of the voltage undershoot amplitude is multiplied by the absolute value of the load change slope, and then added to the absolute value of the timing margin to obtain a temporary value. For example, if the timing margin is -10 picoseconds, the absolute value of the voltage undershoot amplitude is 0.02 volts, and the absolute value of the load change slope is 50 amperes per microsecond, then the temporary value is the absolute value of -10 picoseconds plus 0.02 volts multiplied by 50 amperes per microsecond, resulting in 1 volt-ampere per microsecond. This is then added to 10 picoseconds-ampere per microsecond to obtain 1.00001 volt-ampere per microsecond. The temporary value is then divided by a preset fixed reference voltage of 0.05 volts to obtain a dimensionless ratio, which is then multiplied by the square root of the product of the absolute value of the load change slope and the absolute value of the voltage undershoot amplitude to obtain the current timing robustness quantization value. This quantitative value is a number greater than or equal to zero under non-positive time series margin, representing the urgency of emergency compensation. The larger the value, the more serious the time series violation, requiring immediate intervention.

[0028] The sampling frequency involved in the calculation is typically 4 GHz to 8 GHz, the fixed reference voltage is typically 0.05 volts, and the voltage acquisition accuracy is typically 8 bits. These parameters are derived from the power management chapter of the integrated circuit design manual and the statistical results of experimental data for 28 nm to 3 nm process nodes. The measurement window length for the load change slope is set to four clock cycles.

[0029] The amplitude of the lead compensation pulse is the amount of temporary increase or decrease in the output voltage of the voltage regulator before a load transition. This amplitude and duration are calculated based on the load change slope and timing robustness quantization, and also depend on the difference between the current operating temperature and the nominal temperature of the integrated circuit. The nominal temperature is the junction temperature of the chip under typical operating conditions, usually taken as 25 degrees Celsius or 85 degrees Celsius. This value comes from the midpoint of the recommended operating temperature range in the device manual. The current operating temperature is obtained in real time through an on-chip thermistor or temperature sensor, with a measurement accuracy of ±1 degree Celsius.

[0030] When the current operating temperature is higher than the nominal temperature, the amplitude increases by an increment proportional to the difference. This proportionality coefficient is called the temperature compensation coefficient, and its value ranges from 0.5% to 2% per degree Celsius, with a typical value of 1% per degree Celsius. This value is derived from aging test data: it is obtained by statistically analyzing the additional voltage margin required for the same load transition at different temperatures and then performing linear fitting. For example, if the current operating temperature is 105 degrees Celsius and the nominal temperature is 85 degrees Celsius, the difference is 20 degrees Celsius. If the proportionality coefficient is 1%, then the amplitude increment is equal to 20% of the original amplitude. If the original amplitude is 50 millivolts, then after adding 10 millivolts, the new amplitude will be 60 millivolts.

[0031] The duration is extended by a factor proportional to the square of the temperature difference; this proportionality is called the temperature difference square factor, ranging from 0.01 microseconds to 0.1 microseconds per square degree Celsius, with a typical value of 0.05 microseconds per square degree Celsius. This value comes from transient response experiments at multiple temperature points: measuring the extra time required for voltage stabilization under different temperature differences, a linear relationship was found with the square of the temperature difference. Continuing the example, a temperature difference of 20 degrees Celsius squared is 400 degrees Celsius. Multiplying this by 0.05 microseconds per square degree Celsius gives 20 microseconds, meaning the duration is extended by 20 microseconds from the original value. If the original duration was 100 microseconds, the new duration would be 120 microseconds.

[0032] When the current operating temperature is lower than or equal to the nominal temperature, the aforementioned amplitude increment and duration extension operations are not performed; that is, the amplitude and duration remain unchanged from their original calculated values. For example, if the current operating temperature is 65 degrees Celsius, which is lower than 85 degrees Celsius, the compensation pulse parameters are not affected by temperature. This setting is based on the fact that transistor mobility increases at low temperatures, and timing margins are generally better than at room temperature, requiring no additional compensation.

[0033] When dynamically switching proportional-integral-derivative coefficients, a lookup table is pre-stored. The lookup table is indexed by the magnitude and rate of load change. Each set of indices corresponds to a set of pre-calibrated proportional coefficients, integral coefficients, and derivative coefficients. When the magnitude and rate of the current load change are detected to fall into a certain index range, the control parameters of the voltage regulator are immediately switched to that set of coefficients.

[0034] The training process for the lookup table is as follows: During the chip factory calibration phase or system power-on initialization, a series of standard load transition waveforms are applied to the integrated circuit. Each waveform has a specific load change amplitude and load change rate. The load change amplitude is defined as the absolute value of the difference between the load current and the target value as it transitions from the initial value to the target value, in amperes, and ranges from 0 amperes to the chip's maximum rated current, typically 100 amperes. The load change rate is defined as the load change amplitude divided by the transition time, in amperes per microsecond, and ranges from 1 ampere per microsecond to 1000 amperes per microsecond. The amplitude and rate are each divided into N intervals, with N ranging from 4 to 8. For example, the amplitude interval is 0 to 25 amps, 25 to 50 amps, 50 to 75 amps, and 75 to 100 amps, and the rate interval is 0 to 250 amps per microsecond, 250 to 500 amps per microsecond, 500 to 750 amps per microsecond, and 750 to 1000 amps per microsecond, thus forming a lookup table with 16 sets of 4x4 indexes.

[0035] For each index interval, the optimal proportional, integral, and derivative coefficients are obtained through experimental measurement. Specifically, a typical point is selected within the load change amplitude and rate range corresponding to that index, for example, the amplitude is taken as the midpoint of the interval (37.5 amps) and the rate as 125 amps per microsecond. Then, an automatic closed-loop optimization algorithm (such as the Ziegler-Nichols method or a genetic algorithm) is used to tune the proportional-integral-derivative coefficients, ensuring that the transient response overshoot of the voltage regulator is less than 5% and the settling time is less than 10 microseconds. The tuned proportional, integral, and derivative coefficients are stored in a set of pre-calibrated values ​​corresponding to that index. This training process is based on integrated circuit power management design manuals and simulation statistics for specific process nodes, with experimental data derived from the statistical average of at least 100 chip samples.

[0036] The real-time detection method for load change amplitude and rate is as follows: The transient current of the output inductor is continuously monitored through a current sampling circuit. The current change within each clock cycle is calculated, the changes are accumulated to obtain the amplitude, and the change is divided by the clock cycle to obtain the rate. The sampling clock frequency is synchronized with the chip's main frequency, typically 2 GHz. When the detected current load change amplitude and rate fall within a certain index range, the proportional, integral, and derivative coefficients of the voltage regulator are immediately switched to that set of pre-calibrated values. For example, if the detected load current jumps from 10 amps to 60 amps, with an amplitude of 50 amps, a jump time of 0.2 microseconds, and a rate of 250 amps per microsecond, and the amplitude falls within the 50-75 amp range and the rate falls within the 250-500 amps per microsecond range, then the index range is (amplitude range 3, rate range 2), and the corresponding set of proportional coefficients is 0.8, integral coefficient is 0.1, and derivative coefficient is 0.05. After the switching is complete, the voltage regulator operates under this set of parameters. The switching action is completed within the first clock cycle after the load transition is detected, with a delay of no more than 5 nanoseconds, which comes from the hardware lookup table read time.

[0037] The timing and number of forced idle commands are determined through the following steps: The system continuously samples the rate of change of current and the temperature gradient, calculating the instantaneous product of these two factors at each sampling moment. The rate of change of current is the change in current per unit time, measured in amperes per second, and is continuously measured by a current sampling circuit at a sampling frequency two to four times the chip's main frequency, typically 4 GHz. The temperature gradient is the change in temperature per unit time, measured in degrees Celsius per second, and is measured by an on-chip temperature sensor at the same sampling frequency as the rate of change of current. At each sampling moment, the instantaneous product of the rate of change of current and the temperature gradient is calculated. This product can be positive or negative; a positive value indicates that the current and temperature change in the same direction and increase power consumption, while a negative value indicates that they change in opposite directions or mitigate power consumption.

[0038] Arrange the instantaneous product values ​​over the most recent four sampling periods into a sequence. The sampling period length is equal to the reciprocal of the sampling frequency, typically 0.25 nanoseconds. For example, the instantaneous product values ​​over four sampling periods are [150, 180, 200, 170] in amperes per square second. Calculate the amplitude of the fundamental frequency component of the discrete Fourier transform of this sequence. The fundamental frequency corresponds to one-quarter of the sampling frequency (because four sampling points constitute a complete period). The amplitude is calculated by multiplying each of the four values ​​by the fundamental frequency cosine and sine coefficients, and then taking the square root of the sum of the squares. Specifically, take four sampling points x0, x1, x2, x3, and the amplitude of the fundamental frequency component is sqrt(((x0-x2) / 2)^2+((x1-x3) / 2)^2). Taking the above sequence as an example, (150-200) / 2=-25, (180-170) / 2=5, amplitude≈25.5. This amplitude reflects the intensity of the fundamental frequency oscillation component in the instantaneous product and is used to identify periodic positive feedback threats.

[0039] The moving average is the arithmetic mean of the instantaneous products over the most recent four sampling periods. Continuing with the previous example, the average is (150+180+200+170) / 4=175. When the moving average is greater than zero, the amplitude is divided by the moving average to obtain the ratio. In the previous example, the ratio is 25.5 / 175≈0.1457. The second threshold is preset to 0.8. This value comes from experimental data: statistically analyzing the ratio distribution of multiple chips during the positive feedback loop startup, it was found that a performance avalanche is inevitably triggered when the ratio exceeds 0.8. Therefore, 0.8 is taken as the critical point.

[0040] If the ratio exceeds the second threshold twice consecutively, a forced idle instruction for one clock cycle is inserted. For example, if the ratios for two consecutive sampling cycles are 0.82 and 0.85, a forced idle instruction for one clock cycle is inserted, during which the processor suspends the execution of valid instructions to reduce the rate of current change. If the ratio remains above the second threshold in the following two sampling cycles, for example, if the subsequent ratios are 0.83 and 0.81, a forced idle instruction for two more clock cycles is inserted to completely block the positive feedback loop. If the ratio is below or equal to the second threshold in the following two sampling cycles, no additional instructions are inserted.

[0041] When the moving average is less than or equal to zero, the ratio is not calculated, and no forced idle command is inserted. This is because a moving average of zero or negative indicates that the instantaneous product has no positive drive, and there is no risk of positive feedback. For example, if the four sampling points have values ​​of [-20, 10, -5, 5] and an average of -2.5, then the ratio is not calculated and no command is inserted. This processing is based on the fact that a large amount of experimental data shows that a non-positive moving average has never triggered a positive feedback chain reaction. The sampling period is set to 4 because, through analysis of the detection sensitivity and false alarm rate of sliding windows of different lengths, 4 periods at a 2 GHz main frequency correspond to a 2 nanosecond window, which can capture the characteristic frequency of the voltage-current-temperature positive feedback loop, and has the lowest hardware implementation cost.

[0042] The duration of the stretched clock high level is equal to the length of the entire time window during which the timing robustness quantization value is below a first threshold. The timing robustness quantization value is calculated in real-time using the method described above. The first threshold is a preset critical value, set based on the maximum allowed timing margin decay percentage in the chip's static timing analysis. A typical value range is 10% to 30% of the maximum possible range of the timing robustness quantization value. For example, if the maximum possible range of the timing robustness quantization value is -100 to +100, and the first threshold is set to -20, then timing begins when the quantization value drops from +10 to below -20 and stops when the quantization value rises back above -20. This time window length is the duration of the stretched clock high level. The unit of this time window length is nanoseconds or picoseconds, and the specific value depends on the load transition duration and the response speed of the positive feedback chain. In actual measurements, the window length is generally between 2 nanoseconds and 50 nanoseconds. The duration is measured using an on-chip high-precision counter with a clock frequency eight times the chip's main frequency, typically 16 gigahertz, and a counting error of less than one counting cycle.

[0043] Within this time window, the freeze signal for the data pipeline is determined by the sign of the difference between the timing margin and the voltage undershoot amplitude. Both the timing margin and the voltage undershoot amplitude are real-time measured values. The sign of the difference indicates whether it is positive, negative, or zero. When the difference is positive, it means the timing margin is greater than the voltage undershoot amplitude. In this case, only the clock high level is stretched without freezing the data pipeline. Stretching the clock high level is achieved by extending the duration of the system clock high level by a programmable step size through the clock control circuit. The typical step size is 50 picoseconds to 200 picoseconds. This step size comes from the experimentally calibrated optimal balance point between the timing path delay increment and the power consumption increase. For example, if the timing margin is 30 picoseconds, the voltage undershoot amplitude is 20 picoseconds, and the difference is positive 10 picoseconds, then only the clock high level is stretched by 80 picoseconds to ensure correct data capture, while the pipeline continues to execute subsequent instructions.

[0044] When the difference is negative, it indicates that the timing margin is less than the voltage undershoot. In this case, the data pipeline is frozen. Freezing the data pipeline means invalidating the enable signals of the registers at each stage of the pipeline, preventing new data from being written, and causing the current instruction to stall until timing recovery. For example, if the timing margin is 15 picoseconds, the voltage undershoot is 25 picoseconds, and the difference is -10 picoseconds, then in addition to stretching the clock high, a freeze signal is generated to latch the current pipeline state. The freeze time is equal to the duration of the stretched clock high level, i.e., the entire time window length. The freeze signal is generated by a dedicated timing monitoring unit, which outputs a high-level valid signal connected to the clock enable pins of the registers at each stage of the pipeline. During the freeze, the processor does not execute new instructions, reducing power consumption and thus helping to mitigate the voltage undershoot. When the time window ends, the stretched clock returns to normal, the freeze signal is removed, and the pipeline continues to operate. This operation is designed based on experimental data: the sign of the difference determines the severity of the timing violation; when the difference is negative, simply stretching the clock is insufficient to prevent metastability propagation, and the pipeline must be frozen to prevent erroneous data from entering the next stage.

[0045] An asynchronous level shifter circuit comprises a pair of back-to-back metal-oxide-semiconductor (MOSFETs) and a capacitor-isolated gate. A pair of back-to-back MOSFETs refers to two N-channel transistors or two P-channel transistors connected with their sources connected and their drains connected to the input and output terminals respectively, forming a bidirectional conduction path. This path is used to transmit digital signals between two voltage domains without generating DC current. The channel width to length ratio of the transistor is set according to the highest voltage difference between the two voltage domains, typically ranging from 0 volts to 1.8 volts. The channel width is typically 500 nanometers to 2 micrometers, and the length is typically 65 nanometers to 180 nanometers. These dimensions are derived from recommended values ​​in the design manuals for level shifters in the standard cell library.

[0046] A capacitive isolation barrier (CAPB) is a miniature capacitor integrated inside the chip or on the package substrate. Its capacitance ranges from 0.5 picofarads to 5 picofarads, with a typical value of 2 picofarads. This value is determined based on the signal frequency and the required common-mode rejection ratio (CMRR). The signal frequency range is 100 MHz to 2 GHz, and the required CMRR is greater than 40 dB. The two plates of the CAPB connect to the voltage domain of the compute-intensive core and the voltage domain of the surrounding logic, respectively. This allows AC signals (data transition edges) to be transmitted through capacitive coupling, while DC voltage components are blocked, thus achieving electrical isolation between the voltage domains. The two ground planes are independent, meaning the ground potential of the compute-intensive core and the ground potential of the surrounding logic are physically separated and not directly connected. They are each connected to different ground networks, achieving weak coupling only through the high-impedance path of the CAPB. The independent ground plane setup is based on electromagnetic compatibility (EMC) experimental data: when the ground plane isolation impedance is greater than 1 kΩ, the interference of transient current noise from one voltage domain to the ground potential of the other can be reduced by more than 30 dB. Typical isolation impedance ranges from 10 kΩ to 100 kΩ.

[0047] For example, the voltage domain of the compute-intensive core is 0.8 volts, and the voltage domain of the peripheral logic is 1.2 volts, with a DC resistance greater than 1 megohm between the two ground planes. When the core outputs a digital signal that jumps from 0 volts to 0.8 volts, this jump is coupled to the peripheral side through a capacitive isolation barrier. The receiving circuit on the peripheral side (containing a pair of back-to-back transistors) shapes the coupled voltage change into a signal of 0 volts to 1.2 volts. The back-to-back transistors prevent mis-conduction due to voltage differences between the two sides. When the level of either voltage domain is higher than the threshold voltage of the transistor on the other side, one of the transistors is turned off, blocking the DC path. The capacitor isolation barrier is designed to withstand at least twice the maximum voltage difference, with a typical withstand voltage of 3.3 volts, a value derived from integrated circuit reliability testing standards. The transmission delay of the entire asynchronous level conversion circuit is less than 1 nanosecond, which comes from capacitor charging time and transistor switching time, meeting the requirements for high-speed cross-domain signal communication.

[0048] The first and second thresholds employ an adaptive calibration method, which is performed once per calibration cycle. The calibration cycle is set to 1 to 10 milliseconds, with a typical value of 5 milliseconds. This cycle is derived from the typical change time constant of system load statistics, meaning that the number of load jump events within every 5 milliseconds is sufficient to be statistically significant. Within each calibration cycle, the number of times metastable propagation is successfully prevented and the number of times positive feedback loops are interrupted are counted.

[0049] Successful prevention of metastability propagation means that after stretching the clock or freezing the data pipeline, the output of the flip-flops in the downstream logic stabilizes to a valid logic level within one clock cycle after the clock edge, without any level instability or oscillation. This determination is achieved through an on-chip timing violation detection circuit, which samples the output level of the flip-flops after each clock edge. If the level stabilizes within 30% to 70% of the supply voltage before the next clock edge, it is considered a successful prevention. Positive feedback loop interruption means that after inserting a forced idle command, the product of the current change rate and the temperature gradient is lower than the last sampled value before the forced idle command was inserted in each of the following two sampling cycles. This determination is achieved through a comparator. For example, if the last sampled value before the forced idle command was 200, and the sampled values ​​in the following two sampling cycles are 150 and 130 respectively, then the interruption is considered successful; if any sampled value is greater than or equal to 200, the interruption is considered unsuccessful.

[0050] When the total number of times the timing robustness quantization value is below the first threshold is greater than zero, if the proportion of times metastable propagation is successfully prevented to the total number of times the timing robustness quantization value is below the first threshold is less than 95%, then the first threshold is lowered. For example, if the total number of times the timing robustness quantization value is below the first threshold in a calibration cycle is 100, and 93 of those times metastable propagation is successfully prevented (93%), which is less than 95%, then the first threshold is lowered. If the proportion is greater than or equal to 95%, then the first threshold remains unchanged. This 95% setting is based on the commonly used 5% error tolerance upper limit in industrial control, which allows a maximum failure rate of 5%, derived from empirical data in reliability engineering.

[0051] When the total number of times the product of the current change rate and temperature gradient exceeds the second threshold is greater than zero, if the proportion of the number of times the positive feedback loop is interrupted to the total number of times the product of the current change rate and temperature gradient exceeds the second threshold is less than 90%, then the second threshold is increased. For example, if the total number of times the product exceeds the second threshold in a calibration cycle is 50, and the number of times the positive feedback loop is successfully interrupted is 43, the proportion is 86%, which is less than 90%, then the operation of increasing the second threshold is performed. If the interruption success rate is greater than or equal to 90%, then the second threshold remains unchanged. This 90% setting is based on the system's allowable failure rate of 10%, because once positive feedback has a cascading effect, the tolerance is slightly lower than the metastable state of 5%. The new values ​​of the first and second thresholds after adjustment will take effect at the beginning of the next calibration cycle, and each calibration cycle is counted independently, with historical data not accumulated to avoid long-term drift. The design of this adaptive calibration method is based on simulation experiments running on a field-programmable gate array: statistical analysis of the system stability after threshold adjustment under 100 different load modes revealed that the above proportional thresholds can enable the system to converge to the optimal operating point within a finite number of cycles.

[0052] When the stable operating state of each voltage domain after decoupling and isolation is fed back to calibrate the first and second thresholds, the stable operating state includes the actual peak-to-peak value of voltage fluctuation, the minimum timing margin, and the longest load transient recovery time for each voltage domain. The actual peak-to-peak value of voltage fluctuation refers to the difference between the maximum and minimum values ​​of the power supply network voltage under stable operating conditions. It is obtained by continuously sampling for one calibration period (typically 5 milliseconds) using an on-chip analog-to-digital converter at a sampling frequency of 100 MHz. The peak-to-peak value is the maximum value minus the minimum value within the sampling window. The minimum timing margin refers to the minimum timing margin among all critical paths within the calibration period. This minimum value is measured and stored in real-time by an online timing margin sensing unit. The longest load transient recovery time refers to the maximum time elapsed from the start of a load transition until the voltage stabilizes to within 5% of the target value, measured in nanoseconds. It is obtained by monitoring the output voltage waveform of the voltage regulator.

[0053] The calibration employs proportional-integral (PI) regulation, where the first coefficient is the proportional gain and the second coefficient is the integral gain. The first coefficient is set based on the sensitivity to the deviation between the actual voltage fluctuation peak and the target value, typically ranging from 0.1 to 1.0, with an example value of 0.5. This value comes from the small-signal model analysis results of the voltage regulator's closed-loop control. The second coefficient is set based on the cumulative elimination rate of the minimum timing margin deviation, typically ranging from 0.01 to 0.1, with an example value of 0.05. This value comes from statistical tuning of 100 chip samples.

[0054] The preset target voltage fluctuation peak-to-peak value is set to 5% to 10% of the chip's nominal voltage, with a typical value of 0.05 volts. This value comes from the upper limit of ripple recommended in the power integrity design manual. The preset minimum timing margin target value is set to the minimum settling time margin required in the chip's timing library, with a typical value of 30 picoseconds. This value comes from the constraint report of the critical path by the static timing analysis tool.

[0055] When the minimum timing margin is greater than zero, the deviation between the actual peak-to-peak voltage fluctuation and the preset target peak-to-peak voltage fluctuation is multiplied by a first coefficient to obtain the first adjustment amount. For example, if the actual peak voltage fluctuation is 0.07 volts, the target value is 0.05 volts, and the deviation is 0.02 volts, multiplying by the first coefficient 0.5 yields a first adjustment amount of 0.01 volts. The deviation between the reciprocal of the minimum timing margin and the reciprocal of the preset minimum timing margin target value is multiplied by a second coefficient to obtain the second adjustment amount. For example, if the minimum timing margin is 40 picoseconds, the reciprocal is 0.025 picoseconds; if the target value is 30 picoseconds, the reciprocal is 0.0333 picoseconds, and the deviation is -0.0083 picoseconds, multiplying by the second coefficient 0.05 yields a second adjustment amount of -0.000415 picoseconds.

[0056] The first adjustment amount is superimposed on the first threshold, and the second adjustment amount is superimposed on the second threshold. Both the first and second thresholds are dimensionless numbers or voltage values. When superimposing them, the dimensions must be unified. In actual implementation, the unit of the first adjustment amount is converted to be the same as that of the first threshold. For example, if the first threshold is -20 millivolts, superimposing 0.01 volts results in -10 millivolts. The second threshold is dimensionless, and the second adjustment amount needs to be normalized before superposition. For example, if the second threshold is originally 0.8, superimposing -0.01 results in 0.79.

[0057] When the minimum timing margin is zero or negative, both the first and second adjustments are set to zero, while the first and second thresholds remain unchanged. This is because the timing is already in violation or at a critical point, and any adjustment could exacerbate instability; therefore, the current thresholds are kept constant. This operation is based on experimental data: adjusting the threshold when the timing margin is non-positive prolongs the recovery time, and performance degradation occurs in over 70% of the test samples. The entire proportional-integral adjustment is performed once at the end of each calibration cycle, and the new thresholds take effect at the beginning of the next calibration cycle.

[0058] Example 2: A dynamic voltage regulation and power consumption balance control system in an integrated circuit, comprising: The sensing quantization module is used to measure the timing margin, load change slope, and voltage undershoot magnitude of the critical path in the integrated circuit in real time, and calculate the current timing robustness quantization value based on the timing margin, load change slope, and voltage undershoot magnitude. The feedforward compensation module is used to calculate the amplitude and duration of the lead compensation pulse based on the load change slope and timing robustness quantization value, and send the lead compensation pulse to the voltage regulator before the load jumps or at the synchronization moment. The gain adjustment module is used to dynamically switch the proportional-integral-derivative coefficients of the voltage regulator according to the amplitude and rate of load change after sending the lead compensation pulse, so as to suppress the nonlinear oscillation of the voltage regulator at the boundary between discontinuous conduction mode and continuous conduction mode. The protection and blocking module is used to stretch the clock high level or freeze the data pipeline to prevent metastability from propagating to downstream logic when the timing robustness quantization value is lower than the preset first threshold after dynamically switching the proportional-integral-derivative coefficients. It also monitors the current change rate and temperature gradient. When the product of the current change rate and temperature gradient exceeds the preset second threshold, it inserts a forced idle instruction for one or more clock cycles to cut off the positive feedback loop between voltage-current-temperature-voltage. The isolation calibration module is used to configure the computationally intensive core and peripheral logic in independent voltage domains. It uses asynchronous level conversion circuits and capacitor isolation barriers to electrically decouple and isolate each voltage domain, and feeds back the stable operating state of each decoupled and isolated voltage domain for calibration of the first and second thresholds.

[0059] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0060] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0061] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0062] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0063] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for dynamic voltage regulation and power consumption balance control in integrated circuits, characterized in that, Includes the following steps: The timing margin, load change slope, and voltage undershoot magnitude of the critical path in the integrated circuit are measured in real time, and the current timing robustness quantization value is calculated based on the timing margin, load change slope, and voltage undershoot magnitude. Based on the load change slope and timing robustness quantization value, the amplitude and duration of the lead compensation pulse are calculated, and the lead compensation pulse is sent to the voltage regulator before the load jumps or at the synchronization moment. After sending the lead compensation pulse, the proportional-integral-derivative coefficients of the voltage regulator are dynamically switched according to the amplitude and rate of load change in order to suppress the nonlinear oscillation of the voltage regulator at the boundary between discontinuous conduction mode and continuous conduction mode. After dynamically switching the proportional-integral-derivative coefficients, when the timing robustness quantization value is lower than the preset first threshold, the clock is stretched to high level or the data pipeline is frozen to prevent metastability from propagating to downstream logic; then the current change rate and temperature gradient are monitored, and when the product of the current change rate and temperature gradient exceeds the preset second threshold, a forced idle instruction for one or more clock cycles is inserted to cut off the positive feedback loop between voltage-current-temperature-voltage. The computationally intensive core and peripheral logic are configured in independent voltage domains. The voltage domains are electrically decoupled and isolated by asynchronous level conversion circuits and capacitor isolation barriers. The stable operating state of each decoupled and isolated voltage domain is fed back to calibrate the first and second thresholds.

2. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 1, characterized in that, The current time series robustness quantification value is calculated through the following steps: When the timing margin is greater than zero, the product value is obtained by multiplying the timing margin by the absolute value of the load change slope. The quotient is obtained by squaring the voltage undershoot amplitude and dividing it by the ratio of the timing margin to a preset fixed reference voltage. Determine if the sum of the product and the quotient is greater than zero: If the value is greater than zero, the product value is added to the quotient value and the natural logarithm is taken. Then, the product is multiplied by the product of the absolute value of the load change slope and the absolute value of the voltage undershoot amplitude to obtain the intermediate value. Then, the intermediate value is multiplied by the sign value of the load change slope. The sign value is positive one when the load change slope is positive, negative one when the load change slope is negative, and zero when the load change slope is zero to obtain the current timing robustness quantization value. If it equals zero, then set the current time series robustness quantization value to zero; When the timing margin is zero or negative, the absolute value of the voltage undershoot amplitude is multiplied by the absolute value of the load change slope, and then added to the absolute value of the timing margin to obtain a temporary value. Divide the temporary value by the preset fixed reference voltage, and then multiply it by the square root of the product of the absolute value of the load change slope and the absolute value of the voltage undershoot amplitude to obtain the current timing robustness quantization value.

3. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 1, characterized in that, The amplitude and duration of the lead compensation pulse also depend on the difference between the current operating temperature and the nominal temperature of the integrated circuit: When the current operating temperature is higher than the nominal temperature, the amplitude increases by an increment proportional to the difference, and the duration is extended by a duration proportional to the square of the difference.

4. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 1, characterized in that, When dynamically switching proportional-integral-derivative coefficients, a lookup table is pre-stored. The lookup table is indexed by the magnitude and rate of load change. Each set of indices corresponds to a set of pre-calibrated proportional coefficients, integral coefficients, and derivative coefficients. When the magnitude and rate of the current load change are detected to fall into a certain index range, the control parameters of the voltage regulator are immediately switched to that set of coefficients.

5. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 1, characterized in that, The timing and number of forced idle commands are determined through the following steps: Continuously sample the rate of change of current and the temperature gradient, and calculate the instantaneous product of the rate of change of current and the temperature gradient at each sampling moment; Arrange the values ​​of the instantaneous product over the most recent four sampling periods into a sequence, and calculate the amplitude of the discrete Fourier transform fundamental frequency component of the sequence. When the moving average is greater than zero, the amplitude is divided by the moving average of the instantaneous product. The moving average is the arithmetic mean of the instantaneous products in the most recent four sampling periods to obtain the ratio. When the ratio exceeds the second threshold twice in a row, a forced idle instruction for one clock cycle is inserted. If the ratio is still higher than the second threshold in the following two sampling periods, a forced idle instruction for two more clock cycles is inserted. When the moving average is less than or equal to zero, the ratio is not calculated and no forced idle command is inserted.

6. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 1, characterized in that, The duration of the high-level clock stretch is equal to the length of the entire time window during which the timing robustness quantization value is below the first threshold. Within this time window, the freeze signal of the data pipeline is determined by the sign of the difference between the timing margin and the voltage undershoot amplitude. When the difference is positive, only the clock is stretched; when the difference is negative, the data pipeline is frozen simultaneously.

7. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 1, characterized in that, The asynchronous level shifting circuit includes a pair of back-to-back metal-oxide-semiconductor field-effect transistors and a capacitor isolation gate. The two sides of the capacitor isolation gate are connected to the voltage domain of the computationally intensive core and the voltage domain of the peripheral logic, respectively, and the ground planes on both sides are independent of each other.

8. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 1, characterized in that, The first and second thresholds are calibrated using an adaptive method. Within each calibration cycle, the number of times metastability propagation was successfully prevented and the number of times positive feedback loops were interrupted are counted. Successful prevention of metastability propagation means that after stretching the clock or freezing the data pipeline, the flip-flop output of the downstream logic stabilizes to a valid logic level within one clock cycle after the clock edge, without level indeterminacy or oscillation. Interruption of positive feedback loops means that after inserting a forced idle instruction, the product of the current rate of change and the temperature gradient is lower than the last sampled value before the forced idle instruction was inserted in each of the following two sampling cycles. If the total number of times the time-order robustness quantization value is below the first threshold is greater than zero, and the proportion of the number of times metastable propagation is successfully prevented to the total number of times the time-order robustness quantization value is below the first threshold is less than 95%, then the first threshold is lowered. If the total number of times the product of the current change rate and the temperature gradient exceeds the second threshold is greater than zero, and the proportion of the number of times the positive feedback loop is cut off to the total number of times the product of the current change rate and the temperature gradient exceeds the second threshold is less than 90%, then the second threshold is raised.

9. The dynamic voltage regulation and power consumption balance control method in an integrated circuit according to claim 8, characterized in that, When the stable operating states of each voltage domain after decoupling and isolation are fed back to calibrate the first and second thresholds, the stable operating states include the actual peak-to-peak voltage fluctuations, minimum timing margin, and longest load transient recovery time of each voltage domain. The calibration uses proportional-integral regulation. When the minimum timing margin is greater than zero, the deviation between the actual peak-to-peak value of the voltage fluctuation and the preset target peak-to-peak value of the voltage fluctuation is multiplied by a first coefficient to obtain a first adjustment amount. The deviation between the reciprocal of the minimum timing margin and the reciprocal of the preset minimum timing margin target value is multiplied by a second coefficient to obtain a second adjustment amount. The first adjustment amount is added to the first threshold, and the second adjustment amount is added to the second threshold. When the minimum time margin is equal to zero or the minimum time margin is negative, both the first adjustment and the second adjustment are set to zero, while the first threshold and the second threshold remain unchanged.

10. A dynamic voltage regulation and power consumption balance control system in an integrated circuit, used to implement the dynamic voltage regulation and power consumption balance control method in an integrated circuit as described in any one of claims 1-9.

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