Virtual interrupt mapping method and apparatus

Abstract

The application relates to the computer technical field and provides a virtual interrupt mapping method and device. The method comprises the following steps: receiving and extracting a target physical interrupt source identifier according to a physical interrupt request of an external device; performing hardware mapping retrieval according to the target physical interrupt source identifier to obtain a target virtual machine identifier, a target virtual processor identifier and a target virtual interrupt number corresponding to the target virtual processor identifier; performing address offset calculation according to the target virtual machine identifier and the target virtual processor identifier to obtain a physical address of a target virtual machine interrupt file; and writing the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file. Based on the application scheme, the fast mapping of a physical interrupt to a virtual interrupt is realized without the intervention of a virtualization management program, so that the interrupt processing time delay and system overhead in the virtualization environment are effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a virtual interrupt mapping method and apparatus. Background Technology

[0002] With the development of virtualization technology, the RISC-V architecture has been widely used in servers and embedded systems. In the RISC-V architecture, the Advanced Interrupt Architecture (AIA) provides the processor core and virtual machine with the corresponding virtual machine interrupt file through the Interrupt Message Signal Controller (IMSIC) to support message-based interrupt delivery.

[0003] In a virtualized environment, interrupts generated by physical external devices need to be forwarded to the corresponding virtual machines for processing, a process involving virtual interrupt mapping. However, in relevant implementations, the mapping logic between physical device interrupt sources and virtual machine interrupt files is typically maintained and resolved at the software level by the hypervisor. This software-dependent mechanism inevitably increases the intermediate steps in interrupt handling, resulting in a longer interrupt handling path. A longer interrupt handling path not only increases the system's interrupt response latency but also generates higher system overhead during frequent interrupt forwarding, thus affecting the overall operating efficiency of the virtualized system.

[0004] Therefore, how to reduce interrupt handling latency and system overhead in a virtualized environment has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a virtual interrupt mapping method and apparatus to solve the technical problem of how to reduce interrupt processing latency and system overhead in a virtualized environment.

[0006] In a first aspect, embodiments of this application provide a virtual interrupt mapping method, including: Receive physical interrupt requests from external devices and extract the target physical interrupt source identifier based on the physical interrupt request; Hardware mapping retrieval is performed based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier; The physical address of the target virtual machine interrupt file corresponding to the target virtual processor is obtained by calculating the address offset based on the target virtual machine identifier and the target virtual processor identifier. Write the target virtual interrupt number into the target virtual machine interrupt file based on the physical address of the target virtual machine interrupt file; The hardware mapping retrieval, the address offset calculation, and the process of writing the target virtual interrupt number into the target virtual machine interrupt file are all completed by hardware logic and do not require entering the virtualization management program.

[0007] In conjunction with the first aspect, in some possible implementations, hardware mapping retrieval is performed based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier, including: Hardware mapping retrieval is performed based on the target physical interrupt source identifier and a preset multi-level index table structure to obtain the retrieval results; If the search results indicate a match in the target mapping table, extract the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier from the target mapping table.

[0008] Combining the first aspect and the above implementation methods, in some possible implementation methods, hardware mapping retrieval is performed based on the target physical interrupt source identifier and a preset multi-level index table structure to obtain retrieval results, including: Based on the target physical interrupt source identifier, the base address of the second-level virtual interrupt location table is obtained by searching through the first-level device index table in the preset multi-level index table structure. Based on the base address of the secondary virtual interrupt location table, the search is performed through the secondary virtual interrupt location table in the multi-level index table structure to obtain the search results.

[0009] Combining the first aspect and the above implementation methods, in some possible implementation methods, after performing hardware mapping retrieval based on the target physical interrupt source identifier and a preset multi-level index table structure to obtain the retrieval results, the virtual interrupt mapping method further includes: If the search results indicate that the target mapping table entry was not matched, an interrupt mapping exception signal is sent to the virtualization hypervisor, and the physical interrupt request is forwarded to the virtualization hypervisor so that the virtualization hypervisor can perform software parsing and virtual interrupt injection on the physical interrupt request based on the interrupt mapping exception signal.

[0010] In combination with the first aspect and the above implementation methods, in some possible implementation methods, the virtual interrupt mapping method also includes: During the initialization phase or device pass-through configuration phase, the mapping relationship between physical interrupt source identifier, virtual machine identifier, virtual processor identifier, and virtual interrupt number is configured in the multi-level index table structure required by the virtualization management program for the process of mapping and retrieving to hardware.

[0011] Combining the first aspect and the above implementation methods, in some possible implementation methods, address offset calculation is performed based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine, including: Determine the virtual machine address offset based on the target virtual machine identifier and the preset virtual machine address step size; Determine the virtual processor address offset based on the target virtual processor identifier and the preset virtual processor address step size; The physical address of the target virtual machine interrupt file corresponding to the target virtual processor is obtained by calculating the address offset based on the virtual machine address offset, the virtual processor address offset, and the preset interrupt message signal controller base address. The address offset calculation is based on hardware logic and does not rely on the address translation process involving the operating system or virtualization management program.

[0012] Combining the first aspect and the above implementation methods, in some possible implementation methods, the target virtual interrupt number is written into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file, including: Based on the physical address of the target virtual machine interrupt file, initiate a write bus transaction in an atomic write manner; The target virtual interrupt number is used as the data payload of the write bus transaction and written to the target virtual machine interrupt file.

[0013] Combining the first aspect and the above implementation methods, in some possible implementation methods, after writing the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file, the method further includes: Trigger an interrupt request signal to be sent to the target virtual processor, so that the target virtual processor responds to the interrupt and enters the interrupt handling process of the virtual machine operating system.

[0014] Secondly, embodiments of this application provide a virtual interrupt mapping device, comprising: The interrupt source identification module is used to receive physical interrupt requests from external devices and extract the target physical interrupt source identifier based on the physical interrupt request; The hardware mapping controller is used to perform hardware mapping retrieval based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier; The address offset calculation module is used to calculate the address offset based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine. The hardware writing module is used to write the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file; The hardware mapping retrieval, the address offset calculation, and the process of writing the target virtual interrupt number into the target virtual machine interrupt file are all completed by hardware logic and do not require entering the virtualization management program.

[0015] In conjunction with the second aspect, in some possible implementations, the virtual interrupt mapping device also includes a mapping table configuration module; The mapping table configuration module is used to configure the multi-level index table structure required for the hardware mapping retrieval process.

[0016] The virtual interrupt mapping method and apparatus provided in this application, upon receiving a physical interrupt request from an external device, directly obtains the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number through hardware mapping retrieval. Based on hardware logic, it calculates the physical address of the target virtual machine interrupt file and then directly writes the target virtual interrupt number to the target virtual machine interrupt file, achieving hardware pass-through mapping and delivery from physical interrupt to virtual interrupt. Compared to related technologies where interrupt resolution, mapping lookup, and virtual interrupt injection are performed by the virtualization management program, this application's embodiments push the mapping retrieval, address calculation, and interrupt writing process down to the hardware path. This reduces the additional overhead caused by virtual machine exit (VMExit), software table lookup, and context switching, thereby reducing interrupt handling latency in the virtualization environment, improving the determinism of interrupt handling and system throughput, and enhancing the system's scalability in high-concurrency interrupt scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the virtual interrupt mapping method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the overall process of virtual interrupt mapping provided in the embodiments of this application; Figure 3 This is a schematic diagram of the overall system structure for virtual interrupt mapping provided in the embodiments of this application; Figure 4 This is a schematic diagram of the internal structure of the interrupt redirection mapping engine provided in an embodiment of this application; Figure 5This is a schematic diagram of the virtual interrupt write timing provided in an embodiment of this application; Figure 6 This is a schematic diagram of a virtual interrupt mapping device provided in an embodiment of this application; Figure 7 This is another schematic diagram of the virtual interrupt mapping device provided in the embodiments of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] Explanation of some terms used in the embodiments of this application: Advanced Interrupt Architecture (AIA); Interrupt Message Signal Controller (IMSIC); Message Signal Interrupt (MSI); Virtual Machine (VM); Hypervisor; Virtual CPU (vCPU); Virtual Machine Identifier (VMID); Virtual CPU Identifier (vCPU ID); Virtual Interrupt Identifier (vINT ID); Physical Address (PA); Interrupt Service Routine (ISR); Device Identification (Device ID); Message Signal Interrupt Address (MSI Address); Virtual Machine Exit (VM Exit).

[0021] With the development of virtualization technology, the RISC-V architecture has been widely used in server and embedded systems. In the RISC-V architecture, the Advanced Interrupt Architecture (AIA) provides independent interrupt files for the processor core and virtual machines through the Interrupt Message Signal Controller (IMSIC) to support message-based interrupt delivery. In a virtualized environment, interrupts generated by physical external devices need to be forwarded to the corresponding virtual machine for processing; this process involves virtual interrupt mapping.

[0022] For example, in some related technologies, when a physical external device generates an interrupt, the virtualization management program obtains the interrupt and determines the virtual machine to which the interrupt belongs and the independent interrupt file corresponding to the virtual machine through a mapping relationship maintained by the software; the virtualization management program converts the interrupt number corresponding to the interrupt to obtain a virtual interrupt number and writes the virtual interrupt number into the independent interrupt file to complete the virtual interrupt mapping.

[0023] It is evident that the aforementioned technologies have shortcomings: during the virtual interrupt mapping process, the virtualization management program is relied upon to perform operations such as software-maintained mapping relationship lookup, interrupt number conversion, and writing to a separate interrupt file, resulting in a long interrupt handling path, which in turn increases interrupt handling latency and system overhead in the virtualization environment.

[0024] Therefore, how to reduce interrupt handling latency and system overhead in a virtualized environment has become an urgent problem to be solved.

[0025] To address the aforementioned issues, the solution provided in this application mainly includes: upon receiving a physical interrupt request from an external device, extracting the target physical interrupt source identifier based on the physical interrupt request; then performing a hardware mapping retrieval based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier; next, calculating the address offset based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine; and finally, writing the target virtual interrupt number into the target virtual machine interrupt file based on the physical address of the target virtual machine interrupt file. Through the above process, upon receiving a physical interrupt request from an external device, the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number are directly obtained through hardware mapping retrieval, and the physical address of the target virtual machine interrupt file is calculated based on hardware logic. Subsequently, the target virtual interrupt number is directly written into the target virtual machine interrupt file, realizing hardware pass-through mapping and delivery from physical interrupt to virtual interrupt. Compared to related technologies where interrupt resolution, mapping lookup, and virtual interrupt injection are performed by the virtualization management program, the embodiments of this application push the mapping retrieval, address calculation, and interrupt writing processes down to the hardware path. This reduces the additional overhead caused by virtual machine exit, software table lookup, and context switching, thereby reducing interrupt handling latency in the virtualization environment, improving the determinism of interrupt handling and system throughput, and enhancing the scalability of the system in high-concurrency interrupt scenarios.

[0026] The virtual interrupt mapping method provided in the embodiments of this application will be described in detail below.

[0027] Please see Figure 1 , Figure 1 This is a flowchart illustrating a virtual interrupt mapping method provided in an embodiment of this application. Figure 1 As shown, the method in this application embodiment may include the following steps S101~S104: S101, Receive a physical interrupt request from an external device, and extract the target physical interrupt source identifier based on the physical interrupt request; S102, perform hardware mapping retrieval based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier; S103, calculate the address offset based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine; S104. Write the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file.

[0028] The processes of hardware mapping retrieval, address offset calculation, and writing the target virtual interrupt number into the target virtual machine interrupt file are all completed by hardware logic and do not require entering the virtualization management program.

[0029] Specifically, considering that relying on virtualization management programs for software-level interrupt mapping and injection in related technologies can lead to long interrupt handling paths and high system overhead, this embodiment proposes a virtual interrupt mapping method based on hardware mapping retrieval. By completing the rapid location and writing of the interrupt source to the virtual machine interrupt file at the hardware level, the additional processing steps brought about by software intervention are avoided.

[0030] First, it is necessary to receive physical interrupt requests from external devices and extract the target physical interrupt source identifier based on the physical interrupt request. Here, "external device" refers to a physical hardware device connected to the computing system and sending interrupt signals to the computing system; "physical interrupt request" refers to an interrupt request message signal sent by the external device via the bus to indicate that an interrupt event has occurred; and "target physical interrupt source identifier" refers to the identification information used to uniquely identify the external device that initiated the physical interrupt request.

[0031] Regarding this step, in some possible implementations, a physical interrupt request from an external device can be received by listening to bus write transactions, and the target physical interrupt source identifier can be parsed from the physical interrupt request. The target physical interrupt source identifier can be determined based on the address information, data information, and / or device identification information in the physical interrupt request. Alternatively, field extraction processing can be performed on the received physical interrupt request from the external device to extract the target physical interrupt source identifier based on the physical interrupt request.

[0032] Further, a hardware mapping retrieval is performed based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier. Here, hardware mapping retrieval refers to the process of using a pre-configured hardware mapping structure to find and output the corresponding virtual machine parameters based on the input identifier information. This hardware mapping retrieval process is executed by hardware logic and does not require entering the virtualization management program. The target virtual machine refers to the virtual machine that needs to receive the interrupt corresponding to the physical interrupt request. The target virtual machine identifier is a number used to uniquely identify the target virtual machine at the hardware level. The target virtual processor in the target virtual machine refers to the processor core within the target virtual machine assigned to handle the interrupt. The target virtual processor identifier is a number used to uniquely identify the target virtual processor within the target virtual machine. The target virtual interrupt number corresponding to the target virtual processor identifier is the converted interrupt number that the target virtual machine operating system can recognize.

[0033] Regarding this step, in some possible implementations, the target physical interrupt source identifier can be used as a retrieval index for hardware mapping retrieval to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier. Alternatively, relevant matching operations can be performed on the target physical interrupt source identifier for hardware mapping retrieval, thereby directly obtaining the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier.

[0034] Further, address offset calculations are performed based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor within the target virtual machine. Address offset calculation refers to the process of determining the physical address of the target storage location through hardware logic operations based on the identifier information and preset address step parameters. This address offset calculation process is completed by hardware logic and does not require entering the virtualization management program. The target virtual machine interrupt file corresponding to the target virtual processor refers to the register file independently allocated for receiving virtual interrupt messages in the interrupt message signal controller for that target virtual processor. The physical address of the target virtual machine interrupt file refers to the actual access address of the target virtual machine interrupt file in the system's physical memory mapped input / output space.

[0035] Regarding this step, in some possible implementations, mathematical operations can be performed based on the target virtual machine identifier and the target virtual processor identifier to calculate the address offset, thereby obtaining the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine. Alternatively, the target virtual machine identifier and the target virtual processor identifier can be input into a preset address calculation logic to calculate the address offset, thus obtaining the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine.

[0036] Furthermore, based on the physical address of the target virtual machine interrupt file, the target virtual interrupt number is written into the target virtual machine interrupt file (i.e., interrupt delivery is completed).

[0037] Regarding this step, in some possible implementations, a write transaction can be initiated based on the physical address of the target virtual machine interrupt file to write the target virtual interrupt number into the target virtual machine interrupt file. Alternatively, a data write operation can be performed using the physical address of the target virtual machine interrupt file to write the target virtual interrupt number into the target virtual machine interrupt file. It should be noted that the process of writing the target virtual interrupt number into the target virtual machine interrupt file is completed by hardware logic and does not require entering the virtualization management program.

[0038] In this embodiment, upon receiving a physical interrupt request from an external device, the target physical interrupt source identifier is extracted based on the request. Then, a hardware mapping retrieval is performed based on this identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the corresponding target virtual interrupt number. Next, address offset calculations are performed based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor within the target virtual machine. Finally, the target virtual interrupt number is written to the target virtual machine interrupt file based on its physical address. Through this process, by using hardware mapping retrieval to obtain the target virtual machine identifier, target virtual processor identifier, and target virtual interrupt number, and combining this with address offset calculations to obtain the physical address of the target virtual machine interrupt file for writing, the entire processing chain is executed continuously at the hardware level. This avoids the additional processing steps introduced by software intervention, thereby reducing interrupt handling latency and system overhead in a virtualized environment, and improving the determinism and scalability of the system in high-concurrency interrupt scenarios.

[0039] In one embodiment, the step of "performing hardware mapping retrieval based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier" can be further refined and may include the following steps: Hardware mapping retrieval is performed based on the target physical interrupt source identifier and a preset multi-level index table structure to obtain the retrieval results; If the search results indicate a match in the target mapping table, extract the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier from the target mapping table.

[0040] Specifically, considering that a single mapping table structure has problems such as low search efficiency or excessive hardware resource overhead when storing large-scale mapping relationships, this embodiment proposes a hardware mapping retrieval scheme based on a multi-level index table structure. By using a hierarchical search method, the retrieval speed and storage overhead are balanced to achieve mapping relationship location.

[0041] First, a hardware mapping retrieval is performed based on the target physical interrupt source identifier and a pre-defined multi-level index table structure to obtain the retrieval results. The multi-level index table structure refers to a hardware data structure used to store the association between device interrupt sources and virtual machine target information, containing at least two levels of table structures for indexing and location. The retrieval results include at least a hit flag and the content of the target mapping table entry corresponding to the hit flag, or its index information. This result indicates whether a corresponding mapping relationship was successfully matched and the specific mapping content matched.

[0042] Regarding this step, in some possible implementations, the target physical interrupt source identifier can be used as an index input to a preset multi-level index table structure for hardware lookup. This multi-level index table structure performs a step-by-step matching based on the index input and outputs the search results as successful or unsuccessful.

[0043] Furthermore, if the search results indicate a match in the target mapping table, the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier are extracted from the target mapping table. Here, a match in the target mapping table means that the search results indicate that a valid entry corresponding to the target physical interrupt source identifier has been found in the multi-level index table structure; a target mapping table entry refers to a specific entry in the multi-level index table structure used to record a complete mapping relationship, which stores the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier.

[0044] Regarding this step, in some possible implementations, when the search result indicates a hit, the content of the target mapping table entry is read from the storage medium of the multi-level index table structure according to the address or index of the target mapping table entry contained in the search result, and the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier are parsed from it.

[0045] In this embodiment, a pre-defined multi-level index table structure is used for hardware mapping retrieval. The mapping relationships are stored in a distributed manner, and hierarchical search logic is used to locate the target mapping table entry at the hardware level. When the search result indicates that the target mapping table entry has been matched, the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier are directly extracted from the target mapping table entry. This avoids the memory access and context switching overhead in the software table lookup process, shortens the latency of hardware mapping retrieval, and improves the real-time performance of virtual interrupt mapping.

[0046] In one embodiment, the step of "performing hardware mapping retrieval based on the target physical interrupt source identifier and a preset multi-level index table structure to obtain retrieval results" can be further refined and may include the following steps: Based on the target physical interrupt source identifier, the base address of the second-level virtual interrupt location table is obtained by searching through the first-level device index table in the preset multi-level index table structure. Based on the base address of the secondary virtual interrupt location table, the search is performed through the secondary virtual interrupt location table in the multi-level index table structure to obtain the search results.

[0047] Specifically, considering that directly searching massive mapping data through a single-level table would lead to a waste of hardware resources or an increase in search latency, this embodiment proposes a hierarchical retrieval mechanism that uses a first-level device index table and a second-level virtual interrupt location table to locate the mapping relationship.

[0048] The multi-level index table structure in this embodiment refers to a hardware storage structure used to store the mapping relationship between physical interrupt sources and virtual machine target parameters. The multi-level index table structure includes a first-level device index table and a second-level virtual interrupt location table. The first-level device index table is an index table used to store the correspondence between physical interrupt source identifiers (device identifiers) and the base addresses of the second-level table. The second-level virtual interrupt location table is a mapping table used to store specific virtual machine identifiers, virtual processor identifiers, and virtual interrupt numbers.

[0049] First, based on the target physical interrupt source identifier, the base address of the secondary virtual interrupt location table needs to be obtained by searching the primary device index table in the preset multi-level index table structure. The base address of the secondary virtual interrupt location table refers to the starting physical address of the secondary virtual interrupt location table in the hardware storage unit.

[0050] Regarding this step, in some possible implementations, the target physical interrupt source identifier can be used as the index input of the primary device index table, the corresponding entry can be found in the primary device index table, and the address information stored in the entry can be used as the base address of the secondary virtual interrupt location table.

[0051] Furthermore, based on the base address of the secondary virtual interrupt location table, the search is performed through the secondary virtual interrupt location table in the multi-level index table structure to obtain the search results.

[0052] Regarding this step, in some possible implementations, the starting position of the secondary virtual interrupt location table can be located based on the base address of the secondary virtual interrupt location table. Then, a partial bit field of the target physical interrupt source identifier or a preset offset can be used as an index to search in the secondary virtual interrupt location table, thereby obtaining a search result containing the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier.

[0053] In this embodiment, a hierarchical search mechanism is implemented by first retrieving the base address of the secondary virtual interrupt location table from the primary device index table based on the target physical interrupt source identifier, and then retrieving the search result from the secondary virtual interrupt location table based on this base address. This mechanism disperses the storage of mapping relationships, reduces the amount of data comparison in a single search, lowers the complexity and resource overhead of hardware implementation, and ensures the determinism from the target physical interrupt source identifier to the retrieval result.

[0054] In one embodiment, after the above step "perform hardware mapping retrieval based on the target physical interrupt source identifier to obtain retrieval results", the following steps may also be included: If the search results indicate that the target mapping table entry was not matched, an interrupt mapping exception signal is sent to the virtualization hypervisor, and the physical interrupt request is forwarded to the virtualization hypervisor so that the virtualization hypervisor can perform software parsing and virtual interrupt injection on the physical interrupt request based on the interrupt mapping exception signal.

[0055] Specifically, considering that hardware mapping retrieval may fail due to the mapping relationship not being pre-configured or the configuration being invalid, this embodiment proposes a safe rollback mechanism after hardware fast mapping failure. By transferring the interrupt handling right back to the virtualization management program, the interrupt request is ensured to be processed, thereby guaranteeing the robustness of the system.

[0056] First, if the search results indicate that the target mapping entry was not found, an interrupt mapping exception signal needs to be sent to the hypervisor, and the physical interrupt request needs to be forwarded to the hypervisor. The hypervisor then performs software parsing and virtual interrupt injection based on the interrupt mapping exception signal. Here, "target mapping entry not found" means that the hardware mapping controller has not found a valid mapping entry corresponding to the target physical interrupt source identifier in the multi-level index table structure; the hypervisor is the system software responsible for creating, managing, and scheduling virtual machines; the interrupt mapping exception signal is a specific signal generated by the hardware mapping controller to notify the hypervisor that the current interrupt request cannot be processed through the hardware fast path; software parsing and virtual interrupt injection refer to the process by which the hypervisor executes software instructions to parse the source and attributes of the physical interrupt request and forwards the interrupt to the target virtual machine according to the virtualization process.

[0057] Regarding this step, in some possible implementations, the hardware mapping controller can generate a specific interrupt mapping exception signal when it detects a miss result. This signal directly triggers the execution of the virtualization management program through a preset hardware interrupt channel. At the same time, the hardware mapping controller temporarily stores the original physical interrupt request (including the target physical interrupt source identifier and related data) in a designated hardware register or memory buffer. After responding to the interrupt mapping exception signal, the virtualization management program reads the physical interrupt request and determines the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier based on its internally maintained software mapping table. Finally, the interrupt is injected into the target virtual machine through software.

[0058] In this embodiment, by sending an interrupt mapping exception signal to the virtualization management program and reverting to the software processing flow when the search results indicate that the target mapping entry has not been matched, a fallback guarantee is provided for the hardware fast mapping mechanism. This approach ensures that even in scenarios where hardware mapping relationships are missing or misconfigured, physical interrupt requests can still be correctly captured by the virtualization management program and software parsing and virtual interrupt injection can be performed, avoiding interrupt loss. Thus, while ensuring system robustness and compatibility, it also enables the handling of unexpected interrupt events.

[0059] In one embodiment, the virtual interrupt mapping method of this application may further include the following steps: During the initialization phase or device pass-through configuration phase, the mapping relationship between physical interrupt source identifier, virtual machine identifier, virtual processor identifier, and virtual interrupt number is configured in the multi-level index table structure required by the virtualization management program for the process of mapping and retrieving to hardware.

[0060] Specifically, considering that the hardware mapping controller needs to rely on the pre-established mapping relationship to perform subsequent fast retrieval and write operations, this embodiment proposes a pre-configuration mechanism for the mapping relationship. By having the virtualization management program complete the writing of the mapping relationship at a specific stage, the necessary data foundation for the hardware fast path is provided.

[0061] First, during the initialization or device pass-through configuration phase, the mapping relationship between physical interrupt source identifiers, virtual machine identifiers, virtual processor identifiers, and virtual interrupt numbers needs to be configured in the multi-level index table structure required for the process of retrieving hardware mappings through the virtualization management program. The initialization phase refers to the phase where virtual interrupt mapping rules are initially set when a virtual machine is created or the system starts. The device pass-through configuration phase refers to the phase where the association between interrupts of an external device and the virtual machine is configured when an external device is directly assigned to a specific virtual machine. The mapping relationship between physical interrupt source identifiers, virtual machine identifiers, virtual processor identifiers, and virtual interrupt numbers refers to the corresponding rules used to uniquely associate a physical interrupt source with a specific virtual interrupt number on a specific virtual processor within a virtual machine.

[0062] It is understandable that the multi-level index table structure includes a first-level device index table and a second-level virtual interrupt location table. The mapping relationship is specifically stored and indexed collaboratively through these two tables. The first-level device index table stores the first-level index relationship between physical interrupt source identifiers (such as device identifiers) and the base address of the second-level virtual interrupt location table. When a physical interrupt source identifier is used as the index input to query the first-level device index table, the starting physical address (i.e., the base address) of the second-level virtual interrupt location table corresponding to that device can be located. The second-level virtual interrupt location table is used to store the specific mapping content. In the second-level virtual interrupt location table, the corresponding table entry can be found using a preset indexing method (e.g., based on a partial bit field of the physical interrupt source identifier or a preset index offset). This table entry stores the virtual machine identifier mapped by the physical interrupt source identifier, the virtual processor identifier in the virtual machine, and the virtual interrupt number for that virtual processor. Therefore, the above-mentioned operation of configuring the mapping relationship is essentially the virtualization management program calculating and filling the relevant table entries in the above two-level table structure according to the device allocation strategy, thereby establishing a hardware-queryable link from the physical interrupt source identifier to the physical address of the virtual machine interrupt file.

[0063] Regarding the above configuration mapping steps, in some possible implementations, the virtualization management program can write the mapping data into the internal storage unit of the hardware mapping controller sequentially or in batches through a privileged register interface or a dedicated configuration bus channel. For example, firstly, a primary device index table is configured, establishing an index from the device identifier to the secondary table base address; subsequently, the specific virtual machine identifier, virtual processor identifier, and virtual interrupt number are written into the storage area pointed to by the corresponding secondary table base address.

[0064] In this embodiment, by configuring the mapping relationship in the multi-level index table structure required for hardware mapping retrieval during the initialization phase or device pass-through configuration phase, the hardware association between the physical interrupt source identifier, virtual machine identifier, virtual processor identifier, and virtual interrupt number is established. This configuration enables the hardware mapping controller to directly locate the target parameters based on the first-level device index table and the second-level virtual interrupt location table during subsequent interrupt handling, avoiding runtime software table lookup and parsing overhead, thereby ensuring the effectiveness of the fast hardware mapping path and reducing the latency of virtual interrupt handling.

[0065] In one embodiment, the step of "calculating the address offset based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine" can be further refined and may include the following steps: Determine the virtual machine address offset based on the target virtual machine identifier and the preset virtual machine address step size; Determine the virtual processor address offset based on the target virtual processor identifier and the preset virtual processor address step size; The physical address of the target virtual machine interrupt file corresponding to the target virtual processor is obtained by calculating the address offset based on the virtual machine address offset, the virtual processor address offset, and the preset interrupt message signal controller base address. The address offset calculation is based on hardware logic and does not rely on the address translation process involving the operating system or virtualization management program.

[0066] Specifically, considering that the physical address of the target virtual machine interrupt file needs to be calculated based on the identification system of the virtual machine and virtual processor, this embodiment proposes an address offset calculation scheme based on a preset step size, which locates the target address through hardware logic operations.

[0067] First, the virtual machine address offset needs to be determined based on the target virtual machine identifier and the preset virtual machine address stride. The virtual machine address stride refers to the span of the contiguous address region allocated to each virtual machine in the memory-mapped input / output address space; the virtual machine address offset refers to the starting offset distance of the address region corresponding to the target virtual machine relative to the base address of the interrupt message signal controller.

[0068] Regarding this step, in some possible implementations, the target virtual machine identifier can be multiplied by a preset virtual machine address step size, and the result can be used as the virtual machine address offset.

[0069] For example, the virtual machine address offset can be determined using the following formula: VM_Offset = VMID × VM_Stride; Here, VM_Offset represents the virtual machine address offset, VMID represents the target virtual machine identifier, and VM_Stride represents the preset virtual machine address stride.

[0070] Furthermore, the virtual processor address offset is determined based on the target virtual processor identifier and the preset virtual processor address step size. The virtual processor address step size refers to the span of the virtual machine interrupt file address space allocated to each virtual processor within the address region of a single virtual machine; the virtual processor address offset refers to the offset distance of the virtual machine interrupt file address corresponding to the target virtual processor relative to the starting position of its virtual machine address region.

[0071] Regarding this step, in some possible implementations, the target virtual processor identifier can be multiplied by a preset virtual processor address step size, and the result can be used as the virtual processor address offset.

[0072] For example, the virtual processor address offset can be determined using the following formula: CPU_Offset=vCPU_ID×CPU_Stride; Wherein, CPU_Offset represents the virtual processor address offset, vCPU_ID represents the target virtual processor identifier, and CPU_Stride represents the preset virtual processor address stride.

[0073] Furthermore, address offset calculations are performed based on the virtual machine address offset, the virtual processor address offset, and the preset interrupt message signal controller base address to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine. The interrupt message signal controller base address refers to the starting mapped address of the interrupt message signal controller in the system's physical address space. It should be noted that the above address offset calculation is performed based on hardware logic and does not rely on the address translation process involving the operating system or virtualization management program.

[0074] Regarding this step, in some possible implementations, the interrupt message signal controller base address, virtual machine address offset, and virtual processor address offset can be added together, and the result can be used as the physical address of the target virtual machine interrupt file corresponding to the target virtual processor.

[0075] For example, the address offset can be calculated using the following formula: Target_Address=IMSIC_Base+VM_Offset+CPU_Offset; Wherein, Target_Address represents the physical address of the target virtual machine interrupt file corresponding to the target virtual processor, IMSIC_Base represents the preset interrupt message signal controller base address, VM_Offset represents the virtual machine address offset, and CPU_Offset represents the virtual processor address offset. The above calculations can be completed in a single cycle or a finite cycle by an adder array or address generation unit.

[0076] It should be noted that the specific values ​​or configuration methods of the virtual machine address step size, virtual processor address step size, and interrupt message signal controller base address can be set or adjusted according to the system architecture design, hardware resource allocation strategy, or software configuration rules. This embodiment does not impose specific limitations on these aspects.

[0077] In this embodiment, the physical address of the target virtual machine interrupt file is generated by determining the virtual machine address offset and the virtual processor address offset based on the target virtual machine identifier and the target virtual processor identifier, respectively, and then calculating the address offset in conjunction with the preset interrupt message signal controller base address. This method uses hardware logic operations to replace the memory page table lookup process, avoiding the additional latency caused by relying on memory page table access, thereby completing address location at the hardware level and shortening the processing latency of virtual interrupt mapping.

[0078] In one embodiment, the step of "writing the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file" can be further refined and may include the following steps: Based on the physical address of the target virtual machine interrupt file, initiate a write bus transaction in an atomic write manner; The target virtual interrupt number is used as the data payload of the write bus transaction and written to the target virtual machine interrupt file.

[0079] Specifically, considering the problems of uncontrollable latency and potential interruption by other high-priority tasks in the interrupt injection method by the virtualization management program through software instructions in related technologies, this embodiment proposes a virtual interrupt writing scheme based on hardware atomic writing. The bus write operation is directly initiated and completed through hardware circuitry, ensuring the indivisibility and real-time performance of the interrupt writing process.

[0080] First, a write bus transaction needs to be initiated atomically based on the physical address of the target virtual machine interrupt file. Atomic write refers to a bus operation method that guarantees the integrity of the write operation in terms of protocol semantics, ensuring that the data update of the target address is completed within a single complete transaction, rather than being split into multiple independent write operations. Under this method, the write operation to the target address is completed within a single complete bus transaction, without being interrupted or segmented by access requests from other bus master devices. A write bus transaction refers to a complete data transfer operation initiated by the hardware module to the system bus to write data to a specified physical address space. This operation includes an address phase, a data phase, and a response acknowledgment phase.

[0081] Regarding this step, in some possible implementations, the hardware writing module can use the physical address of the target virtual machine interrupt file as the target address, generate the corresponding bus control signal, and drive the bus interface unit to initiate a write bus transaction with atomic properties. The target address of this write bus transaction is the physical address of the target virtual machine interrupt file.

[0082] Furthermore, the target virtual interrupt number is used as the data payload of the write bus transaction and written to the target virtual machine interrupt file. Here, the data payload refers to the data content actually transmitted and written to the target address during the data phase of the write bus transaction.

[0083] Regarding this step, in some possible implementations, the target virtual interrupt number can be encoded into a data format that conforms to the bus protocol and used as the data payload transmitted in the data phase of the write bus transaction. This data is then written to the storage location pointed to by the physical address of the target virtual machine interrupt file via the bus, thereby completing the operation of writing the target virtual interrupt number to the target virtual machine interrupt file.

[0084] In this embodiment, by initiating a write bus transaction using an atomic write method and writing the target virtual interrupt number as the data payload, direct hardware-level injection of virtual interrupt information is achieved. This method leverages the atomic nature of hardware circuits, eliminating the context switching overhead and instruction execution latency caused by software intervention, ensuring the continuity and determinism of the interrupt writing process. Simultaneously, this process directly manipulates the physical address of the target virtual machine interrupt file, avoiding page table lookups that rely on the virtualization hypervisor, thereby shortening the virtual interrupt handling path and improving system response speed.

[0085] In one embodiment, after the above step "writing the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file", the following step may be further included: Trigger an interrupt request signal to be sent to the target virtual processor, so that the target virtual processor responds to the interrupt and enters the interrupt handling process of the virtual machine operating system.

[0086] Specifically, this embodiment proposes a virtual interrupt triggering mechanism based on hardware status monitoring, which ensures that interrupt requests are responded to by monitoring the status of interrupt files in real time and automatically triggering processor behavior.

[0087] First, the pending status bit of the target virtual machine's interrupt file can be monitored. This pending status bit refers to the register bit in the target virtual machine's interrupt file used to record the status of interrupt requests. When this bit is set to a valid value, it indicates that there are pending interrupt requests.

[0088] Regarding this step, in some possible implementations, hardware circuitry can be used to monitor changes in the state of the target virtual machine's interrupt file in order to detect whether the suspended state bit of the target virtual machine's interrupt file has changed.

[0089] Furthermore, upon detecting the pending state bit corresponding to the target virtual interrupt number, the target virtual processor is triggered to respond to the interrupt and enter the interrupt handling process of the virtual machine operating system. Here, the pending state bit corresponding to the target virtual interrupt number refers to a specific bit in the target virtual machine interrupt file being set to a valid state, indicating that the interrupt request corresponding to that target virtual interrupt number has been received and is awaiting processing; the virtual machine operating system refers to the operating system software running inside the target virtual machine, responsible for managing the virtual machine's hardware and software resources and providing the runtime environment.

[0090] Regarding this step, in some possible implementations, after detecting the pending state bit corresponding to the target virtual interrupt number, an interrupt request signal can be sent to the target virtual processor based on hardware logic, so that the target virtual processor responds to the interrupt and enters the interrupt handling process of the virtual machine operating system.

[0091] In this embodiment, by monitoring the suspended state bit of the target virtual machine interrupt file and triggering the target virtual processor when the bit is set, a correlation is established between hardware write operations and software interrupt responses. This mechanism utilizes hardware detection of changes in the suspended state bit to avoid delays caused by virtualization hypervisor polling or software querying, enabling the target virtual processor to enter the virtual machine operating system's interrupt handling process after an interrupt request is written. This ensures the real-time nature of virtual interrupt responses and achieves seamless integration between hardware writes and software processing.

[0092] In one embodiment, Figure 2 This is a schematic diagram of the overall process of virtual interrupt mapping provided in the embodiments of this application.

[0093] Specifically, when an external device generates an interrupt event, the system first receives the physical interrupt request initiated by the external device and extracts the target physical interrupt source identifier based on the physical interrupt request. Subsequently, based on the target physical interrupt source identifier, a search is performed through a preset primary device index table to obtain the base address of the secondary virtual interrupt location table; then, based on the base address of the secondary virtual interrupt location table, a search is performed through the secondary virtual interrupt location table to determine whether a target mapping table entry has been hit.

[0094] If the search results indicate a match, the operation of extracting the target mapping table entry is performed to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number from the target mapping table entry. Simultaneously, the virtual machine address offset is determined by multiplying the target virtual machine identifier with a preset virtual machine address step size; the virtual processor address offset is determined by multiplying the target virtual processor identifier with a preset virtual processor address step size. Then, based on the preset interrupt message signal controller base address, and combining the aforementioned virtual machine address offset and virtual processor address offset, an address offset calculation is performed (i.e., the interrupt message signal controller base address is added to the virtual machine address offset and the virtual processor address offset) to obtain the physical address of the target virtual machine interrupt file. The above address offset calculation is performed based on hardware logic and does not rely on the address translation process involving the operating system or virtualization management program.

[0095] Based on the physical address of the target virtual machine interrupt file, a write bus transaction is initiated atomically, using the target virtual interrupt number as the data payload, and written to the target virtual machine interrupt file via the bus. This write process is completed by hardware logic without entering the virtualization management program. After the write operation is completed, the suspended status bit is continuously monitored. When the suspended status bit corresponding to the target virtual interrupt number is detected to be set, an interrupt request signal is triggered to the target virtual processor, causing the target virtual processor to respond to the interrupt and enter the interrupt handling process of the virtual machine operating system, completing the virtualization write and processing of the physical interrupt request.

[0096] It should be noted that the above-mentioned hardware mapping retrieval, address offset calculation, and writing of the target virtual interrupt number into the target virtual machine interrupt file are all completed by hardware logic and do not require entering the virtualization management program.

[0097] If the search results indicate a no-match, the physical interrupt request is forwarded to the virtualization management program, which then performs software parsing and virtual interrupt injection. The interrupt information is written to the target virtual machine's interrupt file via software writing to ensure that the interrupt request is handled as a fallback.

[0098] In this embodiment, the primary device index table and the secondary virtual interrupt location table can be specific tables corresponding to the multi-level index table structure in the aforementioned embodiments; the judgment logic for hitting a target mapping table entry can be the hit determination mechanism corresponding to the hardware mapping retrieval process in the aforementioned embodiments; the software parsing and virtual interrupt injection executed by the virtualization management program can be the exception handling mechanism corresponding to the fallback to the software processing path in the aforementioned embodiments. As can be seen from this flowchart, this embodiment achieves fast mapping and automatic writing from physical interrupts to virtual interrupts when a hit occurs through hierarchical index retrieval and address calculation at the hardware level, while providing a software fallback path when a hit occurs, ensuring the robustness and reliability of the processing.

[0099] In one embodiment, Figure 3 This is a schematic diagram of the overall system structure for virtual interrupt mapping provided in an embodiment of this application.

[0100] Specifically, the architecture shown in the figure is divided into two main categories: hardware system and software domain. The hardware system includes an Interrupt Redirection Mapping Engine (which can serve as one of the core hardware processing units of the virtual interrupt mapping method in this application, and contains a mapping information storage unit, Mapping Table / Cache, which can be a hardware storage medium corresponding to a multi-level index table structure) and an IMSIC Guest Interrupt File (an implementation of the target virtual machine interrupt file); the software domain includes a virtual machine (VM) (an implementation of the target virtual machine) and a hypervisor.

[0101] During the configuration phase, the aforementioned hypervisor configures the path through mapping relationships (represented by dashed connecting lines), and writes the association information between the physical interrupt source identifier and the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number into the mapping information storage unit (Mapping Table / Cache) inside the aforementioned Interrupt Redirection MappingEngine, thereby establishing interrupt redirection rules at the hardware level.

[0102] During the interrupt handling phase, when an interrupt event occurs in a peripheral device (an implementation of an external device), an interrupt write transaction is first initiated via MSI / MSI-X (Message Signal Interrupt). This interrupt write transaction can also be considered a memory write transaction. The interrupt is forwarded by the interrupt receiving path to the aforementioned Interrupt Redirection Mapping Engine. This engine, based on the pre-stored mapping relationships in its internal mapping information storage unit (Mapping Table / Cache), performs address calculation and interrupt number conversion on the original interrupt message, generating a converted interrupt write (Target Guest MSI Write) (an implementation of virtual interrupt write operations). This converted interrupt write is then directly sent to the IMSIC Guest Interrupt File. Upon receiving the converted interrupt write, the IMSIC Guest Interrupt File updates its internal state and triggers an interrupt response from the target virtual processor, causing the virtual machine operating system to enter the interrupt handling process, thus completing the hardware pass-through write from the physical interrupt to the virtual interrupt.

[0103] In this embodiment, the peripheral device can be a specific implementation corresponding to the external device in the aforementioned embodiments; the interrupt redirection mapping engine can serve as an execution entity in the relevant embodiments of the virtual interrupt mapping method of this application; the mapping information storage unit (Mapping Table / Cache) can be a high-speed cache or register array corresponding to the multi-level index table structure in the aforementioned embodiments; the IMSIC guest interrupt file can be the target virtual machine interrupt file corresponding to the aforementioned embodiments; the virtual machine (VM) can be the target virtual machine corresponding to the aforementioned embodiments; and the hypervisor can be the hypervisor corresponding to the hypervisor in the aforementioned embodiments. As can be seen from the schematic diagram, this embodiment integrates the mapping relationship configuration and interrupt redirection function at the hardware level, realizing fast mapping and automatic writing from physical interrupts to virtual interrupts. At the same time, the initial configuration of the mapping relationship is completed through the virtualization hypervisor in the software domain, balancing hardware processing efficiency and software management flexibility.

[0104] In one embodiment, please refer to Figure 4 , Figure 4 This is a schematic diagram of the internal structure of the interrupt redirection mapping engine provided in an embodiment of this application.

[0105] Specifically, the internal structure of this interrupt redirection mapping engine involves functional units such as bus, software domain, interrupt source identification module, mapping table configuration module, hardware mapping controller, exception handling / hypervisor intervention, address offset calculation module, and hardware writing module.

[0106] During the configuration phase, the aforementioned software domain sends configuration information to the mapping table configuration module through the configuration flow path. The mapping table configuration module then writes the mapping relationship between the physical interrupt source identifier and the virtual machine identifier, virtual processor identifier, and virtual interrupt number into the mapping information storage unit associated with the aforementioned hardware mapping controller, thereby completing the pre-configuration of the mapping relationship.

[0107] During the interrupt handling phase, physical interrupt requests from external devices are transmitted via the bus to the interrupt source identification module. This module extracts the Device ID / MSI Address (device identifier or message signal interrupt address, a form of the target physical interrupt source identifier) ​​from the physical interrupt request and sends it to the aforementioned Hardware Mapping Controller. The Hardware Mapping Controller performs a hierarchical search based on the Device ID / MSI Address using its internal primary device index table and secondary virtual interrupt location table. If a target mapping table entry is matched, it outputs the VMID / vCPU ID / vINT ID (virtual machine identifier, virtual processor identifier, and virtual interrupt number, respectively, a form of the target virtual machine identifier, target virtual processor identifier, and target virtual interrupt number) to the address offset calculation module. The address offset calculation module calculates the address offset based on the VMID and vCPU ID to obtain the target physical address (a form of the physical address of the target virtual machine interrupt file, also represented as Target PA), and sends this target physical address to the hardware writing module. The hardware writing module initiates a write bus transaction (for performing virtual interrupt writing) in an atomic writing manner based on the target physical address, and writes the above vINT ID as the data payload to the corresponding target virtual machine interrupt file, thereby completing the automatic hardware writing of the virtual interrupt.

[0108] If the retrieval result of the aforementioned hardware mapping controller indicates a mapping miss, the hardware mapping controller triggers an exception handling / Hypervisor intervention path, which rolls back the physical interrupt request to the Hypervisor (virtualization management program) for software resolution and virtual interrupt injection.

[0109] In this embodiment, the primary device index table and the secondary virtual interrupt location table can be specific tables corresponding to the multi-level index table structure in the aforementioned embodiments; exception handling / Hypervisor intervention can be the exception response mechanism corresponding to the fallback to the Hypervisor (virtualization management program) processing flow in the aforementioned embodiments. As can be seen from the schematic diagram, this embodiment implements hardware-level pipelined processing of interrupt mapping, address calculation, and automatic writing through modular design, while providing a software fallback path when mapping misses, ensuring the integrity and reliability of virtual interrupt processing.

[0110] In one embodiment, please refer to Figure 5 , Figure 5 This is a schematic diagram of the virtual interrupt writing timing provided in an embodiment of this application.

[0111] Specifically, the timing diagram involves five interactive entities: Hypervisor (virtualization management program), Device (peripheral / interrupt source, which is an implementation of external devices), Mapping Engine (hardware mapping engine, which is an implementation of hardware mapping controllers), IMSIC (interrupt file / register set, which is an implementation of the interrupt file of the target virtual machine), and VirtualMachine (VM / virtual machine, which is an implementation of the target virtual machine). It is divided into two stages: the mapping relationship pre-configuration stage and the hardware fast interrupt write path (high frequency, low latency path).

[0112] During the mapping relationship pre-configuration phase (during virtual machine / device initialization), the Hypervisor sends a pre-configured mapping relationship (VMID / vCPU ID / vINTID) to the Mapping Engine. This mapping relationship includes the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number. Upon receiving this pre-configured mapping relationship, the Mapping Engine internally updates the hardware hierarchical mapping table (L1 / L2) (this hardware hierarchical mapping table is an implementation of a multi-level index table structure, where L1 corresponds to the first-level device index table and L2 corresponds to the second-level virtual interrupt location table), thereby completing the hardware solidification of the mapping relationship. Subsequently, the Mapping Engine returns a configuration completion signal to the Hypervisor, marking the end of the pre-configuration phase.

[0113] During the hardware fast interrupt write path (high-frequency, low-latency path) phase, when the Device (peripheral / interrupt source) generates an interrupt event, it first sends a raw physical MSI interrupt request (an implementation of a physical interrupt request) to the Mapping Engine and internally marks the interrupt transmission as complete. Upon receiving the raw physical MSI interrupt request, the Mapping Engine performs a hierarchical table lookup internally. It determines the target mapping parameters by searching the hardware mapping table (Hit) (an implementation of hitting a target mapping table entry), and then performs PA = Base + Offset (i.e., the address offset calculation by adding the base address and the offset) to calculate the target physical address (PA) (an implementation of the physical address of the target virtual machine interrupt file).

[0114] It is understandable that the formula PA=Base+Offset can be replaced by the formula Target_Address=IMSIC_Base+VM_Offset+CPU_Offset in the above embodiment.

[0115] Among them, PA=Target_Address, Base=IMSIC_Base, Offset=VM_Offset+CPU_Offset; Target_Address represents the physical address of the target virtual machine interrupt file corresponding to the target virtual processor, IMSIC_Base represents the preset interrupt message signal controller base address, VM_Offset represents the virtual machine address offset, and CPU_Offset represents the virtual processor address offset.

[0116] Subsequently, the Mapping Engine initiates an atomic write transaction (Target Guest MSI Write) to the IMSIC (Interrupt File / Register Set) (an implementation of the atomic write method for initiating a write bus transaction), writing the virtual interrupt number to the target address.

[0117] Upon receiving the atomic write transaction, the IMSIC (Interrupt File / Register Set) internally updates the IMSIC register status (sets the Pending bit) and automatically triggers a virtual interrupt exception signal to the Virtual Machine (VM). Simultaneously, the IMSIC sends a write transaction completion confirmation to the Mapping Engine. Upon receiving this virtual interrupt exception signal, the Virtual Machine executes the virtual machine operating system interrupt handler (ISR) internally, thus completing the virtual interrupt write and processing. In this fast write path, the Hypervisor remains in a zero-participation state internally, thereby reducing VM Exit and avoiding the context switching overhead caused by software intervention.

[0118] In this embodiment, low latency and high determinism of virtual interrupt writing are achieved through the establishment of mapping relationships in the pre-configuration stage and the hardware automation processing in the fast write stage. At the same time, by eliminating the participation of the Hypervisor in the fast path, the virtualization overhead is significantly reduced.

[0119] The following will combine Figure 6 and Figure 7 The virtual interrupt mapping device 800 provided in this application embodiment will be described in detail. The virtual interrupt mapping device 800 and the virtual interrupt mapping method described above can be referred to in correspondence. Specifically, please refer to Figure 6 The virtual interrupt mapping device 800 may include an interrupt source identification module 810, a hardware mapping controller 820, an address offset calculation module 830, and a hardware writing module 840, as detailed below: The interrupt source identification module 810 is used to receive physical interrupt requests from external devices and extract the target physical interrupt source identifier based on the physical interrupt request. The hardware mapping controller 820 is used to perform hardware mapping retrieval based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier; The address offset calculation module 830 is used to calculate the address offset based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine. The hardware writing module 840 is used to write the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file; The hardware mapping retrieval, the address offset calculation, and the process of writing the target virtual interrupt number into the target virtual machine interrupt file are all completed by hardware logic and do not require entering the virtualization management program.

[0120] Optionally, in some embodiments, the hardware mapping controller 820 can be used to: Hardware mapping retrieval is performed based on the target physical interrupt source identifier and a preset multi-level index table structure to obtain the retrieval results; If the search results indicate a match in the target mapping table, extract the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier from the target mapping table.

[0121] Optionally, in some embodiments, the hardware mapping controller 820 can be used to: Based on the target physical interrupt source identifier, the base address of the second-level virtual interrupt location table is obtained by searching through the first-level device index table in the preset multi-level index table structure. Based on the base address of the secondary virtual interrupt location table, the search is performed through the secondary virtual interrupt location table in the multi-level index table structure to obtain the search results.

[0122] Optionally, in some embodiments, the hardware mapping controller 820 can be used to: If the search results indicate that the target mapping table entry was not matched, an interrupt mapping exception signal is sent to the virtualization hypervisor, and the physical interrupt request is forwarded to the virtualization hypervisor so that the virtualization hypervisor can perform software parsing and virtual interrupt injection on the physical interrupt request based on the interrupt mapping exception signal.

[0123] Optionally, in some embodiments, the virtual interrupt mapping device 800 can be used for: During the initialization phase or device pass-through configuration phase, the mapping relationship between physical interrupt source identifier, virtual machine identifier, virtual processor identifier, and virtual interrupt number is configured in the multi-level index table structure required by the virtualization management program for the process of mapping and retrieving to hardware.

[0124] Optionally, in some embodiments, the address offset calculation module 830 can be used for: Determine the virtual machine address offset based on the target virtual machine identifier and the preset virtual machine address step size; Determine the virtual processor address offset based on the target virtual processor identifier and the preset virtual processor address step size; The physical address of the target virtual machine interrupt file corresponding to the target virtual processor is obtained by calculating the address offset based on the virtual machine address offset, the virtual processor address offset, and the preset interrupt message signal controller base address. The address offset calculation is based on hardware logic and does not rely on the address translation process involving the operating system or virtualization management program.

[0125] Optionally, in some embodiments, the hardware writing module 840 can be used to: Based on the physical address of the target virtual machine interrupt file, initiate a write bus transaction in an atomic write manner; The target virtual interrupt number is used as the data payload of the write bus transaction and written to the target virtual machine interrupt file.

[0126] Optionally, in some embodiments, the virtual interrupt mapping device 800 can be used for: The interrupt handling process of the target virtual processor is triggered to enter the virtual machine operating system, and the interrupt handler corresponding to the target virtual interrupt number in the virtual machine operating system is executed.

[0127] Alternatively, in some embodiments, please refer to Figure 7 The virtual interrupt mapping device 800 may also include a mapping table configuration module 850, which is used to configure the multi-level index table structure required for the hardware mapping retrieval process.

[0128] For the effects achievable in this embodiment, please refer to the relevant embodiments of the virtual interrupt mapping method described above, which will not be repeated here.

[0129] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0130] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0131] All actions involving the acquisition of signal information or data in this application are carried out in accordance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A virtual interrupt mapping method, characterized in that, include: Receive a physical interruption request from an external device, and extract the target physical interruption source identifier based on the physical interruption request; Hardware mapping retrieval is performed based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier; The physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine is obtained by calculating the address offset based on the target virtual machine identifier and the target virtual processor identifier. Write the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file; The hardware mapping retrieval, the address offset calculation, and the process of writing the target virtual interrupt number into the target virtual machine interrupt file are all completed by hardware logic and do not require entering the virtualization management program. The step of performing hardware mapping retrieval based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier includes: retrieving the base address of the secondary virtual interrupt location table by searching the primary device index table in a preset multi-level index table structure based on the target physical interrupt source identifier; retrieving the secondary virtual interrupt location table in the multi-level index table structure based on the base address of the secondary virtual interrupt location table to obtain the retrieval result; and extracting the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier from the target mapping table entry if the retrieval result indicates a match in the target mapping table entry; wherein, the multi-level index table structure is a hardware data structure.

2. The virtual interrupt mapping method according to claim 1, characterized in that, After obtaining the retrieval result by searching the secondary virtual interrupt location table in the multi-level index table structure based on the base address of the secondary virtual interrupt location table, the virtual interrupt mapping method further includes: If the search result indicates that the target mapping table entry was not matched, an interrupt mapping exception signal is sent to the virtualization management program, and the physical interrupt request is forwarded to the virtualization management program so that the virtualization management program can perform software parsing and virtual interrupt injection on the physical interrupt request based on the interrupt mapping exception signal.

3. The virtual interrupt mapping method according to claim 1, characterized in that, The virtual interrupt mapping method further includes: During the initialization phase or the device pass-through configuration phase, the mapping relationship between physical interrupt source identifier, virtual machine identifier, virtual processor identifier, and virtual interrupt number is configured in the multi-level index table structure required by the virtualization management program to retrieve the hardware mapping.

4. The virtual interrupt mapping method according to claim 1, characterized in that, The step of calculating the address offset based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine includes: The virtual machine address offset is determined based on the target virtual machine identifier and the preset virtual machine address step size; The virtual processor address offset is determined based on the target virtual processor identifier and the preset virtual processor address step size; The physical address of the target virtual machine interrupt file corresponding to the target virtual processor is obtained by calculating the address offset based on the virtual machine address offset, the virtual processor address offset, and the preset interrupt message signal controller base address.

5. The virtual interrupt mapping method according to claim 1, characterized in that, The step of writing the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file includes: Based on the physical address of the target virtual machine interrupt file, initiate a write bus transaction in an atomic write manner; The target virtual interrupt number is used as the data payload of the write bus transaction and written to the target virtual machine interrupt file.

6. The virtual interrupt mapping method according to claim 1, characterized in that, After writing the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file, the method further includes: An interrupt request signal is triggered and sent to the target virtual processor, so that the target virtual processor responds to the interrupt and enters the interrupt handling process of the virtual machine operating system.

7. A virtual interrupt mapping device, characterized in that, include: The interrupt source identification module is used to receive physical interrupt requests from external devices and extract the target physical interrupt source identifier based on the physical interrupt request; The hardware mapping controller is used to perform hardware mapping retrieval based on the target physical interrupt source identifier to obtain the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier; The address offset calculation module is used to perform address offset calculation based on the target virtual machine identifier and the target virtual processor identifier to obtain the physical address of the target virtual machine interrupt file corresponding to the target virtual processor in the target virtual machine. The hardware writing module is used to write the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file; The hardware mapping retrieval, the address offset calculation, and the process of writing the target virtual interrupt number into the target virtual machine interrupt file are all completed by hardware logic and do not require entering the virtualization management program. The hardware mapping controller is further configured to: retrieve the base address of the secondary virtual interrupt location table by searching the primary device index table in the preset multi-level index table structure based on the target physical interrupt source identifier; retrieve the secondary virtual interrupt location table in the multi-level index table structure based on the base address of the secondary virtual interrupt location table to obtain the retrieval result; and, if the retrieval result indicates a match in the target mapping table entry, extract the target virtual machine identifier, the target virtual processor identifier, and the target virtual interrupt number corresponding to the target virtual processor identifier from the target mapping table entry; wherein, the multi-level index table structure is a hardware data structure.

8. The virtual interrupt mapping device according to claim 7, characterized in that, The virtual interrupt mapping device also includes a mapping table configuration module; The mapping table configuration module is used to configure the multi-level index table structure required for the hardware mapping retrieval process.

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