Debugging interface verification method and device of chip, storage medium and program product

Abstract

Embodiments of the present disclosure provide a debugging interface verification method and device of a chip, a storage medium and a program product. The method comprises: determining, in a storage space in the chip for storing state information, a current field to be verified, field position information of the current field and to-be-written data; writing the to-be-written data into the current field according to the field position information; after 2 clock cycles, reading first read-out data in the current field through a first debugging interface corresponding to the storage space according to the field position information; comparing whether the first read-out data and the to-be-written data are consistent, and determining that the current field passes the verification when the first read-out data and the to-be-written data are consistent; and determining that a first debugging interface mapping passes the verification when all fields to be verified in the storage space corresponding to the first debugging interface pass the verification. Thus, field-level address mapping verification of the debugging interface can be implemented, and the comprehensiveness of the debugging interface verification is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method, apparatus, storage medium, and program product for verifying a chip's debugging interface. Background Technology

[0002] As the complexity of integrated circuit systems continues to increase, various functional modules within a chip typically provide debug interfaces. These debug interfaces are used to output relevant status information from within the chip to support needs such as performance analysis and anomaly localization. Therefore, verifying these debug interfaces becomes necessary.

[0003] In related technologies, the verification of the debug interface mainly focuses on the connectivity check, that is, reading the relevant status information in the chip through the debug interface. If the relevant status information can be read and retrieved, the debug interface is considered to have passed the verification.

[0004] However, the above verification method only guarantees that the debug interface can read status information. Even in cases where the relevant status information is incorrectly mapped in the address space, the status information is still readable through the debug interface. Therefore, even if there is an address space mapping error, the debug interface is considered to have passed verification as long as the status information is readable. Thus, existing verification methods for debug interfaces cannot adequately cover situations involving address mapping errors. Summary of the Invention

[0005] This disclosure provides a method, apparatus, storage medium, and program product for verifying the debug interface of a chip, thereby enabling field-level address mapping verification of the debug interface and improving the comprehensiveness of debug interface verification.

[0006] The embodiments disclosed herein employ the following technical solutions: In a first aspect, embodiments of this disclosure provide a method for verifying a chip's debug interface, comprising: determining a current field to be verified, field position information of the current field, and data to be written in a storage space in the chip used for storing state information; writing the data to be written to the back door of the current field according to the field position information; after two cycles, reading first read data from the current field through a first debug interface corresponding to the storage space according to the front door of the field position information; comparing whether the first read data and the data to be written are consistent, and determining that the current field has passed verification when the first read data and the data to be written are consistent; determining that the first debug interface mapping verification has passed when all fields to be verified in the storage space corresponding to the first debug interface have passed verification, generating random field position information, wherein the random field position information does not belong to the storage space corresponding to the first debug interface; reading field data through the first debug interface according to the random field position information; and determining that the default output behavior of the first debug interface has passed verification when the read field data belongs to preset default data.

[0007] Secondly, embodiments of this disclosure provide a verification device for a chip's debugging interface, comprising: a first determining module, configured to determine a current field to be verified, field position information of the current field, and data to be written in a storage space in the chip used for storing state information; a backdoor writing module, configured to write the data to be written to the backdoor of the current field according to the field position information; a frontdoor reading module, configured to read first read data from the current field through a first debugging interface corresponding to the storage space according to the field position information after two cycles; a verification module, configured to compare whether the first read data and the data to be written are consistent, and determine that the current field has passed verification when the first read data and the data to be written are consistent; a second determining module, configured to determine that the first debugging interface mapping verification has passed when all fields to be verified in the storage space corresponding to the first debugging interface have passed verification; and a random output behavior verification module, configured to generate random field position information, wherein the random field position information does not belong to the storage space corresponding to the first debugging interface, read field data through the first debugging interface according to the random field position information, and determine that the first debugging interface default output behavior verification has passed when the read field data belongs to preset default data.

[0008] Thirdly, embodiments of this disclosure provide an electronic device, including: a memory, a processor, and computer-executable instructions stored in the memory and executable on the processor, wherein the computer-executable instructions, when executed by the processor, implement the method described in the first aspect above.

[0009] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, can implement the method described in the first aspect above.

[0010] Fifthly, embodiments of this disclosure provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the method described in the first aspect above.

[0011] The above-described at least one technical solution adopted in the embodiments of this disclosure can achieve the following beneficial effects: In the chip's storage space used to store state information, the current field to be verified, its position information, and the data to be written are determined. Based on the field position information, the data to be written is written to the back door of the current field. Then, after two cycles, the first read data from the current field is read through the first debug interface corresponding to the storage space, based on the field position information. The first read data is compared with the data to be written. If they match, the current field verification is considered successful. When all fields to be verified in the storage space corresponding to the first debug interface have passed verification, the first debug interface mapping verification is considered successful. A random field position information is generated, which does not belong to the storage space corresponding to the first debug interface. Field data is read through the first debug interface based on the random field position information. If the read field data belongs to the preset default data, the first debug interface default output behavior verification is considered successful. This technical solution enables field-level address mapping verification of the chip's debug interface, improving the comprehensiveness of debug interface verification. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in one or more embodiments of this disclosure, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating a verification method for a chip's debugging interface according to an embodiment of this disclosure. Figure 2 This is a flowchart illustrating a verification method for a chip's debugging interface according to another embodiment of this disclosure; Figure 3 This is a flowchart illustrating a verification method for a chip's debugging interface according to yet another embodiment of this disclosure. Figure 4This is a schematic diagram of the verification process of the debugging interface of a chip according to a specific embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of a verification device for a chip debugging interface proposed in this disclosure. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0015] The term "comprising" and its variations as used in this disclosure are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below. The term "in response to" indicates that the performed operation depends on a condition or state. When the dependent condition or state is met, one or more operations may be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which multiple operations are performed.

[0016] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of the functions performed by these devices, modules or units or their interdependencies.

[0017] It should be noted that the modifiers such as "one" and "multiple" mentioned in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that they should be understood as "one or more" unless explicitly stated in the context.

[0018] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0019] As mentioned earlier, existing technologies cannot verify whether the mapping relationship of chip-related status information in the address space is correct. In the embodiments of this disclosure, the chip-related status information is typically stored for multiple fields, enabling fine-grained verification at the field level. This improves the verification granularity and allows for verification that covers field-level mapping errors.

[0020] The technical solutions provided by the embodiments of this disclosure are described in detail below with reference to the accompanying drawings. In the embodiments of this disclosure, the relevant status information of the chip can be regarded as being stored in a storage space. The storage space may correspond to a register or a signal group, etc. The storage space is a whole space, or it may be distributed in multiple locations. For example, when the storage space corresponds to a register, the register of the relevant status information of each chip can be regarded as a storage space. The storage space contains multiple fields, and the enabled relevant debugging interface can read the relevant status information in the storage space. The type of debugging interface may include at least one of the following: a debug bus interface (which may be called a debug_bus interface), a control and status register interface (which may be called a debug_csr interface), etc.

[0021] Figure 1 This is a flowchart illustrating a verification method for a chip's debugging interface according to an embodiment of this disclosure. Figure 1 As shown, the method includes: Step 101: In the storage space in the chip used to store state information, determine the current field to be verified, the field position information of the current field, and the data to be written.

[0022] The status information can include the status information of each functional module within the chip, such as the operating status information of each functional module. The storage space includes multiple fields. Since each field has a different bit width and starting position, the field location information is used to uniquely indicate the location of the field in the storage space. The field location information can include at least several of the following: field bit width, field starting position, internal signal path of the field (which can be understood as the hierarchical path identifier of the field to be debugged in the chip's Register Transfer Level Design (RTL), used to uniquely point to the physical location of the field to be debugged in the storage space (such as a register), providing debugging tools with logical location information to directly access the field), and address information to be checked (the address information of the storage space to be checked, such as the address information of a register, especially when the memory corresponds to multiple registers, the address information to be checked is used to indicate which of the multiple registers the current register to be debugged is).

[0023] The data to be written is a pre-set backdoor write data. To achieve field-level verification, the backdoor write data between different fields may not be exactly the same; for example, the backdoor write data between adjacent fields may be different. In the embodiments of this disclosure, field-by-field verification is implemented, that is, the current field to be verified is determined, and the field position information and the data to be written of the current field are determined.

[0024] In one embodiment of this disclosure, in order to improve verification efficiency, the current bit field to be verified (i.e., a sub-unit in the storage space, where a bit field (also called a field) may include multiple fields) can be determined in the storage space. The storage space is divided into multiple bit fields, and then all fields included in the bit field are sorted to obtain a sorting result. For example, the sorting result can be determined according to the order of the fields in the bit field from front to back. Then, the current field to be verified is determined according to the order of the sorting result from front to back. Thus, after all fields of a bit field are determined each time, all fields are sorted at once. After each field is verified, the next current field to be verified is determined according to the order in the sorting result, instead of determining the current field to be verified field by field, thereby improving the field verification efficiency.

[0025] Step 102: Write the data to be written to the back door of the current field according to the field position information.

[0026] In the embodiments of this disclosure, data to be written is written to the backdoor of the current field according to the field location information. That is, the specified data to be written is directly written to the storage space corresponding to the current field under test through the backdoor access method. For example, the specified data to be written can be directly written to the register or signal group corresponding to the current field under test through the force instruction.

[0027] Step 103: After 2 cycles, the first read data in the current field is read through the first debugging interface corresponding to the storage space according to the field position information.

[0028] The first debugging interface is the debugging interface corresponding to the storage space where the current field to be verified is located. The relevant status information in the storage space can be read out through the first debugging interface.

[0029] It should be understood that, to compensate for latency in data transmission and writing, a two-cycle delay is configured. After two cycles, the first read data from the current field is retrieved through the first debugging interface corresponding to the storage space, based on the field position information. The number of cycles can also be customized based on the performance of the storage space.

[0030] Step 104: Compare whether the first read data and the data to be written are consistent, and if the first read data and the data to be written are consistent, determine that the current field has passed the verification.

[0031] In one embodiment of this disclosure, the first read data and the data to be written are compared for consistency. If the first read data and the data to be written are consistent, the current field is determined to have passed verification. Then, after the field verification passes, the next current field can be verified.

[0032] Step 105: When all fields to be verified in the storage space corresponding to the first debugging interface have been verified, it is determined that the mapping verification of the first debugging interface has passed.

[0033] When all fields to be verified in the storage space corresponding to the first debugging interface pass verification, it is determined that the first debugging interface mapping verification is successful, that is, the field-level address mapping verification is successful. This verification method realizes field-level mapping and improves the granularity of verification.

[0034] In another embodiment of this disclosure, after comparing whether the first read data and the data to be written are consistent, if the first read data and the data to be written are inconsistent, it is possible that the first debugging interface has a field address mapping error in its design. The current field verification is considered to have failed. Then, the verification process of the next current field can be performed to determine whether there is a problem of multiple field mapping errors. Alternatively, an error can be reported directly and the verification process of the next field can be stopped.

[0035] In another embodiment of this disclosure, after comparing whether the first read data and the data to be written are consistent, if the first read data and the data to be written are inconsistent, in order to avoid misjudgment, it can also be determined whether the storage space also includes the corresponding second debugging interface, that is, whether there are other debugging interfaces that can read the data of the current field.

[0036] When a second debugging interface is included, the second read data in the current field can be read through the second debugging interface according to the field position information. Then, the second read data and the data to be written are compared. If the second read data and the data to be written are consistent, it indicates that the inconsistency between the first read data and the data to be written is not due to data delay or other issues in the current field. It may be that there is an address mapping error in the first debugging interface. Therefore, it is determined that the current field verification fails.

[0037] In practical applications, to avoid affecting the verification results of the debugging interface due to unreasonable duration settings for the two beats, the number of beats can be flexibly adjusted. The adjustment method can vary depending on the application scenario, as shown in the following example: In some possible embodiments, in the above embodiments, if the second read data and the data to be written are also inconsistent, then problems such as incorrect field position information settings or unreasonable cycle settings can be gradually ruled out.

[0038] For example, to determine if the issue stems from an unreasonable setting of the two-beat count, we can check for instances where the first and second read data are inconsistent with the data to be written for a consecutive preset threshold number of fields. If such instances exist, we add a unit beat to the two-beat count to obtain an updated beat count. Then, we continue reading new first read data using this updated beat count. If the new first read data is still inconsistent with the data to be written, we determine that the current field validation has failed. Otherwise, we determine that the current field validation has passed, and we validate subsequent fields using the updated beat count again. Alternatively, if the new read data is still inconsistent with the data to be written, we continue adding a unit beat to the two-beat count to obtain an updated beat count again. We then read the first read data again based on this updated beat count. If the newly read first read data is still inconsistent with the data to be written, we determine that the current field validation has failed. Otherwise, we determine that the current field validation has passed, and we validate subsequent fields using the updated beat count again.

[0039] In some possible embodiments, the current field verification is determined to fail when it is determined that the current field verification fails, for example, when the first read data and the data to be written are inconsistent, and / or, the first read data and the data to be written are inconsistent but the second read data and the data to be written are consistent. In this embodiment, it is counted whether the number of consecutive field verification failures exceeds a preset threshold, wherein the preset threshold can be customized. When the number of consecutive field verification failures exceeds the preset threshold, it is considered that it may be due to an unreasonable clock cycle setting. Therefore, the clock cycle is increased by one unit clock cycle to obtain an updated clock cycle number. Then, new first read data is read again using the updated clock cycle number. If the new first read data and the data to be written are still inconsistent, the current field verification is determined to fail. If the new first read data and the data to be written are consistent, the current field verification is determined to pass, and subsequent fields are verified based on the updated clock cycle number.

[0040] In one embodiment of this disclosure, to further improve the verification coverage, the output behavior of the debugging interface can also be verified. For example... Figure 1 As shown, the method also includes: Step 106: Generate a random field location information, wherein the random field location information does not belong to the storage space corresponding to the first debugging interface.

[0041] The random field location information does not belong to the storage space corresponding to the first debugging interface. That is, for the storage space corresponding to the first debugging interface, the random field location information is a randomly generated invalid address information.

[0042] Step 107: Read field data based on random field position information through the first debugging interface.

[0043] Step 108: If the read field data belongs to the preset default data, confirm that the default output behavior of the first debugging interface has been verified.

[0044] The default data is a predefined default return value when the field being read does not exist. The default output behavior specifies that when reading data for a field that does not exist in the storage space, the default data will be returned.

[0045] In the embodiments of this disclosure, field data is read through a first debugging interface based on random field position information. If the read field data belongs to the preset default data, it is determined that the default output behavior of the first debugging interface has passed verification; otherwise, if the read field data belongs to the preset default data, it is determined that the default output behavior of the first debugging interface has failed verification. In summary, the chip debug interface verification method of this disclosure involves determining the current field to be verified, its field position information, and the data to be written in the storage space used to store state information within the chip. The data to be written is then written to the back door of the current field based on the field position information. After two cycles, the first debug interface corresponding to the storage space reads the first read data from the current field based on the field position information. The first read data is compared with the data to be written. If they match, the current field is verified as passed. When all fields to be verified in the storage space corresponding to the first debug interface are verified as passed, the first debug interface mapping verification is confirmed as passed. A random field position information is generated, which does not belong to the storage space corresponding to the first debug interface. Field data is read through the first debug interface based on the random field position information. If the read field data belongs to a preset default data, the first debug interface default output behavior verification is confirmed as passed. This technical solution enables field-level address mapping verification of the chip's debug interface, improving the comprehensiveness of debug interface verification.

[0046] In actual execution, the debugging interface differs in interface width, alignment method, and timing characteristics. In the embodiments of this disclosure, in order to improve the reliability of verification, verification is also performed based on the differences in the debugging interface, as shown in the following example: In one embodiment of this disclosure, when the first debug interface is a debug bus interface (e.g., debug_bus interface), considering that the least significant bit of the debug bus interface may be multiplexed as a clock signal, a data alignment control mechanism can also be introduced.

[0047] In this embodiment, Figure 2This is a flowchart illustrating a verification method for a chip's debug interface according to another embodiment of this disclosure, as shown below. Figure 2 As shown, the method includes: Step 201: Identify whether the least significant bit of the first debugging interface is multiplexed as a clock signal.

[0048] In the embodiments of this disclosure, it can be determined whether the least significant bit is multiplexed as a clock signal by identifying the clock flag bit corresponding to the first debug interface. For example, when the first debug interface is debug_bus, it can be determined whether the least significant bit of the first debug interface is multiplexed as a clock signal by identifying whether debug_bus_clk_en is 1. When debug_bus_clk_en=1, it is determined that the least significant bit of the first debug interface is multiplexed as a clock signal.

[0049] Step 202: When multiplexed as a clock signal, the starting position of the field reading the first read data is shifted one bit to the left.

[0050] In the embodiments of this disclosure, when the least significant bit of the first debug interface is multiplexed as a clock signal, it indicates that the data corresponding to the least significant bit is a clock signal and not valid data of the first written data. Therefore, the starting position of the field for reading the first written data can be offset. For example, when the least significant bit bit0 of the first debug interface is multiplexed as a clock signal, the starting position of the field for the first read data can be taken from bit1. Thus, the first read data is read from bit1, avoiding the influence of the multiplexed clock signal and realizing the alignment of the read data.

[0051] In this embodiment, the starting position of the field of the first written data can be offset after reading the first written data, or the starting position of the field can be offset before reading the first written data.

[0052] In one embodiment of this disclosure, when the interface width of the debugging interface is smaller than the width of the current field, there may be a scenario where cross-address data is concatenated.

[0053] In embodiments of this disclosure, Figure 3 This is a flowchart illustrating a verification method for a chip's debugging interface according to yet another embodiment of this disclosure, as shown below. Figure 3 As shown, the first debug interface corresponding to the storage space reads the first data from the current field based on the field position information through the front door, including: Step 301: Determine whether the field width of the current field is greater than the interface width of the first debugging interface.

[0054] In the embodiments of this disclosure, it is determined whether the field width of the current field is greater than the interface width of the first debug interface. In some possible addresses, when the first debug interface supports cross-address data reading, the field width of the current field can be determined by the cross-address flag bit configured in the first debug interface. For example, when the first debug interface is the debug_csr interface, if the cross-address flag bit is debug_previous_addr_check_en=1, it indicates that the function of cross-address data reading is enabled.

[0055] Step 302: When the data is greater than the interface width, read the field data multiple times in the current field according to the field position information until the current field is read completely.

[0056] Step 303: Concatenate the read field data from multiple fields to obtain the first read data.

[0057] In the embodiments of this disclosure, when the data is greater than the interface bit width, the field data is read multiple times in the current field according to the field position information until the current field is read completely. Then, the multiple field data read are concatenated to obtain the first read data.

[0058] For example, for the `debug_csr` interface, the data reading interface has a bit width of 16 bits. The currently read data can be considered as the lower 16 bits, and the previously read data can be considered as the higher 16 bits. Concatenating the two read data yields the first read data. This achieves joint verification based on the data read from the current address, combined with a portion of the data from the previous address, to verify the correctness of the cross-address concatenation logic. This mechanism can be enabled or disabled via a configuration switch.

[0059] In one embodiment of this disclosure, to further improve the scalability and versatility of the chip's debug interface verification, a debug verification proxy can be constructed and integrated into the verification environment. Calling this proxy enables the verification method of the chip's debug interface. Specifically, the debug verification proxy can define a configurable debug verification transaction object (referred to as a debug item) to describe the verification behavior of a single field. This transaction object can be configured with: field position information, data to be written, and interface enable control parameters, etc. The interface enable control parameters are used to indicate and control the verification behavior of the debug interface corresponding to the storage space to be verified. These enable control parameters support consistency checks for multiple debug interfaces.

[0060] The following example uses an Interface Debug Unit (IDU) as the device under test for verification. (Refer to...) Figure 4 , Figure 4This is a schematic diagram of the verification process for the debugging interface of a chip according to a specific embodiment of this disclosure, as shown below. Figure 4 As shown, in the embodiments disclosed herein, the first step is to build a verification environment. In the first step, a debug verification agent (which may be called debug_agent) is instantiated. The debug_agent includes debug_driver and debug_sequencer. The debug_driver is responsible for executing the specific field-level verification process of the chip's debug interface, and the debug_sequencer is responsible for distributing verification transaction objects (which may be called debug_item).

[0061] Next, the second step is executed: configuring debug_item. In the second step, the field position information of the fields in the current bit field to be verified can be configured (including the address information debug_addr to be checked, the field width debug_data_width, the field start position debug_data_stb, and the signal path inside the field debug_data_path), and the data to be written (called debug_data). After the configuration is completed, the third step is executed: sending sequence. In the third step, no functional stimulus is required. One debug_item constructed above is directly distributed through debug_sequencer. For example, taking address 0 as an example, the two debug_items to be distributed in the current bit field can be: transpose_rd_st_addr[14:0] and transpose_rd_en; Next, the fourth step is executed: debug_driver performs the corresponding debugging interface verification process for each debug_item. In the first step, debug_driver has already connected to IDU. In the fourth step, step 4.1 is executed first: debug_data is retrieved according to debug_data_path. The force is written to the specified field in the storage space (i.e., the current field to be verified); then step 4.2 is executed: wait for a preset number of beats, which can be the default of 2 beats. In actual execution, this number of beats can be adjusted according to the beat count; then, when the first debug interface to be verified is debug_csr, i.e., if debug_csr_en=1, step 4.3 is executed: read the first read data through debug_csr; when the first debug interface to be verified is debug_bus, i.e., if debug_bus_en=1, step 4.4 is executed: read the first read data through debug_bus; after executing step 4.4, step 4.5 is also executed: data alignment processing, i.e., determining whether the least significant bit of debug_bus is multiplexed as a clock signal, i.e., determining whether debug_bus_clk_en is 1. When debug_bus_clk_en=1, the clock multiplexing is adapted to shift the starting position of the first read data one bit to the left to obtain the first read data after data alignment.

[0062] After executing the fourth step, the fifth step is further executed: data comparison and inspection. In the fifth step, the consistency between the first read data and the data to be written is compared. Specifically, in the fifth step, when the first debug interface is debug_csr, the debug_csr interface has a bit width of 16 bits. It also checks whether debug_previous_addr_check_en is 1. If debug_previous_addr_check_en is 1 and the current address (considered as the lower 16 bits) of the first read data is not the initial address, a joint verification is performed on the previously read historical read data at the previous address (considered as the higher 16 bits) to verify the correctness of the cross-address concatenation logic. That is, the updated first read data is obtained by concatenating the currently obtained first read data with the previously read historical read data. Here, "not the initial address" means that the debug_csr interface has completed at least one valid access operation, and the current address has been updated to a valid access address, no longer the initial value at the time of reset.

[0063] In the fifth step, the first read data is compared with the data to be written. If they match, the current field is confirmed to have passed verification.

[0064] In step six, the field validation results are checked. It is determined whether all enabled first debug interfaces corresponding to the current field have passed the check. That is, each enabled first debug interface can be validated. After all enabled first debug interfaces have passed the validation, the current debug_item validation is considered complete. Then, proceed to step seven: validate the next debug_item, until all issued debug_items have been validated.

[0065] In this embodiment, for multi-interface access scenarios, interface enable control parameters (such as debug_bus_en and debug_csr_en mentioned above) can be introduced to control the verification behavior of different first debug interfaces respectively. By uniformly processing different debug interfaces under the same verification framework, verification of data consistency across multiple interfaces can be achieved.

[0066] In this embodiment, when it is determined whether all enabled first debugging interfaces corresponding to the current field have failed the check, an error can be reported. Other verification operations can also be enabled as needed (not shown in the figure). These other verification operations can be customized according to the scenario requirements. For example, they may include checking whether the interface enable control parameters are set incorrectly, and whether to return default data for invalid field position information.

[0067] In summary, the chip debugging interface verification method of this disclosure embodiment also incorporates the complex characteristics of the first debugging interface, such as the characteristic that there is a data splicing relationship between adjacent addresses and the characteristic that the least significant bit may be reused as a clock signal, to verify the debugging interface, thereby further improving the verification coverage of the first debugging interface.

[0068] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0069] Based on the same inventive concept, this disclosure also provides a verification device for a chip debugging interface. Figure 5 This is a schematic diagram of the structure of a verification device for a chip debugging interface proposed in this disclosure, as shown below. Figure 5 As shown, the device includes: a first determination module 510, a backdoor writing module 520, a front door reading module 530, a verification module 540, a second determination module 550, and a random output behavior verification module 560, wherein... The first determining module 510 is used to determine the current field to be verified, the field position information of the current field, and the data to be written in the storage space in the chip used to store state information. The backdoor writing module 520 is used to write data to be written to the backdoor of the current field according to the field position information. The front door read module 530 is used to read the first read data in the current field through the first debugging interface corresponding to the storage space after 2 cycles, based on the field position information. The verification module 540 is used to compare whether the first read data and the data to be written are consistent, and to determine that the current field has passed the verification when the first read data and the data to be written are consistent; The second determining module 550 is used to determine that the first debugging interface mapping verification is successful when all fields to be verified in the storage space corresponding to the first debugging interface have been verified.

[0070] The random output behavior verification module 560 is used for: Generate a random field location information, wherein the random field location information does not belong to the storage space corresponding to the first debugging interface. The field data is read based on the random field position information through the first debugging interface. If the read field data belongs to the preset default data, the verification of the default output behavior of the first debugging interface is confirmed to be successful. In some possible embodiments, the first determining module 510 is specifically used for: Determine the bit field to be verified in the storage space, and sort all fields included in the bit field to obtain the sorting result; The current field to be validated is determined based on its order from front to back in the sorting results.

[0071] In some possible embodiments, when the first debug interface is a debug bus interface, the device further includes: a data alignment processing module, used for: Identify whether the least significant bit of the first debug interface is multiplexed as a clock signal; When multiplexed as a clock signal, the starting position of the field reading the first read data is shifted one bit to the left.

[0072] In some possible embodiments, the front door readout module 530 is specifically used for: Determine whether the field width of the current field is greater than the interface width of the first debug interface; When the data is greater than the interface width, read the field data multiple times in the current field according to the field position information until the current field is read completely; The read data from multiple fields is concatenated to obtain the first read data.

[0073] In some possible embodiments, the verification module 540 is further configured to: If the first read data and the data to be written are inconsistent, determine whether the storage space still includes the corresponding second debugging interface; When a second debugging interface is included, the second readout data in the current field is read through the front door based on the field position information via the second debugging interface. Compare whether the second read data and the data to be written are consistent; If the second read data matches the data to be written, it is determined that the current field validation has failed.

[0074] In some possible embodiments, the device further includes: a wait-for-beat configuration module, for: The validation failed if the number of consecutive field counts exceeded the preset threshold. If the number of field validation failures exceeds the preset threshold consecutively, the number of beats will be increased by 2 beats to obtain the updated number of beats.

[0075] The chip debugging interface verification device provided in this embodiment can serve as the execution subject of the chip debugging interface verification method, thus enabling the chip debugging interface verification method to be implemented. Figure 5 The functions implemented are the same, so they will not be explained again here.

[0076] This disclosure also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, can implement the steps of the verification method for the debugging interface of the aforementioned chip.

[0077] This disclosure also proposes a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the verification method for the debugging interface of the aforementioned chip.

[0078] In summary, the above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0079] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0080] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0081] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

Claims

1. A method for verifying a chip's debug interface, characterized in that, include: In the storage space of the chip used to store state information, the current field to be verified, the field position information of the current field, and the data to be written are determined, wherein the data to be written of adjacent fields are different; The data to be written is written to the back door of the current field according to the field position information; After two cycles, the first read data in the current field is read through the first debugging interface corresponding to the storage space according to the field position information. Compare whether the first read data and the data to be written are consistent, and if the first read data and the data to be written are consistent, determine that the current field verification is successful; When all fields to be verified in the storage space corresponding to the first debugging interface pass the verification, it is determined that the mapping verification of the first debugging interface is successful. Generate a random field location information, wherein the random field location information does not belong to the storage space corresponding to the first debugging interface; The field data is read through the first debugging interface based on the random field position information; If the read field data belongs to the preset default data, it is determined that the default output behavior of the first debugging interface has been verified. When the first read data and the data to be written are inconsistent, determine whether the storage space also includes a corresponding second debugging interface; When the second debugging interface is included, the second readout data in the current field is read through the front door according to the field position information via the second debugging interface; Compare whether the second read data and the data to be written are consistent; If the second read data and the data to be written are consistent, it is determined that the current field verification fails.

2. The verification method for the chip's debugging interface as described in claim 1, characterized in that, The process of determining the current field to be verified includes: In the storage space, determine the bit field to be verified, and sort all fields included in the bit field to obtain the sorting result; The current field to be verified is determined based on the order from front to back in the sorting results.

3. The verification method for the chip's debugging interface as described in claim 1, characterized in that, When the first debugging interface is a debugging bus interface, before comparing whether the first read data and the data to be written are consistent, the method further includes: Identify whether the least significant bit of the first debugging interface is multiplexed as a clock signal; When multiplexed as a clock signal, the starting position of the field reading the first read data is shifted one bit to the left.

4. The verification method for the chip's debugging interface as described in claim 1, characterized in that, The step of reading the first read data from the current field through the first debugging interface corresponding to the storage space according to the field position information includes: Determine whether the field width of the current field is greater than the interface width of the first debugging interface; When the width is greater than the interface width, read the field data multiple times in the current field according to the field position information until the current field is read completely; The read data from multiple fields is concatenated to obtain the first read data.

5. The verification method for the debug interface of the chip as described in any one of claims 1-4, characterized in that, The method further includes: The validation failed if the number of consecutive field counts exceeded the preset threshold. If the number of field verifications fails for more than the preset threshold consecutively, the two beats are increased by one beat to obtain the updated beat count.

6. A verification device for a chip's debugging interface, characterized in that, include: The first determining module is used to determine, in the storage space in the chip used to store state information, the current field to be verified, the field position information of the current field and the data to be written, wherein the data to be written of adjacent fields are different; The backdoor writing module is used to write the data to be written into the backdoor of the current field according to the field position information; The front door readout module is used to read the first readout data in the current field through the first debugging interface corresponding to the storage space after 2 cycles, based on the field position information. The verification module is used to compare whether the first read data and the data to be written are consistent, and to determine that the current field verification is successful when the first read data and the data to be written are consistent; The second determining module is used to determine that the first debugging interface mapping verification is successful when all fields to be verified in the storage space corresponding to the first debugging interface have been verified successfully. The random output behavior verification module is used to generate a random field position information, wherein the random field position information does not belong to the storage space corresponding to the first debugging interface. The first debugging interface reads field data according to the random field position information. If the read field data belongs to the preset default data, it is determined that the default output behavior verification of the first debugging interface is successful. The verification module is further configured to determine whether the storage space includes a corresponding second debugging interface when the first read data and the data to be written are inconsistent. If the second debugging interface is included, the second read data in the current field is read through the second debugging interface according to the field position information. The second read data and the data to be written are compared to see if they are consistent. If the second read data and the data to be written are consistent, the current field verification is determined to be unsuccessful.

7. An electronic device, characterized in that, include: A memory, a processor, and computer-executable instructions stored in the memory and executable on the processor, wherein the computer-executable instructions, when executed by the processor, implement a verification method for a debug interface of the chip as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, enable the verification method of the debugging interface of the chip as described in any one of claims 1-5.

9. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the verification method for the debugging interface of the chip as described in any one of claims 1-5.

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