Method for configuring dma transfer parameters
By iteratively generating DMA transfer parameters from the input/output buffer list in the DMA communication system, the transfer problem when data addresses are discontinuous is solved, achieving efficient and compatible DMA transfer and reducing hardware design complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MONTAGE TECHNOLOGY CO LTD
- Filing Date
- 2025-01-23
- Publication Date
- 2026-07-24
Smart Images
Figure CN122450872A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of communication technology and relates to a parameter configuration method, particularly a method for configuring DMA transfer parameters. Background Technology
[0002] Direct Memory Access (DMA) allows certain hardware subsystems to access system memory directly without going through the Central Processing Unit (CPU). Currently, DMA is widely used in many fields, such as audio and video processing, network communication, and data storage.
[0003] When using DMA for data transfer, if the addresses of the data being transferred are consecutive, the device's hardware DMA module can easily implement the data transfer. However, this method is not user-friendly for software applications. How to implement DMA transfer when the data addresses are not consecutive has become one of the technical problems that relevant engineers urgently need to solve. Summary of the Invention
[0004] This application provides a method for configuring DMA transfer parameters, which enables DMA transfer whether the data addresses are continuous or discontinuous.
[0005] In a first aspect, embodiments of this application provide a method for configuring DMA transfer parameters. The method is applied to the first device in a DMA communication system including a first device and a second device. The first device includes an input buffer list and an output buffer list. The input buffer list includes multiple input data nodes, and the output buffer list includes multiple output data nodes. Each of the multiple input data nodes and multiple output data nodes corresponds to a memory block. Each input data node and each output data node stores information related to its corresponding memory block. The method includes performing one or more iterations on the input buffer list and the output buffer list through the first device, such that the total length of the memory blocks corresponding to the accessed input data nodes and the total length of the memory blocks corresponding to the accessed output data nodes reach the corresponding end total memory block length. Each iteration includes: starting from the input iteration start address and the output iteration... The starting address sequentially accesses the input data nodes in the input buffer list and the output data nodes in the output buffer list, obtaining information about the accessed input data nodes and output data nodes. Based on the information of the accessed input data nodes and output data nodes, the iteration stops when the accessed input data node meets the preset input target condition and the accessed output data node meets the preset output target condition. DMA transfer parameters corresponding to the iteration are generated based on the information of the accessed input data nodes and output data nodes in the iteration. The DMA transfer parameters corresponding to the iteration are sent to the hardware DMA module of the second device. It is determined whether the total length of the memory block corresponding to the input data node and / or the total length of the memory block corresponding to the output data node, which are processed by the first device to generate the DMA transfer parameters, is less than the corresponding end total memory block length. If the determination result is yes, the next iteration is executed.
[0006] In some implementations, the input target preset conditions include a first input preset condition and a second input preset condition. The first input preset condition is that the total length of the memory blocks corresponding to the accessed input data nodes is greater than or equal to a minimum data threshold. The second input preset condition is that the total length of the memory blocks corresponding to the accessed input data nodes reaches the final total memory block length. When an input data node accessed in one iteration meets either the first or the second input preset condition, it is determined that the accessed input data node meets the input target preset condition. The output target preset conditions include a first output preset condition and a second output preset condition. The first output preset condition is that the total length of the memory blocks corresponding to the accessed output data nodes is greater than or equal to a minimum data threshold. The second output preset condition is that the total length of the memory blocks corresponding to the accessed output data nodes reaches the final total memory block length. When an output data node accessed in one iteration meets either the first or the second output preset condition, it is determined that the accessed output data node meets the output target preset condition.
[0007] In some implementations, the input iteration start address for the next iteration is determined as follows: It is determined whether, among the input data nodes that meet the preset conditions of the input target in the previous iteration, there exists an input data node whose corresponding memory block length has not been fully processed by the first device. If yes, the starting address of the length of the unprocessed memory block in that input data node is used as the input iteration start address for the next iteration; otherwise, the input iteration start address for the next iteration is the address of the first input data node in the input cache list that has not been processed by the first device to generate the DMA transfer parameters. The output iteration start address for the next iteration is determined as follows: It is determined whether, among the output data nodes that meet the preset conditions of the output target in the previous iteration, there exists an output data node whose corresponding memory block length has not been fully processed by the first device. If yes, the starting address of the length of the unprocessed memory block in that output data node is used as the output iteration start address for the next iteration; otherwise, the output iteration start address for the next iteration is the address of the first output data node in the output cache list that has not been processed by the first device to generate the DMA transfer parameters.
[0008] In some implementations, the DMA transfer parameters include DMA input parameters and DMA output parameters, wherein the DMA input parameters include an input address and an input data length, and the DMA output parameters include an output address and an output data length.
[0009] In some implementations, generating the DMA transfer parameters corresponding to the first iteration based on the information of the input data nodes and output data nodes accessed in the first iteration includes: generating corresponding DMA input parameters based on whether the input data nodes accessed in the first iteration can be merged; and generating corresponding DMA output parameters based on whether the output data nodes accessed in the first iteration can be merged.
[0010] In some implementations, if the number of input data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the input data nodes accessed in a single iteration are contiguous, then the input data nodes accessed in a single iteration can be merged.
[0011] In some implementations, if the input data nodes accessed in the first iteration can be merged, generating the DMA input parameters includes: using the starting address of the memory block stored in the data input node corresponding to the input iteration start address of the first iteration as the input address in the DMA input parameters, and using the total length of the memory block corresponding to the merged input data node as the input data length in the DMA input parameters.
[0012] In some implementations, if the number of input data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the input data nodes accessed in a single iteration are not contiguous and conform to a specific physical page location, then the input data nodes accessed in a single iteration can be merged; the conformity to a specific physical page location means that the accessed input data nodes correspond to different physical pages, and the end address of the memory block corresponding to the preceding input data node is located at the end of its respective physical page, while the start address of the memory block corresponding to the following input data node is located at the beginning of its respective physical page.
[0013] In some implementations, if the input data nodes accessed in the first iteration can be merged, generating the DMA input parameters includes: mapping the memory blocks corresponding to the input data nodes accessed in the first iteration to a contiguous virtual address, using the virtual address corresponding to the start address of the memory block stored in the input data node corresponding to the input iteration start address of the first iteration as the input address in the DMA input parameters, and using the total length of the memory blocks corresponding to the merged input data nodes as the input data length in the DMA input parameters.
[0014] In some implementations, if the number of output data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the output data nodes accessed in a single iteration are contiguous, then the output data nodes accessed in a single iteration can be merged.
[0015] In some implementations, if the output data nodes accessed in the first iteration can be merged, generating the DMA output parameters includes: using the starting address of the memory block stored in the output data node corresponding to the output iteration start address of the first iteration as the output address in the DMA output parameters, and using the total length of the memory block corresponding to the merged output data node as the output data length in the DMA output parameters.
[0016] In some implementations, if the number of output data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the output data nodes accessed in a single iteration are not contiguous and conform to a specific physical page location, then the output data nodes accessed in a single iteration can be merged; the conformity to a specific physical page location means that the accessed output data nodes correspond to different physical pages, and the end address of the memory block corresponding to the previous output data node is located at the end of its physical page, while the start address of the memory block corresponding to the next output data node is located at the beginning of its physical page.
[0017] In some implementations, if the output data nodes accessed in the first iteration can be merged, generating the DMA output parameters includes: mapping the memory blocks corresponding to the output data nodes accessed in the first iteration to a contiguous virtual address, using the virtual address corresponding to the starting address of the memory block stored in the output data node corresponding to the output iteration start address of the first iteration as the output address in the DMA output parameters, and using the total length of the memory blocks corresponding to the merged output data nodes as the output data length in the DMA output parameters.
[0018] In some implementations, if the input data nodes and / or output data nodes accessed in a single iteration cannot be merged, and the total lengths of the memory blocks corresponding to the input data nodes and output data nodes accessed in a single iteration are different, then generating the DMA transfer parameters corresponding to the single iteration includes: using the starting address of the memory block stored in the input data node corresponding to the input iteration start address of the single iteration and the starting address of the memory block stored in the output data node corresponding to the output iteration start address as the input address in the DMA input parameters and the output address in the DMA output parameters, respectively; and using the smaller of the total length of the memory blocks corresponding to the input data nodes accessed in a single iteration and the total length of the memory blocks corresponding to the output data nodes as the input data length in the DMA input parameters and the output data length in the DMA output parameters.
[0019] In some implementations, if the input data nodes accessed in a single iteration cannot be merged, generating the DMA input parameters includes: if the total length of the memory blocks corresponding to the input data nodes accessed in a single iteration does not meet the DMA transfer requirements, generating the DMA input parameters based on the length information of the memory blocks that meet the DMA transfer requirements from the total length of the memory blocks corresponding to the input data nodes accessed in a single iteration; if the output data nodes accessed in a single iteration cannot be merged, generating the DMA output parameters includes: if the total length of the memory blocks corresponding to the output data nodes accessed in a single iteration does not meet the DMA transfer requirements, generating the DMA output parameters based on the length information of the memory blocks that meet the DMA transfer requirements from the total length of the memory blocks corresponding to the output data nodes accessed in a single iteration.
[0020] In some implementations, if the input data nodes accessed in the first iteration cannot be merged, generating the DMA input parameters includes: transferring the data in the memory block corresponding to the input data node accessed in the first iteration to an intermediate buffer, and generating the DMA input parameters according to the address of the intermediate buffer; generating the DMA output parameters includes: generating the DMA output parameters according to the address of the intermediate buffer.
[0021] As described above, based on the technical solution provided in this application, even if the hardware DMA module does not support scatterlist DMA, it can still achieve efficient DMA transfer when the data addresses are not contiguous, and has good compatibility and scalability. Attached Figure Description
[0022] Figure 1 The diagram shown is a schematic representation of the DMA communication system in an embodiment of this application.
[0023] Figure 2 The flowchart shown is a method for configuring DMA transfer parameters provided in an embodiment of this application. Detailed Implementation
[0024] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0025] In this application, the terms "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0026] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.
[0027] In some technical solutions, the device's hardware DMA module does not support scatterlists, but the host hardware supports an IOMMU (Input / Output Memory Management Unit). In these solutions, the IOMMU can map non-contiguous physical addresses that conform to certain rules to contiguous virtual addresses, which can be called I / O Virtual Addresses (IOVAs). During DMA transfer, the starting address and data length of the IOVA are configured to the hardware DMA module, which can then perform DMA transfers starting from the IOVA's starting address. However, in scenarios where physical addresses are non-contiguous and cannot be mapped to contiguous virtual addresses, the hardware DMA module struggles to operate efficiently.
[0028] In other technical solutions, the device's hardware DMA module supports scatterlists. In these solutions, before initiating a DMA transfer, the DMA transfer parameters for multiple memory blocks with non-contiguous physical addresses need to be batch configured to the device. The device then parses the DMA transfer parameters for each memory block sequentially before performing the DMA transfer. This approach increases the complexity of the hardware design.
[0029] To address at least the aforementioned problems, embodiments of this application provide a method for configuring DMA transfer parameters. The technical solutions in these embodiments will be described in detail below with reference to the accompanying drawings.
[0030] Figure 1 The diagram shown illustrates an overall implementation environment according to an embodiment of this application. Figure 1As shown, the DMA communication system includes a first device and a second device, which are communicatively connected. In some embodiments, the first device can be a host, such as a computer or server, and the second device can be any peripheral device containing a hardware DMA module, such as a network card, GPU (Graphics Processing Unit), encryption / decryption card, AI (Artificial Intelligence) accelerator card, etc.
[0031] The first device includes an input buffer list (input_buf_list) and an output buffer list (output_buf_list). The input buffer list includes multiple input data nodes, and the output buffer list includes multiple output data nodes. Each of the input and output data nodes corresponds to a memory block. The memory block corresponding to an input data node stores the data to be processed, and the memory block corresponding to an output data node stores the data processing result. Each input and output data node stores information related to its corresponding memory block, including the starting address (also called the "memory start address") and the length of the memory block. The memory blocks corresponding to adjacent input (or output) data nodes can be contiguous or non-contiguous. It is worth noting that "contiguous" or "non-contiguous" here can refer to either the physical address or the virtual address of the memory block; this application does not impose any restrictions on this.
[0032] In some implementations, the first device may include a DMA iterator for iteratively accessing input data nodes in the input buffer list and output data nodes in the output buffer list.
[0033] The second device may include a hardware DMA module and a data processing module. The hardware DMA module can be used to transfer data between the first device and the second device, and the data processing module can be used to process the data to be processed from the first device to generate a data processing result.
[0034] The first device can iterate through the input data nodes in the input buffer list and the output data nodes in the output buffer list once or multiple times. Each iteration may access some or all of the input data nodes and some or all of the output data nodes, and generate corresponding DMA transfer parameters.
[0035] The following describes the configuration method of the DMA transfer parameters of this application, which is applied to the first device.
[0036] Figure 2The flowchart shown is a method for configuring DMA transfer parameters provided in an embodiment of this application. It should be noted that... Figure 2 The diagram only shows one iteration of the process. The DMA transfer parameter configuration method provided in this application includes performing one or more iterations on the input buffer list and the output buffer list through a first device, so that the sum of the lengths of the memory blocks corresponding to the accessed input data nodes (hereinafter also referred to as "total length") and the sum of the lengths of the memory blocks corresponding to the accessed output data nodes reach the corresponding final total memory block length. Each iteration includes:
[0037] S21, access the input data nodes in the input buffer list and the output data nodes in the output buffer list sequentially from the input iteration start address and the output iteration start address, respectively, and obtain the information of the accessed input data nodes and output data nodes. During the first iteration, the input iteration start address is the address of the starting node of the input buffer list, and the output iteration start address is the address of the starting node of the output buffer list.
[0038] In some implementations, each iteration visits some or all of the input and output data nodes.
[0039] S22, based on the information of the accessed input data nodes and output data nodes, the iteration stops when the accessed input data node meets the preset conditions of the input target and the accessed output data node meets the preset conditions of the output target. Specifically, stopping the iteration may mean that the access to the input data nodes and output data nodes in the iteration ends.
[0040] In some implementations, the DMA iterator in the first device accesses input data nodes and output data nodes alternately. For example, it may first access two input data nodes, then access two output data nodes, and so on. When an accessed input data node meets the preset conditions of the input target, access to subsequent input data nodes is stopped; when an accessed output data node meets the preset conditions of the output target, the iteration stops.
[0041] In other implementations, the DMA iterator may first access the input data nodes sequentially until the accessed input data node meets the preset conditions of the input target, at which point access to the subsequent input data nodes is stopped. Then, the output data nodes are accessed sequentially, and access to the subsequent output data nodes is stopped when the accessed output data node meets the preset conditions of the output target. At this point, the iteration can be stopped.
[0042] In some implementations, the input target preset conditions include a first input preset condition and a second input preset condition. The first input preset condition is that the total length of the memory blocks corresponding to the accessed input data nodes is greater than or equal to a minimum data threshold; the second input preset condition is that the total length of the memory blocks corresponding to the accessed input data nodes has reached the end total memory block length (stop_len). This end total memory block length can be set based on the total length of the memory blocks corresponding to all input data nodes in the input buffer list and / or the total length of the memory blocks corresponding to all output data nodes in the output buffer list, or it can be set based on a specific business scenario; this application does not limit this. If an input data node accessed in one iteration meets either the first or second input preset condition, then the accessed input data node is considered to meet the input target preset condition.
[0043] In some implementations, the output target preset conditions include a first output preset condition and a second output preset condition. The first output preset condition is that the total length of the memory blocks corresponding to the accessed output data nodes is greater than or equal to a minimum data threshold; the second output preset condition is that the total length of the memory blocks corresponding to the accessed output data nodes has reached the final total memory block length. If an output data node accessed in one iteration meets either the first or second output preset condition, then the accessed output data node is considered to meet the output target preset condition.
[0044] S23, generate DMA transfer parameters corresponding to the first iteration based on the information of the input data nodes and output data nodes accessed in the first iteration. These DMA transfer parameters may include DMA input parameters and DMA output parameters.
[0045] In some implementations, DMA input parameters may include the starting address of the input data (input_dma_addr, also known as the "input address") and the length of the input memory block (input_dma_len, also known as the "input data length"), and DMA output parameters may include the starting address of the output data (output_dma_addr, also known as the "output address") and the length of the output memory block (output_dma_len, also known as the "output data length").
[0046] S24, the DMA transfer parameters corresponding to the first iteration are sent to the hardware DMA module of the second device. The hardware DMA module of the second device can perform data transfer between the first and second devices according to the DMA transfer parameters. The hardware DMA module can transfer the data (i.e., the data to be processed) in the memory block corresponding to the input data node accessed in the first iteration to the second device for processing according to the DMA input parameters, and transfer the corresponding data processing result to the memory block corresponding to the output data node accessed in the first iteration according to the DMA output parameters. In some embodiments, the input data length is equal to the output data length, and the input data length and output data length in the DMA transfer parameters corresponding to each DMA transfer are, for example, multiples of 16 bytes.
[0047] Specifically, the second device can read the data to be processed from a memory block with a starting address of input_dma_addr and a length of input_dma_len via a hardware DMA module, and process the read data to obtain the data processing result. Afterwards, the second device can write the data processing result to a memory block with a starting address of output_dma_addr and a length of output_dma_len via the hardware DMA module.
[0048] S25, determine whether the total length of the memory block corresponding to the input data node and / or the total length of the memory block corresponding to the output data node that generated the DMA transfer parameters through the first device is less than the corresponding end total memory block length. If yes, execute the next iteration; otherwise, end the process.
[0049] When performing the next iteration, the starting address of the input iteration and the starting address of the output iteration must be determined. Determining the starting address of the input iteration may include: determining whether, among the input data nodes that meet the preset conditions of the input target in the previous iteration, there exists an input data node whose corresponding memory block length has not been fully processed by the first device; if so, the starting address of the length of the unprocessed memory block in that input data node is used as the starting address of the input iteration for the next iteration; if not, the starting address of the input iteration for the next iteration is the address of the first input data node in the input buffer list that has not been processed by the first device to generate DMA transfer parameters. Similarly, determining the starting address of the output iteration for the next iteration may include: determining whether, among the output data nodes that meet the preset conditions of the output target in the previous iteration, there exists an output data node whose corresponding memory block length has not been fully processed by the first device; if so, the starting address of the length of the unprocessed memory block in that output data node is used as the starting address of the output iteration for the next iteration; if not, the starting address of the output iteration for the next iteration is the address of the first output data node in the output buffer list that has not been processed by the first device to generate DMA transfer parameters.
[0050] In some implementations, generating the DMA transfer parameters corresponding to the first iteration based on the information of the input data nodes and output data nodes accessed in the first iteration includes: generating corresponding DMA input parameters based on whether the input data nodes accessed in the first iteration can be merged; and generating corresponding DMA output parameters based on whether the output data nodes accessed in the first iteration can be merged.
[0051] For input data nodes, in some implementations, if the number of input data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the input data nodes accessed in a single iteration are contiguous, then the input data nodes accessed in a single iteration can be merged. In other implementations, if the number of input data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the input data nodes accessed in a single iteration are not contiguous and conform to a specific physical page location, then the input data nodes accessed in a single iteration can be merged. Here, conforming to a specific physical page location means that the accessed input data nodes correspond to different physical pages, and in two adjacent input data nodes, the end address of the memory block corresponding to the preceding input data node is located at the end of its corresponding physical page, and the start address of the memory block corresponding to the following input data node is located at the beginning of its corresponding physical page.
[0052] As mentioned earlier, each data node in the input and output data nodes stores the start address and length of the corresponding memory block. Based on the start address and length of the memory block stored in the accessed data node, the end address of the corresponding memory block can be obtained. Based on the end address of the memory block corresponding to the previous data node and the start address of the memory block corresponding to the next data node, it can be determined whether the memory blocks corresponding to the two adjacent data nodes are contiguous.
[0053] Similarly, for output data nodes, in some implementations, if the number of output data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the output data nodes accessed in a single iteration are contiguous, then the output data nodes accessed in a single iteration can be merged. In other implementations, if the number of output data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the output data nodes accessed in a single iteration are not contiguous and conform to a specific physical page location, then the output data nodes accessed in a single iteration can be merged. Here, conforming to a specific physical page location means that the accessed output data nodes correspond to different physical pages, and in two adjacent output data nodes, the end address of the memory block corresponding to the previous output data node is located at the end of its corresponding physical page, and the start address of the memory block corresponding to the next output data node is located at the beginning of its corresponding physical page.
[0054] For input data nodes, if the input data nodes accessed in the first iteration can be merged, the generation of DMA input parameters includes: taking the starting address of the memory block stored in the input data node corresponding to the input iteration start address of the first iteration as the input address in the DMA input parameters, and taking the total length of the memory block corresponding to the merged input data node as the input data length in the DMA input parameters.
[0055] For output data nodes, if the output data nodes accessed in the first iteration can be merged, the DMA output parameters are generated by: using the starting address of the memory block stored in the output data node corresponding to the output iteration start address of the first iteration as the output address in the DMA output parameters, and using the total length of the memory block corresponding to the merged output data node as the output data length in the DMA output parameters.
[0056] In other words, when the memory blocks corresponding to the m (m is an integer greater than or equal to 2) input data nodes accessed in a single iteration are consecutive, the data in these m input data nodes' memory blocks can be merged and transmitted. The input address in the DMA input parameters is the starting address of the memory block stored in the input data node corresponding to the input iteration start address of the single iteration, and the input data length is the sum of the lengths of the memory blocks corresponding to the m input data nodes. Similarly, when the memory blocks corresponding to the n (n is an integer greater than or equal to 2) output data nodes accessed in a single iteration are consecutive, the data in these n output data nodes' memory blocks can be merged and transmitted. The output address in the DMA output parameters is the starting address of the memory block stored in the output data node corresponding to the output iteration start address of the single iteration, and the output data length is the sum of the lengths of the memory blocks corresponding to the n output data nodes.
[0057] For example, as shown in Tables 1 and 2, the memory blocks corresponding to Node1 and Node2 in the input and output data nodes are contiguous, while the memory blocks corresponding to Node3 and Node2 are not contiguous. For the hardware DMA module, merging and transmitting the data in the memory blocks corresponding to Node1 and Node2 can achieve better transmission performance. The DMA transmission parameters corresponding to one iteration can be configured as follows:
[0058] input_dma_addr=0x10 0000, input_dma_len=0x2000;
[0059] output_dma_addr=0x80 0000, output_dma_len=0x2000.
[0060] Table 1 Example of Input Data Nodes
[0061] Input data nodes Node1 Node2 Node3 Starting address 0x10 0000 0x10 1000 0x10 2001 End address 0x10 0FFF 0x10 1FFF 0x10 2FFF length 0x1000 0x1000 0xFFF
[0062] Table 2 Example of Output Data Nodes
[0063] Output data node Node1 Node2 Node3 Starting address 0x80 0000 0x80 1000 0x80 2001 End address 0x80 0FFF 0x80 1FFF 0x80 2FFF length 0x1000 0x1000 0xFFF
[0064] The starting address of the input iteration and the starting address of the output iteration for the next iteration are the addresses of the input data node and the output data node Node3, respectively.
[0065] In some implementations, when the memory blocks corresponding to the m input data nodes accessed in a single iteration are not contiguous and the physical pages of the memory blocks corresponding to the m input data nodes meet a specific physical page location, the memory blocks corresponding to the m input data nodes are mapped to a contiguous virtual address. In this case, the input address in the generated DMA input parameters is the virtual address corresponding to the starting address of the memory block stored in the input data node corresponding to the input iteration start address of the single iteration, and the input data length is the sum of the lengths of the memory blocks corresponding to the m input data nodes. Similarly, when the memory blocks corresponding to the n output data nodes accessed in a single iteration are not contiguous and the physical pages of the memory blocks corresponding to the n output data nodes meet a specific physical page location, the memory blocks corresponding to the n output data nodes are mapped to a contiguous virtual address. In this case, the output address in the generated DMA output parameters is the virtual address corresponding to the starting address of the memory block stored in the output data node corresponding to the output iteration start address of the single iteration, and the output data length is the sum of the lengths of the memory blocks corresponding to the n output data nodes.
[0066] In other words, if the end address of the memory block corresponding to a data node (input data node or output data node) is the end address of a physical page, and the start address of the memory block corresponding to the next data node is the start address of another physical page, then the memory blocks corresponding to the first and next data nodes can be merged. During merging, multiple non-contiguous memory blocks can be mapped to a contiguous IOVA (Input / Output Virtual Address), and corresponding DMA transfer parameters can be generated based on the IOVA. The mapping relationship between IOVA and the addresses of the memory blocks of the data nodes needs to be written into the page table that the hardware DMA module can use before the DMA transfer is initiated.
[0067] For example, as shown in Tables 3, 4, and 5, assuming a 4K physical page size is used, the memory blocks corresponding to Node3 and Node4 in the input and output data nodes are not contiguous. The end address of the memory block corresponding to Node3 is the end of this physical page, and the start address of the memory block corresponding to Node4 is the start of another physical page. The memory blocks corresponding to Node3 and Node4 can be merged. The mapping relationship between the memory blocks of the input and output data nodes and IOVA is shown in Table 5. The DMA transfer parameters corresponding to one iteration can be configured as follows:
[0068] input_dma_addr=0x110 2001, input_dma_len=0x1000;
[0069] output_dma_addr=0x180 2001, output_dma_len=0x1000.
[0070] Table 3 Example of Input Data Nodes
[0071] Input data nodes Node3 Node4 Node5 Starting address 0x10 2001 0x10 5000 0x10 6000 End address 0x10 2FFF 0x10 5000 0x10 7FFF Data length 0xFFF 0x1 0x2000
[0072] Table 4 Example of Output Data Nodes
[0073] Output data node Node3 Node4 Node5 Starting address 0x80 2001 0x80 5000 0x80 6000 End address 0x80 2FFF 0x80 5000 0x80 6FFF Data length 0xFFF 0x1 0x1000
[0074] Table 5 Example of mapping relationship
[0075] IOVA Node address 0x110 2000 0x10 2000 0x110 3000 0x10 5000 0x180 2000 0x80 2000 0x180 3000 0x80 5000
[0076] The starting address of the input iteration and the starting address of the output iteration for the next iteration are the addresses of the input data node and the output data node Node5, respectively.
[0077] In some implementations, if the input data nodes and / or output data nodes accessed in a single iteration cannot be merged, and the total lengths of the memory blocks corresponding to the input data nodes and output data nodes accessed in a single iteration are different, then generating the DMA transfer parameters corresponding to the single iteration includes: using the starting address of the memory block stored in the input data node corresponding to the input iteration start address of the single iteration and the starting address of the memory block stored in the output data node corresponding to the output iteration start address as the input address in the DMA input parameters and the output address in the DMA output parameters, respectively; and using the smaller of the total length of the memory blocks corresponding to the input data nodes accessed in a single iteration and the total length of the memory blocks corresponding to the output data nodes as the input data length in the DMA input parameters and the output data length in the DMA output parameters.
[0078] For example, as shown in Tables 6 and 7, the memory blocks corresponding to Node5 and Node6 in the input data nodes and output data nodes are not contiguous and do not conform to the specific location of physical pages, and therefore cannot be merged.
[0079] Since the lengths of the memory blocks corresponding to the input data node Node5 and the output data node Node5 are different, the smaller memory block length (0x1000) is selected for transmission. The DMA transmission parameters for the first iteration can be configured as follows:
[0080] input_dma_addr = 0x106000, input_dma_len = 0x1000, the length of the memory block header corresponding to the input data node Node5 is 0x1000;
[0081] output_dma_addr = 0x806000, output_dma_len = 0x1000, the entire 0x1000 length of the memory block corresponding to the output data node Node5.
[0082] The second iteration begins with the unprocessed memory block of input data node Node5 and also with output data node Node6. The input iteration start address for the second iteration is the starting address of the last 0x1000 bytes of input data node Node5, and the output iteration start address is the starting address of output data node Node6. The DMA transfer parameters for the second iteration can be configured as follows:
[0083] input_dma_addr = 0x10 7000, input_dma_len = 0x1000, the length of the memory block corresponding to the input data node Node5 is 0x1000;
[0084] output_dma_addr = 0x80 7001, output_dma_len = 0x1000, the length of the memory block header corresponding to the output data node Node6 is 0x1000.
[0085] The third iteration begins with the input data node Node6 and the unprocessed memory block of the output data node Node6. The input iteration start address is the address of the input data node Node6, and the output iteration start address is the starting address of a 0x1000-character length from the end of the output data node Node6. The DMA transfer parameters for the third iteration can be configured as follows:
[0086] input_dma_addr = 0x10 8001, input_dma_len = 0x1000, the entire 0x1000 length of the memory block corresponding to the input data node Node6;
[0087] output_dma_addr = 0x80 8001, output_dma_len = 0x1000, the length of the memory block corresponding to the output data node Node6 is 0x1000.
[0088] Table 6 Example of Input Data Nodes
[0089] Input data nodes Node5 Node6 Node7 Starting address 0x10 6000 0x10 8001 0x10 a001 End address 0x10 7FFF 0x10 9000 0x10 b001 length 0x2000 0x1000 0x1001
[0090] Table 7 Example of Output Data
[0091] Output data node Node5 Node6 Node7 Starting address 0x80 6000 0x80 7001 0x80 a001 End address 0x80 6FFF 0x80 9000 0x80 b001 length 0x1000 0x2000 0x1001
[0092] In some implementations, if the input data nodes accessed in a single iteration cannot be merged, generating the DMA input parameters includes: if the total length of the memory blocks corresponding to the input data nodes accessed in a single iteration does not meet the DMA transfer requirements, then generating the DMA input parameters based on the length information of the memory blocks that meet the DMA transfer requirements from the total length of the memory blocks corresponding to the input data nodes accessed in a single iteration. The DMA transfer requirements refer to the alignment of the data address and the length of the data transmitted by the DMA transfer parameters. For example, the length of the memory block that meets the requirements of the data processing module and / or DMA transfer is a multiple of 16 bytes.
[0093] In some implementations, if the output data nodes accessed in the first iteration cannot be merged, the generation of DMA output parameters includes: if the total length of the memory blocks corresponding to the output data nodes accessed in the first iteration does not meet the DMA transfer requirements, then generating DMA output parameters based on the length information of the memory blocks that meet the DMA transfer requirements from the total length of the memory blocks corresponding to the output data nodes accessed in the first iteration.
[0094] Specifically, if the total length of the memory block corresponding to an input data node does not meet the DMA transfer requirements, then the input start iteration address of the first iteration is used as the input address in the DMA input parameters, and the length of the memory block that meets the DMA transfer requirements out of the total length of the memory block corresponding to the input data node is used as the input data length in the DMA input parameters; if the total length of the memory block corresponding to an output data node does not meet the DMA transfer requirements, then the output start iteration address of the first iteration is used as the output address in the DMA output parameters, and the length of the memory block that meets the DMA transfer requirements out of the total length of the memory block corresponding to the output data node is used as the output data length in the DMA output parameters.
[0095] If the input data nodes accessed in the first iteration cannot be merged, generating DMA input parameters includes: transferring the data in the memory block corresponding to the input data nodes accessed in the first iteration to an intermediate buffer, and generating DMA input parameters based on the address of the intermediate buffer.
[0096] If the output data nodes accessed in the first iteration cannot be merged, the DMA output parameters are generated by generating DMA output parameters based on the address of the intermediate buffer.
[0097] After generating DMA output parameters based on the address of the intermediate buffer, the hardware DMA module can transmit the corresponding data processing results to the intermediate buffer according to the DMA output parameters. The first device can then transmit the data processing results in the intermediate buffer to the output data node accessed in the first iteration.
[0098] The intermediate buffer is, for example, a segment of memory in the first device that meets the DMA parameter requirements.
[0099] For example, as shown in Tables 8 and 9, if the minimum data threshold is 0x1000 bytes, the memory blocks corresponding to Node7 and Node8 in the input and output data nodes cannot be merged. The length of the memory block corresponding to Node7 in both the input and output data nodes is 0x1001, which is greater than the minimum data threshold and does not meet the DMA transfer requirements (assuming that in this example, the data (or memory block) length of the node must be an integer multiple of 16 bytes). This example will involve two iterations:
[0100] The DMA transfer parameters for the first iteration can be configured as follows:
[0101] input_dma_addr = 0x10 a001, input_dma_len = 0x1000, the length of the memory block corresponding to the input data node Node7 is 0x1000 (0x1000 is a multiple of 16 bytes, which meets the DMA transfer requirements);
[0102] output_dma_addr = 0x80 a001, output_dma_len = 0x1000, the length of the memory block corresponding to the output data node Node7 is 0x1000.
[0103] After the first iteration, there is a remaining 1 byte in the memory block corresponding to Node7 in both the input and output data nodes, and Node7 and Node8 cannot be merged. This 1 byte needs to be configured in the second iteration.
[0104] In the second iteration, a memory block of length 0x1000 is allocated in the first device as an intermediate buffer (dma_cp_buf), and the starting address of this intermediate buffer is aligned to 0x1000, for example, 0x4000 0000. The remaining 1 byte of data in the memory block corresponding to input data node Node7 is output to the intermediate buffer, and all data of length 0xfff in the memory block corresponding to input data node Node8 is output to the intermediate buffer. The address of the intermediate buffer is used as the input and output address for the DMA transfer. The DMA transfer parameters can be configured as follows:
[0105] input_dma_addr=0x4000 0000, input_dma_len=0x1000;
[0106] output_dma_addr=0x4000 0000, output_dma_len=0x1000.
[0107] After the data processing module of the second device finishes processing the data, it puts the corresponding data processing result back into the intermediate buffer. The first device reads 1 byte of data from the intermediate buffer into the memory block corresponding to the output data node Node7 of the output buffer list at address 0x80 b001, and reads the remaining 0xfff bytes of data in the intermediate buffer into the memory block corresponding to the output data node Node8 of the output buffer list.
[0108] Table 8 Example of Input Data Nodes
[0109] Input data nodes Node7 Node8 Starting address 0x10 a001 0x10 c000 End address 0x10 b001 0x10 cffe length 0x1001 0xfff
[0110] Table 9 Example of Input Data Nodes
[0111] Output data node Node7 Node8 Starting address 0x80 a001 0x80 c000 End address 0x80 b001 0x80 cffe length 0x1001 0xfff
[0112] In some implementations, intermediate buffers may be used only during the input or output process to increase throughput.
[0113] For example, as shown in Tables 10 and 11, Node9 in the input data node can be used directly during the input process, and an intermediate buffer can be used during the output process. Specifically, the starting address of the memory block corresponding to the input data node Node9 is used as the input address in the DMA input parameters, and the starting address of the intermediate buffer is used as the output address in the DMA output parameters. The DMA transfer parameters can be configured as follows:
[0114] input_dma_addr=0x11 0000, input_dma_len=0x3000;
[0115] output_dma_addr=0x4000 0000, output_dma_len=0x3000.
[0116] After the data processing module of the second device finishes processing the data, it puts the corresponding data processing result back into the intermediate buffer. The first device sequentially reads 0xfff bytes of data from the intermediate buffer into the memory block corresponding to the output data node Node9 of the output buffer list, reads 0xfff bytes of data from the intermediate buffer into the memory block corresponding to the output data node Node10 of the output buffer list, reads 0xfff bytes of data from the intermediate buffer into the memory block corresponding to the output data node Node11 of the output buffer list, and reads 0x3 bytes of data from the intermediate buffer into the memory block corresponding to the output data node Node12 of the output buffer list.
[0117] Table 10. Example of Input Data Nodes
[0118] Input data nodes Node9 Starting address 0x11 0000 End address 0x11 2FFF Data length 0x3000
[0119] Table 11. Example of Output Data Nodes
[0120] Output data node Node9 Node10 Node11 Node12 Starting address 0x81 0000 0x81 1000 0x81 2000 0x81 3000 End address 0x81 0ffe 0x81 1ffe 0x81 2ffe 0x81 3002 Data length 0xfff 0xfff 0xfff 0x3
[0121] In some implementations, the maximum size (DMA_CP_BUF_MAX_LEN) and / or minimum size (DMA_CP_BUF_MIN_LEN) of the intermediate buffer are determined based on the bus width, memory size, hardware processing power, and / or task descriptors. The minimum data threshold may be equal to the minimum size of the intermediate buffer.
[0122] If the intermediate buffer is too large, it will waste memory on the first device and may even lead to memory allocation failures. In addition, if the intermediate buffer is too large, the time required to pass data from the input data node to the intermediate buffer or from the intermediate buffer to the output data node may be too long, resulting in the second device's computing power not being fully utilized, which is detrimental to the operation of the entire pipeline.
[0123] If the intermediate buffer size is too small, it will incur additional overhead, thereby reducing the effective throughput of the hardware. Specifically, when the first device initiates a task request to the second device, it needs to configure the second device by setting a request descriptor to tell the second device what needs to be done. The request descriptor may be, for example, a task type of SM4 CBC, key, IV, DMA configuration information, etc.
[0124] After the second device completes the request, it needs to inform the first device of the result descriptor, such as ivout or status. Assume that both the request descriptor tx_desc and the result descriptor rx_desc are 512 bytes in size, totaling 1KB. This 1KB is auxiliary data relative to the effective data transferred via DMA; frequent transfers will incur additional overhead, thus reducing the effective throughput of the hardware. To address this issue, in this embodiment, the minimum size of the intermediate buffer can be determined based on the bus width, memory size, hardware processing power, and / or task descriptor to increase effective throughput.
[0125] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A method for configuring DMA transfer parameters, characterized in that, The method is applied to the first device in a DMA communication system including a first device and a second device. The first device includes an input buffer list and an output buffer list. The input buffer list includes multiple input data nodes, and the output buffer list includes multiple output data nodes. Each of the multiple input data nodes and multiple output data nodes corresponds to a memory block. Each input data node and each output data node stores information related to the corresponding memory block. The method includes performing one or more iterations on the input buffer list and the output buffer list through the first device, so that the total length of the memory blocks corresponding to the accessed input data nodes and the total length of the memory blocks corresponding to the accessed output data nodes reach the corresponding final total memory block length. Each iteration includes: The input data nodes in the input buffer list and the output data nodes in the output buffer list are accessed sequentially from the input iteration start address and the output iteration start address, respectively, and the information of the accessed input data nodes and output data nodes is obtained. Based on the information of the accessed input data nodes and output data nodes, the iteration stops when the accessed input data node meets the preset conditions of the input target and the accessed output data node meets the preset conditions of the output target. The DMA transfer parameters corresponding to the first iteration are generated based on the information of the input data nodes and output data nodes accessed in the first iteration. Send the DMA transfer parameters corresponding to the first iteration to the hardware DMA module of the second device; Determine whether the total length of the memory block corresponding to the input data node and / or the total length of the memory block corresponding to the output data node that generated the DMA transfer parameters through the first device is less than the corresponding end total memory block length, and execute the next iteration if the determination result is yes.
2. The method according to claim 1, characterized in that, The input target preset conditions include a first input preset condition and a second input preset condition. The first input preset condition is that the total length of the memory block corresponding to the accessed input data node is greater than or equal to the minimum data threshold. The second input preset condition is that the total length of the memory block corresponding to the accessed input data node reaches the end total memory block length. When the accessed input data node in one iteration meets the first input preset condition or the second input preset condition, it is determined that the accessed input data node meets the input target preset condition. The output target preset conditions include a first output preset condition and a second output preset condition. The first output preset condition is that the total length of the memory block corresponding to the accessed output data node is greater than or equal to the minimum data threshold. The second output preset condition is that the total length of the memory block corresponding to the accessed output data node reaches the end total memory block length. When the accessed output data node in one iteration meets the first output preset condition or the second output preset condition, it is determined that the accessed output data node meets the output target preset condition.
3. The method according to claim 1, characterized in that, The input iteration start address for the next iteration is determined as follows: It is determined whether, among the input data nodes that meet the preset conditions of the input target in the previous iteration, there exists an input data node whose corresponding memory block length has not been fully processed by the first device. If so, the starting address of the length of the unprocessed memory block in that input data node is taken as the input iteration start address for the next iteration. If not, the input iteration start address for the next iteration is the address of the first input data node in the input cache list that has not been processed by the first device to generate the DMA transfer parameters. The starting address of the output iteration for the next iteration is determined as follows: It is determined whether, among the output data nodes that meet the preset conditions of the output target in the previous iteration, there exists an output data node whose corresponding memory block length has not been fully processed by the first device. If so, the starting address of the length of the unprocessed memory block in that output data node is taken as the starting address of the output iteration for the next iteration. If not, the starting address of the output iteration for the next iteration is the address of the first output data node in the output cache list that has not been processed by the first device to generate the DMA transfer parameters.
4. The method according to claim 1, characterized in that, The DMA transfer parameters include DMA input parameters and DMA output parameters. The DMA input parameters include the input address and the input data length, and the DMA output parameters include the output address and the output data length.
5. The method according to claim 4, characterized in that, The DMA transfer parameters for the first iteration are generated based on the information of the input and output data nodes accessed during the first iteration, including: Based on whether the input data nodes accessed in the first iteration can be merged, the corresponding DMA input parameters are generated. The corresponding DMA output parameters are generated based on whether the output data nodes accessed in the first iteration can be merged.
6. The method according to claim 5, characterized in that, If the number of input data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the input data nodes accessed in a single iteration are contiguous, then the input data nodes accessed in a single iteration can be merged.
7. The method according to claim 6, characterized in that, If the input data nodes accessed in the first iteration can be merged, then generating the DMA input parameters includes: taking the starting address of the memory block stored in the data input node corresponding to the input iteration start address of the first iteration as the input address in the DMA input parameters, and taking the total length of the memory block corresponding to the merged input data node as the input data length in the DMA input parameters.
8. The method according to claim 5, characterized in that, If the number of input data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the input data nodes accessed in a single iteration are not contiguous and conform to a specific physical page position, then the input data nodes accessed in a single iteration can be merged; the conformity to a specific physical page position means that the accessed input data nodes correspond to different physical pages, and the end address of the memory block corresponding to the first input data node is located at the end of its physical page, while the start address of the memory block corresponding to the second input data node is located at the beginning of its physical page.
9. The method according to claim 8, characterized in that, If the input data nodes accessed in the first iteration can be merged, then generating the DMA input parameters includes: mapping the memory blocks corresponding to the input data nodes accessed in the first iteration to a contiguous virtual address, using the virtual address corresponding to the starting address of the memory block stored in the input data node corresponding to the input iteration start address of the first iteration as the input address in the DMA input parameters, and using the total length of the memory blocks corresponding to the merged input data nodes as the input data length in the DMA input parameters.
10. The method according to claim 5, characterized in that, If the number of output data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the output data nodes accessed in a single iteration are contiguous, then the output data nodes accessed in a single iteration can be merged.
11. The method according to claim 10, characterized in that, If the output data nodes accessed in the first iteration can be merged, then generating the DMA output parameters includes: taking the starting address of the memory block stored in the output data node corresponding to the output iteration start address of the first iteration as the output address in the DMA output parameters, and taking the total length of the memory block corresponding to the merged output data node as the output data length in the DMA output parameters.
12. The method according to claim 5, characterized in that, If the number of output data nodes accessed in a single iteration is greater than or equal to 2, and the memory blocks corresponding to the output data nodes accessed in a single iteration are not contiguous and conform to a specific physical page position, then the output data nodes accessed in a single iteration can be merged; the conformity to a specific physical page position means that the accessed output data nodes correspond to different physical pages, and the end address of the memory block corresponding to the first output data node is located at the end of its physical page, while the start address of the memory block corresponding to the second output data node is located at the beginning of its physical page.
13. The method according to claim 12, characterized in that, If the output data nodes accessed in the first iteration can be merged, then generating the DMA output parameters includes: mapping the memory blocks corresponding to the output data nodes accessed in the first iteration to a continuous virtual address, using the virtual address corresponding to the starting address of the memory block stored in the output data node corresponding to the output iteration start address of the first iteration as the output address in the DMA output parameters, and using the total length of the memory blocks corresponding to the merged output data nodes as the output data length in the DMA output parameters.
14. The method according to claim 5, characterized in that, If the input data nodes and / or output data nodes accessed in a single iteration cannot be merged, and the total lengths of the memory blocks corresponding to the input data nodes and output data nodes accessed in a single iteration are different, then generating the DMA transfer parameters corresponding to the single iteration includes: using the starting address of the memory block stored in the input data node corresponding to the input iteration start address of the single iteration and the starting address of the memory block stored in the output data node corresponding to the output iteration start address as the input address in the DMA input parameters and the output address in the DMA output parameters, respectively; and using the smaller of the total length of the memory blocks corresponding to the input data nodes accessed in a single iteration and the total length of the memory blocks corresponding to the output data nodes as the input data length in the DMA input parameters and the output data length in the DMA output parameters.
15. The method according to claim 5, characterized in that, If the input data nodes accessed in the first iteration cannot be merged, the generation of the DMA input parameters includes: if the total length of the memory blocks corresponding to the input data nodes accessed in the first iteration does not meet the DMA transfer requirements, the DMA input parameters are generated based on the length information of the memory blocks that meet the DMA transfer requirements from the total length of the memory blocks corresponding to the input data nodes accessed in the first iteration. If the output data nodes accessed in the first iteration cannot be merged, the generation of the DMA output parameters includes: if the total length of the memory blocks corresponding to the output data nodes accessed in the first iteration does not meet the DMA transfer requirements, the DMA output parameters are generated based on the length information of the memory blocks that meet the DMA transfer requirements from the total length of the memory blocks corresponding to the output data nodes accessed in the first iteration.
16. The method according to claim 5, characterized in that, If the input data nodes accessed in the first iteration cannot be merged, generating the DMA input parameters includes: transferring the data in the memory block corresponding to the input data nodes accessed in the first iteration to an intermediate buffer, and generating the DMA input parameters according to the address of the intermediate buffer; generating the DMA output parameters includes: generating the DMA output parameters according to the address of the intermediate buffer.