Data processing method, device, equipment, medium, program product and chip

By working together with the first and second processors, the problems of insufficient data processing efficiency and accuracy in wireless communication are solved, thereby accelerating the data processing process and improving system performance. This technology is suitable for software-defined radio communication systems.

CN122450889APending Publication Date: 2026-07-24BEIJING X RING TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
BEIJING X RING TECHNOLOGY CO LTD
Filing Date
2026-03-31
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

In the field of wireless communication, the efficiency and accuracy of data processing are insufficient to meet the requirements of real-time performance and quality. In particular, complex computational processes such as Fast Fourier Transform, Inverse Fast Fourier Transform, and Hartley Transform lead to insufficient performance of communication systems.

Method used

By introducing the collaborative work of a first processor and a second processor into the data processing device, the first processor is responsible for simple data processing, while the second processor is responsible for complex data processing. This achieves synchronous execution, reduces the computational burden on the first processor, and enables the second processor to perform complex operations such as fast Fourier transform, fast inverse Fourier transform, and Hartley transform.

Benefits of technology

It improves the applicability and real-time performance of the data processing device, enabling it to operate stably under diverse clock frequencies and voltages, thus meeting the real-time and quality requirements of software-defined radio communication systems.

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Abstract

The present disclosure relates to a data processing method, device, equipment, medium, program product and chip. The data processing method comprises: a first processor sends a data processing instruction to a second processor through a bus; the first processor reads first data in a memory and performs a first data processing process on the first data; the second processor reads second data in the memory in response to receiving the data processing instruction and performs a second data processing process on the second data. The first data processing process and the second data processing process can be synchronously executed by the first processor and the second processor. By selecting and designing the second processor, the second data processing process with higher complexity in the preset data processing process can be allocated to the second processor for execution, so as to share the operation pressure of the first processor, accelerate the preset data processing process, and improve the applicability and real-time performance of the system.
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