Clock delay estimation method based on physical perception, electronic device and storage medium

Abstract

The application provides a clock delay estimation method based on physical perception, an electronic device and a storage medium, and relates to the technical field of integrated circuits.The method comprises the following steps: identifying all clock sources and registers driven by the clock sources from a gate netlist, obtaining clock groups and fan-out numbers of the clock sources; performing virtual layout processing on each clock group respectively to obtain estimated coordinates of the clock sources and each register; calculating driving distances from the clock sources to each register driven by the clock sources according to the estimated coordinates of the clock sources and each register; and calculating clock path delay estimation values of the clock sources by using a preset estimation model according to the driving distances and the fan-out numbers of the clock sources, wherein the estimation model is a mathematical model fitted with the fan-out numbers and the driving distances as independent variables and the clock path delay estimation values as a dependent variable.The scheme can accurately estimate the clock delay at the logic synthesis stage, so as to reduce the deviation between the estimation result and the actual physical implementation.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a clock delay estimation method based on physical perception, an electronic device, and a storage medium. Background Technology

[0002] In the digital integrated circuit design flow, logic synthesis is the core step in converting register-transfer level descriptions into gate-level netlists. During logic synthesis, clock delay estimation is performed using logic synthesis tools to generate optimized circuit structures that meet timing, area, and power constraints.

[0003] To estimate clock delays, existing logic synthesis tools generally idealize the clock network, assuming an ideal clock and a zero or globally fixed delay, completely ignoring the actual physical characteristics of the clock network. Previously, clock delay estimates under this ideal assumption were sufficient for most requirements. However, as process nodes continue to evolve towards deeper submicron levels, clock signals need to propagate through clock tree networks to numerous registers, and the propagation path length and load significantly affect clock arrival times. Therefore, when the chip area is large or registers are unevenly distributed, the clock delay errors estimated by existing logic synthesis tools will amplify exponentially. This significant error will cause a disconnect between front-end and back-end design in logic synthesis and physical implementation, leading to frequent timing violations in the generated gate netlist after placement and routing, forcing design teams to perform multiple rounds of iterative debugging and severely extending the design cycle.

[0004] Therefore, how to accurately and effectively estimate clock delays during the logic synthesis stage to reduce the deviation between the estimated results and the actual physical implementation, thereby reducing the number of front-end and back-end design iterations, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The purpose of this application is to provide a physically-aware clock delay estimation method, electronic device, and storage medium that can accurately and effectively estimate clock delay during the logic synthesis stage, thereby reducing the deviation between the estimation result and the actual physical implementation and reducing the number of front-end and back-end design iterations.

[0006] This application is implemented as follows: Firstly, this application provides a physical sensing-based clock delay estimation method, comprising the following steps: identifying all clock sources and their driven registers from a gate netlist to obtain the number of clock groups and the fan-out of each clock source, wherein each clock group contains one clock source and all registers driven by that clock source. Performing virtual layout processing on each clock group to obtain the estimated coordinates of the clock sources and each register in each clock group. Calculating the driving distance from each clock source to each register it drives based on the estimated coordinates of the clock sources and each register in each clock group. Calculating the estimated clock path delay value of each clock source using a preset estimation model based on the driving distance from each clock source to each register it drives and the fan-out of each clock source, wherein the estimation model is a mathematical model fitted with the fan-out of the clock source and the driving distance from the clock source to each register it drives as independent variables, and the estimated clock path delay value of the clock source as the dependent variable.

[0007] In some implementations, virtual layout processing includes using a preset global layout algorithm to pre-allocate the physical locations of clock sources and registers in clock groups, or receiving user-defined virtual layout coordinates.

[0008] In some implementations, the mathematical expression for the estimation model is: Delay = Factor × (k1 × Distance + k2 × Fanout). Where Delay is the estimated clock path delay, Distance is the average spatial distance from the clock source to all registers it drives, Fanout is the fanout number of the clock source, k1 and k2 are weighting coefficients related to the technology library, and Factor is a dynamic estimation factor determined based on the dispersion of the register distribution.

[0009] In some implementations, the weight coefficients k1 and k2 are obtained through the following pre-calibration steps: select multiple design modules with different sizes and layout characteristics as test samples; record the actual clock path delay of each test sample after physical synthesis, as well as the corresponding average spatial distance and fan-out number; set the dynamic estimation factor to 1, and perform linear regression fitting on the actual clock path delay, as well as the corresponding average spatial distance and fan-out number to obtain the weight coefficients k1 and k2.

[0010] In some implementations, the dynamic estimation factor is calculated as: Factor = Fmax - (Fmax - Fmin) × A; where Fmin is the lower limit of the estimation factor when the register distribution is completely concentrated, Fmax is the upper limit of the estimation factor when the register distribution is completely dispersed, and A is the physical distribution clustering value of all registers in the clock group, ranging from 0 to 1.

[0011] In some implementations, the formula for calculating the physical distribution clustering value of all registers within a clock group is: A = 1 / (1 + bbox_area / chip_area); where bbox_area = (Xmax - Xmin) × (Ymax - Ymin), Xmax and Xmin are the maximum and minimum x-coordinates of the estimated coordinates of the registers within the same clock group, Ymax and Ymin are the maximum and minimum y-coordinates of the estimated coordinates of the registers within the same clock group, and chip_area is the total area of ​​the design module described by the current gate netlist.

[0012] In some implementations, Fmin ranges from 0.6 to 0.7, and Fmax ranges from 1.8 to 2.0.

[0013] In some implementations, the clock delay estimation method further includes: inputting the calculated clock path delay estimates of each clock source into the static timing analysis engine of the logic synthesis tool to replace the original ideal clock assumptions or fixed delay estimates, and then re-performing the timing analysis.

[0014] In a second aspect, this application provides an electronic device including a memory for storing one or more programs; a processor; and when the one or more programs are executed by the processor, implementing the clock delay estimation method as described in any one of the first aspects above.

[0015] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the clock delay estimation method as described in any one of the first aspects above.

[0016] Compared with the prior art, this application has at least the following advantages or beneficial effects: First, this application identifies all clock sources and their driven registers from the gate-level netlist and constructs clock groups, thereby structuring the netlist without physical location information according to clock driving relationships. Based on this, virtual placement processing is performed on each clock group to quickly obtain the estimated coordinates of the clock sources and each register in each clock group, enabling the perception of the actual spatial distribution relationship between clock sources and registers during the logic synthesis stage.

[0017] Next, this application calculates the driving distance from each clock source to each register it drives based on the estimated coordinates within the same clock group. Combined with the pre-statistical fan-out number of each clock source, a mathematical model is used to fit the driving distance and fan-out number as independent variables and the estimated clock path delay as the dependent variable to calculate the estimated clock path delay value of each clock source. This allows the delay estimation to simultaneously reflect the impact of the two core factors: physical distance and load scale.

[0018] Therefore, this application can obtain a clock path delay estimate that is closer to the physical reality during the logic synthesis stage, effectively reducing the deviation between the estimation result and the actual physical implementation. Due to the significantly improved estimation accuracy, the netlist generated based on this estimate will have higher timing convergence in the subsequent physical implementation, thereby reducing the number of iterations between logic synthesis and placement and routing, shortening the design cycle, and reducing R&D costs. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of an embodiment of a clock delay estimation method based on physical perception according to this application; Figure 2 This is a flowchart illustrating the steps for determining the weighting coefficients k1 and k2 in the embodiments of this application. Figure 3 This is a flowchart of yet another embodiment of a clock delay estimation method based on physical perception according to this application; Figure 4 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0021] Icons: 201, Processor; 202, Memory; 203, Communication Interface. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0023] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0024] Traditional logic synthesis tools typically employ an ideal clock assumption for clock delay estimation during static timing analysis. Specifically, these tools usually assume that the clock signal arrives at all timing units simultaneously, meaning the clock path delay is zero, or they assign it a global, fixed estimate. This idealized approach ignores the actual physical characteristics of the clock network as a large-scale distributed resistive-capacitive network. This network is a distributed network composed of the parasitic resistance and capacitance of interconnects.

[0025] As process nodes continue to evolve towards deeper submicron levels, the parasitic parameters of interconnects have an increasingly significant impact on signal propagation delay. In practical physical designs, clock signals need to propagate from the clock source to thousands of registers through a carefully constructed clock tree network. The length of this propagation path, the number of buffer stages traversed, and the load on each branch all significantly affect the clock arrival time. However, because the logic synthesis stage completely lacks physical topology information about the clock network, it is impossible to predict the drive distance of the clock source, the dispersion of register distribution, and the differences in fan-out load, making it difficult to accurately assess clock path delay.

[0026] The significant discrepancy between the "ideal clock" assumption during logic synthesis and the "non-ideal clock" reality during physical implementation leads to a severe disconnect between front-end and back-end design. Timing analysis results after logic synthesis are often overly optimistic, causing frequent setup and hold time violations in the generated gate netlist after place-and-route. Design teams are forced to invest considerable effort in multiple rounds of iterative debugging following logic synthesis and place-and-route, severely prolonging the design cycle and increasing development costs.

[0027] To address these issues, designers often manually set a global fixed delay value for the clock network (e.g., 10%-20% of the clock cycle) based on past project experience. However, setting such empirical values ​​relies heavily on the engineer's personal judgment, and the applicability of the same empirical value cannot be guaranteed across different projects or process nodes. For teams lacking similar project experience, the risk of missetting is extremely high. In modern system-on-a-chip (SoC), the register distribution density and drive distance vary significantly across different clock domains (e.g., CPU cores, GPUs, peripheral interfaces). Using a globally uniform fixed delay value cannot reflect this internal heterogeneity, inevitably leading to distorted timing estimates for some modules. Furthermore, during logic synthesis, engineers may perform multiple netlist optimizations (e.g., register copying, gate-level splitting), causing the number and distribution of registers to change dynamically. Fixed empirical values ​​cannot track these changes, causing timing estimates to deviate further from reality. Moreover, setting empirical values ​​is essentially "guessing," and their accuracy can only be verified after the physical design is completed. If the deviation is too large, the entire "logic synthesis-placement and routing" process needs to be restarted.

[0028] Some design flows employ a "physical implementation first, then back-annotation correction" approach, where the actual clock delay is extracted after placement and routing and fed back to the logic synthesis stage for calibration. However, this method has a long iteration cycle and low design efficiency; completing a full placement and routing, clock tree synthesis, parameter extraction, and timing analysis typically takes several hours to several days. Furthermore, each iteration significantly extends the entire design cycle, severely hindering project progress. Additionally, it consumes a lot of resources, and the number of iterations is uncontrollable.

[0029] Therefore, how to accurately and effectively estimate clock delays during the logic synthesis stage to reduce the deviation between the estimated results and the actual physical implementation, thereby reducing the number of front-end and back-end design iterations, has become a technical problem that urgently needs to be solved in this field.

[0030] To address the aforementioned technical problems, this application provides a physical awareness-based clock delay estimation method. This method identifies clock sources and their driven registers from a gate-level netlist to construct clock groups. Each clock group undergoes virtual layout processing to obtain estimated physical coordinates. A fitted mathematical model is then constructed based on the driving distance and fan-out quantity to estimate clock path delay. This solves the problem of significant discrepancies between clock delay estimation and actual physical implementation caused by ideal clock assumptions during logic synthesis. Furthermore, it achieves the goal of obtaining clock delay estimates close to physical reality during logic synthesis, reducing the number of front-end and back-end design iterations.

[0031] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0032] Please see Figure 1 The physical perception-based clock delay estimation method includes the following steps: Step S101: Identify all clock sources and their driven registers from the gate netlist, and obtain the fan-out number of each clock group and each clock source. Each clock group contains a clock source and all registers driven by that clock source.

[0033] It should be noted that the gate-level netlist is a circuit connection description file output by the logic synthesis tool, which contains all clock sources (such as the output of the phase-locked loop, the clock input pins of the chip, etc.) and registers in the design. Step S101 traverses the gate-level netlist to find each clock source and determine which registers it physically drives, thereby establishing the driving relationship between the clock source and the registers. Based on this driving relationship, clock groups can be constructed, each containing a clock source and all the registers driven by that clock source. Simultaneously, the number of registers in each clock group is counted as the fan-out of that clock source. In this way, the originally scattered gate-level netlist information can be structured and grouped according to the driving relationship of the clock sources, laying the foundation for independent delay estimation for each clock source in the future.

[0034] Step S102: Perform virtual layout processing on each clock group to obtain the estimated coordinates of the clock source and the estimated coordinates of each register in each clock group.

[0035] It should be noted that virtual placement processing refers to the process of quickly assigning estimated physical coordinates to clock sources and registers in clock groups using a preset global placement algorithm or a user-defined virtual placement, before the logic synthesis stage and the complete physical placement. This process does not require the coordinates to be manufacturable; it only needs to reflect the approximate spatial distribution relationship between clock sources and registers.

[0036] Through virtual layout processing, two types of information are output for each clock group: the estimated coordinates of the clock source within the group, and the estimated coordinates of each register within the group. In this way, the estimated physical coordinates of the clock source and registers can be obtained at a very low computational cost (in minutes) without performing a complete physical layout that would take hours to days. The introduction of these estimated coordinates facilitates the subsequent incorporation of physical spatial information into the logic synthesis stage. This allows subsequent delay estimation to be aware of the actual physical distance between the clock source and registers, as well as the dispersion of register distribution, thereby accurately and effectively estimating clock delays and reducing the deviation between the estimated results and the actual physical implementation.

[0037] Please continue reading. Figure 1 Step S103: Calculate the driving distance from each clock source to each register it drives based on the estimated coordinates of the clock sources in each clock group and the estimated coordinates of each register.

[0038] It should be noted that step S103 is calculated independently for each clock group based on the estimated coordinates obtained in step S102. Specifically, step S103 obtains the estimated coordinates of the clock source within the same clock group, as well as the estimated coordinates of each register within that group, calculates the spatial distance from the clock source to each register, and obtains the driving distance from the clock source to each register it drives. The driving distance can be calculated using Euclidean distance (i.e., straight-line distance) to reflect the physical path length of the clock signal propagating from the clock source to each register.

[0039] In other words, the calculation in step S103 can quantify the abstract "register distribution" into a specific drive distance value. This drive distance can be used to reflect the physical span of the clock network: the larger the drive distance, the longer the path that the clock signal needs to propagate, the greater the difficulty of clock tree synthesis, and the greater the clock path delay.

[0040] Step S104: Based on the driving distance from each clock source to each register it drives and the fan-out number of each clock source, calculate the estimated clock path delay value of each clock source using a preset estimation model. The estimation model is a mathematical model that fits the fan-out number of the clock source and the driving distance from the clock source to each register it drives as independent variables and the estimated clock path delay value of the clock source as the dependent variable.

[0041] It should be noted that step S104 performs an independent estimation for each clock source, outputting the estimated clock path delay value for each clock source. This allows for the acquisition of the estimated clock path delay value for each clock source during the logic synthesis stage. This estimated value directly reflects the combined impact of the two physical factors—drive distance and fan-out quantity—on clock delay. Compared to the traditional ideal clock assumption (delay of zero or a fixed value), the estimated value output in step S104 is closer to the actual clock path delay after subsequent physical implementation. Static timing analysis based on this estimated value can significantly reduce timing violations after placement and routing caused by overly optimistic timing estimations, thereby reducing the number of iterations in the "logic synthesis-placement and routing" process and shortening the design cycle.

[0042] In summary, this application addresses the latency estimation distortion caused by ideal clock assumptions in traditional logic synthesis by introducing a lightweight physical sensing mechanism. In other words, without performing complete physical placement and routing, this application incorporates spatial distance and fan-out size into latency calculations by rapidly estimating the physical locations of clock sources and registers. This allows for a more accurate clock path latency estimate during logic synthesis, effectively reducing the discrepancy between the estimated result and the actual physical implementation, thereby decreasing the number of front-end and back-end design iterations and shortening the design cycle.

[0043] Specifically, during the logic synthesis stage, this application identifies all clock sources and their driven registers from the gate-level netlist, thereby constructing clock groups. Each clock group contains one clock source and all registers driven by that clock source. Then, a virtual placement process is performed on each clock group to quickly obtain the estimated physical coordinates of the clock sources and registers without performing a full physical placement. Based on this, the driving distance from each clock source to each register it drives is calculated using the estimated coordinates within the same clock group, and the fan-out count of each clock source is also counted. Finally, using the driving distance and fan-out count as independent variables and the estimated clock path delay as the dependent variable, a fitted mathematical model is used to calculate the estimated clock path delay for each clock source, thus obtaining a clock delay estimation result that more closely approximates the physical reality during the logic synthesis stage.

[0044] Based on the aforementioned scheme, in some implementations of this application, virtual layout processing includes using a preset global layout algorithm to pre-allocate the physical locations of clock sources and registers in clock groups, or receiving user-defined virtual layout coordinates.

[0045] Understandably, virtual placement processing can employ a pre-defined global placement algorithm to quickly pre-allocate the physical locations of clock sources and registers within clock groups. This algorithm allows for cell overlap and can obtain approximate coordinates that meet delay estimation accuracy requirements in just minutes. Alternatively, virtual placement processing can also accept user-defined virtual placement coordinates, where designers directly specify the location or region constraints of clock sources and registers based on the chip's top-level planning. This ensures that the estimated coordinates of clock sources and registers can be obtained regardless of whether pre-defined physical planning information is available, providing the necessary input for subsequent drive distance calculations while avoiding the computational overhead of hours or even days required for performing a complete physical placement and routing.

[0046] For example, the preset global layout algorithm can be a partition-based minimum cut algorithm, a simulated annealing algorithm, a nonlinear optimization method in analytical methods (such as ePlace, RePlace), a force-directed algorithm, or a fast layout algorithm such as DREAMPlace based on deep learning or HeteroPlace based on heterogeneous computing.

[0047] Based on the aforementioned scheme, in some implementations of this application, the mathematical expression of the estimation model is: Delay = Factor × (k1 × Distance + k2 × Fanout). Where, Delay is the estimated clock path delay, Distance is the average spatial distance from the clock source to all registers it drives, Fanout is the fanout number of the clock source, k1 and k2 are weighting coefficients related to the technology library, and Factor is a dynamic estimation factor determined according to the degree of dispersion of the register distribution.

[0048] Understandably, this implementation quantifies the physical spatial distribution characteristics into clock path delay estimates by constructing a mathematical expression that includes drive distance, fan-out quantity, weighting coefficients, and dynamic estimation factors. This expression quantifies the contribution of distance and fan-out to delay using k1 and k2 respectively, and adaptively adjusts the distribution dispersion using the Factor function.

[0049] In other words, this implementation explicitly incorporates physical distance into clock delay estimation during the logic synthesis stage, thus taking into account the actual physical characteristics of the clock network as a large-scale distributed resistor-capacitor network, enabling more accurate and effective clock delay estimation. Specifically, by adaptively adjusting the dynamic estimation factor Factor, a smaller value is taken when registers are concentrated and a larger value is taken when they are dispersed, making the estimation results closer to the actual physical characteristics of subsequent clock tree synthesis and effectively reducing the timing analysis discrepancy between logic synthesis and physical implementation.

[0050] Based on the aforementioned solution, please refer to Figure 2 In some implementations of this application, the weighting coefficients k1 and k2 are obtained through pre-calibration via the following steps: Step S201: First, select multiple design modules with different sizes and layout characteristics as test samples. These samples preferably cover the range of register distribution from centralized to decentralized and the range of fan-out numbers from low to high. Step S202: Then, record the actual clock path delay of each test sample after physical synthesis, as well as the corresponding average spatial distance and fan-out number. Step S203: Finally, set the dynamic estimation factor to 1 and perform linear regression fitting on the actual clock path delay, as well as the corresponding average spatial distance and fan-out number, to obtain the weighting coefficients k1 and k2.

[0051] Understandably, this implementation establishes a mapping relationship between weight coefficients k1 and k2 and the target process library by collecting data from the actual physical implementation and performing linear regression fitting. Thus, calibration can be completed with a small number of test samples, ensuring that weight coefficients k1 and k2 accurately reflect the contribution of distance and fan-out to clock delay under the target process library. When a process node migrates, only the above calibration steps need to be repeated to obtain updated weight coefficients, enabling rapid migration of the estimation model between different process nodes and avoiding the problem of poor process adaptability of traditional line load models.

[0052] Based on the aforementioned scheme, in some implementations of this application, the formula for calculating the dynamic estimation factor is: Factor = Fmax - (Fmax - Fmin) × A; where Fmin is the lower limit of the estimation factor when the register distribution is completely concentrated, Fmax is the upper limit of the estimation factor when the register distribution is completely dispersed, and A is the physical distribution aggregation value of all registers in the clock group, with a value range of 0 to 1. The larger A is, the more concentrated the register distribution is.

[0053] Understandably, this implementation achieves adaptive adjustment of the Factor through the aforementioned linear relationship: when registers are concentrated, A approaches 1, and the Factor approaches Fmin, reflecting the physical characteristic of lower latency; when registers are dispersed, A approaches 0, and the Factor approaches Fmax, reflecting the physical reality of higher latency. This dynamic adjustment mechanism enables latency estimation to perceive the actual dispersion of register distribution, avoiding the timing evaluation distortion of some modules caused by the use of globally fixed latency values ​​in traditional methods.

[0054] It's important to note that a completely concentrated register distribution means that the estimated coordinates of all registers within a clock group are located at the same coordinate point or within a pre-defined, extremely small area. In this case, all registers are clustered together, making clock tree balancing very easy. Conversely, a completely dispersed register distribution means that the estimated coordinates of registers within a clock group cover the entire design module. In this case, registers are scattered throughout the chip, making clock tree balancing extremely difficult.

[0055] Based on the aforementioned scheme, in some implementations of this application, the formula for calculating the physical distribution clustering value of all registers within a clock group is: A = 1 / (1 + bbox_area / chip_area); where bbox_area = (Xmax - Xmin) × (Ymax - Ymin), Xmax and Xmin are the maximum and minimum x-coordinates of the estimated coordinates of the registers within the same clock group, Ymax and Ymin are the maximum and minimum y-coordinates of the estimated coordinates of the registers within the same clock group, and chip_area is the total area of ​​the design module described by the current gate netlist.

[0056] Understandably, this implementation quantifies the physical distribution and clustering of registers based on the ratio of the bounding box area to the total chip area. The four coordinate values ​​Xmax, Xmin, Ymax, and Ymin collectively define a minimum axis-aligned rectangle that can enclose all registers within the clock group; the area of ​​this rectangle is bbox_area. chip_area is the total area of ​​the design module described by the current gate-level netlist. Here, a design module refers to the complete circuit functional unit described by the gate-level netlist currently used for clock delay estimation.

[0057] In other words, this implementation quantifies the dispersion of register distribution into a clustering value A between 0 and 1 using the formula A = 1 / (1 + bbox_area / chip_area). When registers are concentrated, bbox_area is much smaller than chip_area, the ratio approaches 0, and A approaches 1; when registers are completely dispersed and cover the entire chip, bbox_area approaches chip_area, the ratio approaches 1, and A approaches 0. This quantization method does not rely on human experience and can objectively reflect the actual distribution characteristics of registers within each clock group, providing accurate input for the adaptive adjustment of the dynamic estimation factor.

[0058] For example, in some implementations of this application, the value of Fmin ranges from 0.6 to 0.7, and the value of Fmax ranges from 1.8 to 2.0, which ensures that the delay estimation is neither too optimistic nor too conservative. Engineering practice has verified that this value range can cover the register distribution dispersion in most design scenarios, effectively solving the problem of timing distortion in some modules caused by the use of fixed empirical values ​​in traditional methods.

[0059] Based on the aforementioned solution, please refer to Figure 3 In some implementations of this application, the clock delay estimation method further includes: step S105: inputting the calculated clock path delay estimates of each clock source into the static timing analysis engine of the logic synthesis tool to replace the original ideal clock assumption or fixed delay estimate, and re-performing timing analysis.

[0060] After estimating the clock path delay for each clock source, step S105 inputs these estimates into the static timing analysis engine of the logic synthesis tool. This engine originally used an ideal clock assumption (i.e., assuming zero clock path delay) or a user-defined fixed delay estimate for timing analysis. These assumptions significantly deviate from the actual delays after physical implementation. This implementation replaces these inaccurate assumptions with the clock path delay estimates for each clock source calculated in step S104, allowing the static timing analysis engine to perform timing checks based on delay data that more closely reflects physical reality. This effectively reduces setup and hold time violations caused by overly optimistic timing estimates, lowers the probability of rework and iteration after placement and routing, and shortens the overall chip design cycle.

[0061] Please see Figure 4This application provides an electronic device including at least one processor 201 and at least one memory 202. The processor 201 and the memory 202 are directly connected to each other, or communicate with each other through a communication interface 203, or are electrically connected through one or more communication buses or signal lines to achieve data transmission or interaction. The memory 202 stores program instructions that can be executed by the processor 201. The processor 201 can call the program instructions to execute the program instructions to implement any of the physical perception-based clock delay estimation methods provided by the above-described implementation methods.

[0062] The memory 202 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0063] The processor 201 can be an integrated circuit chip with signal processing capabilities. The processor 201 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0064] Understandable. Figure 4 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 4 The more or fewer components shown, or having the same Figure 4 The different configurations shown. Figure 4 The components shown can be implemented using hardware, software, or a combination thereof.

[0065] This application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor 201, implements any of the physically-aware clock delay estimation methods provided by the various implementations described above.

[0066] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0067] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A clock delay estimation method based on physical perception, characterized in that, include: Identify all clock sources and their driven registers from the gate netlist to obtain the fan-out number of each clock group and each clock source. Each clock group contains a clock source and all registers driven by that clock source. Virtual layout processing is performed on each clock group to obtain the estimated coordinates of the clock source and the estimated coordinates of each register in each clock group; Based on the estimated coordinates of the clock sources within each clock group and the estimated coordinates of each register, the driving distance from each clock source to each register it drives is calculated. Based on the driving distance from each clock source to each register it drives and the fan-out number of each clock source, the estimated clock path delay value of each clock source is calculated using a preset estimation model. The estimation model is a mathematical model that fits the estimated clock path delay value of the clock source to each register it drives, with the fan-out number of the clock source and the driving distance from the clock source to each register it drives as independent variables. The mathematical expression of the estimation model is: Delay = Factor × (k1 × Distance + k2 × Fanout); where Delay is the estimated clock path delay, Distance is the average spatial distance from the clock source to all registers it drives, Fanout is the fanout number of the clock source, k1 and k2 are weighting coefficients related to the technology library, and Factor is a dynamic estimation factor determined according to the degree of dispersion of the register distribution.

2. The clock delay estimation method according to claim 1, characterized in that, The virtual layout processing includes using a preset global layout algorithm to pre-allocate the physical locations of clock sources and registers in the clock group, or receiving user-defined virtual layout coordinates.

3. The clock delay estimation method according to claim 1, characterized in that, The weighting coefficients k1 and k2 are obtained through pre-calibration via the following steps: Multiple design modules with different sizes and layout features were selected as test samples. Record the actual clock path delay of each test sample after physical synthesis, as well as the corresponding average spatial distance and fan-out number; By setting the dynamic estimation factor to 1, a linear regression fit is performed on the actual clock path delay, the corresponding average spatial distance, and the number of fan-outs to obtain the weighting coefficients k1 and k2.

4. The clock delay estimation method according to claim 1, characterized in that, The formula for calculating the dynamic estimation factor is: Factor = Fmax - (Fmax - Fmin) × A; Where Fmin is the lower limit of the estimation factor when the register distribution is completely concentrated, Fmax is the upper limit of the estimation factor when the register distribution is completely dispersed, and A is the physical distribution clustering value of all registers in the clock group, ranging from 0 to 1.

5. The clock delay estimation method according to claim 4, characterized in that, The formula for calculating the physical distribution clustering value of all registers within the clock group is: A = 1 / (1 + bbox_area / chip_area); Where bbox_area=(Xmax-Xmin)×(Ymax-Ymin), Xmax and Xmin are the maximum and minimum x-coordinates of the estimated coordinates of the registers within the same clock group, Ymax and Ymin are the maximum and minimum y-coordinates of the estimated coordinates of the registers within the same clock group, and chip_area is the total area of ​​the design module described by the current gate netlist.

6. The clock delay estimation method according to claim 4, characterized in that, The value of Fmin ranges from 0.6 to 0.7, and the value of Fmax ranges from 1.8 to 2.

0.

7. The clock delay estimation method according to claim 1, characterized in that, The clock delay estimation method further includes: inputting the calculated clock path delay estimates of each clock source into the static timing analysis engine of the logic synthesis tool to replace the original ideal clock assumptions or fixed delay estimates, and then re-performing the timing analysis.

8. An electronic device, characterized in that, include: Memory, used to store one or more programs; processor; When the processor executes the one or more programs, it implements the clock delay estimation method as described in any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the clock delay estimation method as described in any one of claims 1-7.

Images