A method, apparatus, medium, and program product for post-silicon characterization of a chip

Abstract

The application relates to the chip technical field and discloses a chip silicon post-characterization method, equipment, medium and program product. The method comprises the following steps: acquiring a power supply domain to be measured, and performing white-box disassembly and characterization on the power supply domain to be measured to acquire an intrinsic voltage frequency curve set and a voltage drop drop frequency curve set; performing quantitative comparison and interlocking verification of silicon post-characterization results and silicon pre-design according to the intrinsic voltage frequency curve set and the voltage drop drop frequency curve set to acquire key intellectual property core verification results, margin evaluation results, voltage drop drop component decomposition results and key voltage drop drop component quantities; and updating a chip standard according to the key intellectual property core verification results, the margin evaluation results, the voltage drop drop component decomposition results and the key voltage drop drop component quantities to acquire an updated chip design standard. The method can realize targeted optimization of voltage and frequency characteristics, can improve chip design quality and can optimize a chip design standard.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method, apparatus, medium, and program product for post-silicon characterization of chips. Background Technology

[0002] As the scale of large-scale artificial intelligence models continues to expand, the demand for computing power in training and inference clusters is growing exponentially. In the context of the computing power race, high energy efficiency has become a core competitive indicator for AI chips. Based on the definition of power consumption, optimizing the operating voltage / frequency of AI chips is the most direct and effective way to improve energy efficiency.

[0003] Currently, existing post-silicon characterization methods for chips typically treat the operating voltage / frequency of an AI chip as a complete black box for testing and characterization, obtaining the operational voltage / frequency point of the product solely through functional tests or applied loads. However, this black-box testing and characterization approach cannot distinguish the contributions of the chip design itself and system-level power integrity to the voltage / frequency, making targeted optimization difficult. Furthermore, the lack of mechanisms for interlocking with pre-silicon design and a closed-loop optimization feedback path prevents the application of post-silicon characterization results to chip design updates, resulting in a lack of post-silicon feedback in chip design. Summary of the Invention

[0004] This invention provides a post-silicon characterization method, device, medium, and program product for chips. It can extract the voltage and frequency components corresponding to the chip design itself and the system-level power integrity, respectively. It can achieve targeted optimization of voltage and frequency characteristics, and apply the post-silicon characterization results to chip design, thereby improving chip design quality and optimizing chip design standards.

[0005] According to one aspect of the present invention, a post-silicon characterization method for chips is provided, comprising: The power domain under test is obtained, and the power domain under test is disassembled and characterized in a white box manner to obtain the set of intrinsic voltage frequency curves and the set of voltage drop frequency curves. Based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, perform quantitative comparison and interlock verification between the post-silicon characterization results and the pre-silicon design to obtain key intellectual property core verification results, margin assessment results, voltage drop component decomposition results and key voltage drop component components. Based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component components, the chip standard is updated to obtain the updated chip design standard.

[0006] According to another aspect of the present invention, a post-silicon characterization apparatus for chips is provided, comprising: The set acquisition module is used to acquire the power domain under test and to perform white-box disassembly and characterization of the power domain under test to obtain the set of intrinsic voltage frequency curves and the set of voltage drop frequency curves. The result acquisition module is used to perform quantitative comparison and interlock verification of the post-silicon characterization results and the pre-silicon design based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, so as to obtain the key intellectual property core verification results, margin assessment results, voltage drop component decomposition results and key voltage drop component components. The standard update module is used to update the chip standard based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component components, so as to obtain the updated chip design standard.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that is executed by the at least one processor, which enables the at least one processor to perform the chip post-silicon characterization method according to any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program for causing a processor to execute and implement the chip post-silicon characterization method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the chip post-silicon characterization method according to any embodiment of the present invention.

[0010] The technical solution of this invention involves acquiring the power domain under test and performing white-box disassembly and characterization of the power domain to obtain a set of intrinsic voltage-frequency curves and a set of voltage drop-off frequency curves. Based on the intrinsic voltage-frequency curves and voltage drop-off frequency curves, a quantitative comparison and interlock verification of the post-silicon characterization results and the pre-silicon design are performed to obtain key intellectual property verification results, margin assessment results, voltage drop-off component decomposition results, and key voltage drop-off component components. Based on the key intellectual property verification results, margin assessment results, voltage drop-off component decomposition results, and key voltage drop-off component components, the chip standard is updated to obtain an updated chip design standard. By disassembling the operating voltage into intrinsic voltage and voltage drop-off, post-silicon characterization results are obtained, and the post-silicon characterization results are quantitatively compared and interlocked with the pre-silicon design to obtain verification results. Finally, the chip standard is updated based on the verification results. This allows for the extraction of voltage and frequency components corresponding to the chip design itself and system-level power integrity, enabling targeted optimization of voltage and frequency characteristics. The post-silicon characterization results can be applied to chip design, improving chip design quality and optimizing chip design standards.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a post-silicon characterization method for chips according to Embodiment 1 of the present invention; Figure 2 This is a flowchart of a post-silicon characterization method for chips according to Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of a chip silicon post-characterization device provided in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device that implements the post-silicon characterization method for chips according to embodiments of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," "modification," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] Example 1 Figure 1 This is a flowchart of a post-silicon characterization method for chips according to Embodiment 1 of the present invention. This embodiment is applicable to the white-box characterization and optimization of the voltage and frequency characteristics of artificial intelligence chips. The method can be executed by a post-silicon characterization device, which can be implemented in hardware and / or software. Typically, this post-silicon characterization device can be configured in electronic devices, such as computer equipment, servers, etc. Figure 1 As shown, the method includes: S110. Obtain the power domain under test, and perform white-box disassembly and characterization on the power domain under test to obtain the intrinsic voltage frequency curve set and the voltage drop frequency curve set.

[0017] The power domain under test can be the power domain for which voltage / frequency (V / F) characteristic testing is required. It should be noted that artificial intelligence (AI) chips typically contain multiple independent power domains. This embodiment uses the power domain as the analysis dimension, independently decomposing and characterizing the voltage and frequency characteristics of each power domain. Typically, a power domain can include a deep learning tensor unit domain (DTU domain) and a system on chip domain (SoC domain). For example, the configuration information of the power domain can be shown in Table 1. Each power domain can cover multiple different intellectual property cores (IPs) with different V / F characteristics and characterization focuses.

[0018] Table 1 Configuration information for the power domain

[0019] In this embodiment, Vset = Vdevice + VdroopGB. Here, Vset represents the actual operating voltage of the AI ​​product, i.e., the voltage configured on the board for the chip. Vdevice represents the intrinsic voltage of the AI ​​chip. VdroopGB represents voltage drop protection, which is the extra voltage redundancy intentionally provided to ensure the chip never malfunctions, covering the voltage drop protection margin introduced by system-level power integrity factors during load operation.

[0020] Where VdroopGB = Func(Ldidt, EDC, Package PI, Board PI, VR Policy). Ldidt is the transient voltage drop across the inductor, including the first-order voltage drop (1st Vdroop) and the second-order voltage drop (2nd Vdroop). EDC is the limiting DC current. Package PI, Board PI, and VR Policy are the package-level power integrity (PI), board-level power integrity, and voltage regulator (VR) policies, respectively. It should be noted that different configurations of Package PI, Board PI, and VR Policy have different Ldidt or EDC representations. Func represents the correlation function; the form of Func is not specifically limited in this embodiment.

[0021] Based on the above principles, this embodiment decomposes Vset into Vdevice and VdroopGB, and independently quantizes Vdevice and VdroopGB to obtain the corresponding intrinsic voltage frequency curve set and voltage drop frequency curve set. Specifically, after chip tape-out, for the power domain under test, firstly, voltage drop can be disregarded, and only the key timing paths of each IP corresponding to the power domain under test are covered. The minimum operating voltage (intrinsic voltage) at different operating frequencies is obtained at each test moment. Based on the correspondence between operating frequency and minimum operating voltage, each intrinsic voltage frequency curve Vdevice(F) is generated, and then the intrinsic voltage frequency curves are combined into an intrinsic voltage frequency curve set. The horizontal axis of the intrinsic voltage frequency curve represents the operating frequency, and the vertical axis represents the intrinsic voltage.

[0022] Then, the maximum load is simulated and a realistic power integrity protection strategy is applied to maximize the voltage drop. The test is then repeated to obtain the actual operating voltage at different operating frequencies at each test moment. Based on the correspondence between the operating frequency and the actual operating voltage, the frequency curves Vset(F) for each actual operating voltage are generated. Finally, based on the formula VdroopGB(F) = Vset(F) - Vdevice(F), the frequency curves VdroopGB(F) for each voltage drop are calculated, and a set of voltage drop frequency curves is generated based on each VdroopGB(F).

[0023] In this embodiment, post-silicon characterization refers to the process of quantitatively measuring and calibrating the chip's actual operating voltage, frequency, power consumption, and power integrity through functional and stress testing after chip tape-out, providing real data for chip energy efficiency optimization, timing calibration, and power design improvement. Pre-silicon design refers to the process of performing the entire design, simulation, verification, and approval process before chip tape-out. The pre-silicon design report is the result of the pre-silicon design and may specifically include an overall design report, timing approval report, and power integrity approval report. Typically, the critical timing paths and power integrity protection strategies for each IP can be extracted from the pre-silicon design report.

[0024] S120. Based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, perform quantitative comparison and interlock verification between the post-silicon characterization results and the pre-silicon design to obtain key intellectual property verification results, margin assessment results, voltage drop component decomposition results, and key voltage drop component components.

[0025] In this embodiment, the intrinsic voltage frequency curve set and the voltage drop frequency curve set can be used as the post-silicon characterization results. The post-silicon characterization results are compared and interlocked with the various approval parameters in the pre-silicon design report to verify whether the design of the approval parameters is reasonable, thereby obtaining various verification results.

[0026] The verification results may include key intellectual property verification results, margin assessment results, voltage drop / sag component decomposition results, and key voltage drop / sag component information. Key intellectual property verification results indicate whether the measured key IP is consistent with the key IP set in the pre-silicon design report; they can be consistent or inconsistent. Margin assessment results indicate whether the timing compliance approval target and power integrity compliance approval voltage drop limit set in the pre-silicon design report are insufficient or significantly greater than the measured value. Voltage drop / sag component decomposition results indicate the key power integrity protection strategies that have the greatest impact on each voltage drop / sag component. Key voltage drop / sag component information indicates the key components that have the greatest impact on voltage drop / sag.

[0027] Specifically, corresponding verification rules are pre-set for each verification item, and based on each verification rule, the verification results corresponding to each verification item are analyzed according to the intrinsic voltage frequency curve set, voltage drop frequency curve set, and silicon pre-design report.

[0028] S130. Based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component, update the chip standard to obtain the updated chip design standard.

[0029] In this embodiment, the current chip standard or the next-generation chip standard can be updated based on preset update rules, according to the key intellectual property verification results, margin assessment results, voltage drop component decomposition results, and key voltage drop component components, to obtain an updated chip design standard. Alternatively, a current prompt word can be generated based on the key intellectual property verification results, margin assessment results, voltage drop component decomposition results, key voltage drop component components, pre-silicon design report, and preset prompt word template. This prompt word is then input into a pre-trained standard update model to obtain the updated chip design standard output by the standard update model. The standard update model can be fine-tuned and trained from a basic large language model using historical result data and historical pre-silicon design reports.

[0030] The chip V / F design update can include Vdevice V / F update and VdroopGB update. For Vdevice V / F update, margin calibration and timing methodology iteration can be performed; for VdroopGB update, power integrity protection strategy tuning can be performed.

[0031] Optionally, updating the chip standard based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component to obtain updated chip design standards may include: Based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component components, the updated approval standard, the updated power integrity protection strategy configuration, and the updated power integrity design standard are obtained. Based on the updated approval standard, the updated power integrity protection strategy configuration, and the updated power integrity design standard, the updated chip design standard is obtained.

[0032] The margin assessment results can include timing margin assessment results and power integrity margin assessment results. Specifically, if an inconsistency is detected in the verification results of critical intellectual property (IP), the current critical IP will be updated to the tested critical IP; if the verification results of the critical IP are consistent, the current critical IP will continue to be used. Secondly, if the timing margin assessment result indicates insufficient margin, it indicates a yield risk, and a preset margin value will be added to the current timing compliance approval target to obtain an updated timing compliance approval target; if the timing margin assessment result indicates large margin, the preset margin value will be reduced from the current timing compliance approval target to obtain an updated timing compliance approval target.

[0033] Furthermore, if the PI (Property Invoice) margin assessment result indicates insufficient margin, the current PI compliance approval reduction limit is added to a preset margin value, and the sum is used as the updated PI compliance approval reduction limit. Conversely, if the PI margin assessment result indicates large margin, the current PI compliance approval reduction limit is subtracted from the preset margin value, and the difference is used as the updated PI compliance approval reduction limit. Further, the updated key IP (Property Invoice), updated time-series compliance approval target, and updated PI compliance approval reduction limit are combined to obtain the updated approval standard.

[0034] Then, based on the voltage drop component decomposition results, the target power integrity protection strategy corresponding to each voltage drop component can be obtained, and it can be determined whether each voltage drop component is within the corresponding value range. If a voltage drop component is detected to be outside the corresponding value range, the configuration information of its corresponding target power integrity protection strategy can be modified so that its corresponding voltage value returns to the corresponding value range, thereby obtaining the updated power integrity protection strategy configuration.

[0035] Next, based on the key voltage drop components, such as 1st / 2nd Vdroop or EDC, and the preset correspondence between voltage drop components and optimization directions, the target optimization direction can be determined, and the updated PI design standard can be determined based on the target optimization direction. The optimization direction can include Package PI, Board PI, and VR Policy. By adjusting the configuration information of Package PI, Board PI, or VR Policy, the voltage values ​​corresponding to the respective voltage drop components can be adjusted. Finally, the updated approval standard, updated power integrity protection strategy configuration, and updated power integrity design standard can be combined to obtain the final updated chip design standard.

[0036] The advantage of the above settings is that they enable automatic optimization of chip power supply design and achieve a closed loop between post-silicon and pre-silicon processes.

[0037] The power integrity protection strategy can include a compute unit domain power safety strategy, a system domain on-chip voltage regulation and control strategy, and / or a limit DC current protection strategy. The compute unit domain power safety strategy, corresponding to nanosecond-level Ldidt protection, monitors the activity and power consumption of the scalar arithmetic processor and limits immediate activity before detecting a large Ldidt event, thus keeping Ldidt within the package's acceptable PI range. The system domain on-chip voltage regulation and control strategy, corresponding to microsecond-level Ldidt protection, monitors the on-chip voltage regulation circuit (including on-chip energy storage capacitors and regulation circuits) and stabilizes the on-chip system power supply on a microsecond timescale to suppress second-order voltage drop. The limit DC current protection strategy, corresponding to DC current protection, monitors the load current and actively reduces the frequency when the load current approaches the EDC limit, thus controlling the current to not exceed the DC carrying capacity of the power distribution network.

[0038] The advantage of the above settings is that they can provide targeted and effective protection for different frequency bands of power integrity.

[0039] The technical solution of this invention involves acquiring the power domain under test and performing white-box disassembly and characterization of the power domain to obtain a set of intrinsic voltage-frequency curves and a set of voltage drop-off frequency curves. Based on the intrinsic voltage-frequency curves and voltage drop-off frequency curves, a quantitative comparison and interlock verification of the post-silicon characterization results and the pre-silicon design are performed to obtain key intellectual property verification results, margin assessment results, voltage drop-off component decomposition results, and key voltage drop-off component components. Based on the key intellectual property verification results, margin assessment results, voltage drop-off component decomposition results, and key voltage drop-off component components, the chip standard is updated to obtain an updated chip design standard. By disassembling the operating voltage into intrinsic voltage and voltage drop-off, post-silicon characterization results are obtained, and the post-silicon characterization results are quantitatively compared and interlocked with the pre-silicon design to obtain verification results. Finally, the chip standard is updated based on the verification results. This allows for the extraction of voltage and frequency components corresponding to the chip design itself and system-level power integrity, enabling targeted optimization of voltage and frequency characteristics. The post-silicon characterization results can be applied to chip design, improving chip design quality and optimizing chip design standards.

[0040] Example 2 Figure 2 This is a flowchart of a post-silicon characterization method for chips provided in Embodiment 2 of the present invention. This embodiment is a further refinement of the above technical solution, and the technical solution in this embodiment can be combined with one or more of the above implementation methods. For example... Figure 2 As shown, the method includes: S210. Obtain the power domain under test, and obtain each intellectual property core corresponding to the power domain under test. Based on the pre-silicon design report, obtain the key timing path corresponding to each intellectual property core.

[0041] Specifically, based on the power domain configuration information, each IP corresponding to the power domain under test is obtained, and the pre-silicon design report is parsed to extract the key timing path corresponding to each IP.

[0042] S220. Based on the key timing paths corresponding to each intellectual property core, obtain each path set, and perform a minimum operating voltage sweep test on each path set to obtain the intrinsic voltage frequency curve corresponding to each path set, and generate the intrinsic voltage frequency curve set based on each intrinsic voltage frequency curve.

[0043] Then, based on the pre-defined correspondence between task scenarios and key timing paths, the key timing paths are combined to generate multiple path sets corresponding to multiple task scenarios. Next, for each path set, at each test moment, the operating frequency is fixed, and the system scans from high voltage to low voltage until the path set can no longer operate normally, obtaining the minimum operating voltage. Then, the operating frequency is adjusted, and the scan from high voltage to low voltage is repeated to test and obtain the minimum operating voltage corresponding to each operating frequency. Furthermore, the correspondence between the operating frequency and the minimum operating voltage is fitted to generate the intrinsic voltage frequency curve corresponding to each path set at each test moment, and the intrinsic voltage frequency curves are combined to generate an intrinsic voltage frequency curve set.

[0044] S230. Perform a frequency sweep test on the power domain under test with load mode superimposed power integrity protection strategies to obtain the actual operating voltage frequency curves matching each power integrity protection strategy combination, and generate a set of actual operating voltage frequency curves based on each actual operating voltage frequency curve.

[0045] Simultaneously, for the power domain under test, at each test moment, the maximum current scenario (Ldidt, EDC maximum) is simulated, and different combinations of power integrity protection strategies are superimposed. The operating frequencies are scanned from high voltage to low voltage until normal operation fails, thus obtaining the actual operating voltage (the minimum board configuration voltage under actual load). Then, the correspondence between operating frequency and actual operating voltage is fitted to generate the actual operating voltage-frequency curve matching each power integrity protection strategy combination at each test moment, thereby generating a set of actual operating voltage-frequency curves. For example, when simulating the maximum current scenario, for the computing unit domain, the scalar processing processor and distributed storage module can be controlled to operate at full load; while for the system domain, multiple IPs can be controlled to collaboratively move data.

[0046] S240. Obtain the voltage drop frequency curve set based on the actual operating voltage frequency curve set and the intrinsic voltage frequency curve set.

[0047] Finally, based on the actual operating voltage frequency curve and the intrinsic voltage frequency curve, the actual operating voltage Vset(F) and intrinsic voltage Vdevice(F) corresponding to each operating frequency are obtained. Then, based on the formula VdroopGB(F) = Vset(F) - Vdevice(F), the voltage drop at each operating frequency is calculated. The correspondence between operating frequency and voltage drop is fitted to generate a voltage drop frequency curve matching each power integrity protection strategy combination at each test moment, thereby generating a set of voltage drop frequency curves.

[0048] S250. Based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, perform quantitative comparison and interlock verification between the post-silicon characterization results and the pre-silicon design to obtain key intellectual property verification results, margin assessment results, voltage drop component decomposition results, and key voltage drop component components.

[0049] Optionally, based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, a quantitative comparison and interlocking verification are performed between the post-silicon characterization results and the pre-silicon design to obtain key intellectual property verification results, margin assessment results, voltage drop component decomposition results, and key voltage drop component elements. This may include: Based on the aforementioned pre-silicon design report, obtain the key intellectual property cores for approval and the corresponding timing compliance approval targets, as well as the upper limit of voltage drop for power integrity compliance approval; Based on the intrinsic voltage frequency curve set, the key intellectual property core for signing, and the timing compliance signing target, a timing signing interlock is performed to obtain the verification results of the key intellectual property core and the timing margin assessment results. Based on the set of voltage drop frequency curves and the upper limit of voltage drop for power integrity compliance approval, power integrity approval interlock is performed to obtain power integrity margin assessment results, voltage drop component decomposition results and key voltage drop component components. The margin assessment result is obtained based on the timing margin assessment result and the power integrity margin assessment result.

[0050] In this embodiment, the quantitative comparison and interlock verification between post-silicon characterization results and pre-silicon design can include timing signature interlock and power integrity signature interlock. Specifically, firstly, the key IPs for signature, timing compliance signature targets, and PI compliance signature voltage drop limits are extracted from the pre-silicon design report; then, based on the intrinsic voltage frequency curve set, the measured key IPs and the measured intrinsic voltages corresponding to each operating frequency are obtained, and the measured key IPs are compared and analyzed with the key IPs for signature to obtain the key IP verification results. At the same time, the measured intrinsic voltages corresponding to each operating frequency are compared and analyzed with the timing compliance signature targets to obtain the timing margin assessment results.

[0051] Then, based on the set of voltage drop frequency curves, the measured voltage drop corresponding to each operating frequency is obtained, and the measured voltage drop corresponding to each operating frequency is compared and analyzed with the voltage drop upper limit approved by the PI (Power Integrity) compliance department to obtain the PI margin assessment results. Further, based on the set of voltage drop frequency curves, the voltage drop components are decomposed and the factors with the largest proportion are identified to obtain the voltage drop component decomposition results and key voltage drop components. Finally, the margin assessment results are composed of the timing margin assessment results and the power integrity margin assessment results.

[0052] The advantage of the above settings is that they can improve the accuracy of quantitative comparison and interlock verification, and provide data basis for chip design optimization.

[0053] Optionally, timing verification interlocking can be performed based on the intrinsic voltage frequency curve set, the key intellectual property core for signing off, and the timing compliance signing off target to obtain the verification results of the key intellectual property core and the timing margin assessment results. This may include: Based on the intrinsic voltage frequency curve set, obtain the intrinsic voltage frequency curve corresponding to each path set, and based on the intrinsic voltage frequency curve corresponding to each path set, determine the real key intellectual property core in each intellectual property core. The real key intellectual property core is cross-validated with the signed key intellectual property core to obtain the key intellectual property core verification results, and each intrinsic voltage frequency curve is compared and analyzed with the timing compliance signing target to obtain the timing margin assessment results.

[0054] Specifically, during timing signature interlocking, firstly, the intrinsic voltage frequency curve corresponding to each path set is extracted from the intrinsic voltage frequency curve set. Then, by comparing and analyzing these intrinsic voltage frequency curves, the intrinsic voltage frequency curve corresponding to each IP is obtained. For example, curve 1 corresponds to the set of paths a, b, and c, and curve 2 corresponds to the set of paths a and b. If curve 1 has a worse V / F ratio compared to curve 2, then curve 1 is subtracted from curve 2 to obtain the intrinsic voltage frequency curve corresponding to the IP belonging to path c. Next, based on the intrinsic voltage frequency curves, the IP with the lowest intrinsic voltage is selected as the true critical IP from all IPs. It is then determined whether this true critical IP is the same as the signature critical IP, and the verification result of the critical IP is determined based on the determination result.

[0055] Furthermore, the measured intrinsic voltage corresponding to each operating frequency can be extracted from the intrinsic voltage-frequency curve, and the approval voltage corresponding to each operating frequency can be extracted from the timing compliance approval target. Then, the timing margin value is obtained by subtracting the corresponding approval voltage from the measured intrinsic voltage at each operating frequency. Finally, it is determined whether the timing margin value is within the preset value range. If it is, the timing margin assessment result is determined to be normal; if the timing margin value is less than the minimum value of the preset value range, the timing margin assessment result is determined to be insufficient; and if the timing margin value is greater than the maximum value of the preset value range, the timing margin assessment result is determined to be large. For example, when the operating frequency is 1306 MHz, the approval voltage is 0.765 volts, and the measured intrinsic voltage is 0.78 volts, then the timing margin value is -0.015 volts.

[0056] The advantage of the above settings is that they enable the verification of key IP addresses for signing and time-compliant signing targets, thereby improving the accuracy of time-series signing interlocks.

[0057] Optionally, power integrity signing interlocking can be performed based on the set of voltage drop frequency curves and the upper limit of voltage drop for power integrity compliance signing, to obtain the power integrity margin assessment results, the voltage drop component decomposition results, and the key voltage drop component, which may include: Based on the set of voltage drop frequency curves, obtain the voltage drop frequency curve corresponding to each power integrity protection strategy combination, and compare and analyze each voltage drop frequency curve with the upper limit of voltage drop for power integrity compliance approval to obtain the power integrity margin assessment result. Based on the voltage drop frequency curves and the operating frequency range of the intellectual property core, the voltage drop time curves corresponding to each power integrity protection strategy combination are obtained, and the voltage drop time curves are decomposed in the time domain to obtain the time domain voltage drop data matched by each power integrity protection strategy combination corresponding to each initial voltage drop component. Using the controlled variable method, based on the time-domain voltage drop data matched by the power integrity protection strategy combination corresponding to each of the initial voltage drop components, the target power integrity protection strategy corresponding to each of the initial voltage drop components is obtained, and based on the target power integrity protection strategy corresponding to each of the initial voltage drop components, the voltage drop component decomposition result is obtained. Frequency domain decomposition is performed on each of the voltage drop time curves to obtain the frequency domain components corresponding to each of the initial voltage drop components. Power integrity ratio analysis is then performed based on the frequency domain components to determine the critical voltage drop components in each of the initial voltage drop components.

[0058] In this embodiment, when performing PI (Power Integrity Protection) signature interlocking, firstly, the voltage drop frequency curves corresponding to each test time and power integrity protection strategy combination are extracted from the voltage drop frequency curve set, and the measured voltage drop is identified based on the voltage drop frequency curves. Then, the PI margin value is calculated by subtracting the measured voltage drop from the PI compliance signature voltage drop limit. It is then determined whether the PI margin value is within a preset value range, and the PI margin evaluation result is determined based on the determination result. For example, if the PI compliance signature voltage drop limit is 150 mV and the measured voltage drop is 120 mV, then the PI margin value is 30 mV.

[0059] Then, based on the operating frequency range of the intellectual property core, the current operating frequency is determined. Based on the current operating frequency, the correspondence between the test time, power integrity protection strategy combination, and voltage drop is extracted from each voltage drop frequency curve in the voltage drop frequency curve set (corresponding to a specific test time and power integrity protection strategy combination). Next, the correspondence between the test time and voltage drop is fitted to generate a voltage drop time curve corresponding to each power integrity protection strategy combination. The horizontal axis of the voltage drop time curve represents time, and the vertical axis represents voltage drop.

[0060] It should be noted that each component of the voltage drop corresponds to a different time scale. For example, the time scale for 1st Vdroop is less than 1 microsecond, the time scale for 2nd Vdroop is 1 to 10 microseconds, and the time scale for EDC is greater than 10 microseconds. Based on the correspondence between the components and time scales, the time-domain voltage drop data corresponding to each initial voltage drop component can be extracted from the voltage drop time curve corresponding to each power integrity protection strategy combination. This yields the correspondence between the initial voltage drop components, the power integrity protection strategy combination, and the time-domain voltage drop data. Next, based on the obtained correspondence, for each initial voltage drop component, the time-domain voltage drop data corresponding to each power integrity protection strategy combination is compared and analyzed to obtain the voltage drop value corresponding to each power integrity protection strategy. The strategy with the largest voltage drop value among all power integrity protection strategies is then selected as the target power integrity protection strategy, thus obtaining the target power integrity protection strategy corresponding to each initial voltage drop component.

[0061] The target power integrity protection strategy represents the power integrity protection strategy that has the greatest impact on the corresponding component. When it is necessary to adjust the voltage drop value of a certain component, the configuration information of its corresponding target power integrity protection strategy can be directly adjusted. For example, for the computing unit domain power protection strategy, the current limiting threshold or response delay can be adjusted; for the system domain on-chip voltage regulation control strategy, the adjustment range or response speed can be adjusted; and for the ultimate DC current protection strategy, the EDC threshold can be adjusted.

[0062] Furthermore, each component of the voltage drop corresponds to a different frequency in the frequency domain. For example, the 1st voltage drop corresponds to high frequency, the 2nd voltage drop corresponds to intermediate frequency, and EDC corresponds to DC or low frequency. Based on this, this embodiment can perform Fourier transform processing on the voltage drop time curve to obtain a frequency domain curve, and extract the frequency domain components corresponding to each component from the frequency domain curve according to the correspondence between the component and the frequency domain frequency. Finally, each frequency domain component is divided by the sum of the frequency domain components to calculate the proportion of each component, and the component with the largest proportion is selected as the critical voltage drop component. The critical voltage drop component can be used as the main direction for optimization to significantly reduce voltage drop.

[0063] The advantages of the above settings are that they can verify the upper limit of voltage drop for PI compliance approval, enable efficient and accurate analysis of voltage drop, provide data basis for determining optimization direction, and improve the optimization efficiency of chip design.

[0064] It should be noted that high-performance AI chips exhibit large dynamic fluctuations and rapid switching speeds in power consumption when performing large-scale computations. The voltage response of the chip's power system under such load conditions includes not only the 1st Vdroop caused by sudden load changes, but also, under continuous high-frequency dynamic loads, a phenomenon where the minimum voltage envelope gradually shifts downwards over time, i.e., the 2nd Vdroop. This embodiment can also introduce controlled high-frequency dynamic power consumption changes during testing, causing the chip's power system to enter a continuous non-steady-state response state, thereby inducing the 2nd Vdroop phenomenon after the 1st Vdroop. Based on this, the envelope change of the 2nd Vdroop can be monitored and quantitatively analyzed in real time to assess the robustness and potential risks of the power loop under high-frequency dynamic loads.

[0065] Specifically, when the chip performs continuous high-frequency dynamic loads, the chip's core voltage is acquired in real time using a high-sampling-rate oscilloscope. Next, the chip's voltage response to the high-frequency dynamic load is acquired under different initial voltages, and the initial voltage is continuously reduced until the chip's real-time core voltage drops below the minimum safe operating voltage due to the voltage response, rendering it unable to perform the high-frequency dynamic load normally. This process yields the core voltage signal. Further analysis of the core voltage signal is performed to extract quantization indicators, and the 2nd Vdroop envelope characteristics under different load conditions are evaluated by adjusting the frequency and peak current of the high-frequency dynamic load using a pulse-width modulation-like command sequence.

[0066] The quantitative metrics may include: envelope amplitude, which represents the offset of the voltage minimum point relative to the initial voltage during the 2nd Vdroop; fall time, which represents the time it takes for the envelope to fall from the initial voltage to the minimum point; and recovery time, which represents the time it takes for the voltage to return to a stable value from the minimum point.

[0067] S260. Based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component, update the chip standard to obtain the updated chip design standard.

[0068] In this embodiment, the contributions of V / F from the chip design itself and from system-level power integrity can be distinguished and targeted optimizations can be performed. Secondly, the approval standards of the pre-silicon design stage can be calibrated based on post-silicon characterization data, which can improve the rationality of design margins. Finally, a systematic path is provided to feed back post-silicon characterization results to current product optimization and next-generation product design. The quantified V / F influencing factors can be transformed into targeted optimization methods and fed back to current product optimization and next-generation product design, forming a closed loop of continuous optimization.

[0069] The technical solution of this invention involves obtaining each intellectual property core corresponding to the power domain under test, and obtaining the key timing paths corresponding to each intellectual property core based on the pre-silicon design report; obtaining each path set based on the key timing paths corresponding to each intellectual property core, and performing a minimum operating voltage sweep test on each path set to obtain the intrinsic voltage frequency curves corresponding to each path set, and generating an intrinsic voltage frequency curve set based on each intrinsic voltage frequency curve; performing a load mode superimposed power integrity protection strategy sweep test on the power domain under test to obtain the actual operating voltage frequency curves matching each power integrity protection strategy combination, and... Based on the actual operating voltage frequency curves, a set of actual operating voltage frequency curves is generated. Based on the set of actual operating voltage frequency curves and the set of intrinsic voltage frequency curves, a set of voltage drop frequency curves is obtained. By first performing a frequency sweep test at the minimum operating voltage to obtain the intrinsic voltage frequency curve, and then performing a frequency sweep test with load mode superimposed power integrity protection strategy to obtain the actual operating voltage frequency curve, and finally obtaining the voltage drop frequency curve based on the actual operating voltage frequency curve and the intrinsic voltage frequency curve, a white-box disassembly of the power domain under test can be achieved, which can provide a data basis for targeted optimization of intrinsic voltage and voltage drop.

[0070] Example 3 Figure 3 This is a schematic diagram of a post-silicon characterization device for chips provided in Embodiment 3 of the present invention. Figure 3 As shown, the device includes: a set acquisition module 310, a result acquisition module 320, and a standard update module 330; wherein, The set acquisition module 310 is used to acquire the power domain under test and to perform white-box disassembly and characterization of the power domain under test to obtain the intrinsic voltage frequency curve set and the voltage drop frequency curve set. The result acquisition module 320 is used to perform quantitative comparison and interlocking verification of the post-silicon characterization results and the pre-silicon design based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, so as to obtain the key intellectual property core verification results, margin assessment results, voltage drop component decomposition results and key voltage drop component components. The standard update module 330 is used to update the chip standard based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component components, so as to obtain the updated chip design standard.

[0071] The technical solution of this invention involves acquiring the power domain under test and performing white-box disassembly and characterization of the power domain to obtain a set of intrinsic voltage-frequency curves and a set of voltage drop-off frequency curves. Based on the intrinsic voltage-frequency curves and voltage drop-off frequency curves, a quantitative comparison and interlock verification of the post-silicon characterization results and the pre-silicon design are performed to obtain key intellectual property verification results, margin assessment results, voltage drop-off component decomposition results, and key voltage drop-off component components. Based on the key intellectual property verification results, margin assessment results, voltage drop-off component decomposition results, and key voltage drop-off component components, the chip standard is updated to obtain an updated chip design standard. By disassembling the operating voltage into intrinsic voltage and voltage drop-off, post-silicon characterization results are obtained, and the post-silicon characterization results are quantitatively compared and interlocked with the pre-silicon design to obtain verification results. Finally, the chip standard is updated based on the verification results. This allows for the extraction of voltage and frequency components corresponding to the chip design itself and system-level power integrity, enabling targeted optimization of voltage and frequency characteristics. The post-silicon characterization results can be applied to chip design, improving chip design quality and optimizing chip design standards.

[0072] Optionally, the collection acquisition module 310 is specifically used to acquire each intellectual property core corresponding to the power domain under test, and to acquire the key timing path corresponding to each intellectual property core according to the pre-silicon design report; Based on the key timing paths corresponding to each intellectual property core, obtain each path set, and perform a minimum operating voltage sweep test on each path set to obtain the intrinsic voltage frequency curve corresponding to each path set. Based on each intrinsic voltage frequency curve, generate the intrinsic voltage frequency curve set. A frequency sweep test of load mode superimposed power integrity protection strategy is performed on the power domain under test to obtain the actual operating voltage frequency curve matching each power integrity protection strategy combination, and a set of actual operating voltage frequency curves is generated based on each actual operating voltage frequency curve. The voltage drop frequency curve set is obtained based on the actual operating voltage frequency curve set and the intrinsic voltage frequency curve set.

[0073] Optionally, the result acquisition module 320 includes: The upper limit acquisition unit is used to acquire the key intellectual property core for signing and the corresponding timing compliance signing target, as well as the upper limit of the voltage drop for power integrity compliance signing, based on the silicon pre-design report. The first result acquisition unit is used to perform time-series signing interlocking based on the intrinsic voltage frequency curve set, the key intellectual property core for signing, and the time-series compliance signing target, so as to obtain the verification result of the key intellectual property core and the time-series margin assessment result. The component acquisition unit is used to perform power integrity signing interlocking based on the voltage drop frequency curve set and the power integrity compliance signing voltage drop limit, so as to obtain the power integrity margin assessment result, the voltage drop component decomposition result and the key voltage drop component; The second result acquisition unit is used to acquire the margin assessment result based on the timing margin assessment result and the power integrity margin assessment result.

[0074] Optionally, the first result acquisition unit is specifically used to acquire the intrinsic voltage frequency curve corresponding to each path set based on the intrinsic voltage frequency curve set, and to determine the real key intellectual property core in each intellectual property core based on the intrinsic voltage frequency curve corresponding to each path set. The real key intellectual property core is cross-validated with the signed key intellectual property core to obtain the key intellectual property core verification results, and each intrinsic voltage frequency curve is compared and analyzed with the timing compliance signing target to obtain the timing margin assessment results.

[0075] Optionally, the component acquisition unit is specifically used to acquire the voltage drop frequency curve corresponding to each of the power integrity protection strategy combinations based on the set of voltage drop frequency curves, and to compare and analyze each of the voltage drop frequency curves with the upper limit of the voltage drop for power integrity compliance approval in order to obtain the power integrity margin assessment result. Based on the voltage drop frequency curves and the operating frequency range of the intellectual property core, the voltage drop time curves corresponding to each power integrity protection strategy combination are obtained, and the voltage drop time curves are decomposed in the time domain to obtain the time domain voltage drop data matched by each power integrity protection strategy combination corresponding to each initial voltage drop component. Using the controlled variable method, based on the time-domain voltage drop data matched by the power integrity protection strategy combination corresponding to each of the initial voltage drop components, the target power integrity protection strategy corresponding to each of the initial voltage drop components is obtained, and based on the target power integrity protection strategy corresponding to each of the initial voltage drop components, the voltage drop component decomposition result is obtained. Frequency domain decomposition is performed on each of the voltage drop time curves to obtain the frequency domain components corresponding to each of the initial voltage drop components. Power integrity ratio analysis is then performed based on the frequency domain components to determine the critical voltage drop components in each of the initial voltage drop components.

[0076] Optionally, the standard update module 330 is specifically used to obtain updated approval standards, updated power integrity protection strategy configurations, and updated power integrity design standards based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component components, and to obtain updated chip design standards based on the updated approval standards, the updated power integrity protection strategy configurations, and the updated power integrity design standards.

[0077] Optionally, power integrity protection strategies include computing unit domain power protection strategies, system domain on-chip voltage regulation control strategies, and / or extreme DC current protection strategies.

[0078] The chip post-silicon characterization apparatus provided in the embodiments of the present invention can execute the chip post-silicon characterization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0079] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0080] Example 4 Figure 4A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device 40 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 40 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0081] like Figure 4 As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 42 or loaded from the storage unit 48 into the random access memory 43. The RAM 43 can also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0082] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0083] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, central processing units, graphics processing units, various special-purpose artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as post-silicon characterization methods for chips.

[0084] In some embodiments, the post-silicon characterization method for a chip can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program can be loaded and / or mounted on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the post-silicon characterization method for a chip described above can be performed. Alternatively, in other embodiments, processor 41 can be configured to perform the post-silicon characterization method for a chip by any other suitable means (e.g., by means of firmware).

[0085] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays, application-specific integrated circuits (ASICs), application-specific standard products (ASICs), system-on-a-chip (SoCs), complex programmable logic devices, computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0086] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0087] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0088] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device 40, which includes: a display device (e.g., a cathode ray tube or liquid crystal display) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device 40. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0089] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0090] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact via a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server.

[0091] This embodiment may also include a computer program product, which includes a computer program that, when executed by a processor, implements the chip post-silicon characterization method provided in any embodiment of the present invention.

[0092] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0093] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for characterizing a chip after silicon deposition, characterized in that, include: The power domain under test is acquired, and the power domain under test is disassembled and characterized in a white-box manner to obtain a set of intrinsic voltage frequency curves and a set of voltage drop frequency curves; wherein, the intrinsic voltage is the minimum operating voltage at the operating frequency. Based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, perform quantitative comparison and interlock verification between the post-silicon characterization results and the pre-silicon design to obtain key intellectual property core verification results, margin assessment results, voltage drop component decomposition results and key voltage drop component components. Among them, the margin assessment results are used to indicate whether the timing compliance approval target and the upper limit of the power integrity compliance approval voltage drop set in the silicon pre-design report are insufficient or much greater than the measured value compared with the measured value; the voltage drop component decomposition results are used to indicate the key power integrity protection strategies that have the greatest impact on each voltage drop component; the key voltage drop component is used to indicate the key component that has the greatest impact on voltage drop. Based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component components, the chip standard is updated to obtain the updated chip design standard; Specifically, the power domain under test is subjected to white-box decomposition and characterization to obtain a set of intrinsic voltage frequency curves and a set of voltage drop frequency curves, including: Obtain each intellectual property core corresponding to the power domain under test, and obtain the key timing path corresponding to each intellectual property core according to the pre-silicon design report; Based on the key timing paths corresponding to each intellectual property core, obtain each path set, and perform a minimum operating voltage sweep test on each path set to obtain the intrinsic voltage frequency curve corresponding to each path set. Based on each intrinsic voltage frequency curve, generate the intrinsic voltage frequency curve set. A frequency sweep test of load mode superimposed power integrity protection strategy is performed on the power domain under test to obtain the actual operating voltage frequency curve matching each power integrity protection strategy combination, and a set of actual operating voltage frequency curves is generated based on each actual operating voltage frequency curve. The voltage drop frequency curve set is obtained based on the actual operating voltage frequency curve set and the intrinsic voltage frequency curve set.

2. The method according to claim 1, characterized in that, Based on the intrinsic voltage frequency curve set and the voltage drop frequency curve set, a quantitative comparison and interlocking verification of the post-silicon characterization results and pre-silicon design are performed to obtain key intellectual property verification results, margin assessment results, voltage drop component decomposition results, and key voltage drop component elements, including: Based on the aforementioned pre-silicon design report, obtain the key intellectual property cores for approval and the corresponding timing compliance approval targets, as well as the upper limit of voltage drop for power integrity compliance approval; Based on the intrinsic voltage frequency curve set, the key intellectual property core for signing, and the timing compliance signing target, a timing signing interlock is performed to obtain the verification results of the key intellectual property core and the timing margin assessment results. Based on the set of voltage drop frequency curves and the upper limit of voltage drop for power integrity compliance approval, power integrity approval interlock is performed to obtain power integrity margin assessment results, voltage drop component decomposition results and key voltage drop component components. The margin assessment result is obtained based on the timing margin assessment result and the power integrity margin assessment result.

3. The method according to claim 2, characterized in that, Based on the intrinsic voltage frequency curve set, the key intellectual property core for signing off, and the timing compliance signing off target, a timing signing off interlock is performed to obtain the verification results of the key intellectual property core and the timing margin assessment results, including: Based on the intrinsic voltage frequency curve set, obtain the intrinsic voltage frequency curve corresponding to each path set, and based on the intrinsic voltage frequency curve corresponding to each path set, determine the real key intellectual property core in each intellectual property core. The real key intellectual property core is cross-validated with the signed key intellectual property core to obtain the key intellectual property core verification results, and each intrinsic voltage frequency curve is compared and analyzed with the timing compliance signing target to obtain the timing margin assessment results.

4. The method according to claim 2, characterized in that, Based on the set of voltage drop frequency curves and the upper limit of voltage drop for power integrity compliance approval, a power integrity approval interlock is performed to obtain the power integrity margin assessment results, the voltage drop component decomposition results, and the key voltage drop components, including: Based on the set of voltage drop frequency curves, obtain the voltage drop frequency curve corresponding to each power integrity protection strategy combination, and compare and analyze each voltage drop frequency curve with the upper limit of voltage drop for power integrity compliance approval to obtain the power integrity margin assessment result. Based on the voltage drop frequency curves and the operating frequency range of the intellectual property core, the voltage drop time curves corresponding to each power integrity protection strategy combination are obtained, and the voltage drop time curves are decomposed in the time domain to obtain the time domain voltage drop data matched by each power integrity protection strategy combination corresponding to each initial voltage drop component. Using the controlled variable method, based on the time-domain voltage drop data matched by the power integrity protection strategy combination corresponding to each of the initial voltage drop components, the target power integrity protection strategy corresponding to each of the initial voltage drop components is obtained, and based on the target power integrity protection strategy corresponding to each of the initial voltage drop components, the voltage drop component decomposition result is obtained. Frequency domain decomposition is performed on each of the voltage drop time curves to obtain the frequency domain components corresponding to each of the initial voltage drop components. Power integrity ratio analysis is then performed based on the frequency domain components to determine the critical voltage drop components in each of the initial voltage drop components.

5. The method according to claim 1, characterized in that, Based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component, the chip standard is updated to obtain the updated chip design standard, including: Based on the key intellectual property verification results, the margin assessment results, the voltage drop component decomposition results, and the key voltage drop component components, the updated approval standard, the updated power integrity protection strategy configuration, and the updated power integrity design standard are obtained. Based on the updated approval standard, the updated power integrity protection strategy configuration, and the updated power integrity design standard, the updated chip design standard is obtained.

6. The method according to any one of claims 1-5, characterized in that, Power integrity protection strategies include computing unit domain power protection strategies, system domain on-chip voltage regulation and control strategies, and / or limit DC current protection strategies.

7. An electronic device, characterized in that, The electronic device includes: At least one processor, and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that is executed by the at least one processor to enable the at least one processor to perform the chip post-silicon characterization method according to any one of claims 1-6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the post-silicon characterization method for chips according to any one of claims 1-6.

9. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the post-silicon characterization method for chips according to any one of claims 1-6.

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