A kind of core particle interconnection structure defect detection method based on physical level decomposition

Abstract

The application provides a kind of core particle interconnection structure defect detection method based on physical level decomposition, comprising: obtaining the layout data and connection relationship data of through silicon via and micro-bump level;Form respective independent feature set according to physical space coordinates decomposition;Identify the vertical signal interruption feature of through silicon via and the poor contact feature of micro-bump;Establish physical connection topology graph, and the features existing spatial adjacent or electrical coupling relationship are connected after the above-mentioned features are labeled to generate correlation graph;Iterate the chain path, and mark the first defect feature node as defect source point;According to the level to which the source point belongs, select test signal injection and collect downstream response;Compare response with standard reference point by point, extract difference feature to determine the chain reaction extension range;Output the detection result containing defect level, position and influence range.The application can distinguish different physical level failure features and track chain reaction, realize the accurate identification of defect root and range.

Description

Technical Field

[0001] This invention relates to the field of chip inspection technology, and in particular to a method for detecting defects in chip interconnect structures based on physical level decomposition. Background Technology

[0002] In the field of modern chip design and manufacturing, chip interconnect technology is becoming increasingly important as a core means of achieving high-performance computing and modular integration. Powerful computing systems are built by integrating multiple small chips with different functions into the same package. However, with the continuous improvement of integration density and the increasing complexity of interconnect structures, defects between chips (such as those achieved through through-silicon vias and microbumps) have gradually evolved into a major bottleneck affecting the overall reliability and performance of the chip. How to efficiently and accurately detect and locate these interconnect defects directly determines the final quality of the chip.

[0003] To address the aforementioned issues, several detection methods have been developed in the prior art, such as boundary scan-based electrical testing, optical imaging inspection, and anomaly detection through signal integrity monitoring. These methods can detect obvious faults in interconnect structures, such as open circuits or short circuits, to varying degrees. However, existing solutions generally treat the chip interconnect structure as a single entity or layer, ignoring the objective fact that the interconnect structure is physically composed of multiple different layers (such as the through-silicon via (TSV) layer responsible for vertical through-hole connections and the microbump layer responsible for surface contact). Each layer has a unique geometry, material properties, and failure mode: defects in TSVs mainly manifest as interruptions in vertical signal paths or degraded transmission performance, while microbump failures are more often reflected in unstable contact interfaces or abnormal resistance. More challenging is that defects in these two layers do not exist independently—the performance degradation of TSVs often exacerbates stress distribution changes at the microbumps they connect to, thereby inducing or amplifying poor contact and forming a complex chain reaction.

[0004] Existing detection technologies lack sophisticated decomposition strategies for different physical levels, making it difficult to distinguish whether defects originate from through-silicon vias or microbumps. Furthermore, they cannot effectively track the propagation and expansion paths of defects between levels. This results in either missing deep, subtle faults or misjudging chain reactions as multiple independent defects, thus affecting the accuracy and efficiency of subsequent repairs. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the problem in the prior art that the unique failure characteristics of through-silicon vias and microbumps in different physical levels within the chip interconnect structure and the chain reaction between levels are ignored, which makes it impossible to accurately locate the root cause of defects and track their expansion range. The present invention provides a chip interconnect structure defect detection method based on physical level decomposition, which can determine the defect source and the range of influence by distinguishing the independent characteristics of the through-silicon via level and the microbump level, constructing an association diagram containing the chain path, and determining the defect source and the range of influence based on the comparison of actual signal response, thereby achieving accurate identification of defect level attribution, root cause location and chain influence area.

[0006] To address the aforementioned technical problems, this invention provides a method for detecting defects in chip-particle interconnect structures based on physical level decomposition, comprising the following steps: Obtain the layout and connection data of the two physical layers, through-silicon via (TSV) and microbump, in the chip interconnect structure; Based on the layout data, the through silicon vias and microbumps are decomposed according to their respective physical space coordinates to form a first independent feature set at the through silicon via level and a second independent feature set at the microbump level. The first independent feature set includes the position and vertical penetration attributes of each through silicon via, and the second independent feature set includes the position and surface contact attributes of each microbump. Based on the first independent feature set, vertical signal interruption features on through-silicon vias are identified; based on the second independent feature set, poor contact features on microbumps are identified. Based on the connectivity data, a physical connectivity topology diagram consisting of through-silicon vias and microbumps is established; vertical signal interruption features and poor contact features are marked on the physical connectivity topology diagram, and features with spatial adjacency or electrical coupling are connected into interlocking paths, thereby generating a correlation diagram of interconnection defects. Traverse each chain path in the association graph, mark the first node on the path that shows signal interruption or poor contact as the defect source point, and obtain a defect location list containing the defect source points. Based on the physical layer to which each defect source point belongs in the defect location list, select the corresponding test signal and inject it into the physical link where each defect source point is located; collect the signal response of each downstream node along the physical link in sequence; The signal response is compared point by point with the reference response of a standard defect-free link to extract the differences in the signal response; based on the location and attenuation of the differences in the physical link, the extent to which the chain reaction triggered by each defect source point extends is determined. Based on the type of difference characteristics, the physical level of the defect source, and the extent of the expansion, the defect detection results of the core-particle interconnect structure are output.

[0007] In one embodiment of the present invention, through-silicon vias (TSVs) and microbumps are decomposed according to their respective physical space coordinates to form a first independent feature set at the TSV level and a second independent feature set at the microbump level, including: Based on the three-dimensional spatial coordinates of each through-silicon via in the layout data, through-silicon vias whose vertical coordinates are within the same preset depth range are classified into the first independent feature set. Each entry in the first independent feature set includes the horizontal and vertical coordinates of the center point of the through-silicon via, the penetration depth, and the coordinates of both end points. Based on the two-dimensional planar coordinates of each microbump in the layout data, microbumps whose horizontal coordinates are located in the same chip area are classified into the second independent feature set. Each entry in the second independent feature set includes the center point coordinates, contact surface diameter, and height of the microbump.

[0008] In one embodiment of the present invention, the specific method for identifying vertical signal interruption features present on a through-silicon via is as follows: For each through-silicon via in the first independent feature set, obtain the electrical connectivity test value at both ends of the through-silicon via; When the electrical signal at one end of a through-silicon via cannot be detected from the other end within a preset time window, the through-silicon via is marked as having a vertical signal interruption feature, and the interruption type is recorded as a complete interruption in the first independent feature set, wherein: the preset time window is set to twice the theoretical transmission time required to transmit from one end to the other end. When an electrical signal can be detected but its amplitude is less than 50% of the standard amplitude under defect-free conditions of a through-silicon via (TSV), the TSV is marked as having a vertical signal interruption feature, and the interruption type is recorded as partial interruption in the first independent feature set. The 50% threshold is determined based on the median value of the logic level decision threshold of the signal receiver. That is, when the signal amplitude is less than half of the standard amplitude, the receiver cannot reliably distinguish between high and low levels.

[0009] In one embodiment of the present invention, the specific method for identifying poor contact features present on the micro-bumps is as follows: For each micro-bump in the second independent feature set, the contact resistance measurement value of the contact interface on both sides of the micro-bump is obtained; When the measured contact resistance value is greater than five times the standard contact resistance value under defect-free microbump conditions, the microbump is marked as having poor contact characteristics, and the type of poor contact is recorded as high resistance contact in the second independent feature set. The five-times threshold is determined based on the engineering margin for the allowable fluctuation of contact resistance under normal chip operating conditions. That is, when the contact resistance exceeds five times the standard value, the additional power consumption and signal attenuation caused by the microbump have exceeded the design redundancy range. When the contact resistance measurement value shows unstable fluctuations in multiple measurements, and the relative change rate between two adjacent measurements exceeds 30%, the micro-bump is marked as having poor contact characteristics, and the type of poor contact is recorded as intermittent contact in the second independent feature set. The 30% relative change rate threshold is determined based on the statistical upper limit of the normal contact resistance fluctuation range of the micro-bump contact interface under mechanical vibration or thermal expansion conditions. Exceeding this relative change rate threshold indicates that there is an unstable physical gap at the contact interface.

[0010] In one embodiment of the present invention, connecting features that are spatially adjacent or electrically coupled into a chain path includes: Traverse each through-silicon via with a vertical signal interruption feature in the first independent feature set, and find all microbumps that are directly connected to one or both ends of the through-silicon via in the physical connection topology graph. When the found microbump exists in the second independent feature set and is marked as having poor contact features, the connection edge between the through silicon via and the microbump is marked as spatially adjacent. When the microbump found does not have poor contact characteristics but the interruption characteristics of the through silicon via cause the signal amplitude at the microbump to be lower than the minimum amplitude required for its normal operation, the connection edge between the through silicon via and the microbump is marked as an electrical coupling relationship. By sequentially connecting through-silicon vias and microbumps that have spatial adjacency or electrical coupling, a chain path is formed from the first defective node to the last affected node.

[0011] In one embodiment of the present invention, features that are spatially adjacent or electrically coupled are connected into a chain path, and the method of merging multiple chain paths is also included: When the end node in the first chain path and the start node in the second chain path have a direct connection relationship in the physical connection topology graph, the first chain path and the second chain path are merged into an extended chain path; When two chain paths share the same defect source point, these two chain paths are merged into a branch chain path starting from the defect source point.

[0012] In one embodiment of the present invention, the specific method for traversing each chain path in the association graph and marking the first node on the path showing a signal interruption feature or poor contact feature as the defect source point is as follows: Starting from the beginning of each chain path in the association graph, check the marking status of each node in the first independent feature set or the second independent feature set in sequence along the signal transmission direction; The first node detected that is marked as having vertical signal interruption or poor contact characteristics is identified as a candidate source point for the chain path; When there are no other nodes marked as having vertical signal interruption characteristics or poor contact characteristics in the physical connection topology graph upstream of the candidate source point, the candidate source point is marked as a defect source point. If there are other marked nodes upstream of the candidate source point, mark the marked node that is closest to the candidate source point upstream as the defect source point.

[0013] In one embodiment of the present invention, the specific method for selecting the corresponding test signal and injecting it into the physical link where each defect source point is located according to the physical layer to which each defect source point belongs in the defect location list is as follows: When the defect source point belongs to the through-silicon via (TSV) level, a time-domain reflection pulse signal propagating vertically is selected as the test signal by injecting it from the entrance end of the TSV. When the defect source point belongs to the microbump level, a continuous sinusoidal wave signal propagating in the horizontal direction is injected from the output end of the through silicon via connected to the microbump as the test signal. Set the frequency of the selected test signal to the same value as the normal operating clock frequency of the physical link under test, and set the amplitude of the test signal to 1.5 times the minimum amplitude that can be transmitted normally under the condition that the physical link is defect-free; where the amplitude multiplier of 1.5 times is determined based on the empirical attenuation coefficient of the signal after passing through a defective node on the transmission path.

[0014] In one embodiment of the present invention, the specific method for sequentially collecting the signal responses of each downstream node along the physical link is as follows: Identify all nodes downstream of the signal transmission direction on the physical link where the defect source is located, and arrange the acquisition order of each downstream node in order from near to far along the signal transmission direction starting from the defect source. For each downstream node, a signal acquisition probe is connected at the node, and the voltage waveform at the node is continuously acquired after the test signal is injected. The acquired voltage waveforms are digitally sampled along the time axis to obtain the response sequence of each downstream node.

[0015] In one embodiment of the present invention, the specific method for extracting the difference features of the signal response by comparing the signal response point by point with the reference response of a standard defect-free link is as follows: For each downstream node, the standard response waveform of the node to the same test signal is obtained in advance when the physical link under test is in a defect-free state, and the standard response waveform is digitized into a standard response sequence. The difference sequence is obtained by subtracting the values ​​of the actual response sequence collected by the downstream node from the values ​​of the standard response sequence at the same time point one by one. The difference with the largest absolute value in the difference sequence is recorded as the peak difference of the node, and the duration of consecutive non-zero differences in the difference sequence is recorded as the duration of the node's persistent difference. Among them, when the peak difference is greater than 20% of the standard response amplitude of the node, the node is judged to have significant signal distortion. The 20% threshold is determined based on the engineering experience value of the signal integrity tolerance of the chip receiver. Peak difference and duration of persistent difference are used as the difference features of nodes.

[0016] The technical solution of the present invention has the following advantages compared with the prior art: The chip interconnect structure defect detection method based on physical hierarchy decomposition described in this invention can identify vertical signal interruption features and poor contact features at the two key levels of through-silicon vias (TSVs) and microbumps, respectively, by physically decomposing the chip interconnect structure. Based on the physical connection topology, a defect correlation diagram is generated to accurately locate the defect source point, thereby achieving accurate tracking of cross-level defect chain reactions. It can accurately identify the physical source of defects in the chip interconnect structure, effectively track the chain reaction path of defects between the TSV and microbump levels, reduce detection misjudgments, and improve the accuracy and efficiency of defect location. Attached Figure Description

[0017] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a flowchart of the steps of the chip interconnect structure defect detection method based on physical level decomposition of the present invention; Figure 2 This is a flowchart of the steps in this invention to identify vertical signal interruption features present on through-silicon vias; Figure 3 This is a flowchart of the steps in this invention to identify poor contact features on micro-bumps; Figure 4 This is a flowchart of the steps in this invention to connect features that have spatial adjacency or electrical coupling into a chain path; Figure 5 This is a flowchart of the steps for marking defect sources in this invention; Figure 6 This is a flowchart of the steps in this invention to select the corresponding test signal and inject it into the physical link where each defect source point is located; Figure 7 This is a flowchart of the steps of the present invention to sequentially collect the signal response of each downstream node along the physical link; Figure 8 This is a flowchart of the steps in the present invention to extract the differential features of signal response. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0019] Reference Figure 1 As shown, this invention proposes a defect detection method for chip interconnect structures based on physical hierarchy decomposition: First, the layout and connection data of the through-silicon via (TSV) and microbump layers in the chip interconnect structure are acquired, and then decomposed according to their respective physical spatial coordinates to form a first independent feature set containing position and vertical penetration attributes, and a second independent feature set containing position and surface contact attributes. The core of this technique is that it no longer treats the interconnect structure as an undifferentiated whole, but distinguishes two layers from the fundamental physical structure, laying the foundation for subsequent targeted analysis.

[0020] Based on this, the vertical signal interruption features on the through silicon via and the poor contact features on the microbumps are independently identified according to two feature sets, thus realizing a one-to-one correspondence between failure modes and physical levels.

[0021] Furthermore, by establishing a physical connection topology map composed of through-silicon vias and microbumps, and marking the identified interruption and poor contact features within it, and then connecting features with spatially adjacent or electrically coupled relationships into chain paths, an interconnection map of interconnection defects is generated. This process reveals the hierarchical coupling relationships that existing technologies have consistently failed to grasp—it organizes previously isolated interruption points and poor contact points into paths according to their actual physical connections and influence relationships, making the propagation direction and dependencies of chain reactions clear and traceable for the first time.

[0022] Subsequently, by traversing each chain path, the first node on the path that shows signs of signal interruption or poor contact is marked as the defect source point, thereby accurately locating the root triggering location of the problem from the complex fault phenomena, rather than staying at the surface symptoms.

[0023] For these source points, the method selects the corresponding test signal based on their physical layer and injects it into the corresponding link. It then collects the signal responses of downstream nodes along the link and compares the actual responses with the reference responses of a standard defect-free link point by point, extracting the differences. Based on the location and attenuation of these differences in the link, the scope of the chain reaction triggered by each source point is determined. The key logic of this technical solution lies in the fact that, through layered injection, layered acquisition, and point-by-point comparison, it avoids misjudgments caused by interference from mixed signals and quantifies the impact of defects on downstream nodes.

[0024] Finally, based on the type of difference feature, the physical level of the source point, and the extent of the expansion, the detection results are output, including the level of the defect, the topological location, and the list of affected nodes.

[0025] Through the above technical solution, the present invention achieves the following beneficial effects: First, because the through-silicon vias and microbumps are physically decomposed from the data acquisition stage and the hierarchy is maintained throughout all subsequent identification, labeling, injection, and comparison stages, it is possible to clearly distinguish whether the defect originates from the vertical through-structure or the surface contact structure, avoiding the confusion between the two levels of issues and significantly improving the accuracy of defect location.

[0026] Second, by constructing an association graph and connecting spatially adjacent or electrically coupled features into a chain path, and then taking the first defect node as the source point, the propagation chain of the defect can be reconstructed at the physical mechanism level, thereby accurately identifying the starting point of the chain reaction rather than just reporting all fault phenomena, solving the problem that existing technologies cannot trace the root cause.

[0027] Third, by selecting test signals for the level to which the source point belongs and comparing response differences point by point, it does not need to rely on preset thresholds or empirical criteria. It judges the existence of defects and their scope of influence entirely based on the objective difference between the actual response and the standard reference. Therefore, it has better process adaptability and cross-platform versatility.

[0028] Fourth, the final output test results include the defect level, topology location, and list of affected nodes, providing clear and actionable guidance for subsequent repair or fault-tolerant operations, thereby improving the overall testability and manufacturing yield of the chip interconnect structure.

[0029] In some of the above embodiments, it is proposed to decompose through-silicon vias (TSVs) and microbumps according to their respective physical spatial coordinates based on layout data, so as to form a first independent feature set at the TSV level and a second independent feature set at the microbump level. However, if these physical layer features are not decomposed and their attributes recorded in a refined and structured manner, the resulting feature set information may not be comprehensive or accurate enough, thereby affecting the accuracy and location efficiency of subsequent defect identification.

[0030] In response, this application further proposes to decompose through-silicon vias (TSVs) and microbumps according to their respective physical space coordinates, forming a first independent feature set at the TSV level and a second independent feature set at the microbump level, specifically including: For the decomposition of through-silicon vias (TSVs), the three-dimensional spatial coordinates of each TSV in the layout data provide its precise location information within the chip, including X, Y, and Z axis coordinates. This is crucial for understanding its physical characteristics in the vertical direction. TSVs with vertical coordinates within the same preset depth range are grouped into a first independent feature set. This aims to group TSVs with similar vertical transport characteristics; for example, the depth range can be set according to chip stack levels or functional partitions. This classification helps to apply more targeted detection strategies for TSVs within specific depth ranges in subsequent analysis, improving the accuracy of defect localization. Each entry in the first independent feature set contains the X and Y coordinates of the TSV's center point, its penetration depth, and the coordinates of its two endpoints. The center point's horizontal and vertical coordinates provide the precise location of the through-silicon via (TSV) on the chip plane, which is the basis for planar layout analysis and association with other planar structures. The penetration depth indicates the thickness of the silicon layer that the TSV penetrates in the vertical direction, directly affecting its electrical characteristics such as resistance and capacitance, and is a key parameter for evaluating vertical signal integrity. The coordinates of the two endpoints clarify the connection point between the TSV and the upper and lower metal interconnects, which plays a decisive role in determining whether it is correctly connected to microbumps or other interconnect structures, as well as identifying the precise location of vertical signal interruptions.

[0031] For the decomposition of microbumps, the two-dimensional planar coordinates of each microbump in the layout data provide its precise two-dimensional position information on the chip surface, which is the basis for planar interconnect analysis and defect localization. Microbumps whose horizontal coordinates are located within the same chip region are grouped into a second independent feature set. The chip region can be divided based on functional modules, power domains, or physical partitions, etc. Classifying microbumps within the same region helps with localized analysis, improves processing efficiency, and better identifies regional defect patterns. Each entry in the second independent feature set contains the center point coordinates, contact surface diameter, and height of the microbump. The center point coordinates provide the precise position of the microbump on the chip plane, which is the basis for planar layout analysis and association with other planar structures; the contact surface diameter determines the contact area between the microbump and the corresponding pad, directly affecting contact resistance and current density, and is a key geometric parameter for evaluating contact quality; the height reflects the size of the microbump in the vertical direction, which is crucial for ensuring physical contact during chip stacking and avoiding short circuits or open circuits.

[0032] In some embodiments described above, the method for identifying vertical signal interruption features on through-silicon vias (TSVs) is proposed. However, in practice, accurately and reliably determining whether a TSV has experienced a vertical signal interruption, and distinguishing between different types of interruptions, is a key challenge in ensuring the effectiveness of defect detection. Relying solely on vague signal attenuation or absence may lead to misjudgments or missed detections, affecting the accuracy of subsequent defect localization and analysis.

[0033] Reference Figure 2 As shown, this application further proposes a specific method for identifying vertical signal interruption features present on through-silicon vias (TSVs). This method, for each TSV in a first independent feature set, first acquires electrical connectivity test values ​​at both ends of the TSV. Specifically, this can be achieved by injecting a specific test signal, such as a time-domain reflectometry pulse signal or a DC voltage, into one end of the TSV, and measuring the corresponding signal response, such as voltage waveform, current, or signal logic state, at the other end of the TSV using a signal acquisition probe or built-in test circuitry.

[0034] When the electrical signal at one end of a through-silicon via (TSV) cannot be detected from the other end within a preset time window, the TSV is marked as having a vertical signal interruption feature, and the interruption type is recorded as a complete interruption in a first independent feature set. The preset time window is set to twice the theoretical transmission time required to travel from one end to the other. For example, if the theoretical transmission time is 1 nanosecond, the preset time window can be set to 2 nanoseconds. If the receiving end fails to detect any valid signal within these 2 nanoseconds, it can be determined as a complete interruption. This setting takes into account the normal transmission delay of the signal in a defect-free state and provides sufficient margin to distinguish between a true signal interruption and normal transmission fluctuations.

[0035] Furthermore, when an electrical signal can be detected but its amplitude is less than 50% of the standard amplitude under defect-free conditions in a through-silicon via (TSV), the TSV is marked as having a vertical signal interruption feature, and the interruption type is recorded as partial interruption in the first independent feature set. The 50% threshold is determined based on the median value of the logic level decision threshold at the signal receiver; that is, when the signal amplitude is less than half the standard amplitude, the receiver cannot reliably distinguish between high and low levels. For example, if the standard amplitude is 1 volt, and the received signal amplitude is less than 0.5 volts, even if a signal is present, the receiver may be unable to correctly distinguish logic "0" or "1," thus causing a functional failure. In this way, defects that, although not completely disconnected, have severely affected signal integrity can be identified.

[0036] In some of the embodiments described above in this application, the identification of poor contact features on micro-bumps is proposed. However, in actual testing, poor contact of micro-bumps may manifest in various forms, such as continuous high impedance or intermittent contact interruption. If only a simple poor contact judgment is made, it may not be possible to fully and accurately identify and distinguish these different types of defects, thereby affecting the accuracy of defect location and the formulation of subsequent repair strategies.

[0037] Reference Figure 3As shown, this application further proposes a specific method for identifying poor contact characteristics on microbumps. Specifically, obtaining the contact resistance measurement value of the contact interface on both sides of the microbump is the basis for identifying poor contact characteristics. This measurement value reflects the electrical quality of the connection between the microbump and the upper and lower layers. In practical operation, a high-precision four-wire Kelvin measurement method can be used. A micro probe station is used to accurately contact the probe with the microbump and its connected pads, and a high-precision resistance meter is used for measurement. This method can effectively eliminate the influence of the test lead resistance on the measurement results and ensure the accuracy of the measurement value. To improve detection efficiency, a customized array probe card can also be designed to realize parallel or rapid serial measurement of multiple microbumps.

[0038] Furthermore, this application proposes a quantitative judgment standard for identifying high-resistance contact defects. When the measured contact resistance value of a microbump is greater than five times the standard contact resistance value of the microbump in a defect-free state, the microbump is determined to have a high-resistance contact defect. In this case, the system marks the microbump as having poor contact characteristics and explicitly records the type of poor contact as high-resistance contact in a second independent feature set. The five-fold threshold is not arbitrary but based on in-depth research into the allowable fluctuation range of contact resistance under normal chip operating conditions and engineering margin considerations. When the contact resistance exceeds five times the standard value, the additional power consumption and signal attenuation caused by the microbump exceed the design redundancy range, potentially leading to signal integrity issues or even functional failure. Therefore, this threshold can effectively distinguish between normal fluctuations and actual performance degradation.

[0039] Furthermore, to identify more subtle intermittent contact defects, this application proposes a dynamic detection mechanism. Specifically, the contact resistance of the same microbump is measured multiple times consecutively. If, during these measurements, the contact resistance values ​​exhibit unstable fluctuations, and the relative rate of change between two adjacent measurements exceeds 30%, the microbump is marked as having poor contact characteristics, and its type of poor contact is recorded as intermittent contact in a second independent feature set. The 30% relative rate of change threshold is determined based on the statistical upper limit of the normal contact resistance fluctuation range of the microbump contact interface under the influence of environmental factors such as mechanical vibration and thermal expansion. Once the measurement result exceeds this threshold, it strongly indicates the presence of unstable physical gaps at the microbump contact interface. These gaps may lead to signal interruption or performance degradation under certain conditions, threatening the long-term reliability of the chip. This dynamic detection effectively captures intermittent defects that are difficult to detect through static testing.

[0040] Reference Figure 4 As shown, this application further proposes a method for connecting features with spatial adjacency or electrical coupling relationships into a chain path, specifically including: The system iterates through each via with a vertical signal interruption feature in the first independent feature set, searching the physical connection topology map for all microbumps directly connected to one or both ends of the via. First, the system accesses the first independent feature set to filter out all vias marked with a vertical signal interruption feature. For each such via, using the pre-established physical connection topology map, it queries for all microbumps physically directly connected to either end of the via (e.g., the top or bottom). This is typically done by parsing layout and connection relationship data, for example, by comparing the proximity of the via endpoint coordinates to the microbump center coordinates, or by searching the connection relationship database for microbump identifiers connected to the via.

[0041] When a microbump is found and exists in the second independent feature set and is marked as having poor contact characteristics, the connection edge between the through-silicon via (TSV) and the microbump is marked as spatially adjacent. This step is used to identify direct defect associations between physically connected TSVs and microbumps that both have defects. When a microbump found in the previous step is also explicitly marked as having poor contact characteristics in the second independent feature set, it indicates that both adjacent physical structures have defects. In this case, the edge connecting the TSV and the microbump will be marked as spatially adjacent in the physical connection topology diagram. This indicates that the two defects are physically closely connected and may be mutually causal or jointly cause signal anomalies.

[0042] When a microbump is found to have no poor contact characteristics, but the interruption characteristics of a through-silicon via (TSV) cause the signal amplitude at the microbump to be lower than the minimum amplitude required for its normal operation, the connection edge between the TSV and the microbump is marked as an electrical coupling relationship. This step aims to identify situations where the electrical performance of the microbump is affected by a defect in the upstream TSV, even though the microbump itself is not marked as a defect. In practice, signal integrity analysis or simulation is required. When a TSV exhibits vertical signal interruption characteristics (whether complete or partial), and simulation or actual measurement evaluation reveals that the defect in the TSV causes the signal amplitude (e.g., voltage or current) at the directly connected downstream microbump to be lower than the minimum threshold required for the microbump to operate normally, the connection edge between the TSV and the microbump should be marked as an electrical coupling relationship, even if the microbump itself has no poor contact. This indicates that the defect in the TSV affects the function of the microbump through an electrical path, forming an indirect defect association.

[0043] By sequentially connecting spatially adjacent or electrically coupled vias and microbumps in series, a chain path is formed from the first defective node to the last affected node. This step is crucial for constructing the defect propagation path. After identifying all spatially adjacent or electrically coupled via-microbump connection edges, the system connects the relevant vias and microbumps in series along these marked edges, following the signal transmission direction. This chaining process begins at the first identified defective node (e.g., a via with a vertical signal interruption or a microbump with poor contact) and extends along these marked connection edges until the signal is no longer affected or reaches the end of the chain. This ultimately forms a complete chain path, clearly showing the defect's starting point, propagation path, and affected area.

[0044] In practical applications, when the end node in the first chain path and the start node in the second chain path are directly connected in the physical connection topology, the first and second chain paths are merged into an extended chain path. The end node in the first chain path refers to the last affected physical component in the signal transmission direction of an identified defect propagation path, such as a through-silicon via (TSV) or microbump. The start node in the second chain path refers to the first physical component marked as defective in the signal transmission direction of another identified defect propagation path. A direct connection in the physical connection topology means that the two nodes are directly connected in terms of the actual physical layout and electrical connection of the chip, allowing signals to be seamlessly transmitted from one node to the other. This merging operation connects two previously independent defect propagation paths, forming a longer, continuous defect propagation chain. For example, if a vertical signal interruption in a through-silicon via (TSV) causes an abnormal signal in a downstream microbump, and that microbump is directly connected to another microbump with poor contact, then by merging, a complete defect path from the TSV to the two microbumps can be formed, revealing the cascading effect of defects.

[0045] Furthermore, when two chain paths share the same defect source point, these two chain paths are merged into a branched chain path originating from the defect source point. Sharing the same defect source point refers to two or more independent defect propagation paths whose initial defect occurrence point is the same physical component. For example, a vertical signal interruption in a through-silicon via (TSV) may simultaneously affect two different microbumps it connects, resulting in two defect paths emanating from that TSV. This merging operation integrates all different propagation paths originating from the same defect source point, forming a defect map with a branched structure. This helps identify how a single fundamental defect can cause multiple parallel signal integrity problems, thus enabling more effective location and resolution of the root cause.

[0046] In the process of detecting defects in core-particle interconnect structures, although a physical connection topology map can be built based on connection relationship data to generate an association map of interconnect defects, and then each chain path in the association map can be traversed to identify signal interruption features or poor contact features, accurately locating the defect source point that causes a series of subsequent signal anomalies from these chain paths is a key issue. If only the first detected anomaly on the path is marked as the source point, it may be impossible to distinguish whether it is a primary defect or a secondary phenomenon caused by an upstream defect, thus affecting the accuracy of defect location and the efficiency of subsequent repair.

[0047] Reference Figure 5 As shown, this application further proposes a specific method for traversing each chain path in the association graph and marking the first node on the path showing a signal interruption feature or poor contact feature as the defect source point, including: Traversing each chain path in the correlation graph, the first node on the path exhibiting a signal interruption or poor contact characteristic is marked as the defect source point. The aim is to precisely locate the initial defect node, or defect source point, that causes the entire chain reaction from the identified defect chain paths. The correlation graph is constructed based on a physical connection topology diagram, which labels vertical signal interruption and poor contact characteristics and connects them into chain paths through spatial adjacency or electrical coupling. Traversing these paths is the foundation for systematically analyzing defect propagation chains.

[0048] Starting from the beginning of each chain path in the association diagram, the marking status of each node is checked sequentially along the signal propagation direction in either the first independent feature set or the second independent feature set. This step describes the starting point and direction for checking the chain paths. The starting point is typically the signal injection or design starting point, and checking along the signal propagation direction ensures adherence to the defect propagation logic. The marking status of each node in the first independent feature set (for through-silicon vias) or the second independent feature set (for microbumps) indicates whether that node has a vertical signal interruption feature or a poor contact feature. This check is performed node-by-node to ensure that no potential defect information is missed.

[0049] The first node identified as exhibiting vertical signal interruption or poor contact characteristics is designated as a candidate source point for the chain path. During the inspection along the signal transmission direction, once the first node marked as defective (whether due to vertical signal interruption or poor contact) is encountered, it is preliminarily identified as a candidate source point for that chain path. This represents the location of the first anomaly observed on that path from a signal transmission perspective.

[0050] A candidate source point is marked as a defect source point when there are no other nodes marked as having vertical signal interruption or poor contact characteristics in the physical connection topology graph upstream of it. This step is one of the key criteria for determining the true defect source point. If a candidate source point has no other nodes marked as defective in the entire physical connection topology graph upstream of its signal transmission, then it can be confirmed that the candidate source point is the original defect causing all subsequent anomalies, and therefore it is confirmed as the final defect source point. This excludes secondary anomalies caused by more upstream defects.

[0051] If other marked nodes exist upstream of the candidate source point, the marked node closest to the candidate source point upstream is designated as the defect source point. This is another key criterion for determining the defect source point. If other marked nodes as defects exist upstream of the candidate source point, it means that the candidate source point may not be the original defect, but rather caused by a defect upstream. In this case, to find the true root cause, it is necessary to backtrack upstream and confirm the node marked as defect closest to the candidate source point as the final defect source point. This ensures that even with multiple consecutive defects, the most upstream original defect can be accurately located.

[0052] In some embodiments described above, a method is proposed to traverse each chain path in the association graph, mark the first node on the path exhibiting signal interruption or poor contact characteristics as the defect source point, and obtain a defect location list containing the defect source points. However, after obtaining the defect source point, how to select an appropriate test signal for injection based on its physical level and characteristics to accurately assess the scope and extent of the defect's impact on the physical link is a problem that needs further resolution. If the test signal is not selected properly, it may fail to effectively excite the defect characteristics or accurately reflect the signal propagation behavior in the defective link, thereby affecting the accuracy and efficiency of defect detection.

[0053] Reference Figure 6 As shown, this application further proposes a specific method for selecting the corresponding test signal and injecting it into the physical link where each defect source point is located, based on the physical layer to which each defect source point belongs in the defect location list.

[0054] Specifically, when the defect source is at the through-silicon via (TSV) level, a time-domain reflected pulse (TDR) signal propagating vertically is injected from the TSV's entry point as the test signal. As a vertical interconnect structure, defects in TSVs (such as open circuits, short circuits, and impedance mismatches) typically manifest as reflection or attenuation of the signal during vertical transmission. The TDR signal can accurately detect and locate these vertical impedance discontinuities by analyzing the reflected waveform. The TSV's entry point typically refers to the physical connection point where the signal enters the TSV, such as the pads or traces connecting the top or middle layers of the chip to the TSV.

[0055] When the defect source is at the microbump level, a continuous sinusoidal wave signal propagating horizontally is injected from the output of the via connected to the microbump as the test signal. Microbumps primarily handle horizontal electrical connections between or within chips; defects in them (such as poor contact, high resistance, or intermittent contact) often affect signal amplitude, phase, or cause nonlinear distortion. A continuous sinusoidal wave signal can effectively detect these frequency-dependent characteristics. Contact quality is assessed by measuring the amplitude attenuation, phase shift, or harmonic distortion at the microbump. The output of the via connected to the microbump is the physical connection point from the previous vertical interconnect structure (via) before the signal reaches the microbump, ensuring the test signal reaches the microbump along a normal signal path.

[0056] Furthermore, the frequency of the selected test signal is set to the same value as the normal operating clock frequency of the physical link under test. This is to ensure that the test is conducted at a frequency consistent with actual operating conditions, thus more accurately reflecting the impact of defects on signal transmission during actual operation, as some defects may be frequency-dependent. The normal operating clock frequency is typically determined by the design specifications of the chip interconnect structure. Simultaneously, the amplitude of the test signal is set to 1.5 times the minimum amplitude that can be transmitted normally under defect-free physical link conditions. This 1.5-fold amplitude multiplier is determined based on the empirical attenuation coefficient of the signal after passing through a defective node on the transmission path. This aims to ensure that even if the signal attenuates to some extent when passing through the defect source point, its remaining amplitude is still sufficient to be reliably detected and measured at downstream nodes, thereby avoiding missed detections or underestimation of the defect's impact range due to a weak signal. The minimum amplitude refers to the lowest voltage or current level at which the signal can be correctly identified and processed by the downstream receiver under defect-free conditions.

[0057] Reference Figure 7 As shown, this application further proposes a specific method for sequentially collecting the signal responses of each downstream node along the physical link, including: The first step is to identify all nodes downstream of the defect source point on the physical link in the direction of signal transmission, and then arrange the acquisition sequence of these downstream nodes in ascending order from the defect source point along the expected direction of signal transmission. This step aims to clarify the acquisition range and logical order of the signal response. After identifying the defect source point, the established physical connection topology map is used to identify all downstream nodes that may be affected by the defect, starting from the defect source point and proceeding along the expected direction of signal transmission. These downstream nodes can be through-silicon vias (TSVs) or micro-bumps. To ensure the systematic nature and traceability of data acquisition, these downstream nodes need to be sorted, typically according to their physical distance or logical hop count from the defect source point, from nearest to farthest. For example, graph traversal algorithms (such as breadth-first search or depth-first search) can be used to systematically identify and sort these downstream nodes, ensuring that all affected paths are covered and that the acquisition order reflects the actual path of signal propagation.

[0058] For each downstream node, a signal acquisition probe is connected at the node to continuously acquire the voltage waveform at the node after the test signal is injected. This step describes the physical acquisition method of the signal response. At each node identified as downstream, a corresponding signal acquisition probe needs to be deployed. These probes can be high-impedance voltage probes, current probes, or test structures integrated into the chip (such as voltage sensors or scan chains in a built-in self-test BIST module). After the test signal is injected into the physical link where the defect source is located, these probes will monitor and acquire the voltage waveform at the node in real time and continuously. Continuous acquisition means capturing the complete analog voltage signal at a sufficiently high sampling rate within a certain time window, rather than just a single instantaneous value. This is crucial for analyzing the dynamic characteristics of the signal (such as rise time, fall time, overshoot, undershoot, ringing, etc.).

[0059] The acquired voltage waveforms are digitally sampled along the time axis to obtain the response sequence of each downstream node. This step converts the analog signal into a digital format for subsequent storage, processing, and analysis. The acquired continuous analog voltage waveforms are digitized using an analog-to-digital converter (ADC). The ADC discretizes the analog waveform along the time axis at a preset sampling frequency and quantization precision, converting continuous voltage values ​​into a series of discrete digital samples. These digital samples are arranged in chronological order to form a response sequence that accurately reflects the voltage state of a node at a specific point in time. Digital sampling is fundamental for subsequent signal comparison, feature extraction, and defect analysis; its sampling rate and resolution directly affect the degree of detail preserved in the signal.

[0060] In some of the embodiments described above in this application, although it is possible to collect the signal responses of each downstream node sequentially along the physical link, the key to ensuring the accuracy and reliability of defect detection lies in how to effectively analyze these collected signal responses to accurately identify and quantify signal anomalies caused by defects, and to distinguish between normal fluctuations and significant signal distortions caused by actual defects. Relying solely on visual inspection or simple thresholds may lead to misjudgments or missed detections, affecting the accuracy of defect location.

[0061] Reference Figure 8 As shown, this application further proposes a specific method for extracting the difference features of the signal response by comparing the signal response point by point with the reference response of a standard defect-free link, including: The standard response waveform of a node to the same test signal when the physical link under test is in a defect-free state is acquired in advance and digitized into a standard response sequence to establish a reliable benchmark. This standard response waveform can be obtained in various ways, such as predicting the theoretical response through high-precision circuit simulation of a defect-free physical link (e.g., using SPICE or IBIS models); or acquiring the signal response of a known defect-free chip under the same test conditions through actual testing; or calculating its ideal response by establishing an accurate electromagnetic field model based on the geometry and material parameters of the physical link. The acquired analog waveform is then digitized by an analog-to-digital converter (ADC) at a preset sampling rate and quantization precision to form a discrete standard response sequence, ensuring the accuracy of subsequent digital comparisons.

[0062] The core step in quantifying signal bias is to subtract the values ​​of the actual response sequence acquired by downstream nodes from the standard response sequence at the same time point, obtaining the difference sequence. This process requires precise alignment of the actual and standard response sequences on the time axis, which can be achieved by using a synchronous triggering mechanism during signal acquisition or by applying signal processing techniques such as timestamp calibration and cross-correlation algorithms during data processing. The point-by-point subtraction operation can directly and meticulously reveal the amplitude difference between the actual and ideal signals at each time point, thus forming a difference sequence that reflects the degree of signal distortion.

[0063] Recording the largest absolute difference in the difference sequence as the peak difference of a node, and recording the duration of consecutive non-zero differences as the persistence of the node, is to extract the most representative features from the difference sequence. The peak difference directly reflects the maximum magnitude of the signal deviating from the standard state and is a key indicator for measuring the degree of damage to signal integrity. The persistence of the difference characterizes the duration of signal distortion and is important for determining the type of defect (e.g., transient or persistent faults).

[0064] In practice, to avoid non-zero differences caused by minor noise, a threshold of 20% is set to indicate significant signal distortion at a node when the peak difference exceeds the standard response amplitude. This 20% threshold is determined based on engineering experience regarding the signal integrity tolerance of the chip's receiver. This criterion provides a quantitative basis for identifying defects that truly affect system functionality. The 20% threshold is not arbitrarily set but is based on extensive engineering practice and signal integrity analysis, taking into account the chip's receiver's tolerance for signal waveform distortion. When signal distortion exceeds this threshold, the receiver may be unable to reliably determine the signal's logical state, leading to functional errors. Therefore, this threshold effectively distinguishes between severe signal integrity problems caused by defects and signal fluctuations or measurement noise under normal operating conditions.

[0065] Ultimately, peak differences and duration of persistent differences are used as the difference features of nodes, which form the basis for subsequent defect analysis and localization. They summarize the anomalies in signal response in a concise and comprehensive manner, providing key data for defect type identification, severity assessment, and precise tracking of defect sources.

[0066] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for detecting defects in core-particle interconnect structures based on physical level decomposition, characterized in that, Includes the following steps: Obtain the layout and connection data of the two physical layers, through-silicon via (TSV) and microbump, in the chip interconnect structure; Based on the layout data, the through silicon vias and microbumps are decomposed according to their respective physical space coordinates to form a first independent feature set at the through silicon via level and a second independent feature set at the microbump level. The first independent feature set includes the position and vertical penetration attributes of each through silicon via, and the second independent feature set includes the position and surface contact attributes of each microbump. Based on the first independent feature set, the vertical signal interruption features present on the through silicon via were identified; Based on the second independent feature set, poor contact features present on the micro-bumps are identified; Based on the connectivity data, a physical connectivity topology diagram consisting of through-silicon vias and microbumps is established; vertical signal interruption features and poor contact features are marked on the physical connectivity topology diagram, and features with spatial adjacency or electrical coupling are connected into interlocking paths, thereby generating a correlation diagram of interconnection defects. Traverse each chain path in the association graph, mark the first node on the path that shows signal interruption or poor contact as the defect source point, and obtain a defect location list containing the defect source points. Based on the physical layer to which each defect source point belongs in the defect location list, select the corresponding test signal and inject it into the physical link where each defect source point is located; collect the signal response of each downstream node along the physical link in sequence; The signal response is compared point by point with the reference response of a standard defect-free link to extract the differences in the signal response; based on the location and attenuation of the differences in the physical link, the extent to which the chain reaction triggered by each defect source point extends is determined. Based on the type of difference characteristics, the physical level of the defect source, and the extent of the expansion, the defect detection results of the core-particle interconnect structure are output.

2. The method for detecting defects in core-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: The through-silicon vias (TSVs) and microbumps are decomposed according to their respective physical space coordinates, forming a first independent feature set at the TSV level and a second independent feature set at the microbump level, including: Based on the three-dimensional spatial coordinates of each through-silicon via in the layout data, through-silicon vias whose vertical coordinates are within the same preset depth range are classified into the first independent feature set. Each entry in the first independent feature set includes the horizontal and vertical coordinates of the center point of the through-silicon via, the penetration depth, and the coordinates of both end points. Based on the two-dimensional planar coordinates of each microbump in the layout data, microbumps whose horizontal coordinates are located in the same chip area are classified into the second independent feature set. Each entry in the second independent feature set includes the center point coordinates, contact surface diameter, and height of the microbump.

3. The method for detecting defects in core-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: The specific method for identifying vertical signal interruption features on through-silicon vias is as follows: For each through-silicon via in the first independent feature set, obtain the electrical connectivity test value at both ends of the through-silicon via; When the electrical signal at one end of a through-silicon via cannot be detected from the other end within a preset time window, the through-silicon via is marked as having a vertical signal interruption feature, and the interruption type is recorded as a complete interruption in the first independent feature set, wherein: the preset time window is set to twice the theoretical transmission time required to transmit from one end to the other end. When an electrical signal can be detected but its amplitude is less than 50% of the standard amplitude under defect-free conditions of a through-silicon via (TSV), the TSV is marked as having a vertical signal interruption feature, and the interruption type is recorded as partial interruption in the first independent feature set. The 50% threshold is determined based on the median value of the logic level decision threshold of the signal receiver. That is, when the signal amplitude is less than half of the standard amplitude, the receiver cannot reliably distinguish between high and low levels.

4. The method for detecting defects in chip-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: The specific method for identifying poor contact characteristics on micro-bumps is as follows: For each micro-bump in the second independent feature set, the contact resistance measurement value of the contact interface on both sides of the micro-bump is obtained; When the measured contact resistance value is greater than five times the standard contact resistance value under defect-free microbump conditions, the microbump is marked as having poor contact characteristics, and the type of poor contact is recorded as high resistance contact in the second independent feature set. The five-times threshold is determined based on the engineering margin for the allowable fluctuation of contact resistance under normal chip operating conditions. That is, when the contact resistance exceeds five times the standard value, the additional power consumption and signal attenuation caused by the microbump have exceeded the design redundancy range. When the contact resistance measurement value shows unstable fluctuations in multiple measurements, and the relative change rate between two adjacent measurements exceeds 30%, the micro-bump is marked as having poor contact characteristics, and the type of poor contact is recorded as intermittent contact in the second independent feature set. The 30% relative change rate threshold is determined based on the statistical upper limit of the normal contact resistance fluctuation range of the micro-bump contact interface under mechanical vibration or thermal expansion conditions. Exceeding this relative change rate threshold indicates that there is an unstable physical gap at the contact interface.

5. The method for detecting defects in chip-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: Connecting features that are spatially adjacent or electrically coupled into chain paths includes: Traverse each through-silicon via with a vertical signal interruption feature in the first independent feature set, and find all microbumps that are directly connected to one or both ends of the through-silicon via in the physical connection topology graph. When the found microbump exists in the second independent feature set and is marked as having poor contact features, the connection edge between the through silicon via and the microbump is marked as spatially adjacent. When the microbump found does not have poor contact characteristics but the interruption characteristics of the through silicon via cause the signal amplitude at the microbump to be lower than the minimum amplitude required for its normal operation, the connection edge between the through silicon via and the microbump is marked as an electrical coupling relationship. By sequentially connecting through-silicon vias and microbumps that have spatial adjacency or electrical coupling, a chain path is formed from the first defective node to the last affected node.

6. The method for detecting defects in core-particle interconnect structures based on physical hierarchy decomposition according to claim 5, characterized in that: Connecting features that are spatially adjacent or electrically coupled into chain paths includes methods for merging multiple chain paths: When the end node in the first chain path and the start node in the second chain path have a direct connection relationship in the physical connection topology graph, the first chain path and the second chain path are merged into an extended chain path; When two chain paths share the same defect source point, these two chain paths are merged into a branch chain path starting from the defect source point.

7. The method for detecting defects in core-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: The specific method for traversing each chain path in the association graph and marking the first node on the path showing a signal interruption feature or poor contact feature as the defect source point is as follows: Starting from the beginning of each chain path in the association graph, check the marking status of each node in the first independent feature set or the second independent feature set in sequence along the signal transmission direction; The first node detected that is marked as having vertical signal interruption or poor contact characteristics is identified as a candidate source point for the chain path; When there are no other nodes marked as having vertical signal interruption characteristics or poor contact characteristics in the physical connection topology graph upstream of the candidate source point, the candidate source point is marked as a defect source point. If there are other marked nodes upstream of the candidate source point, mark the marked node that is closest to the candidate source point upstream as the defect source point.

8. The method for detecting defects in chip-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: Based on the physical layer to which each defect source point belongs in the defect location list, the specific method for selecting the corresponding test signal and injecting it into the physical link where each defect source point is located is as follows: When the defect source point belongs to the through-silicon via (TSV) level, a time-domain reflection pulse signal propagating vertically is selected as the test signal by injecting it from the entrance end of the TSV. When the defect source point belongs to the microbump level, a continuous sinusoidal wave signal propagating in the horizontal direction is injected from the output end of the through silicon via connected to the microbump as the test signal. Set the frequency of the selected test signal to the same value as the normal operating clock frequency of the physical link under test, and set the amplitude of the test signal to 1.5 times the minimum amplitude that can be transmitted normally under the condition that the physical link is defect-free; where the amplitude multiplier of 1.5 times is determined based on the empirical attenuation coefficient of the signal after passing through a defective node on the transmission path.

9. The method for detecting defects in chip-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: The specific method for collecting the signal responses of each downstream node sequentially along the physical link is as follows: Identify all nodes downstream of the signal transmission direction on the physical link where the defect source is located, and arrange the acquisition order of each downstream node in order from near to far along the signal transmission direction starting from the defect source. For each downstream node, a signal acquisition probe is connected at the node, and the voltage waveform at the node is continuously acquired after the test signal is injected. The acquired voltage waveforms are digitally sampled along the time axis to obtain the response sequence of each downstream node.

10. The method for detecting defects in chip-particle interconnect structures based on physical hierarchy decomposition according to claim 1, characterized in that: The specific method for extracting the differences in signal response by comparing the signal response point by point with the reference response of a standard defect-free link is as follows: For each downstream node, the standard response waveform of the node to the same test signal is obtained in advance when the physical link under test is in a defect-free state, and the standard response waveform is digitized into a standard response sequence. The difference sequence is obtained by subtracting the values ​​of the actual response sequence collected by the downstream node from the values ​​of the standard response sequence at the same time point one by one. The difference with the largest absolute value in the difference sequence is recorded as the peak difference of the node, and the duration of consecutive non-zero differences in the difference sequence is recorded as the duration of the node's persistent difference. Among them, when the peak difference is greater than 20% of the standard response amplitude of the node, the node is judged to have significant signal distortion. The 20% threshold is determined based on the engineering experience value of the signal integrity tolerance of the chip receiver. Peak difference and duration of persistent difference are used as the difference features of nodes.

Images