Graphics processor, rendering data processing method and related product

Abstract

The present disclosure provides a graphics processor, a rendering data processing method and related products, and belongs to the technical field of computers. The graphics processor comprises a clipping unit and a primitive setting unit, and a shared edge cache unit connected with the clipping unit and / or the primitive setting unit; the shared edge cache unit is used for interacting with the clipping unit to generate edge clipping results of the clipping unit, and / or is used for interacting with the primitive setting unit to generate rasterization results of the primitive setting unit; the clipping unit is used for interacting with the shared edge cache unit to reuse the edge clipping results in the shared edge cache unit or clipping a first primitive corresponding to a first to-be-processed edge, so as to determine the edge clipping results of the first to-be-processed edge; and the primitive setting unit is used for interacting with the shared edge cache unit to reuse the rasterization results in the shared edge cache unit or rasterization setting of a second primitive corresponding to a second to-be-processed edge, so as to determine the rasterization results of the second to-be-processed edge. The embodiment of the present disclosure can reduce the amount of calculation.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a graphics processor, a rendering data processing method, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] The rendering pipeline of a Graphics Processing Unit (GPU) is a key concept in computer graphics. It is an important processing stage in the GPU, responsible for processing and transforming graphics data for rendering. In related technologies, shared edge information can only be utilized for specific primitives during the pruning process. Therefore, shared edge information is not fully utilized, and the corresponding computational load remains high. Summary of the Invention

[0003] This disclosure provides a graphics processor, a rendering data processing method, an electronic device, a computer-readable storage medium, and a computer program product.

[0004] In a first aspect, this disclosure provides a graphics processor, comprising: a cropping unit and a primitive setting unit directly connected in a pipeline, and a shared edge buffer unit connected to the cropping unit and / or the primitive setting unit; the shared edge buffer unit is configured to interact with the cropping unit to obtain edge cropping results generated by the cropping unit, and / or to interact with the primitive setting unit to obtain rasterization results generated by the primitive setting unit; the cropping unit is configured to determine the edge cropping result of the first edge to be processed by interacting with the shared edge buffer unit to reuse the edge cropping results in the shared edge buffer unit or by cropping a first primitive corresponding to a first edge to be processed; the primitive setting unit is configured to determine the rasterization result of the second edge to be processed by interacting with the shared edge buffer unit to reuse the rasterization results in the shared edge buffer unit or by rasterizing a second primitive corresponding to a second edge to be processed, wherein the second primitive includes the cropped first primitive.

[0005] Secondly, this disclosure provides a rendering data processing method applied to a shared edge cache unit in a graphics processor, wherein the graphics processor employs the aforementioned graphics processor. The rendering data processing method includes: receiving and storing an edge clipping result sent by the clipping unit, and returning at least a portion of the stored edge clipping result to the clipping unit, so that the clipping unit reuses the returned edge clipping result or clips a first primitive corresponding to a first edge to be processed, thereby determining the edge clipping result of the first edge to be processed; and / or, receiving and storing a rasterization result sent by the primitive setting unit, and returning at least a portion of the stored rasterization result to the primitive setting unit, so that the primitive setting unit reuses the returned rasterization result or performs rasterization setting on a second primitive corresponding to a second edge to be processed, thereby determining the rasterization result of the second edge to be processed.

[0006] Thirdly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the above-described rendering data processing method.

[0007] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described rendering data processing method.

[0008] Fifthly, this disclosure provides a computer program product comprising computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described rendering data processing method.

[0009] The graphics processor provided in this embodiment takes into account that there are multiple shared edges between primitives, and these shared edges may be repeatedly involved in calculations during clipping and rasterization settings. Therefore, the graphics processor in this embodiment can store the obtained edge clipping results and / or rasterization results in the shared edge cache unit by setting a shared edge cache unit. Based on this, for the clipping unit, when dealing with the first edge to be processed, it can reuse the edge clipping results stored in the shared edge cache unit. Only when there is no reusable cache data in the shared edge cache unit does it need to re-execute the corresponding clipping process. Similarly, for the primitive setting unit, when dealing with the second edge to be processed, it can also reuse the rasterization results stored in the shared edge cache unit. Only when there is no reusable cache data in the shared edge cache unit does it need to re-execute the corresponding rasterization process. In this way, the amount of computation can be effectively reduced and the rendering processing efficiency can be improved.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a graphics processor provided in an embodiment of the present disclosure.

[0013] Figure 2 This is a schematic diagram of a shared side cache unit provided in an embodiment of the present disclosure.

[0014] Figure 3 This is a schematic diagram of another shared side cache unit provided in an embodiment of this disclosure.

[0015] Figure 4 This is a schematic diagram of another shared side cache unit provided in an embodiment of the present disclosure.

[0016] Figure 5 This is a schematic diagram of a graphic element provided in an embodiment of this disclosure.

[0017] Figure 6 This is a flowchart of a rendering data processing method provided in an embodiment of the present disclosure.

[0018] Figure 7 This is a schematic diagram of a hit test provided in an embodiment of the present disclosure.

[0019] Figure 8 This is a flowchart illustrating a rendering data processing method provided in an embodiment of the present disclosure.

[0020] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0021] Figure 10 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0023] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0024] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0026] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0027] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information in this technical solution comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations. For example, appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identification is eliminated when using personal information to avoid precisely targeting specific individuals.

[0028] For example, a graphics rendering pipeline unit is a processing unit in a graphics processor used to perform graphics rendering. It consists of multiple processing stages, each of which performs specific geometric calculations and transformations, and other data processing.

[0029] For example, a graphics rendering pipeline unit may include the following processing stages:

[0030] 1. Vertex Input: This stage passes vertex data from the application to the geometry pipeline. Vertex data includes attribute data such as position, color, and normals.

[0031] 2. Vertex Shader: In this stage, the vertex shader performs calculations on each input vertex and can perform various transformations and operations, such as model transformation, view transformation, projection transformation, etc. It can also calculate the vertex's lighting, texture coordinates, etc.

[0032] 3. Primitive Assembly: In the current stage, the primitive assembler converts vertices into complete geometric primitives, such as points, line segments, triangles, etc.

[0033] 4. Geometry Shader: In the geometry shading stage, the geometry shader can manipulate and generate geometric primitives, including creating new primitives and changing the shape, size, position and other attributes of primitives.

[0034] 5. Clipping: At this stage, the clipper can compare primitives with the screen boundaries and discard parts that are outside the view volume.

[0035] 6. Screen Mapping: This stage maps the clipped primitives to pixel coordinates in screen space.

[0036] 7. Rasterization: The rasterization stage converts geometric primitives into pixels on the screen and determines the position, color, and other attributes of each pixel.

[0037] 8. Fragment Shader: During the fragment shading stage, the fragment shader performs calculations for each rasterized pixel. It can perform pixel-level lighting calculations, texture sampling, depth testing, and other operations.

[0038] 9. Pixel Operations: Perform final pixel processing, such as blending, dithering, and anti-aliasing.

[0039] In summary, the goal of the graphics rendering pipeline unit is to process geometry and generate the final image in an efficient manner. Through parallel processing and specialized hardware support, the GPU is able to perform these calculations quickly to achieve real-time graphics rendering.

[0040] Furthermore, in related technologies, the fact that multiple primitives can share the same edges is not usually fully considered, and the processing results of these shared edges can be reused to a certain extent. As a result, the characteristic of shared edges is not fully utilized, which may require a large amount of repeated calculations, resulting in a large amount of computation.

[0041] In view of the above, embodiments of this disclosure provide a graphics processor, a rendering data processing method, an electronic device, a computer-readable storage medium, and a computer program product.

[0042] In this embodiment of the disclosure, the characteristic that there may be shared edges between primitives is fully utilized, and a shared edge caching unit connected to the clipping unit and / or primitive setting unit is set up. Based on this, during the rendering stage, the clipping unit and / or primitive setting unit can fully reuse the rendering processing results of the shared edges already cached in the shared edge caching unit, thereby effectively reducing the amount of computation and saving computational resources.

[0043] Figure 1 This is a block diagram of a graphics processor provided in an embodiment of the present disclosure. (Refer to...) Figure 1 The graphics processor 100 includes: a clipping unit 110 and a primitive setting unit 120 directly connected in the pipeline, and a shared edge buffer unit 130 connected to the clipping unit 110 and / or the primitive setting unit 120; the shared edge buffer unit 130 is used to interact with the clipping unit 110 to obtain edge clipping results generated by the clipping unit, and / or to interact with the primitive setting unit 120 to obtain rasterization results generated by the primitive setting unit 120; the clipping unit 110 is used to determine the edge clipping result of the first edge to be processed by interacting with the shared edge buffer unit 130 to reuse the edge clipping results in the shared edge buffer unit 130 or to clip the first primitive corresponding to the first edge to be processed; the primitive setting unit 120 is used to determine the rasterization result of the second edge to be processed by interacting with the shared edge buffer unit 130 to reuse the rasterization results in the shared edge buffer unit 130 or to rasterize the second primitive corresponding to the second edge to be processed, wherein the second primitive includes the clipped first primitive.

[0044] For example, clipping units are mainly used to remove or truncate primitives outside the view frustum or viewport, ensuring that only the visible parts are processed and reducing invalid calculations.

[0045] For example, the primitive setup unit is mainly used to perform rasterization setup on the clipped primitives, completing the calculation of key parameters required for rasterization, thus providing a foundation for subsequent rasterization. Rasterization setup may include edge equation calculation, attribute interpolation gradient calculation, etc., and can pass the rasterization results to downstream processing units such as the pixel-stage shader processing unit, providing relatively complete input for subsequent pixel traversal, fragment interpolation, and shading.

[0046] It should be noted that the trimming unit and the primitive setting unit are two processing units directly connected in the pipeline, and the trimming unit is located upstream of the primitive setting unit in the pipeline. Therefore, the primitives processed by the trimming unit will flow to the primitive setting unit for further processing. In other words, the trimming unit needs to trim the first primitive, which may include multiple first edges to be processed. The second primitive obtained after processing by the trimming unit enters the primitive setting unit for corresponding processing. The second primitive includes the trimmed first primitive, and of course, it also includes the first primitive that does not need to be trimmed. Any second primitive may include multiple second edges to be processed, and the second edges to be processed may be the same as the first edges to be processed, or they may be first edges to be processed with a portion of their length trimmed. This embodiment of the present disclosure does not impose any limitations on this.

[0047] For example, the first primitive ABC includes first edges AB, AC and BC to be processed. If the first primitive does not need to be clipped, the first primitive ABC will be sent from the clipping unit to the primitive setting unit as a new second primitive ABC, which includes second edges AB, AC and BC to be processed.

[0048] For example, the first primitive ABC includes first edges AB, AC, and BC to be processed, and the midpoint of the first edge BC corresponds to point D. If the first primitive uses points A and D as clipping edges to clip part of triangle ADC, then the clipped first primitive ABC will be updated to the second primitive ABD and sent from the clipping unit to the primitive setting unit. The second primitive ABD includes second edges AB, BD, and AD to be processed. The first primitive ABC and the second primitive ABD still share the same edge AB.

[0049] Furthermore, as mentioned above, the clipping unit and / or primitive setting unit can be connected to the shared edge cache unit. Therefore, the edge clipping results and / or rasterization results of the clipping unit and / or primitive setting unit can be stored as cached data in the shared edge cache unit. Thus, the clipping unit and / or primitive setting unit can, in some cases, directly reuse the edge clipping results or rasterization results already cached in the shared edge cache unit by interacting with the shared edge cache unit. Only when the cached data in the shared edge cache unit cannot be reused does it need to re-execute the corresponding clipping process or rasterization setting. In this way, the amount of data processing can be effectively reduced and the efficiency of graphics processing can be improved.

[0050] Therefore, this embodiment of the present disclosure takes into account that there may be one or more shared edges between primitives. In order to make full use of this feature, a shared edge caching unit is set up, and the obtained rendering processing results (such as edge clipping results and rasterization results) can be stored in the corresponding shared edge caching unit. Based on this, for any first edge to be processed, the clipping unit first performs a hit test in the shared edge caching unit. If the cache is hit, the edge clipping result of the first edge to be processed can be determined by using the hit target cache data. Compared with obtaining the edge clipping result of the first edge to be processed again by the clipping method, the amount of calculation can be effectively reduced and the rendering processing efficiency can be improved.

[0051] Similarly, for any second edge to be processed, the primitive setting unit first performs a hit test in the shared edge cache unit. If the cache is hit, the rasterization result of the second edge to be processed can be determined using the hit target cache data. Compared with obtaining the rasterization result of the second edge to be processed again through the rasterization setting method, the amount of computation can be effectively reduced and the rendering processing efficiency can be improved.

[0052] It should be noted that the embodiments of this disclosure further consider that the processing objects of the clipping unit and the primitive setting unit include edges in the primitives. Since each edge corresponds to two vertices, and the same two vertices have two different directions, there may be two situations when reusing cached data. In the first case, the edge to be processed and the cached edge corresponding to the cached data have the same vertices and the same direction. In the second case, the edge to be processed and the cached edge corresponding to the cached data have the same vertices but opposite directions. For the first case, the cached data (such as edge clipping results or rasterization results) can be completely reused. For the second case, the cached data can still be reused, but only some simple adjustments need to be made. Compared to completely re-processing the clipping or rasterization, the workload can still be effectively reduced, and the graphics processing effect can still be improved.

[0053] It should also be noted that the reason why the embodiments of this disclosure can still reuse cached data in the second case is mainly due to the characteristics of the edges. In other words, even if the edges are in different directions, the processing results of the two are still very similar when performing clipping and rasterization settings, and the processing results of edges in different directions have a stable regularity. Therefore, the processing results of the opposite edge can be reused without worrying about errors or other problems caused by such reuse.

[0054] In summary, in this embodiment of the present disclosure, considering that there are multiple shared edges between primitives, and that these shared edges may be repeatedly involved in calculations during clipping and rasterization settings, the graphics processor of this embodiment can store the obtained edge clipping results and / or rasterization results in the shared edge cache unit by setting a shared edge cache unit. Based on this, for the clipping unit, when dealing with the first edge to be processed, it can reuse the edge clipping results stored in the shared edge cache unit. Only when there is no reusable cache data in the shared edge cache unit does it need to re-execute the corresponding clipping process. Similarly, for the primitive setting unit, when dealing with the second edge to be processed, it can also reuse the rasterization results stored in the shared edge cache unit. Only when there is no reusable cache data in the shared edge cache unit does it need to re-execute the corresponding rasterization process. In this way, the amount of computation can be effectively reduced and the rendering processing efficiency can be improved.

[0055] The graphics processor of the present disclosure embodiment will now be described in detail.

[0056] Image rendering is the process of generating an image on a display based on a model description. In 3D (3-Dimensional) graphics rendering, the input is a description of a 3D model based on primitive vertices (such as triangles, points, lines, and quadrilaterals). Then, through stages such as vertex processing, rasterization, fragment processing, and output merging, color values ​​are generated for the pixels on the display, ultimately presenting the image. Primitives are the bridge connecting vertex data and the final screen pixels; they define how vertex data is assembled into visible geometry and are the foundation of graphics rendering.

[0057] For example, graphic elements may include point graphic elements, line graphic elements, triangle graphic elements, and graphic elements obtained by combining the above graphic elements. This disclosure does not limit this.

[0058] In some optional embodiments, after processing by the geometry stage shader, the output information undergoes rasterization stage processing before being sent to the pixel processing shader for further processing. The rasterization stage can be divided into sub-stages such as viewport transformation, culling, clipping, and primitive setup. Viewport transformation primarily performs the transformation of primitive coordinates from the clipping space output by the geometry stage to user space. The culling stage primarily removes primitives that do not need to be drawn, including backface culling, small triangle culling, and zero-area triangle culling. The culled results can then enter the clipping section, where primitives exceeding a specific clipping plane (such as the view frustum clipping plane or a user-defined clipping plane) are clipped. The clipped primitives can then enter the primitive setup section, which includes rasterization setup processing such as establishing edge equations and generating fragment information. The processing results can then be sent to the pixel stage shader for further processing.

[0059] Furthermore, a primitive may include several edges; in other words, an edge refers to the geometric structure in a primitive used to connect vertices, and primitives may share edges. For example, edge AC is a shared edge between triangle primitive 1 and triangle primitive 2. Therefore, edge AC belongs to both triangle primitive 1 and triangle primitive 2. Accordingly, the edge clipping and rasterization results of edge AC can be shared by triangle primitive 1 and triangle primitive 2. If the edge clipping and / or rasterization results of edge AC have already been obtained during the processing of triangle primitive 1, then when processing triangle primitive 2, there is no need to repeat the processing of edge AC. Instead, the edge clipping and / or rasterization results of edge AC already obtained in triangle primitive 1 can be reused, thereby effectively reducing the computational load.

[0060] In some optional embodiments, a shared edge cache unit can be used to store the obtained edge clipping results and / or rasterization results, so that the clipping unit and / or rasterization setting unit can easily reuse the cached data therein.

[0061] In some optional embodiments, the shared edge caching unit includes multiple entries, each containing cached edge information. Each cached edge information includes information about the corresponding cached edge, as well as the edge clipping result and / or rasterization result of the cached edge. Therefore, each entry stores cached edge information, where the cached edge information points to the corresponding edge, and the edge clipping result and / or rasterization result is the corresponding processing result for the pointed-to edge.

[0062] Furthermore, in some optional embodiments, the clipping unit may share a shared edge cache unit with the primitive setting unit. In this case, any entry in the shared edge cache unit corresponds to an edge and is used to store the edge clipping result and rasterization result corresponding to that edge.

[0063] For example, the shared edge cache unit includes a first shared edge cache unit; the clipping unit and the primitive setting unit share the first shared edge cache unit, and any entry in the first shared edge cache unit is used to store the edge clipping result and rasterization result of the corresponding edge.

[0064] It should be noted that any entry in the first shared edge cache unit can store both the edge clipping result and the rasterization result of the corresponding edge at the same time. However, some entries may only store the edge clipping result or only store the rasterization result. This embodiment of the present disclosure does not impose any restrictions on this.

[0065] Therefore, since the clipping unit and the primitive setting unit share the same shared edge cache unit, both edge clipping results and rasterization results can be stored in one entry, thus improving the utilization rate of cache resources.

[0066] In some optional embodiments, separate shared edge cache units can be set for the clipping unit and the primitive setting unit respectively. Each entry in the shared edge cache unit corresponding to the clipping unit corresponds to an edge, which is used to store the edge clipping result corresponding to that edge. Each entry in the shared edge cache unit corresponding to the primitive setting unit corresponds to an edge, which is used to store the rasterization result corresponding to that edge.

[0067] For example, the shared edge cache unit includes a second shared edge cache unit and a third shared edge cache unit; the clipping unit is connected to the second shared edge cache unit, and any entry in the second shared edge cache unit is used to store the edge clipping result of the corresponding edge; the primitive setting unit is connected to the third shared edge cache unit, and any entry in the third shared edge cache unit is used for the rasterization result of the corresponding edge.

[0068] Therefore, since the clipping unit and the primitive setting unit each use their own shared edge cache unit, they can access each other independently. The control logic of the shared edge cache unit is relatively simple, and the access efficiency and parallelism are high.

[0069] In summary, shared edge cache units can be flexibly configured according to requirements. If cache resources are limited, the pruning unit and the primitive setting unit can share a single shared edge cache unit to reuse cached data. If cache resources are sufficient, independent shared edge cache units can be set up for the pruning unit and the primitive setting unit, thereby reducing the complexity of memory access control logic for the shared edge cache unit and improving memory access efficiency and parallelism.

[0070] It should be noted that, for any entry in the shared edge cache unit, in addition to including cache edge information, several identification information can also be set to enable more accurate and orderly execution of the corresponding memory access operations.

[0071] In some optional embodiments, the shared edge caching unit includes multiple entries, each entry including a valid identifier and cached edge information. The valid identifier indicates whether the cached edge information stored in the current entry is valid, and the cached edge information includes information about the corresponding cached edge, as well as the edge clipping result and / or rasterization result of that cached edge.

[0072] Therefore, during hit testing, multiple entries in the shared edge cache unit can be tested sequentially according to their order. For the currently being tested entry, if its valid identifier indicates that the entry is invalid, or if the current entry is not hit, the test can jump to the next adjacent entry for hit testing, until all entries have been tested or an entry is hit. This method of testing each entry sequentially avoids issues such as missing entries and allows skipping invalid entries based on valid identifiers, thus avoiding hits on invalid cached data and saving hit testing time.

[0073] It should be noted that the information contained in the above entries is merely illustrative and this disclosure does not limit the scope of the embodiments.

[0074] Furthermore, as mentioned above, since edges with the same vertex can correspond to two different directions, a hit test is required before reusing cached data in the shared edge cache unit. Moreover, due to the directional characteristics of edges, this hit test differs from traditional hit tests. Specifically, this embodiment of the disclosure also needs to determine the hit type when hitting the cache, so as to determine the reuse method for the hit cached data based on different hit types. The hit types include positive hits and negative hits. A positive hit indicates that the edge to be processed has the same vertex and direction as the cached edge corresponding to the hit entry, while a negative hit indicates that the edge to be processed has the same vertex but opposite direction as the cached edge corresponding to the hit entry.

[0075] In some optional embodiments, the trimming unit is further configured to send the information of the first edge to be processed to the shared edge cache unit for a hit test, and if the hit test result indicates a cache hit, reuse the cached edge information stored in the hit entry according to the hit type to obtain the edge trimming result of the first edge to be processed; and / or, the primitive setting unit is further configured to send the information of the second edge to be processed to the shared edge cache unit for a hit test, and if the hit test result indicates a cache hit, reuse the cached edge information stored in the hit entry according to the hit type to obtain the rasterization result of the second edge to be processed; the shared edge cache unit is further configured to perform a hit test based on the received information of the first edge to be processed and / or the information of the second edge to be processed, as well as the cached edge information of multiple entries, to obtain a hit test result corresponding to the first edge to be processed and / or the second edge to be processed, the hit test result being used to characterize whether the cache is hit and the hit type if the cache is hit.

[0076] Therefore, when the pruning unit is connected to the shared edge cache unit, the pruning unit can send the information of the first edge to be processed to the shared edge cache unit. The shared edge cache unit can then perform a hit test based on the received information to obtain the hit test result. If the hit test result indicates a cache hit, the cached edge information in the hit entry can be reused according to the hit type, thus easily and quickly obtaining the edge pruning result of the first edge to be processed without actually performing the pruning operation, saving resource overhead, reducing processing time, and improving processing efficiency.

[0077] Similarly, when the primitive setting unit is connected to the shared edge cache unit, the primitive setting unit can send the information of the second edge to be processed to the shared edge cache unit. The shared edge cache unit can perform a hit test based on the received information of the second edge to be processed and obtain the hit test result. If the hit test result indicates that the cache has been hit, the cached edge information in the hit entry can be reused according to the hit type, thereby easily and quickly obtaining the rasterization result of the second edge to be processed without actually performing the rasterization setting operation, saving resource overhead, reducing processing time, and improving processing efficiency.

[0078] In some alternative embodiments, whether the cache is hit and the hit type in the case of a cache hit can be determined based on the start and end points of the cached edge and the start and end points of the first edge to be processed.

[0079] In some optional embodiments, the information of the cached edge includes first cached vertex information corresponding to the starting point and second cached vertex information corresponding to the ending point; the information of the first edge to be processed or the information of the second edge to be processed includes first vertex information corresponding to the starting point and second vertex information corresponding to the ending point; the shared edge caching unit is used to determine that the cache is hit and the corresponding hit type is a positive hit when the first vertex information is consistent with the first cached vertex information and the second vertex information is also consistent with the second cached vertex information; to determine that the cache is hit and the corresponding hit type is a negative hit when the first vertex information is consistent with the first cached vertex information and the second cached vertex information is inconsistent with both the first vertex information and the second cached vertex information, and / or the second vertex information is inconsistent with both the first cached vertex information and the second cached vertex information; and to determine that the cache is not hit when the first vertex information is inconsistent with both the first cached vertex information and the second cached vertex information.

[0080] In other words, the essence of a hit test is to compare whether the cached edge is the same as the first edge to be processed (or the second edge to be processed). Considering that any edge has two vertices (the start and the end), the edges corresponding to the same two vertices can be either in the same direction or in opposite directions. Therefore, when comparing whether two edges are the same, there are three possible cases: First, the vertices of the two edges are the same and the directions are the same (i.e., the start and end points are the same); second, the vertices of the two edges are the same but the directions are different (i.e., the start of one edge is the same as the end point of another edge, and the end point is the same as the start point of another edge); third, the vertices of the two edges are different (including three cases: only the start point is the same, only the end point is the same, and both the start and end points are different). Based on this, during the hit test, the hit test results corresponding to the aforementioned third case are as follows: cache hit, hit type is positive hit; cache hit, hit type is negative hit; cache miss.

[0081] For example, if an entry corresponds to a cached edge AC, where the first cached vertex information corresponds to the information of vertex A (such as position information), and the second cached vertex information corresponds to the information of vertex C, then if the first vertex information of the current first edge to be processed corresponds to vertex A and the second vertex information corresponds to vertex C, it is considered a positive hit; conversely, if the first vertex information of the first edge to be processed corresponds to vertex C and the second vertex information corresponds to vertex A, it is considered a negative hit. Furthermore, if the first vertex information of the first edge to be processed corresponds to vertex B, and it corresponds to neither vertex A nor vertex C, it is considered a cache miss. Similarly, if the second vertex information of the first edge to be processed corresponds to vertex D, and it corresponds to neither vertex A nor vertex C, it is also considered a cache miss. The hit process for the second edge to be processed is similar and will not be described further here.

[0082] This approach fully considers the case where an edge has two vertices, vertex1 and vertex2, and the corresponding edges can be either vertex1-vertex2 or vertex2-vertex1. The edge clipping and rasterization results of these two cases have a certain similarity. Given the edge clipping and / or rasterization results of an edge in one direction, the edge clipping and / or rasterization results of an edge in another direction can be determined by simple adjustments without having to re-execute clipping and rasterization settings. Therefore, it can effectively improve the hit rate, thereby effectively reducing the amount of computation and improving the rendering efficiency.

[0083] It should be noted that in related technologies, cases of reverse hits are usually directly judged as cache misses. As a result, cached data cannot be fully reused in such cases, and rendering processes such as clipping and rasterization settings need to be restarted. This not only increases resource consumption but also prolongs processing time, thereby affecting processing efficiency.

[0084] Furthermore, if the cache is hit, regardless of the hit type, the cropping unit and / or primitive setting unit can reuse the cached edge information in the hit entry in a reasonable manner; if the cache is not hit, the cropping unit needs to perform cropping processing on the first edge to be processed, and similarly, the primitive setting unit needs to perform rasterization settings on the second edge to be processed in order to obtain a complete and accurate image processing result.

[0085] In some optional embodiments, the clipping unit is further configured to perform clipping processing on the first primitive corresponding to the first edge to be processed when the hit test result indicates that the cache is not hit, to obtain the edge clipping result of the first edge to be processed, and update the edge clipping result of the first edge to be processed to the shared edge cache unit; and / or, the primitive setting unit is further configured to perform rasterization setting on the second primitive corresponding to the second edge to be processed when the hit test result indicates that the cache is not hit, to obtain the rasterization result of the second edge to be processed, and update the rasterization result of the second edge to be processed to the shared edge cache unit.

[0086] In this way, the amount of cached data in the shared edge cache unit can be continuously expanded, which is beneficial to improving the subsequent hit rate, thereby increasing the reuse of cached data, reducing the amount of data processing, and improving processing efficiency.

[0087] It should be noted that the embodiments disclosed herein do not limit the way the clipping unit performs clipping processing, nor do they limit the way the primitive setting unit performs rasterization setting.

[0088] As mentioned earlier, different reuse methods are required when reusing cached edge information in hit entries for different hit types.

[0089] In some optional embodiments, the clipping unit is further configured to, when the hit type is a positive hit, determine the edge clipping result in the corresponding hit entry as the edge clipping result of the first edge to be processed; when the hit type is a negative hit, adjust the edge clipping result in the corresponding hit entry, and determine the edge clipping result of the first edge to be processed based on the adjusted edge clipping result; and / or, the primitive setting unit is further configured to, when the hit type is a positive hit, determine the rasterization result in the corresponding hit entry as the rasterization result of the second edge to be processed; when the hit type is a negative hit, adjust the rasterization result in the corresponding hit entry, and determine the rasterization result of the second edge to be processed based on the adjusted rasterization result.

[0090] Therefore, whether it is a clipping unit or a primitive setting unit, if it is a positive hit, the cached edge information in the hit entry can be directly used as the processing result of the corresponding edge to be processed. If it is a negative hit, only a few simple adjustments need to be made to the cached edge information in the hit entry to obtain the processing result of the corresponding edge to be processed. Compared with restarting the clipping and / or rasterization settings, it can still effectively reduce resource consumption and shorten the processing time.

[0091] In other words, the embodiments of this disclosure adopt different reuse methods for different hit types, which can improve the reuse rate of cached data, reduce resource overhead, and ensure that accurate and reasonable edge cropping and / or rasterization results are obtained, thus ensuring the accuracy of image processing.

[0092] Furthermore, considering the significant differences between the edge clipping and rasterization results, the adjustment methods for the edge clipping and rasterization results after a reverse hit also differ considerably. The following explains how to adjust the edge clipping and rasterization results during a reverse hit.

[0093] In some optional embodiments, the edge trimming result includes third cached vertex information corresponding to the trimmed start point and fourth cached vertex information corresponding to the trimmed end point; correspondingly, the trimming unit is used, in the case of a reverse hit, to use the third cached vertex information and fourth cached vertex information of the edge trimming result in the corresponding hit entry as the sixth vertex information and fifth vertex information in the edge trimming result of the first edge to be processed, respectively; wherein, the fifth vertex information corresponds to the trimmed start point of the first edge to be processed, and the sixth vertex information corresponds to the trimmed end point of the first edge to be processed.

[0094] Therefore, in the case of a reverse hit, the pruning unit can obtain the edge pruning result of the corresponding first edge to be processed by simply swapping the start and end points of the cached edges in the hit entry.

[0095] In some optional embodiments, the rasterization result of the cached edge includes the edge equation; accordingly, the primitive setting unit is used to invert the sign of the edge equation in the corresponding hit entry when the hit type is reverse hit, to obtain the edge equation corresponding to the second edge to be processed.

[0096] Therefore, when a reverse hit occurs, the primitive setting unit can obtain the edge equation of the corresponding second edge to be processed by simply adjusting the edge equation sign.

[0097] In summary, during reverse hits, different adjustment methods can be used for different rendering processing units (such as clipping units and primitive setting units) to obtain accurate rendering results for the corresponding edges to be processed (such as edge clipping results and rasterization results). Based on this, the application scenarios of reusing shared cached edge information are effectively improved, and the obtained rendering results can be reused in different processing stages (or different rendering processing units).

[0098] For example, the clipping unit can clip primitives that are partially or completely outside the visible area, discarding portions of the primitives that will not be displayed on the screen. For the first edge AC to be processed in the first primitive P1, if a hit test is performed in the shared edge cache unit based on the information of the first edge AC to be processed, and the hit test result is a cache miss, the clipping unit needs to determine its edge clipping result based on the relative position of the first edge AC to be processed and the visible area.

[0099] Furthermore, if the first edge AC to be processed is completely within the visible area, there is no need to clip edge AC. Based on this, the edge clipping result of the first edge AC to be processed can be updated to a certain entry in the shared edge cache unit. In this entry, the first cached vertex information in the cached edge information is used to indicate the starting point A, and the second cached vertex information is used to indicate the ending point C. If the ending point C of the first edge AC to be processed is within the visible area, and the starting point A is outside the visible area, then edge AC needs to be clipped. If the clipped first edge AC to be processed becomes BC (B is a point located on AC), based on this, the edge clipping result of the first edge AC to be processed can be updated to a certain entry in the shared edge cache unit. In this entry, the first cached vertex information in the cached edge information is used to indicate the starting point B, and the second cached vertex information is used to indicate the ending point C.

[0100] Based on this, if another first primitive P2 shares edge AC with first primitive P1, then when processing edge AC in first primitive P2, a hit test can be performed in the shared edge cache unit. The hit test result indicates a positive hit, thus directly reusing the edge clipping result of the first edge AC to be processed. If another first primitive P3 includes edge CA, then when processing edge CA in first primitive P3, a hit test can be performed in the shared edge cache unit. The hit test result indicates a negative hit. By adjusting the first cache vertex information and the second cache vertex information in the cached edge information of the first edge AC to be processed, the edge clipping result of edge CA can be obtained.

[0101] Similarly, after the multiple first primitives are processed by the clipping unit, they flow into the primitive setting unit. Through the rasterization settings of the primitive setting unit, the corresponding rasterization result can be obtained. If the first edge AC to be processed is not clipped, after the first primitive P1 enters the primitive setting unit, it becomes the new second primitive P1, including the second edge AC to be processed. The primitive setting unit performs a hit test in the shared edge buffer unit based on the information of the second edge AC to be processed. When the hit test result is a cache miss, the primitive setting unit can obtain the edge equation ax + by + c > 0 of the second edge AC to be processed through rasterization settings and store it in a certain entry of the shared edge buffer unit. Here, a and b are coefficient parameters, and c is an offset parameter. The edge equation indicates the relative positional relationship between the pixel and the edge.

[0102] If the first primitive P2 also enters the primitive setting unit as the new second primitive P2, then for the second edge AC to be processed in the second primitive P2, the primitive setting unit can perform a hit test in the shared edge cache unit. The hit test result indicates a positive hit, so the edge equation of the hit second edge AC can be directly reused. If the first primitive P3 also enters the primitive setting unit as the new second primitive P3, then for the second edge CA to be processed in the second primitive P3, the primitive setting unit can perform a hit test in the shared edge cache unit. The hit test result indicates a negative hit, so the edge equation of the second edge CA to be processed can be obtained by adjusting the sign of the edge equation.

[0103] The following is combined Figures 2 to 4 The shared side cache unit of this disclosure will be described by way of example.

[0104] Figure 2 This is a schematic diagram of a shared side cache unit provided in an embodiment of this disclosure. Figure 2As shown, the first shared edge cache unit is a cache unit shared by the clipping unit and the primitive setting unit. It includes a control unit and a storage unit. The control unit is used to control memory access operations such as reading and writing to ensure accurate and orderly access to the first shared edge cache unit. The storage unit includes multiple entries, each corresponding to an edge. For any given entry, there are a validity field, a field for storing first cache vertex information, a field for storing second cache vertex information, and a data field for storing edge equations and / or edge clipping results. The validity identifier field stores the identifier value of the validity identifier, which reflects whether the data stored in the data field (such as edge equations and edge clipping results) is valid.

[0105] Figure 3 This is a schematic diagram of another shared side cache unit provided in an embodiment of this disclosure. For example... Figure 3 As shown, the second shared edge cache unit is the cache unit corresponding to the pruning unit. It includes a control unit and a storage unit. The control unit is used to control memory access operations such as reading and writing to ensure accurate and orderly access to the second shared edge cache unit. The storage unit includes multiple entries, each corresponding to an edge of a primitive. For any given entry, there are valid fields, fields for storing first cache vertex information, fields for storing second cache vertex information, and data fields for storing edge pruning results.

[0106] Figure 4 This is a schematic diagram of another shared side cache unit provided in an embodiment of this disclosure. For example... Figure 4 As shown, the third shared edge cache unit is the cache unit corresponding to the primitive setting unit. It includes a control unit and a storage unit. The control unit is used to control memory access operations such as reading and writing to ensure accurate and orderly access to the third shared edge cache unit. The storage unit includes multiple entries, each corresponding to an edge of a primitive. For any given entry, there are valid fields, fields for storing first cache vertex information, fields for storing second cache vertex information, and data fields for storing edge equations.

[0107] It should be noted that if an edge (i) is a shared edge among multiple primitives, only one entry needs to be set for that edge (i), and there is no need to set separate entries for each edge (i) in each primitive.

[0108] Figure 5 This is a schematic diagram of a graphic element provided in an embodiment of this disclosure. (Refer to...) Figure 5 A clipping operation is performed on primitive ABC to obtain the clipping result A-C0 for edge AB and the clipping result C1-C for edge BC, and the clipping results are stored in the shared edge cache unit.

[0109] When performing the pruning of primitive DBA, for edge BA, a hit test is first performed in the shared edge buffer unit. After obtaining the hit test result of the reverse hit edge AB, the pruning unit adjusts the edge pruning result A-C0 of edge AB to obtain the edge pruning result C0-A of edge BA. Correspondingly, after pruning edge AD, the corresponding edge pruning result can be obtained as A-C2. Based on this, the edge pruning result of primitive DBA can be obtained as C0-A-C2.

[0110] When performing rasterization settings using the primitive setting unit, if the side equation of side CA in triangle ABC is stored in the shared side buffer unit, it can be reverse-hit by side AC in triangle ACE. Based on this, the side equation of side CA can be adjusted to obtain the side equation of side AC, effectively reducing the amount of calculation of the side equation.

[0111] It should be noted that the diagram only uses a triangle as an example for illustration. Other types of graphic elements can be processed in a similar way, and will not be described in detail here.

[0112] In summary, in this embodiment of the present disclosure, the graphics processor is provided with a shared edge cache unit. Therefore, by automatically detecting the existence of shared edges and the processing results (including edge clipping results, edge equations, etc.) of already cached shared edges, the amount of computation required for rasterization of primitives can be effectively reduced, resource consumption can be reduced, and processing efficiency can be improved.

[0113] This disclosure also provides a rendering data processing method.

[0114] Figure 6 This is a flowchart illustrating a rendering data processing method provided in an embodiment of the present disclosure. The method can be applied to a shared side buffer unit in a graphics processor, which employs any of the graphics processors described in the embodiments of the present disclosure. (Refer to...) Figure 6 The rendering data processing method may include the following steps.

[0115] Step S601: Receive and store the edge clipping result sent by the clipping unit, and return at least a portion of the stored edge clipping result to the clipping unit so that the clipping unit can reuse the returned edge clipping result or clip the first primitive corresponding to the first edge to be processed, thereby determining the edge clipping result of the first edge to be processed; and / or, receive and store the rasterization result sent by the primitive setting unit, and return at least a portion of the stored rasterization result to the primitive setting unit so that the primitive setting unit can reuse the returned rasterization result or rasterize the second primitive corresponding to the second edge to be processed, thereby determining the rasterization result of the second edge to be processed.

[0116] Therefore, this embodiment of the present disclosure takes into account that there are multiple shared edges between primitives, and these shared edges may repeatedly participate in the calculation during the clipping and rasterization settings process. Therefore, the shared edge caching unit can receive and store the edge clipping results obtained by the clipping unit and / or the rasterization results generated by the primitive setting unit. Based on this, in some cases, some edge clipping results can be returned to the clipping unit, and / or the rasterization results can be returned to the primitive setting unit, so that the clipping unit and / or the primitive setting unit can reuse the part of the edge clipping results and / or rasterization results returned by the shared edge unit without having to re-execute the corresponding clipping and / or rasterization processing, thereby effectively reducing the amount of computation and improving the rendering processing efficiency.

[0117] In some optional embodiments, the shared edge caching unit includes multiple entries, each entry including cached edge information. Each cached edge information includes information about the corresponding cached edge, as well as the edge clipping result and / or rasterization result of the cached edge. The method further includes: performing a hit test based on the information of the first edge to be processed sent by the clipping unit and / or the information of the second edge to be processed sent by the primitive setting unit, and the cached edge information of the multiple entries, to obtain a hit test result corresponding to the first edge to be processed and / or the second edge to be processed. The hit test result is used to characterize whether a cache hit occurs and the hit type in the case of a cache hit. The hit type includes positive hit and negative hit. A positive hit indicates that the first edge to be processed or the second edge to be processed has the same vertex and direction as the cached edge corresponding to the hit entry. A negative hit indicates that the first edge to be processed or the second edge to be processed has the same vertex but opposite direction as the cached edge corresponding to the hit entry.

[0118] Therefore, when the pruning unit is connected to the shared edge cache unit, the pruning unit can send the information of the first edge to be processed to the shared edge cache unit. The shared edge cache unit can then perform a hit test based on the received information to obtain the hit test result. If the hit test result indicates a cache hit, the cached edge information in the hit entry can be reused according to the hit type, thus easily and quickly obtaining the edge pruning result of the first edge to be processed without actually performing the pruning operation, saving resource overhead, reducing processing time, and improving processing efficiency.

[0119] Similarly, when the primitive setting unit is connected to the shared edge cache unit, the primitive setting unit can send the information of the second edge to be processed to the shared edge cache unit. The shared edge cache unit can perform a hit test based on the received information of the second edge to be processed and obtain the hit test result. If the hit test result indicates that the cache has been hit, the cached edge information in the hit entry can be reused according to the hit type, thereby easily and quickly obtaining the rasterization result of the second edge to be processed without actually performing the rasterization setting operation, saving resource overhead, reducing processing time, and improving processing efficiency.

[0120] In some optional embodiments, the information of the cached edge includes first cached vertex information corresponding to the starting point and second cached vertex information corresponding to the ending point. The information of the first edge to be processed or the information of the second edge to be processed includes first vertex information corresponding to the starting point and second vertex information corresponding to the ending point. Based on the information of the first edge to be processed sent by the clipping unit and / or the information of the second edge to be processed sent by the primitive setting unit, as well as the cached edge information of multiple entries, a hit test is performed to obtain the hit test result corresponding to the first edge to be processed and / or the second edge to be processed, including: if the first vertex information is consistent with the first cached vertex information and the second vertex information is also consistent with the second cached vertex information, it is determined that the cache has been hit and the corresponding hit type is a positive hit; if the first vertex information is consistent with the second cached vertex information and the second vertex information is also consistent with the first cached vertex information, it is determined that the cache has been hit and the corresponding hit type is a negative hit; if the first vertex information is inconsistent with both the first cached vertex information and the second cached vertex information, and / or the second vertex information is inconsistent with both the first cached vertex information and the second cached vertex information, it is determined that the cache has not been hit.

[0121] In some optional embodiments, returning at least a portion of the stored edge clipping results to the clipping unit includes: if a cache hit is determined based on the information of the first edge to be processed, returning the cached edge information in the hit entry to the clipping unit, so that the clipping unit determines the edge clipping result of the first edge to be processed based on the returned cached edge information; returning at least a portion of the stored rasterization results to the primitive setting unit includes: if a cache hit is determined based on the information of the second edge to be processed, returning the cached edge information in the hit entry to the primitive setting unit, so that the primitive setting unit determines the rasterization result of the second edge to be processed based on the returned cached edge information.

[0122] Figure 7 This is a schematic flowchart illustrating a hit test provided in an embodiment of this disclosure. (Refer to...) Figure 7 The hit test may include the following steps.

[0123] In step S701, the clipping unit determines the current first edge to be processed in the first primitive, generates a hit test request based on the information of the first edge to be processed, and sends the hit test request to the shared edge cache unit.

[0124] The information of the first edge to be processed includes the information of the first vertex corresponding to the starting point and the information of the second vertex corresponding to the ending point.

[0125] In step S702, the shared edge cache unit receives the hit test request, obtains the information of the first edge to be processed, and takes the entry with the entry index value i as 1 as the entry to be tested.

[0126] Where i is an integer greater than or equal to 1, and the information of the cached edge in any entry includes the information of the first cached vertex corresponding to the starting point, the information of the second cached vertex corresponding to the ending point, and the corresponding edge clipping result.

[0127] Step S703: Obtain the identifier value of the valid identifier of the item to be tested.

[0128] Step S704: Determine whether the item to be tested is invalid based on the identifier value of the valid identifier of the item to be tested.

[0129] If the flag value indicates that the item to be tested is invalid, proceed to step S705; if the flag value indicates that the item to be tested is valid, proceed to step S707.

[0130] Step S705: Update the entry index value i to i+1.

[0131] Step S706: Determine whether the updated entry index value i+1 is valid.

[0132] If the total number of entries in the shared edge cache unit is N (N is an integer greater than 1), if i+1≤N, it means that the updated entry index value i+1 is valid; if i+1>N, it means that the updated entry index value i+1 is invalid.

[0133] Furthermore, if the updated entry index value i+1 is valid, proceed to step S703, where entry i+1 is used as the new entry to be tested for a hit test; if the updated entry index value i+1 is invalid, it means that the hit test for all entries has been completed and all entries have not been hit, so proceed to step S711.

[0134] Step S707: Determine whether the first vertex information is consistent with the first cached vertex information, and whether the second vertex information is consistent with the second cached vertex information.

[0135] If any inconsistency exists, the process jumps to step S708; if both are consistent, the process jumps to step S710.

[0136] Step S708: Determine whether the first vertex information is consistent with the second cached vertex information, and whether the second vertex information is consistent with the first cached vertex information.

[0137] If both are consistent, proceed to step S709. If there is a discrepancy, it means that the item to be tested was not hit, so proceed to step S705 to perform a hit test on subsequent items.

[0138] Step S709: Generate hit test results to indicate reverse hits.

[0139] Step S710: Generate hit test results to indicate positive hits.

[0140] Step S711: Generate hit test results to indicate cache misses.

[0141] It should be noted that the process of performing a hit test on primitive setting units is similar and will not be described in detail here.

[0142] It should be noted that if the cache is not hit, the cropping unit needs to perform cropping processing on the first edge to be processed. Similarly, the primitive setting unit needs to perform rasterization settings on the second edge to be processed in order to obtain a complete and accurate image processing result. After obtaining the new edge cropping result and / or rasterization result, the cropping unit and / or primitive setting unit can send the new edge cropping result and / or rasterization result to the shared edge cache unit for caching for later use.

[0143] In some optional embodiments, receiving and storing the edge clipping result sent by the clipping unit includes: if it is determined based on the information of the first edge to be processed that the cache is not hit, receiving and storing the edge clipping result of the first edge to be processed sent by the clipping unit, wherein the edge clipping result of the first edge to be processed is obtained by the clipping unit clipping the first primitive corresponding to the first edge to be processed; receiving and storing the rasterization result sent by the primitive setting unit includes: if it is determined based on the information of the second edge to be processed that the cache is not hit, receiving and storing the rasterization result of the second edge to be processed sent by the primitive setting unit, wherein the rasterization result of the second edge to be processed is obtained by the primitive setting unit rasterizing the second primitive corresponding to the second edge to be processed.

[0144] Figure 8 This is a flowchart illustrating a rendering data processing method provided in an embodiment of the present disclosure.

[0145] In step S801, the pruning unit generates a hit test request based on the information of the current first edge to be processed, and sends the hit test request to the shared edge cache unit.

[0146] In step S802, the shared edge cache unit receives the hit test request and performs a hit test based on the information of the first edge to be processed, and obtains the hit test result.

[0147] If the hit test result indicates that the cache has been hit, the process can proceed to step S803; if the hit test result indicates that the cache has not been hit, the process can proceed to step S804.

[0148] In step S803, if the hit test result indicates a hit in the cache, the shared edge cache unit sends the hit target cache data to the pruning unit. The pruning unit determines the edge pruning result corresponding to the first edge to be processed based on the hit type and target cache data corresponding to the hit test result.

[0149] The target cache data is the cache data stored in the hit entry, which may include the edge clipping results of the corresponding cache edge.

[0150] After completing step S803, you can proceed to step S806.

[0151] In step S804, if the hit test result indicates that the cache was not hit, the pruning unit performs pruning processing on the first edge to be processed to obtain the edge pruning result corresponding to the first edge to be processed.

[0152] In step S805, the trimming unit stores the trimming result of the first edge to be processed into the shared edge cache unit.

[0153] Step S806: The trimming unit determines whether the edges of the first primitive have been processed.

[0154] If the edges of the first primitive have been processed, the processing flow for the first primitive ends; if the edges of the first primitive have not been processed, the process jumps to step S807.

[0155] Step S807: Select one edge from the unprocessed edges of the first primitive as the new first edge to be processed.

[0156] After completing step S807, you can jump to step S801 to start a new round of processing.

[0157] It should be noted that the processing procedure for setting units for graphic elements is similar and will not be described in detail here.

[0158] The modules in the aforementioned graphics processor can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or they can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0159] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0160] Reference Figure 9 This disclosure provides an electronic device, which includes: at least one processor 901, at least one memory 902, and one or more I / O interfaces 903; wherein the memory 902 stores one or more computer programs that can be executed by at least one processor 901, and the one or more computer programs are executed by at least one processor 901 to enable at least one processor 901 to perform the above-described rendering data processing method.

[0161] Figure 10 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0162] Reference Figure 10 This disclosure provides an electronic device that includes multiple processing cores 1001 and an on-chip network 1002. The multiple processing cores 1001 are all connected to the on-chip network 1002, and the on-chip network 1002 is used to exchange data between the multiple processing cores and external data.

[0163] One or more processing cores 1001 store one or more instructions, and the one or more instructions are executed by one or more processing cores 1001 to enable one or more processing cores 1001 to perform the above-described rendering data processing method.

[0164] The modules in the aforementioned electronic devices can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0165] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the rendering data processing method described above. The computer-readable storage medium may be volatile or non-volatile.

[0166] This disclosure also provides a computer program product including computer-readable code, which, when run in a processor of an electronic device, executes the above-described rendering data processing method.

[0167] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0168] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0169] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0170] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0171] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0172] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0173] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0174] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0175] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0176] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A graphics processor, characterized in that, include: A pipeline-connected trimming unit and primitive setting unit, and a shared side buffer unit connected to the trimming unit and / or the primitive setting unit; The shared edge cache unit is used to interact with the clipping unit to obtain the edge clipping result generated by the clipping unit, and / or to interact with the primitive setting unit to obtain the rasterization result generated by the primitive setting unit; The clipping unit is used to reuse the edge clipping result in the shared edge cache unit by interacting with the shared edge cache unit when the cache is hit; when the cache is not hit, the first primitive corresponding to the first edge to be processed is clipped, the edge clipping result of the first edge to be processed is determined, and the edge clipping result of the first edge to be processed is updated in the shared edge cache unit. The primitive setting unit is used to reuse the rasterization result in the shared edge cache unit by interacting with the shared edge cache unit when the cache is hit; when the cache is not hit, it performs rasterization setting on the second primitive corresponding to the second edge to be processed, determines the rasterization result of the second edge to be processed, and updates the rasterization result of the second edge to be processed to the shared edge cache unit, wherein the second primitive includes the first primitive after clipping.

2. The graphics processor according to claim 1, characterized in that, The shared edge cache unit includes multiple entries, each entry including cache edge information. Each cache edge information includes information about the corresponding cache edge, as well as the edge clipping result and / or rasterization result of the cache edge. The trimming unit is further configured to send the information of the first edge to be processed to the shared edge cache unit for a hit test, and, if the hit test result indicates a hit cache, reuse the cached edge information stored in the hit entry according to the hit type to obtain the edge trimming result of the first edge to be processed. And / or, the primitive setting unit is further configured to send the information of the second edge to be processed to the shared edge cache unit for a hit test, and if the hit test result indicates a hit cache, reuse the cached edge information stored in the hit entry according to the hit type to obtain the rasterization result of the second edge to be processed. The shared edge cache unit is further configured to perform a hit test based on the received information of the first edge to be processed and / or the second edge to be processed, as well as the cache edge information of multiple entries, to obtain a hit test result corresponding to the first edge to be processed and / or the second edge to be processed. The hit test result is used to characterize whether the cache is hit and the hit type when the cache is hit. The hit types include positive hits and negative hits. A positive hit indicates that the first edge to be processed or the second edge to be processed has the same vertex and direction as the cached edge corresponding to the hit entry. A negative hit indicates that the first edge to be processed or the second edge to be processed has the same vertex and direction as the cached edge corresponding to the hit entry.

3. The graphics processor according to claim 2, characterized in that, The information of the cached edge includes the information of the first cached vertex corresponding to the starting point and the information of the second cached vertex corresponding to the ending point. The information of the first edge to be processed or the information of the second edge to be processed includes the information of the first vertex corresponding to the starting point and the information of the second vertex corresponding to the ending point. The shared edge cache unit is used to determine that a cache hit has occurred and the corresponding hit type is a positive hit when the first vertex information is consistent with the first cached vertex information and the second vertex information is also consistent with the second cached vertex information. If the first vertex information is consistent with the second cached vertex information, and the second vertex information is also consistent with the first cached vertex information, then a cache hit is determined and the corresponding hit type is a reverse hit. If the first vertex information is inconsistent with both the first cached vertex information and the second cached vertex information, and / or the second vertex information is inconsistent with both the first cached vertex information and the second cached vertex information, a cache miss is determined.

4. The graphics processor according to claim 2 or 3, characterized in that, The trimming unit is further configured to, when the hit type is a positive hit, determine the edge trimming result in the corresponding hit entry as the edge trimming result of the first edge to be processed, and when the hit type is a negative hit, adjust the edge trimming result in the corresponding hit entry, and determine the edge trimming result of the first edge to be processed based on the adjusted edge trimming result. And / or, the primitive setting unit is further configured to, when the hit type is a positive hit, determine the rasterization result of the second edge to be processed by the rasterization result in the corresponding hit entry, and when the hit type is a negative hit, adjust the rasterization result in the corresponding hit entry, and determine the rasterization result of the second edge to be processed based on the adjusted rasterization result.

5. The graphics processor according to claim 4, characterized in that, The edge clipping result includes the third cache vertex information corresponding to the clipped starting point and the fourth cache vertex information corresponding to the clipped ending point; The trimming unit is used, when the hit type is a reverse hit, to take the third cached vertex information and the fourth cached vertex information of the edge trimming result in the corresponding hit entry as the sixth vertex information and the fifth vertex information in the edge trimming result of the first edge to be processed, respectively. The fifth vertex information corresponds to the starting point of the first edge to be processed after clipping, and the sixth vertex information corresponds to the ending point of the first edge to be processed after clipping.

6. The graphics processor according to claim 4, characterized in that, The rasterization result of the cached edge includes the edge equation; The primitive setting unit is used to invert the sign of the edge equation in the corresponding hit entry when the hit type is reverse hit, so as to obtain the edge equation corresponding to the second edge to be processed.

7. The graphics processor according to claim 2 or 3, characterized in that, The trimming unit is further configured to trim the first primitive corresponding to the first edge to be processed when the hit test result indicates that the cache was not hit, to obtain the edge trimming result of the first edge to be processed, and to update the edge trimming result of the first edge to be processed to the shared edge cache unit. And / or, the primitive setting unit is further configured to, when the hit test result indicates that the cache was not hit, perform rasterization setting on the second primitive corresponding to the second edge to be processed, obtain the rasterization result of the second edge to be processed, and update the rasterization result of the second edge to be processed to the shared edge cache unit.

8. The graphics processor according to any one of claims 1-3, characterized in that, The shared edge cache unit includes a first shared edge cache unit; The clipping unit and the primitive setting unit share the first shared edge cache unit, and any entry in the first shared edge cache unit is used to store the edge clipping result and rasterization result of the corresponding edge.

9. The graphics processor according to any one of claims 1-3, characterized in that, The shared edge cache unit includes a second shared edge cache unit and a third shared edge cache unit; The trimming unit is connected to the second shared edge cache unit, and any entry in the second shared edge cache unit is used to store the edge trimming result of the corresponding edge; The primitive setting unit is connected to the third shared edge cache unit, and any entry in the third shared edge cache unit is used for the rasterization result of the corresponding edge.

10. A rendering data processing method, characterized in that, A shared side buffer unit applied in a graphics processor, wherein the graphics processor is a graphics processor as described in any one of claims 1-9; the method includes: The system receives and stores the edge clipping results sent by the clipping unit, and returns at least a portion of the stored edge clipping results to the clipping unit, so that the clipping unit reuses the returned edge clipping results when the cache is hit, and clips the first primitive corresponding to the first edge to be processed when the cache is not hit, determines the edge clipping result of the first edge to be processed, and updates the edge clipping result of the first edge to be processed to the shared edge cache unit. And / or, to receive and store the rasterization result sent by the primitive setting unit, and to return at least part of the stored rasterization result to the primitive setting unit, so that the primitive setting unit reuses the returned rasterization result when the cache is hit, and performs rasterization setting on the second primitive corresponding to the second edge to be processed when the cache is not hit, determines the rasterization result of the second edge to be processed, and updates the rasterization result of the second edge to be processed to the shared edge cache unit.

11. The method according to claim 10, characterized in that, The shared edge caching unit includes multiple entries, each entry including cached edge information. Each cached edge information includes information about the corresponding cached edge, as well as the edge clipping result and / or rasterization result of the cached edge. The method further includes: Based on the information of the first edge to be processed sent by the clipping unit and / or the information of the second edge to be processed sent by the primitive setting unit, as well as the cache edge information of multiple entries, a hit test is performed to obtain a hit test result corresponding to the first edge to be processed and / or the second edge to be processed. The hit test result is used to characterize whether the cache is hit and the hit type when the cache is hit. The hit types include positive hits and negative hits. A positive hit indicates that the first edge to be processed or the second edge to be processed has the same vertex and direction as the cached edge corresponding to the hit entry. A negative hit indicates that the first edge to be processed or the second edge to be processed has the same vertex and direction as the cached edge corresponding to the hit entry.

12. The method according to claim 11, characterized in that, The information of the cached edge includes the information of the first cached vertex corresponding to the starting point and the information of the second cached vertex corresponding to the ending point. The information of the first edge to be processed or the information of the second edge to be processed includes the information of the first vertex corresponding to the starting point and the information of the second vertex corresponding to the ending point. The step of performing a hit test based on the information of the first edge to be processed sent by the clipping unit and / or the information of the second edge to be processed sent by the primitive setting unit, as well as the cached edge information of multiple entries, to obtain a hit test result corresponding to the first edge to be processed and / or the second edge to be processed, includes: If the first vertex information is consistent with the first cached vertex information, and the second vertex information is also consistent with the second cached vertex information, it is determined that the cache has been hit and the corresponding hit type is a positive hit. If the first vertex information is consistent with the second cached vertex information, and the second vertex information is also consistent with the first cached vertex information, then a cache hit is determined and the corresponding hit type is a reverse hit. If the first vertex information is inconsistent with both the first cached vertex information and the second cached vertex information, and / or the second vertex information is inconsistent with both the first cached vertex information and the second cached vertex information, a cache miss is determined.

13. The method according to claim 11 or 12, characterized in that, Returning at least a portion of the stored edge clipping results to the clipping unit includes: If a cache hit is determined based on the information of the first edge to be processed, the cache edge information in the hit entry is returned to the pruning unit so that the pruning unit determines the edge pruning result of the first edge to be processed based on the returned cache edge information. The step of returning at least a portion of the stored rasterization results to the primitive setting unit includes: If a cache hit is determined based on the information of the second edge to be processed, the cache edge information in the hit entry is returned to the primitive setting unit so that the primitive setting unit can determine the rasterization result of the second edge to be processed based on the returned cache edge information.

14. The method according to claim 11 or 12, characterized in that, The process of receiving and storing the edge trimming results sent by the trimming unit includes: If a cache miss is determined based on the information of the first edge to be processed, the edge clipping result of the first edge to be processed sent by the clipping unit is received and stored. The edge clipping result of the first edge to be processed is obtained by the clipping unit clipping the first primitive corresponding to the first edge to be processed. The step of receiving and storing the rasterization result sent by the primitive setting unit includes: If a cache miss is determined based on the information of the second edge to be processed, the rasterization result of the second edge to be processed sent by the primitive setting unit is received and stored. The rasterization result of the second edge to be processed is obtained by the primitive setting unit performing rasterization settings on the second primitive corresponding to the second edge to be processed.

15. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor to enable the at least one processor to perform the rendering data processing method as described in any one of claims 10-14.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the rendering data processing method as described in any one of claims 10-14.

17. A computer program product comprising computer-readable code, characterized in that, When the computer-readable code is run in the processor of an electronic device, the processor in the electronic device performs the rendering data processing method as described in any one of claims 10-14.

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