Gate driving circuit and display panel

Abstract

The application provides a driving circuit and a display panel. The driving circuit comprises a complementary metal oxide semiconductor circuit composed of at least one N-type thin film transistor and at least one P-type thin film transistor, and is matched with a first clock signal, a second clock signal, an inverted signal of the first clock signal and an inverted signal of the second clock signal. At least two scanning signals with different time sequences and / or pulse widths can be output in the same driving circuit, so that the circuit occupied space can be effectively reduced, and the frame width of the display panel can be compressed.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a gate driving circuit and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] In order to overcome the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a gate driving circuit, the gate driving circuit including a first module, a second module, a third module and a fourth module, wherein the first module, the second module, the third module and the fourth module include a complementary metal-oxide-semiconductor circuit composed of at least one P-type thin film transistor and at least one N-type thin film transistor; The first module includes a first input terminal and a first output terminal; the first module includes a function to make the first output terminal follow the level of the first input terminal during a first level phase of the first clock signal and to maintain the current level of the first output terminal during a second level phase of the first clock signal, based on a first clock signal and an inverted signal of the first clock signal. The second module includes a second input terminal and a second output terminal; the second input terminal is connected to the first output terminal; the second module is used to, according to the second clock signal and its inverted signal, cause the second output terminal to output a preset low-level signal during the third level stage of the second clock signal, and cause the second output terminal to output the inverted signal of the second clock signal when the second input terminal follows and maintains the valid level signal output by the first input terminal; The third module includes a third input terminal and a third output terminal; the third input terminal is connected to the second output terminal; the third module is used to output a first inverted signal under a preset high-level signal and a preset low-level signal from the third output terminal according to the signal output from the second output terminal, the waveform of the first inverted signal being opposite to the waveform of the signal output from the second output terminal; The fourth module includes a fourth input terminal and a fourth output terminal; the fourth input terminal is connected to the first output terminal; the fourth module is used to output a second inverted signal under the preset high-level signal and the preset low-level signal from the fourth output terminal according to the signal output from the first output terminal, the waveform of the second inverted signal being opposite to the waveform of the signal output from the first output terminal.

[0005] In some possible implementations, the first module includes a first P-type thin-film transistor, a first N-type thin-film transistor, and a first capacitor. The first electrodes of the first P-type thin-film transistor and the first N-type thin-film transistor are both connected to the first input terminal, and the second electrodes of the first P-type thin-film transistor and the first N-type thin-film transistor are both connected to the first output terminal. The control electrode of the first P-type thin-film transistor is connected to a trace that transmits a first clock signal, and the control electrode of the first N-type thin-film transistor is connected to a trace that transmits an inverted signal of the first clock signal. The first capacitor is connected to the first output terminal and the trace that transmits the preset low-level signal; Preferably, the active layer of the first P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the first N-type thin film transistor is made of metal oxide.

[0006] In some possible implementations, the first N-type thin-film transistor includes a first top gate and a first bottom gate, the first top gate being the control electrode of the first N-type thin-film transistor, the first top gate being connected to a trace that transmits the inverted signal of the first clock signal, and the first bottom gate being connected to a trace that transmits a low-level modulation signal.

[0007] In some possible implementations, the second module includes a second P-type thin-film transistor, a second N-type thin-film transistor, and a second capacitor; The control terminal of the second P-type thin film transistor is the second input terminal of the second module, and the control terminal of the second P-type thin film transistor is connected to the first output terminal of the first module; the first terminal of the second P-type thin film transistor is connected to the trace that transmits the inverted signal of the second clock signal, and the second terminal of the second P-type thin film transistor is connected to the second output terminal. The control electrode of the second N-type thin film transistor is connected to the trace that transmits the second clock signal, the first electrode of the second N-type thin film transistor is connected to the second output terminal, and the second electrode of the second N-type thin film transistor is connected to the trace that transmits the preset low-level signal. The second capacitor is connected between the second output terminal and the trace that transmits the preset low-level signal; Preferably, the active layer of the second P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the second N-type thin film transistor is made of metal oxide.

[0008] In some possible implementations, the second N-type thin-film transistor includes a second top gate and a second bottom gate, the second top gate being the control electrode of the second N-type thin-film transistor, the second top gate being connected to a trace transmitting the second clock signal, and the second bottom gate being connected to a trace transmitting a low-level modulation signal.

[0009] In some possible implementations, the third module includes a third P-type thin-film transistor and a third N-type thin-film transistor; The control electrodes of the third P-type thin-film transistor and the third N-type thin-film transistor are both connected to the second output terminal. The first electrode of the third P-type thin-film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the third N-type thin-film transistor is connected to the trace that transmits the preset low-level signal. The second electrode of the third P-type thin-film transistor and the first electrode of the third N-type thin-film transistor are both connected to the third output terminal of the third module. The fourth module includes a fourth P-type thin-film transistor and a fourth N-type thin-film transistor; The control electrodes of the fourth P-type thin-film transistor and the fourth N-type thin-film transistor are both connected to the first output terminal. The first electrode of the fourth P-type thin-film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the fourth N-type thin-film transistor is connected to the trace that transmits the preset low-level signal. The second electrode of the fourth P-type thin-film transistor and the first electrode of the fourth N-type thin-film transistor are both connected to the fourth output terminal of the fourth module. Preferably, the active layer of the third P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the third N-type thin film transistor is made of metal oxide. Preferably, the active layer of the fourth P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the fourth N-type thin film transistor is made of metal oxide.

[0010] In some possible implementations, the third N-type thin-film transistor includes a third top gate and a third bottom gate, the third top gate being the control electrode of the third N-type thin-film transistor, and the third top gate being connected to the second output terminal; The gate drive circuit further includes a first control module, which includes a fifth P-type thin-film transistor, a fifth N-type thin-film transistor, and a third capacitor. The control electrode of the fifth P-type thin film transistor is connected to the second output terminal, the first electrode of the fifth P-type thin film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the fifth P-type thin film transistor is connected to the control electrode of the fifth N-type thin film transistor. The first terminal of the fifth N-type thin film transistor is connected to the third bottom gate of the third N-type thin film transistor, and the second terminal of the fifth N-type thin film transistor is connected to the trace that transmits the low-level control signal. The third capacitor is connected between the third bottom gate of the third N-type thin film transistor and the second output terminal; The fourth N-type thin film transistor includes a fourth top gate and a fourth bottom gate. The fourth top gate is the control electrode of the fourth N-type thin film transistor and is connected to the first output terminal. The gate drive circuit further includes a second control module, which includes a sixth P-type thin-film transistor, a sixth N-type thin-film transistor, and a fourth capacitor. The control electrode of the sixth P-type thin film transistor is connected to the first output terminal, the first electrode of the sixth P-type thin film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the sixth P-type thin film transistor is connected to the control electrode of the sixth N-type thin film transistor. The first terminal of the sixth N-type thin film transistor is connected to the fourth bottom gate of the fourth N-type thin film transistor, and the second terminal of the sixth N-type thin film transistor is connected to the trace that transmits the preset low-level signal. The fourth capacitor is connected between the fourth bottom gate of the fourth N-type thin film transistor and the first output terminal; Preferably, the fifth N-type thin-film transistor includes a fifth top gate and a fifth bottom gate, the fifth top gate being the control electrode of the fifth N-type thin-film transistor, and the fifth bottom gate being connected to a trace that transmits a low-level control signal; Preferably, the sixth N-type thin-film transistor includes a sixth top gate and a sixth bottom gate, the sixth top gate being the control electrode of the sixth N-type thin-film transistor, and the sixth bottom gate being connected to the trace that transmits the low-level control signal.

[0011] In some possible implementations, the low-level signal interval of the first clock signal is within the duration of the high-level signal interval of the second clock signal, and the low-level signal interval of the second clock signal is within the duration of the high-level signal interval of the first clock signal. Preferably, the duration of the low-level signal of the first clock signal is less than the duration of the high-level signal of the first clock signal; the duration of the low-level signal of the second clock signal is less than the duration of the high-level signal of the second clock signal.

[0012] This application also provides a display panel, which includes the gate driving circuit provided in this application.

[0013] In some possible implementations, the display panel includes a plurality of cascaded gate drive circuits; The plurality of gate driving circuits include an adjacent first gate driving circuit and a second gate driving circuit, wherein the fourth output terminal of the first gate driving circuit is connected to the first input terminal of the second gate driving circuit. The first clock signal terminal of the first gate driving circuit for receiving the first clock signal and the second clock signal receiving terminal of the second gate driving circuit for receiving the second clock signal are connected to the first clock signal line; The second clock signal receiving terminal of the first gate driving circuit for receiving the second clock signal and the first clock signal connection of the second gate driving circuit for receiving the first clock signal are connected to the second clock signal line. Preferably, the first gate driving circuit is used to receive the inverted signal of the first clock signal, and the second gate driving circuit is used to receive the inverted signal of the second clock signal, with the first inverted clock signal receiving terminal connected to the first inverted clock signal line. The second inverted clock signal receiving terminal of the first gate driving circuit for receiving the inverted signal of the second clock signal and the first inverted clock signal of the second gate driving circuit for receiving the inverted signal of the first clock signal are connected to the second inverted clock signal line.

[0014] Compared with the prior art, this application has the following beneficial effects: This application provides a driving circuit and a display panel. By setting at least one pair of complementary metal-oxide-semiconductor circuits composed of N-type thin-film transistors and P-type thin-film transistors in the driving circuit, and cooperating with a first clock signal, a second clock signal, an inverted signal of the first clock signal, and an inverted signal of the second clock signal, at least two scanning signals with different timing and / or pulse widths can be output in the same driving circuit, thereby effectively reducing the space occupied by the circuit and helping to compress the width of the display panel bezel. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a functional module diagram of the gate drive circuit provided in this embodiment; Figure 2 This is one of the circuit diagrams of the gate drive circuit provided in this embodiment; Figure 3 This is a signal timing diagram of the gate drive circuit provided in this embodiment; Figure 4 The second schematic diagram of the gate drive circuit provided in this embodiment; Figure 5 The third schematic diagram of the gate drive circuit provided in this embodiment; Figure 6 This is a cascaded schematic diagram of the gate drive circuit provided in this embodiment; Figure 7 This is a schematic diagram of the cascaded signal timing of the gate drive circuit provided in this embodiment.

[0017] Reference numerals: M1 - First module; IN-1 - First input terminal; OUT-1 - First output terminal; M2 - Second module; IN-2 - Second input terminal; OUT-2 - Second output terminal; M3 - Third module; IN-3 - Third input terminal; OUT-3 - Third output terminal; M4 - Fourth module; IN-4 - Fourth input terminal; OUT-4 - Fourth output terminal; T1 - First P-type thin-film transistor; T2 - First N-type thin-film transistor; T3 - Second P-type thin-film transistor; T4 - Second N-type thin-film transistor; T5 - Third P-type thin-film transistor; T6 - Third N-type thin-film transistor; T7 - Fourth P-type thin-film transistor; T8 - Fourth N-type thin-film transistor; T9 - Fifth P-type thin-film transistor; T10 - Fifth N-type thin-film transistor; T11 - Sixth P-type thin-film transistor; T12 - Sixth N-type thin-film transistor; SCK1 - First clock signal; SCK1-B - Inverted signal of the first clock signal; SCK2 - Second clock signal; SCK2-B - Inverted signal of the second clock signal; VGL - Preset low-level signal; VGL - Preset high-level signal; VGLL - Low-level control signal; C1 - First capacitor; C2 - Second capacitor; C3 - Third capacitor; C4 - Fourth capacitor. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0023] In some related display panels, a gate drive in panel (GIP) circuit is typically required in the bezel area to provide the pixel drive circuit located in the display area AA with a scan signal Scan and / or a light emission control signal EM for line-by-line scanning.

[0024] The inventors discovered that in such display panels, different driving circuits are typically required to generate the scan signal (Scan) and the light emission control signal (EM), resulting in a large circuit area and making it difficult to further reduce the bezel width of the display surface. Furthermore, the gate circuits often use P-type thin-film transistors to form the driving circuit, requiring relatively complex self-contained circuitry to address the threshold voltage loss problem when maintaining a low level.

[0025] In view of this, this embodiment provides a solution that can reduce the area occupied by the gate drive circuit and improve the threshold voltage loss problem of the gate drive circuit. The solution provided in this embodiment will be described in detail below.

[0026] This embodiment provides a gate driving circuit, which can be used to provide scanning signals and / or light emission control signals to the pixel driving circuit in the display panel. The gate driving circuit provided in this embodiment can be a gate drive in panel (GIP), that is, the gate driving circuit provided in this embodiment can be disposed on the display panel and located in the non-display area of ​​the display panel, for example, in the left and right bezel areas.

[0027] Please see Figure 1 , Figure 1 This is a functional module diagram of a gate driving circuit provided in this embodiment. The gate driving circuit may include a first module M1, a second module M2, a third module M3, and a fourth module M4. The first module M1, the second module M2, the third module M3, and the fourth module M4 include a complementary metal-oxide-semiconductor (CMOS) circuit composed of at least one P-type thin-film transistor and at least one N-type thin-film transistor. For example, a complementary metal-oxide-semiconductor circuit composed of paired P-type and N-type thin-film transistors.

[0028] The first module M1 includes a first input terminal IN-1 and a first output terminal OUT-1. The first module M1 includes functions to, based on a first clock signal SCK1 and its inverted signal SCK1-B, cause the first output terminal OUT-1 to follow the level of the first input terminal IN-1 during a first level phase of the first clock signal SCK1, and to maintain the current level of the first output terminal OUT-1 during a second level phase of the first clock signal SCK1. The first level phase and the second level phase are respectively a low-level phase and a high-level phase within one clock cycle.

[0029] The first clock signal SCK1 can be a square wave signal that repeatedly generates low-level pulses or high-level pulses according to a set period. At any given moment, the inverted signal SCK1-B of the first clock signal has the opposite level to the first clock signal SCK1. For example, when the first clock signal SCK1 is high, the inverted signal SCK1-B is always low; when the first clock signal SCK1 is low, the inverted signal SCK1-B is always high. In this case, when the first clock signal SCK1 is a continuously changing square wave signal, the inverted signal SCK1-B is a continuously changing square wave signal with a waveform opposite to that of the first clock signal SCK1.

[0030] It should be noted that, in this embodiment, a clock cycle refers to the period consisting of a high-level phase and a low-level phase in the clock signal. The duration of a valid signal refers to the duration of either a high-level or a low-level signal that is a valid level within one clock cycle.

[0031] In this embodiment, the low-level phases of the first clock signal SCK1 and the second clock signal SCK2 will be used as examples to explain the corresponding circuit working principle and workflow.

[0032] In other implementations of this embodiment, the high-level phase of the clock signal can also be used as the effective signal phase, but this embodiment does not impose any specific limitations.

[0033] In this embodiment, if the signal received at the first input terminal IN-1 has the same duration as a first level phase in the first clock signal SCK1, the first module M1 can extend the effective signal pulse received from the first input terminal IN-1 to a complete clock cycle and output it from the first output terminal OUT-1.

[0034] The second module M2 includes a second input terminal IN-2 and a second output terminal OUT-2. The second input terminal IN-2 is connected to the first output terminal OUT-1 of the first module M1. The second module M2 is used to output a preset low-level signal VGL at the second output terminal OUT-2 during the third level phase of the second clock signal SCK2, based on the second clock signal SCK2 and its inverted signal SCK2-B. When the second input terminal IN-2 follows and maintains the valid level signal output by the first input terminal IN-1, the second output terminal OUT-2 outputs the inverted signal SCK2-B of the second clock signal.

[0035] The second clock signal SCK2 can be a square wave signal that repeatedly generates low-level or high-level pulses according to a set period. At any given moment, the inverted signal SCK2-B is opposite in level to the second clock signal SCK2. For example, when the second clock signal SCK2 is high, the inverted signal SCK2-B is always low; when the second clock signal SCK2 is low, the inverted signal SCK2-B is always high. In this case, when the second clock signal SCK2 is a continuously changing square wave signal, the inverted signal SCK2-B is a continuously changing square wave signal with a waveform opposite to that of the second clock signal SCK2.

[0036] In this embodiment, when the first module M1 outputs a valid level signal, due to the difference between the second clock signal SCK2 and the first clock signal SCK1, the second module M2 can convert the signal output by the first module M1 into a valid pulse signal with a valid signal duration delayed by one second clock signal SCK2 and with an opposite waveform to the valid signal received at the first input terminal IN-1 of the first module M1.

[0037] The third module M3 includes a third input terminal IN-3 and a third output terminal OUT-3; the third input terminal IN-3 is connected to the second output terminal OUT-2; the third module M3 is used to output a first inverted signal under a preset high-level signal VGH and a preset low-level signal VGL from the third output terminal OUT-3 according to the signal output from the second output terminal OUT-2, and the waveform of the first inverted signal is opposite to the waveform of the signal output from the second output terminal OUT-2.

[0038] The fourth module M4 includes a fourth input terminal IN-4 and a fourth output terminal OUT-4; the fourth input terminal IN-4 is connected to the first output terminal OUT-1; the fourth module M4 is used to output a second inverted signal under a preset high-level signal VGH and a preset low-level signal VGL from the fourth output terminal OUT-4 according to the signal output from the first output terminal OUT-1, and the waveform of the second inverted signal is opposite to the waveform of the signal output from the first output terminal OUT-1.

[0039] In this embodiment, the third module M3 is used to invert the waveform of the signal output from the first output terminal OUT-1 of the first module M1, and the fourth module M4 is used to invert the waveform of the signal output from the second output terminal OUT-2 of the second module M2.

[0040] Thus, the signal output from the fourth output terminal OUT-4 of the fourth module M4 is the signal obtained from the first input terminal IN-1 of the first module M1, delayed until the arrival of the valid signal of the next second clock signal SCK2. The signal output from the fourth output terminal OUT-4 of the fourth module M4 can be used as the scan signal Scan required by the pixel driving circuit.

[0041] The signal output from the third output terminal OUT-3 of the third module M3 is obtained by extending the effective signal obtained from the first input terminal IN-1 of the first module M1 to one clock cycle of the first clock signal SCK1, and then inverting the waveform. The signal output from the third output terminal OUT-3 of the third module M3 can be used as the light emission control signal EM required by the pixel driving circuit.

[0042] Based on the above design, in the driving circuit provided in this application, by setting at least one pair of complementary metal-oxide-semiconductor circuits composed of N-type thin-film transistors and P-type thin-film transistors in the driving circuit, and cooperating with the first clock signal SCK1, the second clock signal SCK2, the inverted signal SCK1-B of the first clock signal and the inverted signal SCK2-B of the second clock signal, at least two scanning signals with different timing and / or pulse widths can be output in the same driving circuit, thereby effectively reducing the space occupied by the circuit and helping to compress the width of the display panel bezel.

[0043] See also some possible implementations. Figure 2 The first module M1 includes a first P-type thin-film transistor T1, a first N-type thin-film transistor T2, and a first capacitor C1. The first terminals of the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are both connected to the first input terminal IN-1, and the second terminals of the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are both connected to the first output terminal OUT-1. The control terminal of the first P-type thin-film transistor T1 is connected to the trace that transmits the first clock signal SCK1, and the control terminal of the first N-type thin-film transistor T2 is connected to the trace that transmits the inverted signal SCK1-B of the first clock signal.

[0044] The first capacitor C1 is connected to the first output terminal OUT-1 and the trace that transmits the preset low-level signal VGL.

[0045] In this embodiment, the first electrode of the N-type thin-film transistor can be the drain and the second electrode can be the source; the first electrode of the P-type thin-film transistor can be the source and the second electrode can be the drain.

[0046] The control electrode of the first P-type thin-film transistor T1 is connected to the first clock signal SCK1, and the first P-type thin-film transistor T1 turns on during the low-level phase of the first clock signal SCK1. The control electrode of the first N-type thin-film transistor T2 is connected to the inverted signal SCK1-B of the first clock signal, and the first N-type thin-film transistor T2 turns on during the high-level phase of the inverted signal SCK1-B of the first clock signal. Therefore, the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 always turn on and off simultaneously.

[0047] In this embodiment, the low-level phase of the signal received by the first input terminal IN-1 of the first module M1 is the valid signal phase.

[0048] When the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are simultaneously turned on, the voltage level at point N1 is consistent with the voltage level at the first input terminal IN-1 of the first module M1. When the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are simultaneously turned off, the first capacitor C1 maintains the voltage level at point N1 until the next time the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are simultaneously turned on.

[0049] Optionally, the active layer of the first P-type thin-film transistor T1 is made of low-temperature polycrystalline silicon, and the active layer of the first N-type thin-film transistor T2 is made of metal oxide.

[0050] In this way, the first P-type thin-film transistor T1 can output a high-level signal without loss, and the second N-type thin-film transistor T4 can output a low-level signal without loss, thereby effectively reducing the threshold voltage loss problem at the first module M1.

[0051] Please see Figure 3 ,by Figure 3 Taking the signal timing shown as an example, during the time period t0, the signal received at the first input terminal IN-1 of the first module M1 is at a high level. When the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are simultaneously turned on, the level at point N1 is pulled up to a high level. When the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are simultaneously turned off, the first capacitor C1 maintains the level at point N1 at a high level. Therefore, during the time period t0, the level at point N1 is always at a high level.

[0052] During time period t1, the signal received at the first input terminal IN-1 of the first module M1 transitions to a low level, and the first clock signal SCK1 simultaneously transitions to a low level. The inverted signal SCK1-B of the first clock signal ( Figure 3 (Not shown in the image) then jumps to a high level. At this time, the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are turned on simultaneously, and the level at point N1 is pulled low.

[0053] During the time interval t2 to t4, the signal received at the first input terminal IN-1 of the first module M1 transitions to a high level and remains at a high level. The first clock signal SCK1 transitions to a high level, while the inverted signal SCK1-B of the first clock signal transitions to a low level. At this time, the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are switched on and off, and the first capacitor C1 maintains the level at point N1 at a low level.

[0054] During time interval t5, the signal received at the first input terminal IN-1 of the first module M1 is at a high level, the first clock signal SCK1 transitions to a low level again, and the inverted signal SCK1-B of the first clock signal transitions to a high level. At this time, the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 turn on simultaneously again, pulling the level at point N1 to a high level. Subsequently, when the first P-type thin-film transistor T1 and the first N-type thin-film transistor T2 are simultaneously turned off, the first capacitor C1 maintains the level at point N1 at a high level.

[0055] Thus, the waveform of the first output terminal OUT-1 (i.e., point N1) of the first module M1 is such that the duration of the effective signal received by the first input terminal IN-1 of the first module M1 is extended to the cycle of a complete first clock signal SCK1.

[0056] See also some possible implementations. Figure 2 The second module M2 includes a second P-type thin-film transistor T3, a second N-type thin-film transistor T4, and a second capacitor C2.

[0057] The control terminal of the second P-type thin film transistor T3 is the second input terminal IN-2 of the second module M2. The control terminal of the second P-type thin film transistor T3 is connected to the first output terminal OUT-1 of the first module M1. The first terminal of the second P-type thin film transistor T3 is connected to the trace of the inverted signal SCK2-B that transmits the second clock signal. The second terminal of the second P-type thin film transistor T3 is connected to the second output terminal OUT-2.

[0058] The control electrode of the second N-type thin film transistor T4 is connected to the trace that transmits the second clock signal SCK2. The first electrode of the second N-type thin film transistor T4 is connected to the second output terminal OUT-2. The second electrode of the second N-type thin film transistor T4 is connected to the trace that transmits the preset low-level signal VGL.

[0059] The second capacitor C2 is connected between the second output terminal OUT-2 and the trace that transmits the preset low-level signal VGL.

[0060] Please see Figure 3 In some possible implementations, the low-level signal interval of the first clock signal SCK1 is within the duration of the high-level signal interval of the second clock signal SCK2, and the low-level signal interval of the second clock signal SCK2 is within the duration of the high-level signal interval of the first clock signal SCK1.

[0061] Optionally, the duration of the low-level signal of the first clock signal SCK1 is shorter than the duration of the high-level signal of the first clock signal SCK1; the duration of the low-level signal of the second clock signal SCK2 is shorter than the duration of the high-level signal of the second clock signal SCK2.

[0062] For example, the length of one clock cycle of the first clock signal SCK1 is the same as the length of one clock cycle of the second clock signal SCK2. The duration of the valid signal in one clock cycle of the first clock signal SCK1 is the same as the duration of the valid signal in one clock cycle of the second clock signal SCK2. The arrival time of the valid signal in the second clock signal SCK2 is delayed compared to the arrival time of the valid signal in the first clock signal SCK1, and the delay time is greater than or equal to the duration of the valid signal in one clock cycle of the first clock signal SCK1.

[0063] by Figure 3Taking the signal timing shown as an example, during the time period t0, point N1 (i.e., the second input terminal IN-2 of the second module M2) remains at a high level, and the second P-type thin-film transistor T3 is always in the off state. When the second clock signal SCK2 is at a high level, the second N-type thin-film transistor T4 turns on, pulling the level of point N2 (i.e., the second output terminal OUT-2 of the second module M2) down to the low level corresponding to the preset low-level signal VGL; when the second clock signal SCK2 is at a low level, the second N-type thin-film transistor T4 turns off, and the low-voltage capacitor keeps the level of point N2 at a low level.

[0064] During time intervals t1 and t2, point N1 transitions to a low level, the second clock signal SCK2 transitions to a high level, and the inverted signal SCK2-B of the second clock signal ( Figure 3 (Not shown in the image) then transitions to a low level. At this time, since point N1 is low, the second P-type thin-film transistor T3 turns on, the second clock signal SCK2 is high, and the second N-type thin-film transistor T4 also turns on. Since the first terminal of the second P-type thin-film transistor T3 and the second terminal of the second N-type thin-film transistor T4 are both low, the level at point N2 remains low after the second P-type thin-film transistor T3 and the second N-type thin-film transistor T4 are turned on.

[0065] During time interval t3, point N1 remains at a low level, the second clock signal SCK2 transitions to a low level, and its inverted signal SCK2-B transitions to a high level. At this time, the second N-type thin-film transistor T4 is turned off, while the second P-type thin-film transistor T3 remains on because N1 remains at a low level. After the inverted signal SCK2-B of the second clock signal goes high, it pulls the level of point N2 to a high level.

[0066] During stage t4, point N1 remains at a low level, the second clock signal SCK2 jumps to a high level, and the inverted signal SCK2-B of the second clock signal jumps to a low level. Both the second P-type thin film transistor T3 and the second N-type thin film transistor T4 are turned on. Since the first terminal of the second P-type thin film transistor T3 and the second terminal of the second N-type thin film transistor T4 are both at a low level, after the second P-type thin film transistor T3 and the second N-type thin film transistor T4 are turned on, the level of point N2 is pulled low again.

[0067] During stage t5, point N1 remains at a low level, and the second P-type thin-film transistor T3 is always off. When the second clock signal SCK2 is high, the second N-type thin-film transistor T4 turns on, pulling the level of point N2 down to the low level corresponding to the preset low-level signal VGL; when the second clock signal SCK2 is low, the second N-type thin-film transistor T4 turns off, and the low-voltage capacitor keeps the level of point N2 at a low level.

[0068] Thus, the waveform of the second output terminal OUT-2 (i.e., point N2) of the second module M2 is such that the valid signal of the signal received by the first input terminal IN-1 of the first module M1 is delayed from the valid signal duration of the first clock to the valid signal duration of the most recent second clock signal SCK2, and the waveform is reversed.

[0069] Optionally, in this embodiment, the active layer of the second P-type thin-film transistor T3 is made of low-temperature polycrystalline silicon, and the active layer of the second N-type thin-film transistor T4 is made of metal oxide. Thus, the second P-type thin-film transistor T3 can output the high level of the second clock signal SCK2 to point N2 without loss, and the second N-type thin-film transistor T4 can output the low level corresponding to the preset low-level signal VGL to point N2 without loss, thereby effectively reducing the threshold voltage loss problem at the second module M2.

[0070] See also some possible implementations. Figure 2 The third module M3 includes a third P-type thin-film transistor T5 and a third N-type thin-film transistor T6; The control electrodes of the third P-type thin-film transistor T5 and the third N-type thin-film transistor T6 are both connected to the second output terminal OUT-2. The first electrode of the third P-type thin-film transistor T5 is connected to the trace that transmits the preset high-level signal VGH, and the second electrode of the third N-type thin-film transistor T6 is connected to the trace that transmits the preset low-level signal VGL. The second electrode of the third P-type thin-film transistor T5 and the first electrode of the third N-type thin-film transistor T6 are both connected to the third output terminal OUT-3 of the third module M3. The fourth module M4 includes the fourth P-type thin-film transistor T7 and the fourth N-type thin-film transistor T8; The control electrodes of the fourth P-type thin-film transistor T7 and the fourth N-type thin-film transistor T8 are both connected to the first output terminal OUT-1. The first electrode of the fourth P-type thin-film transistor T7 is connected to the trace that transmits the preset high-level signal VGH, and the second electrode of the fourth N-type thin-film transistor T8 is connected to the trace that transmits the preset low-level signal VGL. The second electrode of the fourth P-type thin-film transistor T7 and the first electrode of the fourth N-type thin-film transistor T8 are both connected to the fourth output terminal OUT-4 of the fourth module M4.

[0071] For the third module M3, please refer to Figure 3 Taking the timing sequence shown in Figure 3 as an example, in stage t0, point N1 is continuously at a high level, the third P-type thin film transistor T5 is continuously turned off, the third N-type thin film transistor T6 is continuously turned on, and the level of the third output terminal OUT-3 is continuously maintained at the low level corresponding to the preset low level signal VGL.

[0072] During the t1 to t4 phase, point N1 is at a low level, the third N-type thin film transistor T6 remains off, the third P-type thin film transistor T5 remains on, and the level of the third output terminal OUT-3 remains at the high level corresponding to the preset high level signal.

[0073] During stage t5, point N1 remains at a high level, the third P-type thin film transistor T5 remains off, the third N-type thin film transistor T6 remains on, and the level of the third output terminal OUT-3 remains at the low level corresponding to the preset low level signal VGL.

[0074] That is, the signal waveform output from the third output terminal OUT-3 of the third module M3 is opposite to the signal waveform at point N1.

[0075] For module M4, please refer to [link / reference]. Figure 3 Taking the timing sequence shown in Figure 3 as an example, during the t0 to t2 stage, point N2 is continuously at a low level, the fourth N-type thin film transistor T8 is continuously turned off, the fourth P-type thin film transistor T7 is continuously turned on, and the level of the third output terminal OUT-3 is continuously maintained at the high level corresponding to the preset high level signal VGH.

[0076] During segment t3, point N2 is at a high level, the fourth P-type thin film transistor T7 remains off, the fourth N-type thin film transistor T8 remains on, and the level of the fourth output terminal OUT-4 remains at the low level corresponding to the preset low level signal.

[0077] During stages t4 and t5, point N2 remains at a low level, the fourth N-type thin film transistor T8 remains off, the fourth P-type thin film transistor T7 remains on, and the level of the fourth output terminal OUT-4 remains at the high level corresponding to the preset high-level signal VGH.

[0078] That is, the signal waveform output from the fourth output terminal OUT-4 of the fourth module M4 is opposite to the signal waveform at point N2.

[0079] Optionally, in this embodiment, the active layer of the third P-type thin-film transistor T5 is made of low-temperature polycrystalline silicon, and the active layer of the third N-type thin-film transistor T6 is made of metal oxide. Thus, the third P-type thin-film transistor T5 can output the high level corresponding to the preset high-level signal VGH to the third output terminal OUT-3 without loss, and the third N-type thin-film transistor T6 can output the low level corresponding to the preset low-level signal VGL to the third output terminal OUT-3 without loss, thereby effectively reducing the threshold voltage loss problem at the third module M3.

[0080] Optionally, in this embodiment, the active layer of the fourth P-type thin-film transistor T7 is made of low-temperature polycrystalline silicon, and the active layer of the fourth N-type thin-film transistor T8 is made of metal oxide. Thus, the fourth P-type thin-film transistor T7 can output the high level corresponding to the preset high-level signal VGH to the fourth output terminal OUT-4 without loss, and the fourth N-type thin-film transistor T8 can output the low level corresponding to the preset low-level signal VGL to the fourth output terminal OUT-4 without loss, thereby effectively reducing the threshold voltage loss problem at the fourth module M4.

[0081] See also some possible implementations. Figure 4 The first N-type thin film transistor T2 includes a first top gate and a first bottom gate. The first top gate is the control electrode of the first N-type thin film transistor T2. The first top gate is connected to the trace of the inverted signal SCK1-B that transmits the first clock signal. The first bottom gate is connected to the trace of the low-level control signal VGLL.

[0082] That is, the bottom gate of the first N-type thin film transistor T2 is connected to a low-level control signal VGLL, so that the threshold voltage of the first N-type thin film transistor T2 can be controlled by the low-level control signal VGLL.

[0083] See also some possible implementations. Figure 4 The second N-type thin film transistor T4 includes a second top gate and a second bottom gate. The second top gate is the control electrode of the second N-type thin film transistor T4. The second top gate is connected to the trace that transmits the second clock signal SCK2, and the second bottom gate is connected to the trace that transmits the low-level control signal VGLL.

[0084] That is, the bottom gate of the second N-type thin film transistor T4 is connected to a low-level control signal VGLL, so that the threshold voltage of the second N-type thin film transistor T4 can be controlled by the low-level control signal VGLL.

[0085] See also some possible implementations. Figure 5 The third N-type thin film transistor T6 includes a third top gate and a third bottom gate. The third top gate is the control electrode of the third N-type thin film transistor T6 and is connected to the second output terminal OUT-2. The gate drive circuit also includes a first control module, which includes a fifth P-type thin film transistor T9, a fifth N-type thin film transistor T10, and a third capacitor C3. The control electrode of the fifth P-type thin film transistor T9 is connected to the second output terminal OUT-2, the first electrode of the fifth P-type thin film transistor T9 is connected to the trace that transmits the preset high-level signal VGH, and the second electrode of the fifth P-type thin film transistor T9 is connected to the control electrode of the fifth N-type thin film transistor T10. The first terminal of the fifth N-type thin film transistor T10 is connected to the third bottom gate of the third N-type thin film transistor T6, and the second terminal of the fifth N-type thin film transistor T10 is connected to the trace that transmits the low-level control signal VGLL. The third capacitor C3 is connected between the third bottom gate and the second output terminal OUT-2 of the third N-type thin film transistor T6.

[0086] Specifically, when point N1 is at a low level, the third N-type thin-film transistor T6 needs to be in the off state. At this time, the fifth P-type thin-film transistor T9 turns on, pulling the control electrode level of the fifth N-type thin-film transistor T10 high, thus turning on the fifth N-type thin-film transistor T10. After the fifth N-type thin-film transistor T10 turns on, the low-level control signal VGLL is connected to the bottom gate of the third N-type thin-film transistor T6, thereby controlling the threshold voltage of the third N-type thin-film transistor T6, turning off the third N-type thin-film transistor T6 to prevent leakage.

[0087] When point N1 is at a high level, both the fifth P-type thin-film transistor T9 and the fifth N-type thin-film transistor T10 are turned off. By utilizing the coupling effect of the third capacitor C3, the bottom gate voltage of the third N-type thin-film transistor T6 is raised, ensuring that the third N-type thin-film transistor T6 is turned on.

[0088] Optionally, the fifth N-type thin-film transistor T10 includes a fifth top gate and a fifth bottom gate. The fifth top gate is the control electrode of the fifth N-type thin-film transistor, and the fifth bottom gate is connected to the trace that transmits the low-level control signal VGLL.

[0089] See also some possible implementations. Figure 5 The fourth N-type thin film transistor T8 includes a fourth top gate and a fourth bottom gate. The fourth top gate is the control electrode of the fourth N-type thin film transistor T8 and is connected to the first output terminal OUT-1. The gate drive circuit also includes a second control module, which includes a sixth P-type thin film transistor T11, a sixth N-type thin film transistor T12, and a fourth capacitor C4. The control electrode of the sixth P-type thin film transistor T11 is connected to the first output terminal OUT-1, the first electrode of the sixth P-type thin film transistor T11 is connected to the trace that transmits the preset high-level signal VGH, and the second electrode of the sixth P-type thin film transistor T11 is connected to the control electrode of the sixth N-type thin film transistor T12. The first terminal of the sixth N-type thin film transistor T12 is connected to the fourth bottom gate of the fourth N-type thin film transistor T8, and the second terminal of the sixth N-type thin film transistor T12 is connected to the trace that transmits the preset low-level signal VGL. The fourth capacitor C4 is connected between the fourth bottom gate of the fourth N-type thin film transistor T8 and the first output terminal OUT-1.

[0090] Specifically, when point N2 is at a low level, the fourth N-type thin-film transistor T8 needs to be in the off state. At this time, the sixth P-type thin-film transistor T11 turns on, pulling the control electrode level of the sixth N-type thin-film transistor T12 high, thus turning on the sixth N-type thin-film transistor T12. After the sixth N-type thin-film transistor T12 turns on, the low-level control signal VGLL is connected to the bottom gate of the fourth N-type thin-film transistor T8, thereby controlling the threshold voltage of the fourth N-type thin-film transistor T8, turning off the fourth N-type thin-film transistor T8 to prevent leakage.

[0091] When point N2 is at a high level, both the sixth P-type thin-film transistor T11 and the sixth N-type thin-film transistor T12 are turned off. By utilizing the coupling effect of the fourth capacitor C4, the bottom gate voltage of the fourth N-type thin-film transistor T8 is raised, ensuring that the fourth N-type thin-film transistor T8 is turned on.

[0092] Optionally, the sixth N-type thin-film transistor T12 includes a sixth top gate and a sixth bottom gate. The sixth top gate is the control electrode of the sixth N-type thin-film transistor, and the sixth bottom gate is connected to the trace that transmits the low-level control signal VGLL.

[0093] This application also provides a display panel, which includes a plurality of gate driving circuits provided in this embodiment, and the plurality of gate driving circuits are cascaded.

[0094] Specifically, the multiple gate driving circuits include adjacent first gate driving circuits and second gate driving circuits, wherein the first gate driving circuit is the next level in the cascaded hierarchy of the second gate driving circuit.

[0095] The fourth output terminal OUT-4 of the first gate drive circuit is connected to the first input terminal IN-1 of the second gate drive circuit.

[0096] The first clock signal terminal of the first gate driving circuit for receiving the first clock signal SCK1 and the second clock signal terminal of the second gate driving circuit for receiving the second clock signal SCK2 are connected to the first clock signal line SCK-I.

[0097] The second clock signal terminal of the first gate drive circuit for receiving the second clock signal SCK2 and the first clock signal terminal of the second gate drive circuit for receiving the first clock signal SCK1 are connected to the second clock signal line SCK-II.

[0098] Accordingly, the first inverted clock signal terminal of the first gate driving circuit for receiving the inverted signal SCK1-B of the first clock signal and the second inverted clock signal terminal of the second gate driving circuit for receiving the inverted signal SCK2-B of the second clock signal are connected to the first inverted clock signal line SCK-IB.

[0099] The second inverted clock signal terminal of the first gate drive circuit, which is used to receive the inverted signal SCK2-B of the second clock signal, and the first inverted clock signal terminal of the second gate drive circuit, which is used to receive the inverted signal SCK1-B of the first clock signal, are connected to the second inverted clock signal line SCK-II-B.

[0100] For example, see Figure 6 , Figure 6 The diagram shows the cascading configuration of the gate drive circuit GIP1 corresponding to the first row L1, the gate drive circuit GIP2 corresponding to the second row L2, the gate drive circuit GIP3 corresponding to the third row L3, and the gate drive circuit GIP4 corresponding to the fourth row L4.

[0101] The display panel provided in this embodiment includes a first clock signal line SCK-I, a first inverted clock signal line SCK-IB, a second clock signal line SCK-II, and a second inverted clock signal line SCK-II-B.

[0102] The signal transmitted by the first clock signal line SCK-I is inverted by an inverter and then transmitted to the first inverted clock signal line SCK-IB.

[0103] The signal transmitted by the second clock signal line SCK-II is inverted by another inverter and then transmitted to the second inverted clock signal line SCK-II-B.

[0104] The fourth output terminal OUT-4 of the gate drive circuit GIP1 is connected to the first input terminal IN-1 of the gate drive circuit GIP2, in addition to being output to the pixel drive circuit corresponding to the first row L1 in the display area. The fourth output terminal OUT-4 of the gate drive circuit GIP2 is connected to the first input terminal IN-1 of the gate drive circuit GIP3, in addition to being output to the pixel drive circuit corresponding to the second row L2 in the display area, and so on.

[0105] Furthermore, the first clock signal SCK1 received by the gate drive circuit GIP1 and the second clock signal SCK2 received by the gate drive circuit GIP2 come from the same first clock signal line SCK-I, the second clock signal SCK2 received by the gate drive circuit GIP1 and the first clock signal SCK1 received by the gate drive circuit GIP2 come from the same second clock signal line SCK-II, and so on.

[0106] Correspondingly, the inverted signal SCK1-B of the first clock signal received by the gate drive circuit GIP1 and the inverted signal SCK2-B of the second clock signal received by the gate drive circuit GIP2 come from the same first inverted clock signal line SCK-IB, the inverted signal SCK2-B of the second clock signal received by the gate drive circuit GIP1 and the inverted signal SCK1-B of the first clock signal received by the gate drive circuit GIP2 come from the same second inverted clock signal line SCK-II-B, and so on.

[0107] Therefore, please see Figure 7 ,exist Figure 7 In the timing sequence shown, the effective pulses in the output signals of the fourth output terminal OUT-4 of the gate drive circuits GIP1, GIP2, GIP3, and GIP4 are delayed line by line, so that the pixel drive circuits corresponding to the first row L1, the second row L2, the third row L3, and the fourth row L4 receive the scan signal Scan in turn.

[0108] The effective pulses in the output signals of the third output terminal OUT-3 of the gate driving circuits GIP1, GIP2, GIP3, and GIP4 are also delayed row by row, so that the pixel driving circuits corresponding to the first row L1, the second row L2, the third row L3, and the fourth row L4 receive the light emission control signal EM in turn.

[0109] This application also provides an electronic device, which includes the display panel provided in this application. The electronic device may include mobile phones, tablets, smart wearable devices, televisions, laptops, monitors, and other devices with display functions.

[0110] In summary, this application provides a driving circuit and a display panel. By setting at least one pair of complementary metal-oxide-semiconductor circuits composed of N-type thin-film transistors and P-type thin-film transistors in the driving circuit, and cooperating with a first clock signal, a second clock signal, an inverted signal of the first clock signal, and an inverted signal of the second clock signal, at least two scanning signals with different timing sequences and / or pulse widths can be output in the same driving circuit. This can effectively reduce the space occupied by the circuit and is beneficial for compressing the bezel width of the display panel.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A gate driving circuit, characterized in that, The gate drive circuit includes a first module, a second module, a third module, and a fourth module, wherein the first module, the second module, the third module, and the fourth module include a complementary metal-oxide-semiconductor circuit composed of at least one P-type thin-film transistor and at least one N-type thin-film transistor. The first module includes a first input terminal and a first output terminal; the first module includes a function to make the first output terminal follow the level of the first input terminal during a first level phase of the first clock signal and to maintain the current level of the first output terminal during a second level phase of the first clock signal, based on a first clock signal and an inverted signal of the first clock signal. The second module includes a second input terminal and a second output terminal; the second input terminal is connected to the first output terminal; the second module is used to, according to the second clock signal and the inverted signal of the second clock signal, cause the second output terminal to output a preset low-level signal during the third level stage of the second clock signal, and cause the second output terminal to output the inverted signal of the second clock signal when the second input terminal follows and maintains the output valid level signal of the first input terminal; The third module includes a third input terminal and a third output terminal; the third input terminal is connected to the second output terminal; the third module is used to output a first inverted signal under a preset high-level signal and a preset low-level signal from the third output terminal according to the signal output from the second output terminal, the waveform of the first inverted signal being opposite to the waveform of the signal output from the second output terminal; The fourth module includes a fourth input terminal and a fourth output terminal; the fourth input terminal is connected to the first output terminal; the fourth module is used to output a second inverted signal under the preset high-level signal and the preset low-level signal from the fourth output terminal according to the signal output from the first output terminal, the waveform of the second inverted signal being opposite to the waveform of the signal output from the first output terminal.

2. The gate driving circuit according to claim 1, characterized in that, The first module includes a first P-type thin-film transistor, a first N-type thin-film transistor, and a first capacitor. The first electrodes of the first P-type thin-film transistor and the first N-type thin-film transistor are both connected to the first input terminal. The second electrodes of the first P-type thin-film transistor and the first N-type thin-film transistor are both connected to the first output terminal. The control electrode of the first P-type thin-film transistor is connected to the trace that transmits the first clock signal, and the control electrode of the first N-type thin-film transistor is connected to the trace that transmits the inverted signal of the first clock signal. The first capacitor is connected to the first output terminal and the trace that transmits the preset low-level signal; Preferably, the active layer of the first P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the first N-type thin film transistor is made of metal oxide.

3. The gate driving circuit according to claim 2, characterized in that, The first N-type thin-film transistor includes a first top gate and a first bottom gate. The first top gate is the control electrode of the first N-type thin-film transistor. The first top gate is connected to a trace that transmits the inverted signal of the first clock signal. The first bottom gate is connected to a trace that transmits a low-level control signal.

4. The gate driving circuit according to claim 1, characterized in that, The second module includes a second P-type thin-film transistor, a second N-type thin-film transistor, and a second capacitor; The control terminal of the second P-type thin film transistor is the second input terminal of the second module, and the control terminal of the second P-type thin film transistor is connected to the first output terminal of the first module; the first terminal of the second P-type thin film transistor is connected to the trace that transmits the inverted signal of the second clock signal, and the second terminal of the second P-type thin film transistor is connected to the second output terminal. The control electrode of the second N-type thin film transistor is connected to the trace that transmits the second clock signal, the first electrode of the second N-type thin film transistor is connected to the second output terminal, and the second electrode of the second N-type thin film transistor is connected to the trace that transmits the preset low-level signal. The second capacitor is connected between the second output terminal and the trace that transmits the preset low-level signal; Preferably, the active layer of the second P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the second N-type thin film transistor is made of metal oxide.

5. The gate driving circuit according to claim 4, characterized in that, The second N-type thin film transistor includes a second top gate and a second bottom gate. The second top gate is the control electrode of the second N-type thin film transistor. The second top gate is connected to the trace that transmits the second clock signal, and the second bottom gate is connected to the trace that transmits the low-level control signal.

6. The gate driving circuit according to claim 1, characterized in that, The third module includes a third P-type thin-film transistor and a third N-type thin-film transistor; The control electrodes of the third P-type thin-film transistor and the third N-type thin-film transistor are both connected to the second output terminal. The first electrode of the third P-type thin-film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the third N-type thin-film transistor is connected to the trace that transmits the preset low-level signal. The second electrode of the third P-type thin-film transistor and the first electrode of the third N-type thin-film transistor are both connected to the third output terminal of the third module. The fourth module includes a fourth P-type thin-film transistor and a fourth N-type thin-film transistor; The control electrodes of the fourth P-type thin-film transistor and the fourth N-type thin-film transistor are both connected to the first output terminal. The first electrode of the fourth P-type thin-film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the fourth N-type thin-film transistor is connected to the trace that transmits the preset low-level signal. The second electrode of the fourth P-type thin-film transistor and the first electrode of the fourth N-type thin-film transistor are both connected to the fourth output terminal of the fourth module. Preferably, the active layer of the third P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the third N-type thin film transistor is made of metal oxide. Preferably, the active layer of the fourth P-type thin film transistor is made of low-temperature polycrystalline silicon, and the active layer of the fourth N-type thin film transistor is made of metal oxide.

7. The gate driving circuit according to claim 6, characterized in that, The third N-type thin film transistor includes a third top gate and a third bottom gate. The third top gate is the control electrode of the third N-type thin film transistor and is connected to the second output terminal. The gate drive circuit further includes a first control module, which includes a fifth P-type thin-film transistor, a fifth N-type thin-film transistor, and a third capacitor. The control electrode of the fifth P-type thin film transistor is connected to the second output terminal, the first electrode of the fifth P-type thin film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the fifth P-type thin film transistor is connected to the control electrode of the fifth N-type thin film transistor. The first terminal of the fifth N-type thin film transistor is connected to the third bottom gate of the third N-type thin film transistor, and the second terminal of the fifth N-type thin film transistor is connected to the trace that transmits the low-level control signal. The third capacitor is connected between the third bottom gate of the third N-type thin film transistor and the second output terminal; The fourth N-type thin film transistor includes a fourth top gate and a fourth bottom gate. The fourth top gate is the control electrode of the fourth N-type thin film transistor and is connected to the first output terminal. The gate drive circuit further includes a second control module, which includes a sixth P-type thin-film transistor, a sixth N-type thin-film transistor, and a fourth capacitor. The control electrode of the sixth P-type thin film transistor is connected to the first output terminal, the first electrode of the sixth P-type thin film transistor is connected to the trace that transmits the preset high-level signal, and the second electrode of the sixth P-type thin film transistor is connected to the control electrode of the sixth N-type thin film transistor. The first terminal of the sixth N-type thin film transistor is connected to the fourth bottom gate of the fourth N-type thin film transistor, and the second terminal of the sixth N-type thin film transistor is connected to the trace that transmits the preset low-level signal. The fourth capacitor is connected between the fourth bottom gate of the fourth N-type thin film transistor and the first output terminal; Preferably, the fifth N-type thin-film transistor includes a fifth top gate and a fifth bottom gate, the fifth top gate being the control electrode of the fifth N-type thin-film transistor, and the fifth bottom gate being connected to a trace that transmits a low-level control signal; Preferably, the sixth N-type thin-film transistor includes a sixth top gate and a sixth bottom gate, the sixth top gate being the control electrode of the sixth N-type thin-film transistor, and the sixth bottom gate being connected to the trace that transmits the low-level control signal.

8. The gate driving circuit according to claim 1, characterized in that, The low-level signal interval of the first clock signal is within the duration range of the high-level signal interval of the second clock signal, and the low-level signal interval of the second clock signal is within the duration range of the high-level signal interval of the first clock signal. Preferably, the duration of the low-level signal of the first clock signal is less than the duration of the high-level signal of the first clock signal; the duration of the low-level signal of the second clock signal is less than the duration of the high-level signal of the second clock signal.

9. A display panel, characterized in that, The display panel includes the gate driving circuit according to any one of claims 1-8.

10. The display panel according to claim 9, characterized in that, The display panel includes multiple cascaded gate drive circuits; The plurality of gate driving circuits include adjacent first gate driving circuits and second gate driving circuits, wherein the fourth output terminal of the first gate driving circuit is connected to the first input terminal of the second gate driving circuit. The first clock signal terminal of the first gate driving circuit for receiving the first clock signal and the second clock signal receiving terminal of the second gate driving circuit for receiving the second clock signal are connected to the first clock signal line; The second clock signal receiving terminal of the first gate driving circuit for receiving the second clock signal and the first clock signal connection of the second gate driving circuit for receiving the first clock signal are connected to the second clock signal line. Preferably, the first gate driving circuit is used to receive the inverted signal of the first clock signal, and the second gate driving circuit is used to receive the inverted signal of the second clock signal, with the first inverted clock signal receiving terminal connected to the first inverted clock signal line. The second inverted clock signal receiving terminal of the first gate driving circuit for receiving the inverted signal of the second clock signal and the first inverted clock signal of the second gate driving circuit for receiving the inverted signal of the first clock signal are connected to the second inverted clock signal line.

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