Organic light emitting display device and driving method thereof

Abstract

Disclosed is an organic light emitting display device and a driving method thereof. The organic light emitting display device includes a display panel including a plurality of sub-pixels, scanning the plurality of sub-pixels based on a scan signal of one of a plurality of frequency-variable scan patterns; a sensing circuit configured to sense an off-change timing of the scan signal for each scan pattern and panel position in a first sensing sequence, and sense a ripple voltage added to an initialization voltage of each of the plurality of sub-pixels at the off-change timing of the scan signal during a second sensing sequence independent of the first sensing sequence; and a correction circuit configured to correct a data voltage to be input to each of the sub-pixels based on a compensation gain for compensating for a luminance change caused by the ripple voltage.

Description

Technical Field

[0001] This disclosure relates to organic light-emitting display devices and driving methods thereof. Background Technology

[0002] Organic light-emitting display devices support multiple variable frequency scanning modes to meet various consumer needs. Variable frequency scanning modes include dynamic frequency & resolution (DFR) scanning mode and scanning modes with various predetermined frequencies.

[0003] Organic light-emitting display devices can change the scan mode midway through driving. The 240Hz, 60Hz, and 480Hz DFR scan modes differ in their scan overlap characteristics. Due to these differences, the initial level of the source voltage of the driving transistors may vary during data programming depending on the scan mode, and therefore, brightness deviations may occur when changing the scan mode. The level of brightness deviation is affected by the degree of RC delay and thus varies depending on the panel position. Panel positions with relatively high gate loads exhibit greater brightness deviations compared to panel positions with relatively low gate loads. Display quality is degraded due to these position-based brightness deviations occurring at varying levels when changing scan modes. Summary of the Invention

[0004] In order to overcome the above-mentioned problems in the related technologies, this disclosure provides an organic light-emitting display device and a driving method thereof, which can compensate for brightness deviations based on panel position that occur at different levels for each scanning mode.

[0005] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, an organic light-emitting display device includes: a display panel including a plurality of sub-pixels, scanning the plurality of sub-pixels based on a scan signal of one of a plurality of frequency-variable scan modes; a sensing circuit configured to sense off-change timings of the scan signal for each scan mode and panel position in a first sensing sequence, and to sense an initialization voltage of an initialization voltage added to each of the plurality of sub-pixels during the off-change timings of the scan signal in a second sensing sequence independent of the first sensing sequence; and a correction circuit configured to correct a data voltage to be input to each sub-pixel based on a compensation gain for compensating for brightness variations caused by the ripple voltage. Attached Figure Description

[0006] The accompanying drawings, which provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0007] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an embodiment of the present disclosure;

[0008] Figure 2 The diagram illustrates the pixel connection structure according to an embodiment of the present disclosure;

[0009] Figure 3 The initial level of the source voltage of the driving transistor is shown in data programming in 240Hz scan mode;

[0010] Figure 4 The initial level of the source voltage of the driving transistor is shown in data programming in 60Hz scan mode;

[0011] Figure 5 The initial level of the source voltage of the driving transistor is shown in data programming in 480Hz DFR scan mode;

[0012] Figure 6 This illustrates an example of how the ripple voltage caused by the discharge operation of a sub-pixel affects the source voltage of an adjacent sub-pixel in a scan overlap drive.

[0013] Figure 7 This illustrates an example of source voltage distortion in sub-pixels caused by ripple voltage added to the initialization voltage during the off-time of the scan signal (which is the timing for setting Vgs) in a scan overlap drive.

[0014] Figure 8 An example is shown where the degree of RC delay of the scan signal varies based on the panel position;

[0015] Figure 9 The output waveforms of the scan signal are shown with respect to point A, which is relatively close to the input position of the scan signal, and point B, which is relatively far from the input position of the scan signal.

[0016] Figure 10 The connection structure between the sensing circuit, the correction circuit, and the memory according to an embodiment of the present disclosure is shown;

[0017] Figure 11 An operational sequence is shown for a first sensing sequence used to time the timing of the shutdown change of the scan signal for each scan mode and panel position;

[0018] Figure 12 The operation sequence for a second sensing sequence used to sense the ripple voltage added to the initial voltage of each sub-pixel at the timing of the off-state change of the scan signal is shown.

[0019] Figures 13 to 15 Used to describe the operation of sub-pixels and sensing circuitry in the first sensing sequence;

[0020] Figure 16 and Figure 17 Used to describe the operation of sub-pixels and sensing circuitry in the second sensing sequence;

[0021] Figure 18 This describes the principle that ripple voltage added to the initial voltage can be sensed in the display driver;

[0022] Figure 19 The ripple voltage levels are shown for brightness and for each scan mode;

[0023] Figure 20 The compensation gain values ​​for brightness and each scan mode are shown. Detailed Implementation

[0024] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concepts of the disclosure to those skilled in the art.

[0025] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0026] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for describing various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. The same reference numerals always refer to the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "comprising," "having," "including," etc., indicate that additional parts may be added, unless "only" is used. As used herein, the singular forms "a," "described," and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0027] Even if not explicitly stated, elements in the various embodiments of this disclosure will be interpreted to include error tolerance.

[0028] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "over", "below", and "next", one or more other parts may be placed between the two parts unless "immediately following" or "directly" is used.

[0029] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions unnecessarily obscure important points of this disclosure. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an embodiment of the present disclosure.

[0032] Reference Figure 1 The display panel 100 may include a screen AA for displaying an input image. The screen AA may include a pixel array for displaying pixel data (hereinafter referred to as "image data") DATA of the input image. The pixel array may include multiple data lines DL, multiple gate lines GL intersecting the data lines DL, multiple reference voltage lines, and multiple pixels.

[0033] Pixels can be arranged in a matrix on the screen AA, defined by data lines DL, gate lines GL, and reference voltage lines. Pixels can be arranged in various types on the screen AA, such as striped, diamond, and matrix patterns.

[0034] A pixel array may include multiple pixel columns and multiple pixel rows L1 to Ln intersecting the pixel columns. Each pixel column may include pixels arranged in the Y-axis direction. A pixel row may include pixels arranged in the X-axis direction. A vertical period may be a frame period required to write a frame of image data DATA to all pixels on the screen. A horizontal period may be the time obtained by dividing a frame period by the number of pixel rows L1 to Ln. A horizontal period may be the time required to write a pixel row of image data DATA to the pixels of a pixel row sharing a gate line GL.

[0035] Each pixel may include a red (R) subpixel 101, a green (G) subpixel 101, a blue (B) subpixel 101, and a white (W) subpixel 101 for implementing the color.

[0036] The display device according to this embodiment can be implemented as an organic light-emitting display device. In this case, the pixel circuit of the frequency-variable display device may include a light-emitting device, a driving element, one or more switching elements, and a capacitor. The light-emitting device may be implemented as an organic light-emitting diode (OLED). The driving current that allows the light-emitting device to emit light can be adjusted based on the gate-source voltage of the driving element. Each of the driving element and the switching element may be implemented as a transistor. The semiconductor layer of the transistor may include amorphous silicon or polycrystalline silicon. At least some of the transistors' semiconductor layers may include oxide. The pixel circuit may be connected to a data line DL and a gate line GL. Figure 1 In the diagram, "D1 to D3" indicated by circles can be data lines, and "Gn-2 to Gn" can be gate lines.

[0037] A touch sensor can be disposed in the display panel 100. The touch sensor can be arranged on the screen AA of the display panel 100 as an on-cell type or an additional type, or it can be implemented as an in-cell type touch sensor embedded in the pixel array. Touch input can be sensed by the touch sensor, or touch input can be sensed by pixels alone even without a touch sensor.

[0038] The source driver 110 can use a digital-to-analog converter (DAC) to convert image data DATA received from the timing controller 130 into a gamma-compensated voltage to generate a data voltage. The source driver 110 can supply the data voltage to the data line DL. The data voltage can be supplied to the data line DL and can also be applied to the gate electrode of the driving element through the switching elements of the sub-pixel 101. The source driver 110 can provide an initialization voltage VpreR received from the power supply circuit 200 to a reference voltage line connected to the sub-pixel. The initialization voltage VpreR can be supplied to the reference voltage line and can also be applied to the source electrode of the driving element through the switching elements of each sub-pixel 101.

[0039] The source driver 110 can be implemented using one or more source driver integrated circuits (ICs). The source driver IC can be connected to the timing controller 130 via an internal interface circuit. This internal interface circuit can be implemented as an embedded point-to-point clock interface (EPI). The source driver IC may also include a touch driver. The touch driver can generate touch sensor drive signals and convert the charge changes of the touch sensor into raw touch data. The touch driver can transmit the raw touch data to the host system (not shown) via a separate interface circuit. This separate interface circuit can be implemented as a Serial Peripheral Interface (SPI).

[0040] Gate driver 120 can be disposed in a bezel region BZ, which is located outside the screen AA in the display panel 100. The bezel region BZ may not display an image. Gate driver 120 can sequentially provide gate signals synchronized with the data voltage to the gate line GL under the control of timing controller 130. The gate signals can simultaneously activate pixels in the same pixel row to which the data voltage is charged. Gate driver 120 can use one or more shift registers to output the gate signals and can shift the gate signals. The gate signals can be referred to as scan signals. Scan signals may include the gate on-voltage VON and gate off-voltage VOFF received from power supply circuit 200.

[0041] Gate driver 120 can perform scan overlap driving. Based on scan overlap driving, the scan-on periods of adjacent scan signals can partially overlap with each other. During the scan-on period of the scan signal in the sub-pixel of each pixel row, data programming operations, i.e., setting operations of the gate-source voltage (hereinafter referred to as Vgs) of the driving transistor, can be performed. When the frame frequency is high, scan overlap driving can increase the scan-on period and thus achieve a stable Vgs setting.

[0042] The gate driver 120 can support multiple frequency-variable scan modes and can change the scan mode in the middle of the display drive based on the control of the timing controller 130. In addition to normal scan modes such as 240Hz scan mode or 60Hz scan mode, the multiple frequency-variable scan modes can also include dynamic frequency & resolution (DFR) scan mode.

[0043] In DFR scan mode, scan signal pairs with the same phase can be provided to two adjacent gate lines. That is, in DFR scan mode, gate lines (two pairs) can be scanned sequentially using scan signal pairs with phase-shifted order. Compared to normal scan mode, the vertical resolution of the screen image in DFR scan mode can be halved.

[0044] Due to the differences in overlap characteristics among various scan modes, the initial level of the source voltage of the driving transistor can vary based on the scan mode in the data programming, and therefore, brightness deviation may occur when the scan mode is changed. The level of this brightness deviation may be affected by the degree of RC delay of the scan signal, and therefore may vary based on the panel position.

[0045] To compensate for brightness deviations based on panel position that occur at different levels in each scanning mode, the organic light-emitting display device according to this embodiment may include a sensing circuit and a correction circuit in the source driver 110.

[0046] Multiple sensing circuits can be configured in the source driver 110. The sensing circuits can sense the off-change timings of the scan signal for each scan mode and panel position in a first sensing sequence, and can sense the ripple voltage added to the initial voltage of each sub-pixel at the off-change timings of the scan signal in a second sensing sequence.

[0047] The correction circuit can correct the data voltage to be input to each sub-pixel based on the compensation gain to compensate for brightness variations caused by ripple voltage. The correction circuit can be included in the timing controller 130.

[0048] The timing controller 130 can receive video data DATA and timing signals synchronized with the video data DATA from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync defines the vertical period (i.e., one frame). The horizontal synchronization signal Hsync defines the horizontal period. The data enable signal DE defines the time during which the data voltage is input to the sub-pixel in the vertical period (i.e., the vertical activity period). Other times in the vertical period besides the vertical activity period can be vertical blanking periods. The data enable signal DE can oscillate during the vertical activity period but not during the vertical blanking period.

[0049] The timing controller 130 can generate a source timing control signal DDC for controlling the operating timing of the source driver 110 and a gate timing control signal GDC for controlling the operating timing of the gate driver 120 based on the timing signals Vsync, Hsync and DE received from the host system.

[0050] The host system can be one of a television (TV), set-top box, navigation system, personal computer (PC), home theater, vehicle display system, mobile device, or wearable device. In mobile devices and wearable devices, the source driver 110, timing controller 130, and level shifter 140 can be integrated into a single driver IC.

[0051] Level shifter 140 can shift the logic voltage level of the gate timing control signal GDC output from timing controller 130 to either the gate on voltage VON or the gate off voltage VOFF to supply the gate driver 120. The low logic voltage of the gate timing control signal GDC can be shifted down to the gate off voltage VOFF, and the high logic voltage of the gate timing control signal GDC can be shifted up to the gate on voltage VON.

[0052] The power supply circuit 200 can generate various source voltages required for panel driving. The power supply circuit 200 can generate the gate on voltage VON and gate off voltage VOFF required for scanning signal generation, generate the high-level source voltage EVDD and low-level source voltage EVSS to be provided to each sub-pixel 101, and generate the initialization voltage VpreR to be provided to the reference voltage line.

[0053] Figure 2 The diagram illustrates a pixel connection structure according to an embodiment of the present disclosure.

[0054] Reference Figure 2 A pixel may include four sub-pixels SP1 to SP4 that share a reference voltage line RL. The four sub-pixels SP1 to SP4 may be R, G, B, and W sub-pixels used to constitute the same pixel. Each of the sub-pixels SP1 to SP4 may include, for example, a light-emitting device OLED, a driving transistor DT, a first switching transistor ST1, a second switching transistor ST2, and a storage capacitor Cst.

[0055] An OLED (Optical Display Panel) emits light to achieve brightness by using a drive current supplied from a driving transistor DT. The anode of the OLED can be connected to a second node N2, and the cathode can be connected to the input terminal of a low-level source voltage EVSS.

[0056] The driving transistor DT can generate a driving current based on its gate-source voltage to provide driving current to the OLED light-emitting device. The gate electrode of the driving transistor DT can be connected to the first node N1, the drain electrode can be connected to the input terminal of the high-level source voltage EVDD, and the source electrode can be connected to the second node N2.

[0057] The gate electrode of the first switching transistor ST1 can be connected to the scan gate line GL. The first electrode of the first switching transistor ST1 can be connected to the data line DL, and the second electrode can be connected to the first node N1.

[0058] The gate electrode of the second switching transistor ST2 can be connected to the sensing gate line GL. The first electrode of the second switching transistor ST2 can be connected to the reference voltage line RL, and the second electrode can be connected to the second node N2.

[0059] One electrode of the storage capacitor Cst can be connected to the first node N1, and the other electrode can be connected to the second node N2.

[0060] The first switching transistor ST1 and the second switching transistor ST2 can be turned on during the vertical activity period based on the scan signal SCAN with gate turn-on voltage VON. Therefore, the gate electrode of the driving transistor DT can be connected to the data line DL, and the source electrode of the driving transistor DT can be connected to the reference voltage line RL. Thus, a data programming operation corresponding to image data can be performed. This data programming operation can be referred to as the gate-source voltage (Vgs) setting operation on the driving transistor DT. The gate-source voltage (Vgs) can be the voltage difference Vdata-VpreR between the data voltage Vdata and the initialization voltage VpreR. Although described below, the gate-source voltage (Vgs) and the brightness based on this gate-source voltage may be distorted when a ripple voltage based on the scan overlap drive is added to the initialization voltage VpreR. When the data programming operation is completed during the vertical activity period, the first switching transistor ST1 and the second switching transistor ST2 can be turned off based on the scan signal SCAN with gate turn-off voltage VOFF.

[0061] First switch SW1 and second switch SW2 can be further connected to a reference voltage line RL. First switch SW1 can connect the input of the initialization voltage VpreR to the reference voltage line RL. Second switch SW2 can connect the sensing circuit SU to the reference voltage line RL during the first sensing sequence and the second sensing sequence. First switch SW1 and second switch SW2 can be included together with the sensing circuit SU in the source driver.

[0062] Figure 3 The initial level of the source voltage of the driving transistor is shown in data programming in 240Hz scan mode. Figure 4 The initial level of the source voltage of the driving transistor is shown in data programming in 60Hz scan mode. Figure 5 The initial level of the source voltage of the driving transistor is shown in data programming in 480Hz DFR scan mode.

[0063] refer to Figures 3 to 5 The 240Hz, 60Hz, and 480Hz DFR scan modes can differ in their scan overlap characteristics. Due to this difference in overlap characteristics, the initial level of the source voltage Vs of the driving transistor can be varied based on the scan mode in the data programming.

[0064] For example, in Figure 4 In the 60Hz scan mode, the initial level of the source voltage Vs used for Vgs setting can be ΔV1 higher than the initial voltage VpreR. Figure 3 In the 240Hz scan mode, the initial level of the source voltage Vs used for Vgs setting can be ΔV2 higher than the initial voltage VpreR. Figure 5In the 480Hz DFR scan mode, the initial level of the source voltage Vs used for Vgs setting can be ΔV3 higher than the initial voltage VpreR.

[0065] In this case, ΔV2 can be greater than ΔV1, and ΔV3 can be greater than ΔV2. The initialization characteristics are likely to be relatively optimal in the 60Hz scan mode and relatively worst in the 480Hz DFR scan mode.

[0066] Compared to the relatively short overlap time of the 60Hz scan mode, the overlap time in the 240Hz and 480Hz DFR scan modes can be longer. Therefore, the 240Hz and 480Hz DFR scan modes may be significantly affected by the discharge of adjacent pixel rows. In both modes, the discharge of adjacent pixel rows may make it difficult to sufficiently reduce the reference voltage line to the initialization voltage VpreR. Specifically, in the 480Hz DFR scan mode, subpixels located in two adjacent pixel rows can be discharged at once, resulting in the worst initialization level of the source voltage Vs used for Vgs setting.

[0067] In the display driver, when the 240Hz scan mode is changed to the 60Hz scan mode, assuming the same panel position and the same data voltage, the initial level of the source voltage Vs can be reduced, so Vgs can be increased, thereby increasing the brightness.

[0068] On the other hand, in display driving, when the 60Hz scan mode is changed to the 480Hz DFR scan mode, assuming the same panel position and the same data voltage, the initial level of the source voltage Vs can be increased, so Vgs can be decreased, thereby reducing the brightness.

[0069] The level of brightness deviation caused by this change in scanning mode may be affected by the degree of RC delay of the scanning signal, and therefore may vary based on the panel position.

[0070] Figure 6 This illustrates an example of how the ripple voltage caused by the discharge operation of a sub-pixel affects the source voltage of an adjacent sub-pixel in a scan overlap drive. Figure 7 This illustrates an example of source voltage distortion in sub-pixels caused by ripple voltage added to the initialization voltage during the off-time of the scan signal (which is the timing for setting Vgs) in a scan overlap drive.

[0071] refer to Figure 6Based on the discharge operation in the scan overlap drive, the sub-pixel set in the i-th (where i can be a natural number) pixel row L(i) and the sub-pixel set in the (i+1)-th pixel row L(i+1) can influence each other.

[0072] For example, based on the discharge operation of the sub-pixels set in the i-th pixel row L(i) and the (i+1)-th pixel row L(i+1), a ripple voltage is added to the initialization voltage VpreR of the reference voltage line RL. In the Vgs setting of the sub-pixels set in the i-th pixel row L(i) and the (i+1)-th pixel row L(i+1), the ripple voltage added to the initialization voltage VpreR can affect the source voltage Vs.

[0073] Reference Figure 7 The Vgs setting for each pixel row can be completed during the off-state timing of the scan signal SCAN. In other words, the off-state timing of the scan signal SCAN can be the time at which the source voltage Vs reflected in the Vgs setting for each pixel row is determined.

[0074] The determination time of the source voltage Vs of the i-th pixel row L(i) can be the timing of the turn-off change of the i-th scan signal SCAN(i), the determination time of the source voltage Vs of the (i+1)-th pixel row L(i+1) can be the timing of the turn-off change of the (i+1)-th scan signal SCAN(i+1), and the determination time of the source voltage Vs of the (i+2)-th pixel row L(i+2) can be the timing of the turn-off change of the (i+2)-th scan signal SCAN(i+2).

[0075] Because the ripple voltage added to the initialization voltage VpreR during the off-time of the i-th scan signal SCAN(i), the source voltage Vs of the sub-pixel set in the i-th pixel row L(i) may be distorted. Similarly, because the ripple voltage added to the initialization voltage VpreR during the off-time of the (i+1)-th scan signal SCAN(i+1), the source voltage Vs of the sub-pixel set in the (i+2)-th pixel row L(i+2) may be distorted.

[0076] Figure 8 This illustrates an example of how the RC delay of the scan signal varies based on the panel position. Figure 9 The output waveforms of the scan signal are shown with respect to point A, which is relatively close to the input position of the scan signal, and point B, which is relatively far from the input position of the scan signal.

[0077] refer to Figure 8 and Figure 9The RC delay can be smaller at point A, which is relatively close to the input position of the scan signal, and larger at point B, which is relatively far from the input position of the scan signal.

[0078] The RC delay of the scan signal can alter the timing of the turn-off changes of the scan signal applied to the same pixel row. As the RC delay of the scan signal increases, the turn-off timing of the scan signal can be delayed. In the turn-off timing of the scan signal, point B can be later than point A.

[0079] As described above, when the timing of the off-state of the scan signal varies for each scan mode and panel position, the level of the ripple voltage added to the initialization voltage VpreR also changes, which may distort the color and brightness characteristics of the displayed image.

[0080] Figure 10 The connection structure between the sensing circuit, the correction circuit, and the memory according to an embodiment of the present disclosure is shown. Figure 11 The operation sequence of the first sensing sequence for sensing the timing of the off-state change of the scan signal for each scan mode and panel position is shown. Figure 12 The operation sequence for a second sensing sequence used to sense the ripple voltage added to the initial voltage of each sub-pixel at the timing of the off-state change of the scan signal is shown.

[0081] Reference Figure 11 In steps S1 and S2, the sensing circuit SU can execute a first sensing sequence in either a power-on sequence or a power-off sequence. The first sensing sequence senses the off-time OST of the scan signal for each scan mode and panel position. The power-on sequence can be a pre-drive sequence preceding the start of display driving, immediately following the application of system power (AC power). The power-off sequence can be a post-drive sequence preceding the release of system power, immediately following the end of display driving.

[0082] The sensing circuit SU can individually sense the timing of the off-state changes of the scan signal, which varies for each scan mode and panel position, relative to all scan modes and all sub-pixels.

[0083] In step S3, the sensing circuit SU can store the sensing value obtained through the first sensing sequence (i.e., the sensing value of the off-time OST of the scan signal) in the memory MEM.

[0084] refer to Figure 12In steps S11 and S12, the sensing circuit SU can execute a second sensing sequence during the display driving sequence. The second sensing sequence senses the ripple voltage RV added to the initial voltage of each sub-pixel during the timing of the off-state change of the scan signal stored in the memory MEM. The display driving sequence can be set between the power-on sequence and the power-off sequence and can be used for display driving.

[0085] In step S13, the sensing circuit SU can store the sensing value obtained through the second sensing sequence (i.e., the sensing value of the ripple voltage RV added to the initial voltage of each sub-pixel) in the memory MEM.

[0086] refer to Figure 10 and Figure 12 The correction circuit CPC can read the compensation gain Gain corresponding to the ripple voltage RV from a predetermined lookup table. In step S14, the correction circuit CPC can correct the data voltage Vdata to be input to each sub-pixel based on the compensation gain Gain used to compensate for the brightness change caused by the ripple voltage.

[0087] Figures 13 to 15 Used to describe the operation of sub-pixels and sensing circuitry in the first sensing sequence.

[0088] refer to Figure 13 and Figure 14 For the first sensing sequence, the reference voltage line RL connected to the sub-pixel can be connected to a ground voltage GND that is lower than the initialization voltage VpreR via a ground switch SW-GND. The ground switch SW-GND can remain on only during the first sensing sequence and can be off during the second sensing sequence. The initialization voltage VpreR can be approximately 2V to 5V, and the ground voltage GND can be 0V. The ground switch SW-GND can be located in the source driver.

[0089] In the first sensing sequence, the drive current corresponding to the sensing data voltage Vdata-SEN can flow through the drive transistor DT of the sub-pixel. The Vgs setting operation for generating the drive current can be performed during the on-time Ton of the scan signal SCAN.

[0090] Due to the RC delay deviation caused by the panel position, the on-time Ton of the scan signal SCAN cannot be directly sensed. Therefore, the sensing circuit SU can sample the line voltage VRL stored in the line capacitor LC of the reference voltage line RL multiple times during the multi-sampling time Tms.

[0091] Based on the applied drive current, the line voltage VRL of the line capacitor LC can increase from the first inflection point IP1, which corresponds to the on-change timing of the scan signal SCAN applied to the sub-pixel. When the drive current discharges to ground voltage GND, the voltage applied to the connecting resistor Rr can be the line voltage VRL of the line capacitor LC. Since the drive current is cut off, the line voltage VRL can decrease from the second inflection point IP2 and discharge to ground voltage GND, which corresponds to the off-change timing of the scan signal SCAN applied to the sub-pixel. In other words, based on the on-time Ton of the scan signal SCAN, the line voltage VRL of the line capacitor LC can have an inflection point period SON located between the first inflection point IP1 and the second inflection point IP2. Due to the RC delay, the timing of the inflection point period SON can be later than the on-time Ton of the scan signal SCAN.

[0092] The sensing circuit SU can sample the line voltage VRL of the line capacitor LC multiple times during the first sensing sequence to sense the second inflection point IP2, and use it as the timing for the off-state change of the scan signal SCAN applied to the sub-pixel.

[0093] In order to accurately sense the second inflection point IP2, the multi-sampling period Tms for performing multiple sampling operations can be set to be greater than the conduction period Ton of the scan signal SCAN, and overlap with the entire conduction period Ton of the scan signal SCAN.

[0094] Such a first sensing sequence can be executed independently on a sub-pixel basis.

[0095] As the range of the line voltage VRL of the line capacitor LC in SON increases during the inflection point period, the sensing circuit SU can easily sense the second inflection point IP2, therefore... Figure 15 As shown, the first sensing sequence can be executed independently, column by column of pixels. Figure 15 In this process, considering the input position of the scan signal SCAN, a scan signal SCAN with a first amplitude RC delay can be input to a sub-pixel SP located in the first pixel column PC1, and a scan signal SCAN with a second amplitude RC delay greater than the first amplitude can be input to a sub-pixel SP located in the m-th (where m can be a natural number) pixel column PCm. Among the sub-pixels SP included in the same pixel column, the timing of the off-state changes of the scan signal SCAN can be almost equal to each other. Therefore, the first sensing sequence can be executed independently on a pixel column basis by different sensing circuits SU.

[0096] Figure 16 and Figure 17 Used to describe the operation of sub-pixels and sensing circuitry in the second sensing sequence.

[0097] refer to Figure 16 and 17 For the second sensing sequence, the reference voltage line RL connected to the sub-pixel can be connected to the initialization voltage VpreR via the first switch SW1. The ground switch SW-GND can be turned off, thus breaking the connection between the reference voltage line RL and the ground voltage GND.

[0098] In the second sensing sequence, the drive current corresponding to the data voltage Vdata used for display driving can flow through the drive transistor DT of the sub-pixel. The drive current can discharge to the reference voltage line RL, and therefore, the line voltage VRL can be stored in the in-line capacitor LC.

[0099] The line voltage VRL stored in the online capacitor LC can include a ripple voltage, which is added to the initialization voltage VpreR based on the scan overlap drive and the off-time of the scan signal SCAN.

[0100] The sensing circuit SU can sample the line voltage VRL stored in the online capacitor LC during the second sensing sequence, and thus can sense the ripple voltage added to the initialization voltage VpreR.

[0101] The sensing circuit SU can sample the line voltage VRL stored in the online capacitor LC at the time of the off change of the scan signal SCAN applied to the i-th pixel row L(i) to sense the ripple voltage corresponding to the sub-pixel SP(i,j).

[0102] The sensing circuit SU can sample the line voltage VRL stored in the online capacitor LC at the time of the off change of the scan signal SCAN applied to the (i+1)th pixel row L(i+1) to sense the ripple voltage corresponding to the sub-pixel SP(i+1,j).

[0103] Similarly, the sensing circuit SU can sample the line voltage VRL stored in the online capacitor LC at the time of the off change of the scan signal SCAN applied to the (i+2)th pixel row L(i+2) to sense the ripple voltage corresponding to the sub-pixel SP(i+2,j).

[0104] Figure 18 This describes the principle that allows sensing of ripple voltage added to the initialization voltage in a display driver.

[0105] refer to Figure 18 The power supply for the initialization voltage VpreR can be located on the control printed circuit board C-PCB, and the first switch SW1 can be located in the source driver IC S-IC. The sensing circuit SU can be further installed in the source driver IC S-IC.

[0106] The sensing circuit SU can be positioned closer to the display panel than the power supply of the initialization voltage VpreR. Therefore, provided the connection resistor Rx between the control printed circuit board C-PCB and the source driver IC S-IC is sufficiently large, the ripple voltage caused by the scan overlap drive can be sensed when the line voltage stored in the line capacitor LC of the reference voltage line RL is sampled in the on state of the first switch SW1. Figure 18 In this context, Lr can represent the line resistor of the reference voltage line RL, and CC can represent the decoupling capacitor installed on the control printed circuit board (C-PCB). The decoupling capacitor CC can be omitted from the control printed circuit board (C-PCB).

[0107] Figure 19 The ripple voltage levels are shown for brightness and for each scan mode. Figure 20 The compensation gain values ​​for brightness and each scan mode are shown.

[0108] refer to Figure 19 In each of the 60Hz scan mode, 240Hz scan mode, and 480Hz DFR scan mode, the level of the sensed ripple voltage can increase as the brightness of the displayed image increases.

[0109] At the same brightness, the ripple voltage level can be gradually increased in the directions of 60Hz scan mode, 240Hz scan mode and 480Hz DFR scan mode.

[0110] refer to Figure 20 In each of the 60Hz scan mode, 240Hz scan mode, and 480Hz DFR scan mode, the compensation gain used to compensate for brightness variations based on ripple voltage can be increased as the brightness of the displayed image increases.

[0111] At the same brightness, the compensation gain can be gradually increased in the directions of 60Hz scan mode, 240Hz scan mode and 480Hz DFR scan mode.

[0112] The embodiments disclosed herein can achieve the following effects.

[0113] This disclosure can sense the timing of the off-state changes of the scan signal for each scan mode and panel position based on a first sensing sequence, and can sense the ripple voltage added to the initialization voltage of each sub-pixel during the off-state change timing of the scan signal during a second sensing sequence in the display driver. Furthermore, this disclosure can correct the data voltage with a compensation gain corresponding to the ripple voltage to compensate for brightness variations caused by the ripple voltage.

[0114] As described above, this disclosure can compensate for brightness deviations based on panel position that occur at different levels in each scanning mode, and thus can enhance display quality.

[0115] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0116] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. An organic light-emitting display device, comprising: The display panel includes multiple sub-pixels, which are scanned based on a scan signal of one of multiple frequency-variable scan modes. The sensing circuit is configured to sense the timing of a shutdown change of a scan signal for each scan mode and panel position in a first sensing sequence, and during a second sensing sequence independent of the first sensing sequence, sense the ripple voltage of an initialization voltage added to each of the plurality of sub-pixels at the timing of the shutdown change of the scan signal. and The correction circuit is configured to correct the data voltage to be input to each sub-pixel based on a compensation gain used to compensate for brightness variations caused by the ripple voltage.

2. The organic light-emitting display device according to claim 1, wherein, The first sensing sequence is executed in either the power-on sequence or the power-off sequence. The second sensing sequence is executed in the display driving sequence between the power-on sequence and the power-off sequence.

3. The organic light-emitting display device according to claim 1, wherein, In the first sensing sequence, The driving current flows through the driving transistor of the corresponding sub-pixel. The line voltage corresponding to the drive current is stored in the line capacitor of the reference voltage line. The reference voltage line connected to the corresponding sub-pixel is connected to a ground voltage lower than the initialization voltage. Based on the applied drive current, the line voltage of the line capacitor increases from a first inflection point, which corresponds to the on-time of the scan signal applied to the corresponding sub-pixel, and as the drive current is cut off and the line voltage of the line capacitor is discharged to the ground voltage, the line voltage of the line capacitor decreases from a second inflection point, which corresponds to the off-time of the scan signal applied to the corresponding sub-pixel.

4. The organic light-emitting display device according to claim 3, wherein, The sensing circuit samples the line voltage of the line capacitor multiple times during the first sensing sequence to sense the second inflection point, using it as the timing for the off-state change of the scan signal applied to the corresponding sub-pixel.

5. The organic light-emitting display device according to claim 4, wherein, The multiple sampling period of the sensing circuit is longer than the conduction period of the scanning signal and overlaps with the entire conduction period of the scanning signal.

6. The organic light-emitting display device according to claim 1, wherein, Each of the first sensing sequence and the second sensing sequence is executed independently on a sub-pixel basis.

7. The organic light-emitting display device according to claim 1, wherein, The first sensing sequence is executed independently on a per-pixel basis, and the second sensing sequence is executed independently on a per-subpixel basis.

8. The organic light-emitting display device according to claim 1, wherein, In the second sensing sequence, The driving current flows through the driving transistor of the corresponding sub-pixel. The line voltage corresponding to the drive current is stored in the line capacitor of the reference voltage line. At the timing of the off-state change of the scan signal, the ripple voltage is added to the line voltage of the line capacitor.

9. A driving method for an organic light-emitting display device, the organic light-emitting display device comprising a display panel, the display panel comprising a plurality of sub-pixels scanned by a scan signal based on a scan mode of a plurality of frequency-variable scan modes, the driving method comprising: In the first sensing sequence, the timing of the off-state changes of the scanning signal is sensed for each scanning mode and panel position; During a second sensing sequence independent of the first sensing sequence, the ripple voltage of the initial voltage added to each of the plurality of sub-pixels is sensed at the timing of the off change of the scan signal; and The data voltage to be input to each sub-pixel is corrected based on the compensation gain used to compensate for the brightness changes caused by the ripple voltage.

10. The driving method according to claim 9, wherein, The first sensing sequence is executed in either the power-on sequence or the power-off sequence. The second sensing sequence is executed in the display driving sequence between the power-on sequence and the power-off sequence.

11. The driving method according to claim 9, wherein, In the first sensing sequence, The driving current flows through the driving transistor of the corresponding sub-pixel. The line voltage corresponding to the drive current is stored in the line capacitor of the reference voltage line. The reference voltage line connected to the corresponding sub-pixel is connected to a ground voltage lower than the initialization voltage. Based on the applied drive current, the line voltage of the line capacitor increases from a first inflection point, which corresponds to the on-time of the scan signal applied to the corresponding sub-pixel, and as the drive current is cut off and the line voltage of the line capacitor is discharged to the ground voltage, the line voltage of the line capacitor decreases from a second inflection point, which corresponds to the off-time of the scan signal applied to the corresponding sub-pixel.

12. The driving method according to claim 11, wherein, The timing of the off-state change of the scanning signal includes: sampling the line voltage of the line capacitor multiple times during the first sensing sequence to sense the second inflection point, and using it as the timing of the off-state change of the scanning signal applied to the corresponding sub-pixel.

13. The driving method according to claim 12, wherein, The multiple sampling period of the sensing circuit is longer than the conduction period of the scanning signal and overlaps with the entire conduction period of the scanning signal.

14. The driving method according to claim 9, wherein, Each of the first sensing sequence and the second sensing sequence is executed independently on a sub-pixel basis.

15. The driving method according to claim 9, wherein, The first sensing sequence is executed independently on a per-pixel basis, and the second sensing sequence is executed independently on a per-subpixel basis.

16. The driving method according to claim 9, wherein, In the second sensing sequence, The driving current flows through the driving transistor of the corresponding sub-pixel. The line voltage corresponding to the drive current is stored in the line capacitor of the reference voltage line. At the timing of the off-state change of the scan signal, the ripple voltage is added to the line voltage of the line capacitor.

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