A microwave solid-state power amplifier power combining control method and system

Abstract

The present application relates to the field of microwave communication and radar technology, disclose a kind of microwave solid-state power amplifier power synthesis control method and system, the method comprises: obtaining microwave signal to be synthesized and each branch signal and extracting original instantaneous envelope data, its amplitude is smoothed to obtain smooth envelope data sequence;According to its trend fitting, obtain synthesis control characteristics;Obtain each branch initial signal and according to the characteristics, carry out consistency correction processing in time and space dimension, obtain response alignment data;Accordingly, carry out closed-loop parameter iterative optimization processing, generate branch synchronous compensation signal containing distortion evaluation factor;If the factor is over limit, carry out waveform high-precision reconstruction processing to generate high-fidelity signal data;The data is carried out multi-path collaborative dynamic equalization processing to obtain system balance state index, according to adaptive stability control processing, output target synthesis power signal.The present application can realize the dynamic accurate adjustment of power synthesis branch parameter, improve output stability.

Description

Technical Field

[0001] This invention relates to the field of microwave communication and radar technology, and in particular to a method and system for power combining control of microwave solid-state power amplifiers. Background Technology

[0002] Currently, power amplifiers play a crucial role in modern communication and radar systems (such as millimeter-wave radar), directly affecting the stability of signal transmission and the overall system performance. In applications processing radar pulses or complex communication signals, power amplifiers need to maintain efficient and stable power output under varying electromagnetic environments and ensure the consistency of signals from each branch during the synthesis process to cope with dynamically changing signal envelopes.

[0003] In a current technology, a fixed voltage bias control scheme is typically used, where multiple power amplification branches are combined using pre-defined hardware circuitry. First, the input microwave signal is power-divided; second, each independent power amplification branch amplifies the signal; finally, a synthesizer combines the amplified signals in space or through waveguides for output. However, this scheme often struggles to detect real-time dynamic changes in the signal envelope when dealing with complex signal environments and lacks an effective feedback adjustment mechanism. When processing signals with high dynamic range, each branch cannot accurately and in real-time adjust its voltage parameters to match the signal envelope, leading to an imbalance in operating states among the branches, and even causing signal waveform distortion and uneven power distribution.

[0004] In summary, existing technologies suffer from poor power synthesis stability and are prone to signal distortion. Summary of the Invention

[0005] This invention provides a power combining control method and system for microwave solid-state power amplifiers to solve the problems of poor power combining stability and easy signal distortion.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a power combining control method for a microwave solid-state power amplifier, comprising: The microwave signal to be synthesized and the signals of each branch are acquired, and the envelope of the microwave signal to be synthesized is extracted to obtain the original instantaneous envelope data. The original instantaneous envelope data is subjected to amplitude smoothing to obtain a smoothed envelope data sequence; feature fitting is performed on the smoothed envelope data sequence to obtain synthetic control features; Based on the synthetic control characteristics, the spatiotemporal consistency correction process is performed on the signals of each branch to obtain response alignment data; Based on the response alignment data, signal processing delay optimization is performed to obtain a branch synchronization compensation signal containing a distortion evaluation factor; If the distortion evaluation factor of the branch synchronization compensation signal exceeds the preset distortion threshold, the branch synchronization compensation signal is subjected to high-precision waveform reconstruction processing to generate high-fidelity signal data. The high-fidelity signal data is subjected to multi-channel collaborative dynamic equalization processing to obtain a system balance state index; based on the system balance state index, the high-fidelity signal data is subjected to adaptive stability control processing to obtain a target synthetic power signal.

[0007] In a second aspect, the present invention provides a microwave solid-state power amplifier power combining control system, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0008] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention acquires envelope data by combining signal envelope extraction technology with high real-time sampling frequency, and uses wavelet denoising and first-order difference calculation to determine the envelope change rate. This scheme uses high-frequency sampling to capture subtle changes in the signal and uses targeted denoising algorithms to improve the signal-to-noise ratio, thereby realizing automated and high-precision judgment of signal abrupt changes. This not only ensures the smoothness and accuracy of subsequent data processing, but also lays a precise foundation of data support for the system's rapid response under complex dynamic envelopes.

[0009] (2) This invention adjusts the dynamic range of the signal and updates the real-time data stream buffering mechanism through an adaptive algorithm, and combines the least squares method to fit the trend curve to extract the signal change characteristics. This scheme uses the compression or stretching of the dynamic range to ensure the stability of the signal during the buffering process, and deeply analyzes the evolution trend of the signal through polynomial fitting, thereby realizing intelligent assessment and early warning of system operation risks, effectively solving the limitations of existing technologies in the face of uneven power distribution or slow system response when facing dynamic signals.

[0010] (3) This invention optimizes signal processing delay through a real-time stability feedback mechanism and integrates multiple signals synchronously with pulse signal timing calibration and communication signal modulation and demodulation technology. This scheme dynamically adjusts the sampling frequency and compensation coefficient through closed-loop feedback, thereby achieving precise correction of signal waveform distortion and balanced control of phase and power of each branch, which greatly improves the control accuracy of power synthesis and the consistency of the system, ensuring extremely high stability of power synthesis output in complex radar pulse application scenarios such as millimeter waves. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the microwave solid-state power amplifier power synthesis control method provided in the first embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] Reference Figure 1 The first embodiment of the present invention provides a power combining control method for a microwave solid-state power amplifier, comprising the following steps: S11, acquire the microwave signal to be synthesized and the signals of each branch, and perform envelope extraction processing on the microwave signal to be synthesized to obtain the original instantaneous envelope data; S12, the original instantaneous envelope data is subjected to amplitude smoothing processing to obtain a smoothed envelope data sequence; feature fitting processing is performed on the smoothed envelope data sequence to obtain synthetic control features; S13, Based on the synthetic control features, perform spatiotemporal consistency correction processing on the signals of each branch to obtain response alignment data; S14, perform signal processing delay optimization processing based on the response alignment data to obtain a branch synchronization compensation signal containing a distortion evaluation factor; S15, if the distortion evaluation factor of the branch synchronization compensation signal exceeds the preset distortion threshold, then the branch synchronization compensation signal is subjected to high-precision waveform reconstruction processing to generate high-fidelity signal data. S16, perform multi-channel collaborative dynamic equalization processing on the high-fidelity signal data to obtain a system balance state index; based on the system balance state index, perform adaptive stability control processing on the high-fidelity signal data to obtain a target synthesized power signal.

[0014] In step S11, the microwave signal to be synthesized and the signals of each branch are acquired, and the envelope extraction processing is performed on the microwave signal to be synthesized to obtain the original instantaneous envelope data, including: Perform a fast Fourier transform on the microwave signal to be synthesized to obtain a single-sided frequency spectrum that includes the positive frequency component; The positive frequency portion of the single-sided frequency domain spectrum is subjected to a multiplication mapping process to obtain a single-sided weighted spectrum. Perform an inverse Fourier transform on the single-sided weighted spectrum to obtain the corresponding analytical signal, and analyze the analytical signal to obtain the original instantaneous envelope data.

[0015] In this embodiment, the microwave signal to be synthesized refers to a multi-channel analog alternating microwave signal source with high dynamic range modulation characteristics, input from a microstrip transmission line or a space metal waveguide at the RF front end. Each branch signal refers to a real-time electrical signal characterizing the channel response state, fed back from the end of each power amplification channel in the microwave solid-state power amplifier. The microwave signal to be synthesized and each branch signal are acquired by directional couplers deployed at the total input of the power amplification system and the output of each single-stage power amplification branch. The high-frequency alternating electromagnetic field energy is sampled and shunted according to a preset coupling degree and input to a parallel high-speed data acquisition card. The preset coupling degree is determined by an engineering calibration method, i.e., by acquiring the rated power peak of the microwave signal to be synthesized and adjusting the coupling coefficient stepwise under a passive network test environment. When the coupling degree is set to -20 dB, the power of the shunted sampled signal falls exactly within the optimal linear dynamic range of the analog-to-digital converter built into the high-speed data acquisition card, and the power shunting loss of the total transmission line is less than 0.05 dB. Therefore, the preset coupling degree is calibrated to be -20 dB.

[0016] A Fast Fourier Transform (FFT) is performed on the microwave signal to be synthesized to obtain a single-sided frequency domain spectrum containing the positive frequency component. Specifically, a high-speed multi-channel data acquisition card performs synchronous discrete analog-to-digital conversion on the input microwave signal to be synthesized, extracting a frame of discrete digital time-domain sequence from the local high-speed buffer. The number of sampling points in the frame of discrete digital time-domain sequence is set to 1024. In this embodiment, the radix-2 Fast Fourier Transform algorithm is used to project the 1024-point time-domain voltage sequence from the time dimension to the frequency domain, outputting a discrete spectrum sequence composed of 1024 complex elements. Since the Fourier spectrum of the physical real signal has complex conjugate symmetry on the positive and negative frequency axes, this embodiment traverses the discrete spectrum sequence and extracts only the 511 positive frequency discrete complex spectrum components with frequency index values ​​greater than zero and less than 512, thereby obtaining a single-sided frequency domain spectrum containing the positive frequency component.

[0017] The positive frequency portion of the single-sided frequency spectrum is subjected to a multiplication mapping process to obtain a single-sided weighted spectrum. The physical essence of the multiplication mapping process is to maintain the total energy of the signal while eliminating negative frequency components. In specific implementation, the system uses a digital multiplier to multiply the real and imaginary values ​​of the 511 positive frequency complex spectral lines with frequency indices from 1 to 511 in the single-sided frequency spectrum containing the positive frequency portion by two respectively; at the same time, the complex amplitudes of the DC component with a frequency index of 0 and the Nyquist frequency component with a frequency index of 512 are kept fixed and not doubled; finally, the complex amplitudes of the 511 negative frequency points with frequency indices from 513 to 1023 in the full-frequency axis are all forcibly reset to zero; after completing the above amplitude reshaping and symmetry suppression, a single-sided weighted spectrum with 1024 complete physical frequency domain boundaries is reassembled and spliced ​​on the full-frequency axis.

[0018] The inverse Fourier transform is performed on the single-sided weighted spectrum to obtain the corresponding analytic signal. The analytic signal is then analyzed to obtain the original instantaneous envelope data. In this embodiment, the 1024-point single-sided weighted spectrum is input into the inverse fast Fourier transform module, and an inverse radix-2 fast Fourier transform is performed to remap the complex sequence in the frequency domain back to the time domain, outputting a 1024-point time-domain complex sequence containing two channels of real and two channels of imaginary parts, i.e., the corresponding analytic signal. Analyzing the analytic signal refers to extracting the instantaneous energy envelope of the complex sequence. In specific implementation, the system uses pipelined multipliers and adders to sequentially traverse the 1024-point complex number sequence, calculating the square of the real part and the square of the imaginary part of the complex number at each sampling moment, and summing the square of the real part and the square of the imaginary part to obtain the energy sum. Then, the arithmetic square root of the energy sum is calculated using a successive approximation square root algorithm, thereby determining the instantaneous amplitude value at that sampling moment. The 1024-point discrete real voltage sequence formed by sequentially arranging the instantaneous amplitude values ​​on the time axis is the original instantaneous envelope data, and its physical dimension is unified in volts.

[0019] It should be noted that the real-time data sampling frequency of the high-speed multi-channel data acquisition card in this embodiment is objectively determined through a performance-driven method. First, the highest operating frequency of the microwave signal to be synthesized under specific millimeter-wave radar pulse modulation conditions is measured using an acoustic and microwave spectrum analyzer, and this highest operating frequency is multiplied by 2.5. For example, when the highest operating frequency of the microwave signal to be synthesized is 4GHz, 10GHz is calculated using the formula. 10GHz is used as the critical lower limit value of the real-time data sampling frequency to reserve a 25% attenuation edge for the transition band of the hardware anti-aliasing filter, while satisfying the Nyquist sampling theorem, thereby completely eliminating the risk of spectral aliasing caused by high-frequency sidelobes in the underlying hardware link.

[0020] It is worth noting that the number of sampling points for the Fast Fourier Transform (FFT) was determined as the performance inflection point through offline simulation. Specifically, a microwave synthesis control simulation model was established within the central processing unit (CPU). A typical microwave signal stream containing high-order harmonics and multi-source noise was input. Under the constraint of a reference microsecond-level clock, the above analytical process was executed with iteration frame lengths of 256, 512, 1024, and 2048 points, respectively. The computational cost and envelope reconstruction residuals for different point numbers were statistically analyzed. Experimental data show that as the number of points increases from 256 to 1024, the reconstruction residual decreases by more than 85%. When the number of points continues to increase from 1024 to 2048, the improvement rate of the reconstruction residual curve is less than 3%, entering the convergence plateau region. However, the computational cost exhibits a nonlinear logarithmic surge, exceeding the real-time response safety boundary for microsecond-level phase-locked loop synthesis of solid-state power amplifiers. Therefore, the comprehensive performance inflection point of 1024 points was selected as the standard sampling point number for the FFT.

[0021] In step S12, the original instantaneous envelope data is subjected to amplitude smoothing to obtain a smoothed envelope data sequence; feature fitting is performed on the smoothed envelope data sequence to obtain synthetic control features.

[0022] The original instantaneous envelope data is subjected to amplitude smoothing processing to obtain a smoothed envelope data sequence, including: Wavelet denoising is performed on the original instantaneous envelope data to obtain a five-level hierarchical decomposition matrix, and high-frequency coefficient soft thresholding is performed on the five-level hierarchical decomposition matrix to obtain high-frequency noise components and low-frequency components. The high-frequency noise component is subjected to noise suppression processing to obtain the updated high-frequency component; The low-frequency component is superimposed and reconstructed with the updated high-frequency component to obtain a smooth envelope data sequence.

[0023] In this embodiment, the original instantaneous envelope data refers to the discrete real amplitude sequence with 1024 sampled voltage values ​​output in step S11. Wavelet denoising is performed on the original instantaneous envelope data to obtain a five-level hierarchical decomposition matrix. High-frequency coefficients are then subjected to soft thresholding based on the five-level hierarchical decomposition matrix to obtain high-frequency noise components and low-frequency components. Specifically, this embodiment selects a multi-scale analysis wavelet basis function with good compact support and orthogonality, namely the Db4 wavelet in the Daubechies wavelet basis function. The system uses a discrete wavelet transform filter bank to downsample the 1024-point original instantaneous envelope data by half through alternating orthogonal high-pass and low-pass filters. This decomposition process is iterated five times consecutively at the bottom layer of the algorithm, thereby constructing a discrete wavelet coefficient set containing a five-level frequency band decomposition structure, i.e., a five-level hierarchical decomposition matrix. The first five rows of the five-level hierarchical decomposition matrix correspond sequentially to the detail coefficients of the five frequency bands from high frequency to low frequency, and the sixth row corresponds to the approximation coefficients of the fifth level.

[0024] The process of performing high-frequency coefficient soft thresholding refers to the system calling a digital signal processor to perform nonlinear mapping and numerical reduction on the first five rows of detail coefficients in the five-level hierarchical decomposition matrix. Specifically, the system first extracts the absolute values ​​of all detail coefficients from the first to the fifth level, and then calculates the soft threshold specific to each frequency band level using a preset threshold generation method. Specifically, when the absolute value of a detail coefficient in a certain level is less than or equal to the soft threshold specific to that level, the system forcibly resets the coefficient value at that node to 0 using a zeroer; when the absolute value of a detail coefficient in a certain level is greater than the soft threshold specific to that level, the system keeps its original positive or negative sign unchanged, subtracts the soft threshold specific to that level from its absolute value, and uses this difference as the updated coefficient value. After completing the above global nonlinear transformation, all the zeroed-out and amplitude-reduced detail coefficients together constitute the high-frequency noise component in the time-frequency space; while the sixth row of fifth-level approximation coefficients, which did not participate in threshold reduction, are directly output as low-frequency components.

[0025] The high-frequency noise components are subjected to noise suppression processing to obtain updated high-frequency components. The core of noise suppression processing is to further converge the dynamic hardware response error between channels. In specific implementation, the system adopts a fixed coefficient scaling method, using a hardware-level multiplier to multiply the first to fifth layer detail coefficients, which have already undergone soft thresholding, by the corresponding suppression weight factor. In this embodiment, the suppression weight factor is uniformly set to 0.85. The system attenuates the residual high-frequency fluctuation energy of the microwave channels and encapsulates the scaled and adjusted coefficient combination into the updated high-frequency components. The low-frequency components and the updated high-frequency components are superimposed and reconstructed to obtain a smooth envelope data sequence. Specifically, the system simultaneously feeds the fifth-layer approximation coefficients (which serve as low-frequency components) and the five-layer fine detail coefficients (which serve as updated high-frequency components) into the inverse discrete wavelet transform reconstruction filter bank. The reconstruction filter bank strictly follows the reverse timing logic of the decomposition, performing upsampling and mirror filtering reconstruction layer by layer starting from the highest decomposition level, remapping the coefficient values ​​in the time-frequency space back to the physical time domain, and finally superimposing and synthesizing to output a 1024-point discrete real number sequence in the time domain that eliminates high-frequency spike interference and completely encapsulates the signal change trend information, i.e., a smooth envelope data sequence, whose physical dimension remains unchanged in volts.

[0026] It should be noted that the selection of the Db4 wavelet and the setting of five decomposition layers in this embodiment were objectively determined through a performance-driven method. In a microwave solid-state amplifier multi-channel synthesis control simulation environment, time-domain envelope samples containing high-order RF parasitic oscillations were injected offline. Haar wavelet, Sym4 wavelet, Db2 wavelet, Db4 wavelet, and Db6 wavelet were used as basis functions, and three-, four-, five-, six-, and seven-layer decomposition structures were established for denoising calibration. The system calculated the signal-to-noise ratio improvement and root mean square error of the denoised output signal and found that when using the Db4 wavelet in conjunction with five-layer decomposition, the reconstructed waveform exhibited the highest smoothness at thermal noise levels, and the retention rate of abrupt changes at the waveform's leading edge was better than 98%. When the number of decomposition layers continues to increase to six or seven layers, the overall improvement in signal-to-noise ratio is less than 0.5%, but the number of multiply-accumulate operations of the reconstruction filter shows a non-linear exponential surge, and the entire process takes more than 10 microseconds, which seriously exceeds the real-time response safety boundary of the power amplifier's microsecond-level phase-locked synthesis. In this embodiment, the number of decomposition layers is objectively set to five layers.

[0027] It is worth noting that the soft thresholds specific to each layer of detail coefficients are objectively determined through a combination of the global threshold principle in statistical analysis and hierarchical noise estimation. The system first extracts the first-layer detail coefficients representing the highest frequency band from the five-layer hierarchical decomposition matrix and calculates the median of the absolute values ​​of all coefficients in that row. Since the first-layer high-frequency coefficients are physically dominated by high-frequency white noise, the system uses a statistical relationship to divide this median by a constant 0.6745, using this quotient as an estimate of the standard deviation of white noise in the original instantaneous envelope data. Subsequently, the system performs a comprehensive decision factor calculation based on the currently captured frame length of 1024 points, calculating the square root of the natural logarithm of 2 multiplied by 1024, obtaining a fixed value of 3.723 for the decision factor. The system then multiplies this standard deviation estimate by 3.723 to calculate the standard global threshold. In order to adapt to the inherent physical characteristic that the noise spectral density energy of high-frequency microwave signals decreases logarithmically as the frequency increases, the system uses cascaded attenuation to objectively calibrate the exclusive soft thresholds of the first to fifth layers to 1.0 times, 0.85 times, 0.72 times, 0.61 times and 0.52 times the standard global threshold, respectively, so that the threshold boundary is completely matched with the physical distribution of random noise in the microwave channel.

[0028] The process of performing feature fitting based on the smoothed envelope data sequence to obtain synthetic control features includes: The real-time rate of change is obtained by performing a first-order difference calculation on the smoothed envelope data sequence. If the real-time change rate exceeds a preset change threshold, the smooth envelope data sequence is subjected to amplitude logarithmic transformation compression to obtain a dynamically adjusted sequence. The dynamic adjustment sequence is subjected to cubic polynomial fitting to obtain the trend feature slope; The real-time rate of change and the slope of the trend feature are concatenated to obtain the synthetic control feature.

[0029] In this embodiment, the smooth envelope data sequence refers to the 1024-point time-domain discrete voltage waveform sequence output from step S12, after wavelet denoising and reconstruction. First-order difference calculation is performed on the smooth envelope data sequence to obtain the real-time rate of change input stream. Specifically, the system calls the digital signal processor to sequentially traverse the 1024-point smooth envelope data sequence, using a hardware subtractor to subtract the voltage sample value from the previous time step from the current voltage sample value on the time axis, obtaining the net voltage change value between adjacent sample points. Subsequently, a hardware divider is used to divide the net voltage change value by a fixed sampling time interval. In this embodiment, this sampling time interval is 0.1 nanoseconds corresponding to a 10GHz sampling frequency. Through this operation, the system obtains a real number sequence consisting of 1023 sequentially arranged difference values ​​on the entire time axis, i.e., the real-time rate of change, with its physical dimension unified as volts per nanosecond, used to accurately quantify the instantaneous abrupt changes in the amplitude of the envelope signal.

[0030] If the real-time change rate exceeds a preset change threshold, the smooth envelope data sequence undergoes an amplitude logarithmic transformation compression process to obtain a dynamically adjusted sequence. The system uses a cascaded comparator to scan and compare the absolute value of each node in the calculated real-time change rate with the preset change threshold one by one. When the absolute value of the real-time change rate within a certain continuous time interval is detected to be greater than the preset change threshold, it is determined that the signal envelope has entered a nonlinear abrupt change period (such as a forward jump at the leading edge of a radar pulse). To prevent high-dynamic signals with large amplitudes from directly entering the fitting module, causing numerical overflow or matrix inverse operation divergence, the system utilizes an adaptive amplitude adjustment mechanism. It calls the logarithmic calculation unit to perform a natural logarithmic transformation on the smooth envelope data sequence corresponding to a 50-nanosecond time window intercepted within the abrupt change period, performing nonlinear compression mapping on its high dynamic range voltage amplitude, thereby generating a discrete sequence with a smooth waveform amplitude and values ​​within a stable and calculable range—the dynamically adjusted sequence.

[0031] It should be noted that if the absolute value of the real-time rate of change is less than or equal to the preset change threshold, the signal envelope is determined to be in a steady-state smoothing period. The system automatically skips the logarithmic transformation compression process and directly outputs the smoothed envelope data sequence corresponding to the original 50 nanosecond time window as the dynamic adjustment sequence, thereby reducing the power consumption and computational overhead of the microprocessor. The dynamic adjustment sequence is then subjected to cubic polynomial fitting to obtain the trend characteristic slope. In this embodiment, the polynomial fitting process involves constructing a cubic polynomial mathematical function model on the time independent variable axis corresponding to the 50 nanosecond sliding window using the least squares method, with the dynamic adjustment sequence as the dependent variable as the time independent variable. Specifically, the system transposes the time matrix of the independent variable within the window and performs self-multiplication to generate a complete VanderMein coefficient matrix. Subsequently, a hardware-level homogeneous linear equation solver is used to perform matrix inversion and vector multiplication to calculate the four core coefficients corresponding to the cubic polynomial: the cubic coefficient, the quadratic coefficient, the linear coefficient, and the constant coefficient.

[0032] Finally, the system performs a first-order derivative operation on the constructed cubic polynomial function at the end time node of the sliding window. The instantaneous derivative value at the current time slice obtained by the derivative is defined as the trend feature slope, with its physical dimension being volts per second, used to characterize the evolution of the macroscopic trend. The real-time rate of change and the trend feature slope are concatenated to obtain the synthetic control feature. In specific implementation, the system uses a linear memory address concatenation instruction to combine the discrete real-time rate of change scalar value and the trend feature slope scalar value corresponding to the index at the same time moment, encapsulating them into a dual-channel high-dimensional feature vector, i.e., the synthetic control feature. This feature vector retains the sensitivity of the microscopic first-order difference and incorporates the trend predictiveness of macroscopic curve fitting, perfectly serving as the feature driving source for the dynamic adjustment of power synthesis parameters.

[0033] It should be noted that the truncation window length and cubic equation structure used in this embodiment for polynomial fitting were determined through offline simulation to identify performance inflection points. In a multi-channel solid-state power amplifier simulation test platform, complex-mode modulated microwave signals containing various high-order nonlinear distortions were injected. The fitting polynomials were set to first, second, third, and fourth order equations, and the sliding window lengths were set to 10 nanoseconds, 20 nanoseconds, 50 nanoseconds, and 100 nanoseconds for curve fitting skin topology experiments. By statistically analyzing the fitting residuals and matrix inverse calculation time under different parameter combinations, the system found that when using a cubic polynomial structure with a 50 nanosecond window length, the residual value of the fitted curve was less than 0.01 volts, and the curve approximation accuracy exceeded 97%. When the fourth-order polynomial was increased, the accuracy improvement rate was less than 0.8%, the computational overhead of regularized matrix inversion increased exponentially, and the processing delay exceeded 15 microseconds, exceeding the safe time boundary of the solid-state power amplifier's phased-loop control. Therefore, this embodiment objectively calibrates using cubic polynomial fitting, and the window length is locked at 50 nanoseconds.

[0034] It is worth noting that the preset change threshold is objectively determined using the percentile method in statistical analysis. First, under normal ignition and stable operation of the microwave amplifier, a smooth envelope data sequence is continuously captured over 48 hours, and its first-order difference value is calculated point by point. The system statistically analyzes the probability density distribution of the absolute values ​​of all difference values ​​within these 48 hours and extracts the difference slope value corresponding to the 95th percentile of this cumulative probability distribution. In this embodiment, this value is objectively fixed at 0.05 volts per nanosecond after statistical calculation. Since differential jumps exceeding this percentile naturally correspond to nonlinear abrupt changes in the signal envelope, using 0.05 volts per nanosecond as the preset change threshold perfectly achieves intelligent decoupling and accurate identification of steady-state and abrupt signals at the hardware level.

[0035] In step S13, based on the synthetic control characteristics, spatiotemporal consistency correction processing is performed on the signals of each branch to obtain response alignment data, including: Analyze the synthetic control characteristics to determine the response time difference between the signals of each branch; Based on the response time difference, nonlinear time-axis stretching is performed on each branch signal to obtain response alignment data.

[0036] In this embodiment, the synthetic control feature refers to the dual-channel feature vector output in step S12, which highly integrates the real-time change rate of the envelope and the slope of the macroscopic trend feature at each time node. Each branch signal refers to the time-domain analog electrical signal fed back from each power amplification physical channel in the microwave solid-state power amplifier. The synthetic control feature is analyzed to determine the response time difference between each branch signal. Specifically, this analysis operation is implemented at the underlying level through cross-correlation delay estimation combined with feature weighted mapping. First, the system calls the digital signal processor within the current frame to extract the synthetic control feature corresponding to a preset reference channel, and sequentially extracts the synthetic control features corresponding to other physical channels to be corrected. Subsequently, the system uses the feature vector of the reference channel as a template to calculate the generalized cross-correlation function between the feature vector of each physical channel to be corrected and the template.

[0037] To improve the accuracy of delay identification during nonlinear abrupt changes, the system utilizes a digital multiplier in memory to square the real-time change rate at each sampling point, generating a corresponding time-varying weight sequence. This weight sequence is then sequentially assigned to the integration kernel of the corresponding cross-correlation multiplication term using matrix dot multiplication, serving as a weighting factor introduced into the integration kernel of the cross-correlation function. By identifying the peak point of the weighted cross-correlation function output curve, the system pinpoints the relative offset steps of the peak point from the zero-delay center. Finally, the system uses a digital divider to divide this relative offset step number by the 10GHz sampling frequency of the data acquisition card, thereby accurately calculating the absolute time delay of each physical channel relative to the reference channel, i.e., the response time difference, with its physical dimension unified in nanoseconds.

[0038] Based on the response time difference, time-axis nonlinear stretching is performed on the signals of each branch to obtain response alignment data. Specifically, the "time-axis nonlinear stretching" operation is implemented through a dynamic time warping algorithm combined with a cubic spline interpolation filter bank to correct the non-uniform time delay caused by high-order thermal nonlinearity within the channel; the dynamic time warping algorithm uses Itakura parallelogram constraints. In specific implementation, the system establishes a bidirectional mapped spatiotemporal alignment matrix in local memory based on the calculated response time difference of each channel. Due to the time-varying nonlinearity caused by thermal accumulation during microwave power amplification, the stretching operation does not use a simple overall time translation, but dynamically adjusts the interpolation step size coefficient according to the instantaneous change trend of the trend feature slope in the synthetic control feature. During periods with a large trend feature slope, indicating that the signal waveform is in a high-speed abrupt change period, the system reduces the interpolation step size and calls the cubic spline interpolation algorithm to insert more digital virtual nodes between two adjacent physical sampling points; during periods with a small trend feature slope and a smooth waveform, the system increases the interpolation step size proportionally. After completing the non-uniform interpolation, the system performs non-uniform resampling of the discrete digital sequences of each channel according to the non-linear time axis trajectory of the spatiotemporal alignment matrix, thereby adjusting the electrical signal waveforms of all amplified branches to a completely overlapping alignment state on the physical time axis, and finally generating matrix data composed of multiple time-aligned digital sequences, i.e., response alignment data.

[0039] It should be noted that the reference channel used for delay calculation in this embodiment is objectively determined through a performance-driven method. Specifically, during the system initialization ignition phase, the control core synchronously injects a reference calibration signal with a consistent pulse kurtosis into all power amplification physical channels. The system calls a high-speed acquisition card to synchronously capture the feedback waveforms at the output of each amplification channel and uses a high-precision time-to-digital converter to measure the absolute physical transmission delay of each channel from signal injection to waveform output. The system calculates the arithmetic mean of the absolute physical transmission delays of all channels and selects the physical channel whose physical transmission delay is closest to this arithmetic mean, locking it as the global reference channel. This channel serves as the reference template for subsequent cross-correlation calculations.

[0040] It is worth noting that the nonlinear mapping curve of the real-time change rate weighting factor introduced into the cross-correlation integral kernel was determined through offline simulation to identify the performance inflection point. The specific construction and comparison process involves injecting a microwave envelope sequence containing multiple independent random group delay perturbations into the digital signal generator simulation model. Different mapping functions, such as linear weighting, square weighting, exponential weighting, and logarithmic weighting, are established to dynamically weight the cross-correlation calculation. The delay identification error rate and algorithm iteration convergence time under each weighting scheme are statistically analyzed within the central processing unit. Experimental data shows that when using the square weighting function, the system achieves a recognition resolution of up to 98.5% for nanosecond-level small group delays, and the convergence speed of the cross-correlation matrix multiplication and addition operation is the fastest. When further increased to the exponential weighting function, the recognition resolution improves by less than 0.2%, but because the exponential operation occupies a large number of hardware floating-point units, the calculation time drastically increases from 3 microseconds to 18 microseconds, severely breaking the real-time technical barrier of solid-state power amplifier phase-locked loop synthesis. Therefore, this embodiment objectively calibrates the use of the square weighting function as the weighting mapping standard for the real-time change rate.

[0041] In step S14, signal processing delay optimization is performed based on the response alignment data to obtain a branch synchronization compensation signal containing a distortion evaluation factor, including: The processing delay time for generating the response alignment data is monitored. If the processing delay time is greater than a preset delay tolerance threshold, the response alignment data is thinned to obtain optimized delay data. Perform frequency domain analysis on the optimized delay data to obtain the distortion frequency components and amplitude deviation. Calculate the distortion assessment factor based on the amplitude deviation; Based on the distortion frequency component and the distortion evaluation factor, the optimized delay data is subjected to complex weighted compensation to generate a branch synchronization compensation signal containing the distortion evaluation factor.

[0042] In this embodiment, the response alignment data refers to the 1024-point multi-channel digital discrete sequence matrix output in step S13, which achieves multi-channel waveform overlap after nonlinear regularization and stretching on the time axis. The processing delay time for generating the response alignment data is monitored. If the processing delay time exceeds a preset delay tolerance threshold, the response alignment data is thinned to obtain optimized delay data. Specifically, the system calls the high-precision hardware timer counter built into the digital signal processor. An interrupt is triggered and timing begins the instant the time axis correction program in step S13 starts, and counting stops the instant the response alignment data is generated and written to the high-speed cache. The system multiplies the total number of clock pulses between the two points by the processor's base clock cycle to calculate the actual time consumption of the current frame, i.e., the processing delay time, with its physical dimension unified in nanoseconds.

[0043] Subsequently, the system inputs the processing delay time into a cascaded comparator and performs a global scan comparison with a preset delay tolerance threshold. When the processing delay time is detected to be greater than the preset delay tolerance threshold, it is determined that the digital processing link has experienced hardware overload. The system immediately initiates downsampling adaptive control logic to perform thinning processing on the current 1024-point response aligned data. According to a preset thinning step size factor (e.g., set to two), one sample value is removed from every one sample point in the full time domain sequence, thereby forcibly compressing the entire frame data length to 512 points. By significantly reducing the hardware data throughput of subsequent frequency domain analysis, the system forces the computational bottleneck to converge within a safe time boundary, and the output data is the optimized delay data.

[0044] It should be noted that if the detected processing delay time is less than or equal to the preset delay tolerance threshold, and the current hardware computing power is deemed sufficient, the system automatically skips the thinning process and directly outputs the original 1024-point response aligned data as the optimized delay data, maintaining the highest density signal fidelity. Frequency domain analysis is performed on the optimized delay data to obtain the distortion frequency component and amplitude deviation. Specifically, the system performs a radix-2 fast Fourier transform on the 512-point optimized delay data, projecting its time-domain amplitude sequence to the frequency domain and outputting a 512-point complex amplitude-frequency characteristic distribution map. The system uses a peak search algorithm to traverse the entire frequency spectrum, identifying the highest spectral line feature point with abnormally elevated energy amplitude outside the preset fundamental frequency, and defining its corresponding physical frequency value as the distortion frequency component; the preset fundamental frequency is determined by the center frequency of the microwave signal to be synthesized, obtained through spectrum analysis, and is set to 4GHz in this embodiment. Meanwhile, the system uses a hardware subtractor to subtract the preset standard waveform design amplitude corresponding to the frequency point from the actual complex modulus value at the distorted frequency component, and obtains the absolute amplitude difference between the two, that is, the amplitude deviation, whose physical dimension is unified in volts; the preset standard waveform design amplitude is obtained by injecting a pure sine fundamental signal into the lossless ideal amplification link and measuring its frequency domain amplitude-frequency characteristics as a standard template.

[0045] The distortion evaluation factor is calculated based on the amplitude deviation. Specifically, the system calls the arithmetic unit and uses a hardware divider to divide the amplitude deviation (numerator) by a preset root mean square value of the total energy of the fundamental standard waveform (RMS). To give this dimensionless deviation index a higher nonlinear convergence gradient, the system squares the quotient, thus outputting a scalar index characterizing the severity of nonlinear distortion in the channel waveform, i.e., the distortion evaluation factor. The preset RMS value of the total energy of the fundamental standard waveform is obtained by inputting a standard distortion-free test signal during the system calibration phase and calculating its RMS energy at the fundamental frequency.

[0046] Based on the distorted frequency components and the distorted evaluation factor, the optimized delay data is subjected to complex weighted compensation to generate a branch synchronization compensation signal containing the distorted evaluation factor. Specifically, the system first calculates the corresponding anti-phase compensation phase angle in the time-frequency coordinate system based on the distorted frequency components. Then, using a complex multiplier, the distorted evaluation factor is used as an amplitude weighting coefficient, and Euler's formula is expanded with the anti-phase compensation phase angle. That is, the amplitude is multiplied by a cosine term to obtain the real part, and the amplitude is multiplied by a sine term to obtain the imaginary part, constructing a complex control weight with both real and imaginary parts. Finally, the system performs a matrix multiplication operation on this complex control weight and the optimized delay data. This operation performs nonlinear dynamic gain adjustment and phase lead compensation at each sampling point of each signal in the time domain, ultimately encapsulating and producing a branch synchronization compensation signal with feedforward anti-distortion characteristics.

[0047] It should be noted that the preset delay tolerance threshold described in this embodiment is objectively determined through engineering calibration, specifically by manually injecting and calculating the delay in steps while the microwave solid-state power amplifier and radar antenna array are being integrated. The system monitors the transmit coherence of the RF synthesizer under different delays. When the processing delay reaches 10 microseconds, the spatial beamforming efficiency of the phased array begins to drop; when it exceeds 12 microseconds, severe phase tearing occurs in multiple signals. The system selects the critical performance point of 10 microseconds for system instability as the preset delay tolerance threshold, thereby building an absolutely secure timing protection wall at the hardware level.

[0048] It is worth noting that the thinning step size factor used in the thinning process was determined as a performance inflection point through offline simulation. A multi-channel nonlinear amplification simulation model was established in the central processing unit, and adaptive downsampling comparison experiments were conducted with thinning step sizes of 2, 4, 8, and 16, respectively. The delay reduction improvement rate and residual distortion waveform reconstruction error under different thinning intensities were statistically analyzed. Experimental data show that when the thinning step size factor is set to 2, the overhead of the subsequent frequency domain Fourier transform is reduced by more than 50%, the processing delay directly converges to 9 microseconds, and the waveform reconstruction error is less than 1.5%. When the thinning step size factor is further increased to 4 or 8, severe Nyquist frequency aliasing occurs due to the excessively low spatial sampling density, causing the waveform distortion identification error to exceed 15%, rendering the feedforward compensation mechanism completely ineffective. Therefore, this embodiment objectively locks the thinning step size factor at 2.

[0049] In step S15, if the distortion evaluation factor of the branch synchronization compensation signal exceeds a preset distortion threshold, then the branch synchronization compensation signal undergoes high-precision waveform reconstruction processing to generate high-fidelity signal data, including: Calculate the corresponding timing offset based on the distortion evaluation factor in the branch synchronization compensation signal; The branch synchronization compensation signal is reconstructed and aligned based on the physical time axis according to the time offset to obtain the time calibration signal; The timing calibration signal is subjected to residual electromagnetic noise suppression processing to generate high-fidelity signal data.

[0050] In this embodiment, the branch synchronization compensation signal refers to the 512-point complex discrete signal sequence matrix output in step S14, which has undergone delay thinning optimization and frequency domain complex weighted compensation. The corresponding timing offset is calculated based on the distortion evaluation factor in the branch synchronization compensation signal. Specifically, the system uses a high-speed hardware multiplier to multiply the scalar value of the distortion evaluation factor, representing the severity of waveform nonlinear distortion, by a preset time window scaling factor. Subsequently, the system uses a hardware adder to add the product result to the inherent hardware group delay constant determined by the inherent microstrip line length differences of each power amplification physical channel of the current microwave solid-state power amplifier. Through this combined linear and nonlinear operation, the system dynamically calculates the absolute value of the waveform leading-edge timing offset caused by nonlinear distortion in the current time slice, i.e., the timing offset, whose physical dimension is uniformly nanoseconds.

[0051] The branch synchronization compensation signal is reconstructed and aligned based on the physical time axis according to the timing offset to obtain a timing calibration signal. Specifically, the "reconstruction and alignment based on the physical time axis" is implemented at the underlying level through high-speed clock phase fine-tuning technology combined with a digital fractional extension filter matrix. In specific implementation, the system converts the calculated timing offset into a hard sampling phase control word of the digital-to-analog converter module and the digital signal processor. Since the timing offset is usually a time deviation at the nanosecond level, it cannot be simply shifted by an integer number of standard clock cycles. The system adopts a fractional byte delay adjustment mechanism to calculate the non-integer multiple residual of the timing offset corresponding to the standard sampling period. Subsequently, the system dynamically loads a set of preset Lagrange fractional time delay interpolation filters to perform spatial reference reprojection on the time-domain discrete point matrix of the branch synchronization compensation signal, and forces amplitude centerline normalization and reconstruction on the physical time axis; the order of the Lagrange fractional time delay interpolation filter is 5th order. By filling in or reducing the non-integer multiple of the time residual, the pulse start point offset of the waveform is strictly tightened, thereby achieving absolute alignment of the waveform pulse edges on the full-channel digital clock chain. The output time-domain continuous digital sequence is the timing calibration signal.

[0052] The timing calibration signal undergoes residual electromagnetic noise suppression processing to generate high-fidelity signal data. Specifically, the system invokes a cascaded adaptive digital filter. First, the timing calibration signal is sliced ​​using a discrete window function, and the power spectral density distribution of the signal within the slice window is statistically analyzed in real time using a hardware computing unit. The system adaptively updates the cutoff frequency control point of the filter, dynamically aligning it to the physical boundary frequency where the current signal's cumulative energy accounts for 95%. Subsequently, the system uses this optimal cutoff frequency to perform a dual-threshold hard-threshold low-pass filter operation on the timing calibration signal, forcibly filtering out residual high-frequency electromagnetic spurious components caused by multipath electromagnetic reflection, high-frequency sidelobe aliasing, and radio frequency parasitic oscillations, while completely retaining the fundamental wave and low-order core modulation components below this cutoff frequency. After this selective purification in the spatial and energy domains, the system finally outputs a 512-point high-fidelity signal data segment with high signal-to-noise ratio recovery at the waveform leading edge, and its physical dimension remains unchanged at volts.

[0053] It should be noted that the inherent hardware group delay constant and the preset time window scaling factor used to calculate the timing offset in this embodiment are objectively determined through engineering calibration. During the hardware assembly and calibration stage of the microwave solid-state power amplifier, the feedforward compensation logic of the algorithm is turned off. The physical input-output time difference of each channel under the injection of a distortion-free pure microwave signal is measured using a picosecond-level high-precision oscilloscope. The arithmetic mean of the time differences of all channels is calculated, and this arithmetic mean is objectively calibrated as the inherent hardware group delay constant. In this embodiment, this value is fixed at 0.0012 nanoseconds. At the same time, the distortion evaluation factor of the signal is stepped up under different power load conditions. The change in the pulse along the actual timing offset is statistically analyzed. The slope relationship between the distortion evaluation factor and the timing offset increment is fitted using least squares regression, and this slope value is objectively calibrated as the preset time window scaling factor.

[0054] It is worth noting that the preset distortion threshold for determining whether to trigger high-precision waveform reconstruction processing is objectively determined through a performance-driven method. On a phased array spatial synthesis physical simulation platform, microwave waveforms with different nonlinear distortions are continuously injected, and the total power synthesis efficiency and spatial spurious radiation intensity of the back-end synthesizer are monitored in real time. Experimental data shows that when the signal distortion evaluation factor is lower than or equal to 0.015, the power synthesis efficiency remains above 95%, and multiple signals are in a spatial resonant synthesis state. When the distortion evaluation factor exceeds the critical physical performance inflection point of 0.015, nonlinear distortion between channels begins to produce destructive interference, and spatial spurious radiation increases sharply by more than 6 dB, causing a precipitous drop in the total synthesized power. Therefore, this embodiment objectively locks the preset distortion threshold at 0.015. If the current distortion evaluation factor is detected to be less than or equal to 0.015, the system is determined to be in a high-efficiency operating state. The system automatically skips the reconstruction alignment processing and directly outputs the branch synchronization compensation signal as a high-fidelity signal data to minimize the multiply-accumulate computation overhead of the microprocessor.

[0055] In step S16, the high-fidelity signal data is subjected to multi-channel collaborative dynamic equalization processing to obtain a system balance state index; based on the system balance state index, the high-fidelity signal data is subjected to adaptive stability control processing to obtain a target synthesized power signal.

[0056] The high-fidelity signal data undergoes multi-channel collaborative dynamic equalization processing to obtain system balance state indices, including: The high-fidelity signal data is mapped to a preset constellation diagram space to obtain a constellation feature distribution matrix, and the phase correction value between multiple signals is calculated based on the constellation feature distribution matrix. The phase alignment adjustment is performed on the high-fidelity signal data according to the phase correction value to obtain a multi-channel demodulated equalized signal. Extract the power detection values ​​of the multi-channel demodulated equalization signals in the spatial distribution, and calculate the power variance of each power detection value; The system balance degree is calculated based on the power variance to obtain the system balance state index.

[0057] In this embodiment, the high-fidelity signal data refers to the 512-point time-domain high signal-to-noise ratio discrete voltage sequence matrix output from step S15, after time-series reconstruction alignment and low-pass filtering purification. First, the high-fidelity signal data is mapped to a preset constellation diagram space to obtain a constellation feature distribution matrix. The phase correction value between multiple signals is then calculated based on this constellation feature distribution matrix. Specifically, the system calls the baseband digital demodulation unit to perform orthogonal demodulation processing on the input 512-point high-fidelity signal data, separating the in-phase component and the quadrature component. Subsequently, the system projects each time-domain sampling point onto the preset constellation diagram space, using the in-phase component as the horizontal axis and the quadrature component as the vertical axis. The preset constellation diagram space is a two-dimensional orthogonal coordinate system based on 16th-order orthogonal amplitude modulation. After projection, the system obtains a real-valued matrix containing 512 coordinate nodes on the two-dimensional complex plane. This means all mapped coordinates are linearly encapsulated in matrix form, and the output data is the constellation feature distribution matrix.

[0058] Next, the system calculates the phase correction value between multiple signals based on the constellation feature distribution matrix. Specifically, the system traverses the constellation feature distribution matrix using a search algorithm, calculating the geometric distance of each coordinate node relative to the coordinates of the 16-QAM ideal constellation point. The system determines the instantaneous phase deviation vector of each signal by finding the optimal center point with the smallest geometric distance in the entire array. Using a hardware adder, the system subtracts the instantaneous phase deviation vector of each channel from a preset standard ideal phase control reference, thereby calculating the scalar angle offset used to eliminate relative phase misalignment between branches, i.e., the phase correction value, whose physical dimension is uniformly in radians. The preset standard ideal phase control reference is determined through engineering calibration. During the system calibration phase, a distortion-free standard modulation signal is input, the phase of the output signal of each channel is measured, and the arithmetic mean is calculated as the reference value; in this embodiment, it is set to 0 radians.

[0059] The high-fidelity signal data is phase-aligned according to the phase correction value to obtain a multi-channel demodulated equalized signal. Specifically, the phase alignment adjustment operation is implemented through a digitally controlled complex rotator. In practice, the system uses the calculated phase correction value in radians as the rotation angle parameter, substitutes it into Euler's formula expansion, and uses hardware-level multipliers and subtractors to construct a dedicated two-dimensional complex rotation operator for each branch. Subsequently, the system sequentially performs complex matrix multiplication operations on the high-fidelity signal data and the two-dimensional complex rotation operator. This operation performs an equivalent phase lead or lag shift operation on each sampling point in the time domain, thereby completely aligning the initial phase between the multi-channel amplification branches at the underlying level, tightening the phase error within a very small physical boundary, and the output digital sequence is the multi-channel demodulated equalized signal.

[0060] The system extracts the power detection values ​​of the multi-channel demodulated equalization signals in their spatial distribution and calculates the power variance of each power detection value. Specifically, the system calls on-chip power detectors deployed at the ends of each power amplification channel to capture the instantaneous voltage fluctuations generated at the output terminals of the corresponding physical channels by the multi-channel demodulated equalization signals in real time. The system uses an arithmetic square circuit to calculate the sum of squares of the instantaneous voltage of each physical channel within the current sampling window and multiplies it by a preset channel equivalent characteristic impedance coefficient to obtain the actual absolute output power of each amplification channel, i.e., each power detection value, whose physical dimension is uniformly watts. The preset channel equivalent characteristic impedance coefficient is determined by an engineering calibration method. During the system calibration phase, the actual load impedance at the output terminal of each power amplification channel is measured, and its reciprocal is taken as the coefficient. In this embodiment, it is set to 0.05. Subsequently, the system invokes the variance calculation pipeline of the multi-channel data processor. First, it uses an accumulator to sum the power detection values ​​of all channels and divides them by the total number of physical channels (in this embodiment, the total number of physical channels is fixed at four) to calculate the global average output power. Next, it uses a hardware subtractor and exponentiation unit to calculate the absolute difference between the power detection value of each channel and the global average output power, and then squares the absolute difference to obtain the local variance term. Finally, it sums the local variance terms of all channels and divides them by the total number of physical channels (four) to calculate the statistical index reflecting the uniformity of power distribution among the amplification channels, namely the power variance.

[0061] The system balance is calculated based on the power variance to obtain a system balance state index. Specifically, the system uses a hardware divider to divide the calculated power variance (numerator) by a preset power variance safety threshold (denominator) to obtain a dimensionless balance attenuation ratio. Then, a hardware subtractor subtracts this balance attenuation ratio from the calculated value. To make the output index more consistent with the typical distribution of industrial control, the system multiplies the difference obtained from the subtraction by 100%, ultimately outputting a percentage value within the 0-100% range for globally evaluating the synthesizer's stable state—the system balance state index.

[0062] It should be noted that the construction of the preset 16-QAM constellation diagram space and the corresponding ideal constellation point coordinates described in this embodiment is objectively determined through engineering calibration. During the initialization and debugging phase of the system transmit link, the control chip continuously injects a standard, distortion-free 16-QAM baseband modulation test code stream into the ideal RF load through offline communication testing. The system records the 16 center coordinate points demodulated on the complex plane by the high-precision signal analyzer and pre-writes these 16 center coordinate points into the microprocessor's read-only memory in the form of hard encoding, which serves as the standard ideal position template for subsequent calculation of the geometric residual of the constellation feature distribution matrix. It is worth noting that the preset power variance safety threshold value used to calculate the system balance state index is objectively determined through performance-driven methods. On the solid-state amplifier high-power combining network physical simulation platform, the bias voltage of each amplification channel is artificially adjusted to create different power distribution non-uniformities. The system monitors the local return loss of the waveguide combining cavity in real time. Experimental data shows that when the power variance is less than or equal to 0.02 watts, the multi-channel signals are in benign steady-state combining. When the power variance increases and exceeds the core physical performance inflection point of 0.02 watts, the return loss exhibits a non-linear, precipitous deterioration, leading to a significant drop in the total combined power. Therefore, in order to establish an absolute safety protection boundary, this embodiment objectively locks 0.02 watts as the preset power variance safety threshold.

[0063] Specifically, based on the system equilibrium state index, adaptive stability control processing is performed on the high-fidelity signal data to obtain the target synthesized power signal, including: Based on the system balance state index, the high-fidelity signal data is dynamically jittered to predict the jitter suppression parameter. The fluctuation coefficient of the high-fidelity signal data is iteratively calculated using the jitter suppression parameter to obtain the gain adjustment weight. Based on the gain adjustment weight, multi-branch voltage regulation control is performed on the high-fidelity signal data to output the target composite power signal.

[0064] In this embodiment, the system balance state index is a percentage value representing the uniformity of power distribution across multiple amplification channels. High-fidelity signal data refers to the 512-point multi-channel digital discrete sequence matrix output in step S15, which has undergone time-domain sampling timing reconstruction and alignment, and has been denoised by low-pass filtering. Based on the system balance state index, dynamic jitter rate prediction is performed on the high-fidelity signal data to obtain jitter suppression parameters. Specifically, "dynamic jitter rate prediction" is implemented at the underlying level through a combination of discrete Kalman filter data processing and a time autoregressive model. In practice, the system first converts the system balance state index into a one-dimensional time-series state input. The system initializes and constructs a discrete Kalman filter in the microprocessor memory, containing a two-dimensional state transition matrix and a one-dimensional observation matrix, using the instantaneous amplitude variation variance of each sampling point of the high-fidelity signal data as the current measured input vector. By predicting and dynamically correcting the periodic time update equation of the Kalman filter model and the measurement update equation, the algorithm recursively performs statistical decoupling on high-frequency random phase disturbances, thereby discretely calculating the coherent jitter rate characteristics reflecting the transient thermal accumulation within each power amplification physical channel. Subsequently, the system uses a hardware multiplier to multiply the coherent jitter rate characteristics by a preset smoothing convergence operator, converting it into a corresponding inverse amplitude smoothing scalar. This scalar value is the jitter suppression parameter. The preset smoothing convergence operator is selected by testing the jitter suppression effect of different operator values ​​in the range of 0.1 to 1.0, and the value that minimizes the variance of the output signal without introducing additional oscillations is chosen. In this embodiment, it is set to 0.5.

[0065] The high-fidelity signal data is subjected to iterative calculation of the fluctuation coefficient using the jitter suppression parameter to obtain the gain adjustment weight. Specifically, the "fluctuation coefficient iterative calculation" is a process of calculating the rolling variance convergence of the signal's time-domain envelope using a dynamic gain control algorithm. In practice, the system extracts a continuous sliding time window within the high-speed data buffer and sends the high-fidelity signal data into the arithmetic pipeline. The system first calculates the absolute difference between the maximum and minimum waveform voltage values ​​within the sliding window and divides it by the arithmetic mean of the voltages within the window to determine the initial waveform fluctuation coefficient. Subsequently, the system uses a hardware subtractor to subtract the jitter suppression parameter obtained in the above steps from the initial waveform fluctuation coefficient, thereby dynamically deducting the influence of high-frequency jitter components on the macroscopic envelope to obtain the purified fluctuation coefficient. Finally, the system inputs the purified fluctuation coefficient into the cost function of the gradient descent algorithm and performs iterative optimization with the goal of minimizing the energy swing amplitude of the entire channel within the window, calculating the bias gain compensation adjustment factor, i.e., the gain adjustment weight, specific to each single-stage amplification channel.

[0066] Based on the gain adjustment weights, multi-branch voltage regulation control is performed on the high-fidelity signal data to output the target synthesized power signal. Specifically, "multi-branch voltage regulation control" is a process of dynamically adjusting the source or drain power supply bus of the power amplification physical channel directly through a high-speed hardware driver interface. In practice, the system converts the calculated gain adjustment weights of each channel into corresponding digital voltage control words. The processor sends this control word quasi-synchronously to the digital-to-analog converter control interface of the low-dropout linear regulator deployed at the power supply end of each amplification channel via a high-speed bus. According to the received control word, the power module adaptively adjusts the drain bias voltage of the field-effect transistor in the physical channel, thereby linearly changing the output power saturation gain of the independent channel and eliminating the asymmetry in the final energy amplitude caused by physical anisotropy between channels. After the bias voltage hardware adjustment is completed, the multi-channel microwave electromagnetic waves amplified by each physical channel are combined through a spatial waveguide synthesis cavity to finally output a stable microwave signal with maximized coherence efficiency, i.e., the target synthesized power signal.

[0067] It should be noted that the initialization parameters of the state transition matrix and observation matrix used in this embodiment of the discrete Kalman filter were objectively determined through engineering calibration. During the factory interrupt calibration phase of the microwave solid-state power amplifier, a constant-power, unmodulated single-frequency fundamental signal is injected into the amplification system. The system uses an on-chip high-speed power detector to continuously capture the output voltage fluctuation waveform for 48 hours, calculating the background thermal noise variance and the inherent crosstalk jitter frequency distribution of the system hardware clock source under stable operating conditions. The system directly uses this hardware background thermal noise variance as the initialization reference value of the observation noise covariance matrix of the Kalman filter, and writes the inherent crosstalk jitter characteristic matrix into the state transition model, thereby establishing a state estimation basis that is completely bound to the physical characteristics of the actual chip hardware.

[0068] It is worth noting that the sliding time window length and the iteration step size of the fluctuation coefficient used to calculate the gain adjustment weights were determined through offline simulation of the performance inflection point. In the RF high-power combining network simulation software, a millimeter-wave radar pulse sequence containing rapid amplitude abrupt changes was injected. The sliding window lengths were set to 10 nanoseconds, 20 nanoseconds, 50 nanoseconds, and 100 nanoseconds, respectively, and the iteration step sizes of the gradient descent method were set to 0.01, 0.05, and 0.10, respectively, for optimization calculations. The system statistically analyzed the convergence success rate of the fluctuation coefficient under each parameter combination and the total parameter optimization computational cost within the central processing unit. Experimental data show that when the sliding time window length is set to 50 nanoseconds and the iteration step size is set to 0.05, the fluctuation coefficient of the envelope can rapidly converge to a safe and healthy range below 0.01 within 3 microsecond periods. When the window length is shortened to 10 nanoseconds, the insufficient number of sampling points leads to frequent and severe oscillations in gradient calculations, causing low-frequency thermal jumps in the power supply system. When the window length is extended to 100 nanoseconds, the processing time exceeds 15 microseconds, severely breaching the real-time response safety boundary of microsecond-level phase-locked synthesis in solid-state power amplifiers. Therefore, this embodiment objectively sets the sliding time window length to 50 nanoseconds and the gradient descent step size to 0.05.

[0069] In summary, this invention integrates high real-time envelope trend analysis, dynamic range adaptive adjustment, and multi-channel signal synchronous compensation technology to construct a closed-loop feedback system covering the entire process from signal feature extraction to waveform distortion correction, thereby achieving dynamic and precise adjustment of parameters of each branch in power synthesis and efficient integration of multiple signals.

[0070] It is worth noting that the second embodiment of the present invention provides a microwave solid-state power amplifier power combining control system, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor executes all the process steps of the microwave solid-state power amplifier power combining control method of the above embodiment. The working principles and beneficial effects of the two are one-to-one, and therefore will not be described in detail again.

[0071] It should be noted that the system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0072] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A power combining control method for a microwave solid-state power amplifier, characterized in that, include: The microwave signal to be synthesized and the signals of each branch are acquired, and the envelope of the microwave signal to be synthesized is extracted to obtain the original instantaneous envelope data. The original instantaneous envelope data is subjected to amplitude smoothing to obtain a smoothed envelope data sequence; feature fitting is performed on the smoothed envelope data sequence to obtain synthetic control features; Based on the synthetic control characteristics, the spatiotemporal consistency correction process is performed on the signals of each branch to obtain response alignment data; Based on the response alignment data, signal processing delay optimization is performed to obtain a branch synchronization compensation signal containing a distortion evaluation factor; If the distortion evaluation factor of the branch synchronization compensation signal exceeds the preset distortion threshold, the branch synchronization compensation signal is subjected to high-precision waveform reconstruction processing to generate high-fidelity signal data. The high-fidelity signal data is subjected to multi-channel collaborative dynamic equalization processing to obtain a system balance state index; based on the system balance state index, the high-fidelity signal data is subjected to adaptive stability control processing to obtain a target synthetic power signal.

2. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, The process of acquiring the microwave signal to be synthesized and the signals of each branch, and performing envelope extraction processing on the microwave signal to be synthesized to obtain the original instantaneous envelope data, includes: Perform a fast Fourier transform on the microwave signal to be synthesized to obtain a single-sided frequency spectrum that includes the positive frequency component; The positive frequency portion of the single-sided frequency domain spectrum is subjected to a multiplication mapping process to obtain a single-sided weighted spectrum. Perform an inverse Fourier transform on the single-sided weighted spectrum to obtain the corresponding analytical signal, and analyze the analytical signal to obtain the original instantaneous envelope data.

3. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, The step of performing amplitude smoothing processing on the original instantaneous envelope data to obtain a smoothed envelope data sequence includes: Wavelet denoising is performed on the original instantaneous envelope data to obtain a five-level hierarchical decomposition matrix, and high-frequency coefficient soft thresholding is performed on the five-level hierarchical decomposition matrix to obtain high-frequency noise components and low-frequency components. The high-frequency noise component is subjected to noise suppression processing to obtain the updated high-frequency component; The low-frequency component is superimposed and reconstructed with the updated high-frequency component to obtain a smooth envelope data sequence.

4. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, The step of performing feature fitting processing based on the smoothed envelope data sequence to obtain synthetic control features includes: The real-time rate of change is obtained by performing a first-order difference calculation on the smoothed envelope data sequence. If the real-time change rate exceeds a preset change threshold, the smooth envelope data sequence is subjected to amplitude logarithmic transformation compression to obtain a dynamically adjusted sequence. The dynamic adjustment sequence is subjected to cubic polynomial fitting to obtain the trend feature slope; The real-time rate of change and the slope of the trend feature are concatenated to obtain the synthetic control feature.

5. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, The step of performing spatiotemporal consistency correction processing on the signals of each branch according to the synthetic control characteristics to obtain response alignment data includes: Analyze the synthetic control characteristics to determine the response time difference between the signals of each branch; Based on the response time difference, nonlinear time-axis stretching is performed on each branch signal to obtain response alignment data.

6. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, The step of performing signal processing delay optimization based on the response alignment data to obtain a branch synchronization compensation signal containing a distortion evaluation factor includes: The processing delay time for generating the response alignment data is monitored. If the processing delay time is greater than a preset delay tolerance threshold, the response alignment data is thinned to obtain optimized delay data. Perform frequency domain analysis on the optimized delay data to obtain the distortion frequency components and amplitude deviation. Calculate the distortion assessment factor based on the amplitude deviation; Based on the distortion frequency component and the distortion evaluation factor, the optimized delay data is subjected to complex weighted compensation to generate a branch synchronization compensation signal containing the distortion evaluation factor.

7. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, If the distortion evaluation factor of the branch synchronization compensation signal exceeds a preset distortion threshold, then the branch synchronization compensation signal undergoes high-precision waveform reconstruction processing to generate high-fidelity signal data, including: Calculate the corresponding timing offset based on the distortion evaluation factor in the branch synchronization compensation signal; The branch synchronization compensation signal is reconstructed and aligned based on the physical time axis according to the time offset to obtain the time calibration signal; The timing calibration signal is subjected to residual electromagnetic noise suppression processing to generate high-fidelity signal data.

8. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, The process of performing multi-channel collaborative dynamic equalization on the high-fidelity signal data to obtain system balance state indices includes: The high-fidelity signal data is mapped to a preset constellation diagram space to obtain a constellation feature distribution matrix, and the phase correction value between multiple signals is calculated based on the constellation feature distribution matrix. The phase alignment adjustment is performed on the high-fidelity signal data according to the phase correction value to obtain a multi-channel demodulated equalized signal. Extract the power detection values ​​of the multi-channel demodulated equalization signals in the spatial distribution, and calculate the power variance of each power detection value; The system balance degree is calculated based on the power variance to obtain the system balance state index.

9. The microwave solid-state power amplifier power combining control method according to claim 1, characterized in that, The step of performing adaptive stability control processing on the high-fidelity signal data according to the system balance state index to obtain the target synthetic power signal includes: Based on the system balance state index, the high-fidelity signal data is dynamically jittered to predict the jitter suppression parameter. The fluctuation coefficient of the high-fidelity signal data is iteratively calculated using the jitter suppression parameter to obtain the gain adjustment weight. Based on the gain adjustment weight, multi-branch voltage regulation control is performed on the high-fidelity signal data to output the target composite power signal.

10. A microwave solid-state power amplifier power combining control system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 9.

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