Semiconductor device and method of manufacturing the same, electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and an electronic device, and relates to the technical field of semiconductor chips, and aims to solve the problem of low minority carrier lifetime of a semiconductor device; the preparation method of the semiconductor device comprises the following steps: forming a first epitaxial layer on a substrate; implanting a doping element in a target region of the first epitaxial layer to form a doping structure; the surface of the doping structure away from the substrate forms part of the surface of the first epitaxial layer away from the substrate; a second epitaxial layer is formed on the side of the doping structure away from the substrate; the second epitaxial layer is formed on the surface of at least part of the doping structure away from the substrate; the second epitaxial layer is subjected to a thermal oxidation treatment, so that the second epitaxial layer is converted into an oxidation material layer; and the oxidation material layer is removed.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] In semiconductor devices, the average time it takes for minority carriers to recombine and disappear from the semiconductor material is called the minority carrier lifetime. A low minority carrier lifetime in a semiconductor device will affect its electrical characteristics, such as the forward voltage drop of ultra-high voltage (10KV, 20KV) semiconductor devices, which in turn leads to high turn-on losses and thus affects the performance of the semiconductor device. Summary of the Invention

[0003] The embodiments of this disclosure provide a semiconductor device and a method for fabricating the same, as well as an electronic device, aimed at solving the problem of low minority carrier lifetime in semiconductor devices.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a method for fabricating a semiconductor device is provided. The method includes: forming a first epitaxial layer on a substrate; implanting dopant elements into a target region of the first epitaxial layer to form a doped structure; the surface of the doped structure away from the substrate forming a portion of the surface of the first epitaxial layer away from the substrate; forming a second epitaxial layer on at least a portion of the surface of the doped structure away from the substrate; subjecting the second epitaxial layer to thermal oxidation to convert the second epitaxial layer into an oxide layer; and removing the oxide layer.

[0005] The semiconductor device fabrication method provided in the above embodiments of this disclosure involves thermally oxidizing the second epitaxial layer to convert it into an oxide material layer. During this process, the second epitaxial layer is heated and oxidized, causing oxygen atoms to enter the doped structure, filling dangling bonds, and simultaneously promoting internal atomic migration, repairing lattice damage, reducing the recombination center density of the doped structure, thereby improving minority carrier lifetime.

[0006] In some embodiments, the first epitaxial layer includes an epitaxial portion. The epitaxial portion is arranged along a first direction with the doped structure, and the first direction and the stacking direction of the first epitaxial layer are perpendicular to the substrate. During the formation of the second epitaxial layer on the side of the doped structure away from the substrate, the second epitaxial layer also covers the surface of the epitaxial portion away from the substrate.

[0007] In some embodiments, after removing the oxide material layer, the preparation method further includes activating the doped structure. Alternatively, before forming the second epitaxial layer, the preparation method further includes activating the doped structure.

[0008] In some embodiments, the thickness of the second epitaxial layer ranges from 0.1 μm to 1.5 μm.

[0009] In some embodiments, the temperature range for the thermal oxidation treatment of the second epitaxial layer is 1300°C to 1600°C.

[0010] In some embodiments, the thermal oxidation treatment of the second epitaxial layer takes a duration of 6 to 60 hours.

[0011] In some embodiments, the material of the second epitaxial layer includes SiC; the material of the oxide layer includes SiO2.

[0012] In some embodiments, after thermal oxidation of the second epitaxial layer, an initial semiconductor device is obtained; removing the oxide material layer includes: placing the initial semiconductor device in a hydrofluoric acid buffer solution and immersing it for 3 to 30 minutes.

[0013] In some embodiments, forming a second epitaxial layer on the surface of at least partially doped structures away from the substrate includes: forming the second epitaxial layer using an epitaxial process at a preset temperature. The preset temperature ranges from 1500°C to 1650°C.

[0014] In some embodiments, before forming a second epitaxial layer on the side of the doped structure and / or epitaxial portion away from the substrate, the minority carriers in the doped structure and / or epitaxial portion have a first minority carrier lifetime; after thermal oxidation of the second epitaxial layer, the minority carriers in the doped structure and / or epitaxial portion have a second minority carrier lifetime. The ratio of the second minority carrier lifetime to the first minority carrier lifetime ranges from 1.1 to 2.

[0015] In some embodiments, the second minority carrier lifetime is greater than or equal to 6 microseconds.

[0016] In some embodiments, the doped structure includes: a first doped portion and / or a second doped portion. The surface of the first doped portion away from the substrate forms a portion of the surface of the first epitaxial layer away from the substrate. The second doped portion is disposed between the first doped portion and the first epitaxial layer and encapsulates the first doped portion.

[0017] In some embodiments, the fabrication method includes: forming a first electrode on the side of the first doped portion away from the first epitaxial layer; and forming a second electrode on the side of the substrate away from the first epitaxial layer.

[0018] In another aspect, a semiconductor device is provided. This semiconductor device is prepared using the semiconductor device preparation method described in any of the above embodiments.

[0019] In another aspect, an electronic device is provided. This electronic device includes: a circuit board and a semiconductor device as described in the above embodiments; the conductor device and the circuit board are electrically connected.

[0020] It is understood that the beneficial effects of the semiconductor devices and electronic devices provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor preparation methods described above, and will not be repeated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments; Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 A step diagram illustrating a method for fabricating a semiconductor device according to some embodiments; Figure 7 This is a schematic diagram of the structure of an electronic device according to some embodiments. Detailed Implementation

[0023] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0024] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0025] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0026] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0027] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0028] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0029] In this disclosure, the meaning of “on” should be interpreted in the broadest sense, such that “on” means not only “directly on something”, but also includes the meaning of “on something” with intermediate features or layers.

[0030] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0031] The technical terms used in the embodiments of this disclosure are explained below: Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. Among them, when the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this disclosure, this type of impurity semiconductor is also called a conductive semiconductor, for example, a conductive silicon carbide material doped with impurities such as nitrogen (N), boron (B), and aluminum (Al). Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this disclosure, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0032] It should be noted that in this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0033] In semiconductor devices, charge carriers are divided into two types: majority carriers (i.e., many carriers) and minority carriers (i.e., few carriers).

[0034] Majority carriers are the dominant charge carriers. For example, in an N-type semiconductor, electrons are the majority carriers; in a P-type semiconductor, holes are the majority carriers.

[0035] Minority carriers are charge carriers that occupy a secondary position. For example, in an N-type semiconductor, holes are minority carriers; in a P-type semiconductor, electrons are minority carriers.

[0036] Minority carrier lifetime refers to the average time it takes for minority carriers to recombine with majority carriers after being injected into a semiconductor (i.e., electrons and holes disappear in pairs).

[0037] A low minority carrier lifetime can affect the electrical characteristics of semiconductor devices, such as the forward voltage drop of ultra-high voltage (10KV, 20KV) semiconductor devices, which in turn leads to high turn-on losses and thus affects the performance of semiconductor devices.

[0038] Based on this, embodiments of this disclosure provide a method for fabricating a semiconductor device. For example... Figure 1 As shown, the method for fabricating this semiconductor device includes steps S1 to S5.

[0039] S1: Reference Figure 2 A first epitaxial layer 20 is formed on the substrate 10.

[0040] For example, the material of substrate 10 may be silicon carbide.

[0041] S2: Doping elements are implanted in the target region of the first epitaxial layer 20 to form a doped structure 30; the surface of the doped structure 30 away from the substrate 10 forms a part of the surface of the first epitaxial layer 20 away from the substrate 10.

[0042] For example, the doped structure 30 can be a P-type ion doped region, such as a P-well; or an N-type ion doped region, such as an N-fin.

[0043] S3: Reference Figure 3 A second epitaxial layer 40 is formed on the surface of at least partially doped structure 30 away from substrate 10.

[0044] Here, before the second epitaxial layer 40 is formed, the second epitaxial layer 40 can be cleaned by a standard wet chemical cleaning process, such as RCA cleaning, which can remove contaminants such as particles, metal ions, and organic matter from the surface of the second epitaxial layer 40.

[0045] S4: Reference Figure 4 The second epitaxial layer 40 is subjected to thermal oxidation treatment to convert the second epitaxial layer 40 into an oxide material layer 50.

[0046] S5: Combination Figure 2 Remove 50% of the oxide material layer.

[0047] During the process of injecting doping elements into the target region to form the doped structure 30, the lattice order in the target region of the first epitaxial layer 20 is disrupted, introducing lattice defects. These defects form recombination centers in the band gap, accelerating the recombination rate of minority carriers, thereby reducing the minority carrier lifetime.

[0048] During the process of thermally oxidizing the second epitaxial layer 40 by S4 to transform the second epitaxial layer 40 into an oxide material layer 50, the second epitaxial layer 40 is heated and oxidized, which allows carbon atoms to enter the doped structure 30, fill carbon vacancies, and promote the migration of internal atoms, repair lattice damage, reduce the recombination center density of the doped structure 30, thereby improving the minority carrier lifetime.

[0049] In some embodiments, combined with Figures 2-4 The first epitaxial layer 20 includes an epitaxial portion 21. The epitaxial portion 21 and the doped structure 30 are arranged along a first direction X, and the first direction X and the first epitaxial layer 20 are perpendicular to the stacking direction of the substrate 10. During the formation of the second epitaxial layer 40 on the side of the doped structure 30 away from the substrate 10, the second epitaxial layer 40 also covers the surface of the epitaxial portion 21 away from the substrate 10.

[0050] Understandably, the second epitaxial layer 40 also covers the surface of the epitaxial portion 21 away from the substrate 10, which allows the second epitaxial layer 40 to be heated and oxidized during the thermal oxidation process of the second epitaxial layer 40 in S4 to convert the second epitaxial layer 40 into an oxide material layer 50. This reduces the interface state density of the epitaxial portion 21, thereby improving the minority carrier lifetime of the epitaxial portion 21 and improving the overall minority carrier lifetime of the semiconductor device.

[0051] In some embodiments, after removing the oxide material layer 50 in S5, the preparation method further includes activating the doped structure 30.

[0052] Understandably, placing the activation step after removing the oxide layer in S5 allows for the improvement of minority carrier lifetime during the formation of the oxide material layer 50, followed by the activation annealing process to perfect the ion implantation process. This not only improves the minority carrier lifetime but also achieves doping with a higher activation rate, thereby increasing the process yield.

[0053] In some other embodiments, the preparation method further includes activating the doped structure 30 before forming the second epitaxial layer 40.

[0054] Understandably, defects such as carbon vacancies may be generated during the activation of the doped structure 30, causing these defects to form recombination centers in the band gap. After the doped structure 30 is activated, a second epitaxial layer 40 is formed, and the second epitaxial layer 40 is thermally oxidized to convert it into an oxide material layer 50. This process reduces the carbon vacancy density of the doped structure 30 and the epitaxial portion 21, improves the minority carrier lifetime of the epitaxial portion 21, and further enhances the overall minority carrier lifetime of the semiconductor device.

[0055] In some embodiments, reference Figure 3 The thickness D of the second epitaxial layer 40 ranges from 0.1 μm to 1.5 μm.

[0056] For example, the thickness D of the second epitaxial layer 40 can be 0.1μm, 0.5μm, 0.7μm, 1μm, 1.2μm or 1.5μm, etc., and there is no limitation here.

[0057] Understandably, the thickness D of the second epitaxial layer 40 is in the range of 0.1 μm to 1.5 μm, which can ensure that the second epitaxial layer 40 can be completely oxidized, thereby reducing the recombination center density of the doped structure 30; at the same time, it can ensure that the consumption of the first epitaxial layer 20 is small, thereby improving the electrical characteristics of the semiconductor device.

[0058] In some embodiments, the temperature range for the thermal oxidation treatment of the second epitaxial layer 40 is 1300°C to 1600°C.

[0059] For example, the temperature of the thermal oxidation treatment of the second epitaxial layer 40 can be 1300℃, 1350℃, 1400℃, 1450℃, 1500℃, 1550℃ or 1600℃, etc., and there is no limitation here.

[0060] In some embodiments, the thermal oxidation treatment time of the second epitaxial layer 40 ranges from 6 hours to 60 hours.

[0061] For example, the thermal oxidation treatment time of the second epitaxial layer 40 can be 6 hours, 10 hours, 20 hours, 30 hours, 40 hours, 50 hours or 60 hours, etc., and there is no limitation here.

[0062] Understandably, the thermal oxidation temperature of the second epitaxial layer 40 is in the range of 1300℃ to 1600℃ and the thermal oxidation time of the second epitaxial layer 40 is in the range of 6 hours to 60 hours. This can ensure that the second epitaxial layer 40 can be completely oxidized and that the consumption of the first epitaxial layer 20 is small, thereby improving the electrical characteristics of the semiconductor device.

[0063] In some embodiments, the material of the second epitaxial layer 40 includes SiC; the material of the oxide material layer 50 includes SiO2.

[0064] Understandably, during the thermal oxidation process, the SiC material of the second epitaxial layer 40 reacts with oxygen to generate the SiO2 material of the oxide material layer 50, which reduces the recombination center density of the doped structure 30 and thus improves the minority carrier lifetime. Furthermore, the complete oxidation of the second epitaxial layer 40 into the oxide material layer 50 ensures that the recombination center density of the doped structure 30 is low, thereby improving the minority carrier lifetime.

[0065] In some embodiments, after thermal oxidation of the second epitaxial layer 40, an initial semiconductor device is obtained; S5 removes the oxide material layer 50, including: placing the initial semiconductor device in a hydrofluoric acid buffer solution and soaking it for 3 to 30 minutes.

[0066] Understandably, firstly, using a buffer solution can maintain a stable etching rate, preventing uneven etching caused by excessively rapid reactions or temperature changes. This ensures that the oxide layer on the entire wafer surface is removed smoothly and cleanly, avoiding residues or over-etching pits. Secondly, compared to dry etching, hydrofluoric acid buffer etching is a chemical reaction that does not introduce surface damage or charge injection caused by plasma. It can also release the mechanical stress caused by the difference in thermal expansion coefficients between the oxide material layer 50 and the first epitaxial layer 20.

[0067] Furthermore, when the material of the second epitaxial layer 40 includes SiC and the material of the oxide layer 50 includes SiO2, hydrofluoric acid corrodes silicon dioxide faster but silicon carbide slower. This high selectivity ensures that the oxide layer 50 is completely stripped away, while the first epitaxial layer 20 is almost undamaged, thus protecting the surface of the semiconductor device.

[0068] In some embodiments, S3 forms a second epitaxial layer 40 on the surface of at least partially doped structure 30 away from substrate 10, including: forming the second epitaxial layer 40 using an epitaxial process at a preset temperature. The preset temperature ranges from 1500°C to 1650°C.

[0069] For example, the preset temperature can be 1500℃, 1550℃, 1600℃ or 1650℃, etc., and there is no limitation here.

[0070] Understandably, by using the above-mentioned epitaxial process and within the preset temperature range of 1500℃ to 1650℃, a second epitaxial layer 40 of good quality can be formed, which provides a good foundation for subsequent thermal oxidation treatment, thereby reducing the recombination center density of the doped structure 30 and thus improving the minority carrier lifetime.

[0071] In some embodiments, before forming the second epitaxial layer 40 on the side of the doped structure 30 and / or the epitaxial portion 21 away from the substrate 10 in step S3, the minority carriers in the doped structure 30 and / or the epitaxial portion 21 have a first minority carrier lifetime; after thermal oxidation of the second epitaxial layer 40, the minority carriers in the doped structure 30 and / or the epitaxial portion 21 have a second minority carrier lifetime. The ratio of the second minority carrier lifetime to the first minority carrier lifetime ranges from 1.1 to 2.

[0072] Here, minority carrier lifetime can be tested using the microwave photoconductivity decay method.

[0073] Understandably, the semiconductor device fabrication method of this disclosure can improve the minority carrier lifetime of the doped structure 30 and / or the epitaxial portion 21, further enhancing the minority carrier lifetime of the semiconductor device fabricated by the semiconductor device fabrication method of this disclosure. This can meet the high minority carrier lifetime requirement of bipolar semiconductor devices (e.g., insulated gate bipolar transistors, IGBTs) for epitaxial materials, and produce high-power electronic devices with significantly reduced energy consumption.

[0074] In some embodiments, the second minority carrier lifetime is greater than or equal to 6 microseconds.

[0075] For example, the second minority carrier lifetime can be 6 microseconds, 7 microseconds, 8 microseconds or 9 microseconds, etc., and there is no limitation here.

[0076] Understandably, compared to the low minority carrier lifetime of SiC epitaxial wafers (typically between 0.1 microseconds and 4 microseconds), by first forming a second epitaxial layer 40 in this application and then thermally oxidizing the second epitaxial layer 40, the minority carrier lifetime of the doped structure 30 and / or the epitaxial portion 21 can be greater than or equal to 6 microseconds, which can further improve the electrical performance of semiconductor devices.

[0077] In some embodiments, reference Figures 2-6 The doped structure 30 includes: a first doped portion 31 and / or a second doped portion 32.

[0078] The surface of the first doped portion 31 away from the substrate 10 forms a portion of the surface of the first epitaxial layer 20 away from the substrate 10.

[0079] The second doped portion 32 is disposed between the first doped portion 31 and the first epitaxial layer 20, and encapsulates the first doped portion 31.

[0080] Understandably, during the formation of the first doped portion 31 and the second doped portion 32, such as through ion implantation or annealing, recombination centers are formed, accelerating the recombination rate of minority carriers and thus reducing the minority carrier lifetime. By performing thermal oxidation treatment on the second epitaxial layer 40 in S4, transforming the second epitaxial layer 40 into an oxide material layer 50, the heating and oxidation of the second epitaxial layer 40 allows oxygen atoms to enter the doped structure 30, filling dangling bonds and simultaneously promoting internal atomic migration, repairing lattice damage, and reducing the recombination center density of the doped structure 30, thereby improving the minority carrier lifetime. In some embodiments, reference Figure 5 The methods for fabricating semiconductor devices include: S5: A first electrode 60 is formed on the side of the first doped portion 31 away from the first epitaxial layer 20.

[0081] S6: A second electrode 70 is formed on the side of the substrate 10 away from the first epitaxial layer 20.

[0082] For example, the first electrode 60 can be the source or anode, and the second electrode 70 can be the drain or cathode.

[0083] For example, the material of the first electrode 60 can be Ti, Al, Cu, TiN, and Ni, etc.

[0084] For example, the material of the second electrode 70 can be Ti, Al, Cu, TiN, Ag, and Ni, etc.

[0085] In some examples, combined Figure 4 ,like Figure 5 As shown, the semiconductor device 100 also includes a gate 90 and a gate oxide layer 80. The gate 90 is disposed on the side of the epitaxial portion 21 away from the substrate 10. The gate oxide layer 80 is disposed between the gate 90 and the epitaxial portion 21. For example, the first electrode 60 of the semiconductor device 100 is the source electrode, the second electrode 70 is the drain electrode, and the semiconductor device 100 can be an IGBT.

[0086] For example, the material of the gate 90 can be polycrystalline silicon. The material of the gate 90 can also be phosphorus-doped.

[0087] For example, the material of the gate oxide layer 80 can be silicon dioxide.

[0088] In yet another example, combined Figure 4 ,like Figure 6 As shown, the first electrode 60 of the semiconductor device 100 is the anode, and the second electrode 70 is the cathode. The semiconductor device 100 can be a diode.

[0089] Understandably, the first electrode 60 is one of the main current output terminals of the semiconductor device. The second electrode 70, as another main current output terminal of the semiconductor device, forms a vertical conductive channel with the first electrode 60. Together, these two steps complete the construction of the vertical conductive path, realizing the construction of the vertical semiconductor device structure.

[0090] Embodiments of this disclosure provide a semiconductor device 100. (See reference...) Figure 5 The semiconductor device 100 is prepared using the semiconductor device preparation method described in any of the above embodiments.

[0091] This disclosure provides an electronic device 1000. For example... Figure 7 As shown, the electronic device 200 can be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic devices.

[0092] Continue to refer to Figure 1The electronic device 200 includes a semiconductor device 100 and a circuit board 201, which are electrically connected. The circuit board 201 converts external power into the voltage or current required for the semiconductor device 100 to operate.

[0093] For example, circuit board 201 may include a printed circuit board (PCB) or the like.

[0094] For example, circuit board 201 may include multiple conductive layers. The multiple conductive layers within circuit board 201 may be separated from each other by dielectric layers.

[0095] The technical solutions disclosed herein can be applied to electronic devices, including various types of user equipment or terminal devices such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices; these electronic devices can also be network equipment such as base stations. The electronic devices can also be devices such as power amplifiers used in the aforementioned electronic devices. The embodiments of this disclosure do not impose any special limitations on the specific form of the aforementioned electronic devices.

[0096] It is understood that the beneficial effects of the semiconductor devices and electronic devices provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor preparation methods described above, and will not be repeated here.

[0097] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A first epitaxial layer is formed on the substrate; Doping elements are implanted in the target region of the first epitaxial layer to form a doped structure; the surface of the doped structure away from the substrate forms a portion of the surface of the first epitaxial layer away from the substrate. A second epitaxial layer is formed on at least a portion of the doped structure on a surface remote from the substrate; The second epitaxial layer is subjected to thermal oxidation treatment to convert the second epitaxial layer into an oxide material layer; Remove the oxide material layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first epitaxial layer includes: The epitaxial portion is arranged along a first direction with the doped structure, and the first direction and the stacking direction of the first epitaxial layer are perpendicular to the substrate. During the process of forming a second epitaxial layer on the side of the doped structure away from the substrate, the second epitaxial layer also covers the surface of the epitaxial portion away from the substrate.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After removing the oxide material layer, the preparation method further includes: activating the doped structure; Alternatively, before forming the second epitaxial layer, the preparation method may further include activating the doped structure.

4. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, The thickness of the second epitaxial layer ranges from 0.1 μm to 1.5 μm.

5. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, The temperature range for the thermal oxidation treatment of the second epitaxial layer is 1300℃~1600℃; and / or, The processing time for the thermal oxidation treatment of the second epitaxial layer ranges from 6 hours to 60 hours.

6. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, The material of the second epitaxial layer includes SiC; the material of the oxide material layer includes SiO2.

7. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, After the second epitaxial layer is subjected to thermal oxidation treatment, an initial semiconductor device is obtained; The removal of the oxide material layer includes: placing the initial semiconductor device in a hydrofluoric acid buffer solution and immersing it for 3 to 30 minutes.

8. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, The step of forming a second epitaxial layer on a surface of at least a portion of the doped structure away from the substrate includes: forming the second epitaxial layer at a preset temperature using an epitaxial process; The preset temperature range is 1500℃~1650℃.

9. The method for fabricating a semiconductor device according to claim 2, characterized in that, Before forming a second epitaxial layer on the side of the doped structure and / or the epitaxial portion away from the substrate, the minority carriers in the doped structure and / or the epitaxial portion have a first minority carrier lifetime; after thermal oxidation of the second epitaxial layer, the minority carriers in the doped structure and / or the epitaxial portion have a second minority carrier lifetime. The ratio of the second minority carrier lifetime to the first minority carrier lifetime ranges from 1.1 to 2.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The second minority carrier lifetime is greater than or equal to 6 microseconds.

11. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, The doped structure includes: A first doped portion, the surface of the first doped portion remote from the substrate, forms a portion of the surface of the first epitaxial layer remote from the substrate; and / or The second doped portion is disposed between the first doped portion and the first epitaxial layer, and encapsulates the first doped portion.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The preparation method includes: A first electrode is formed on the side of the first doped region away from the first epitaxial layer; A second electrode is formed on the side of the substrate away from the first epitaxial layer.

13. A semiconductor device, characterized in that, It is prepared by the method of any one of claims 1 to 12.

14. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 13; the conductor device and the circuit board are electrically connected.

Images