Semiconductor device with guard ring structure

Abstract

A semiconductor device having a guard ring structure. A semiconductor device includes a substrate having a chip region and a guard ring region surrounding the chip region; a guard ring structure and a crack detection circuit structure disposed on the substrate in the guard ring region; a crack detection pad structure disposed on the substrate in the chip region; and a crack detection pad connection feature embedded in the substrate for electrically connecting the crack detection circuit structure with the crack detection pad structure through a portion of the guard ring structure. The crack detection pad connection feature includes a crack detection pad connection embedded electrode and a crack detection pad connection embedded cap disposed on the crack detection pad connection embedded electrode.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority to Korean Patent Application No. 10-2025-0009243, filed on January 22, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a semiconductor device, and more specifically, to a semiconductor device having a guard ring structure. Background Technology

[0004] The guard ring structure in semiconductor devices is a design feature used to prevent crack propagation and moisture penetration. As semiconductor chips become increasingly thinner, maintaining the structural stability and physical robustness of the guard ring structure becomes increasingly important. Summary of the Invention

[0005] Embodiments of this disclosure provide a protective ring structure for maintaining the structural stability and physical robustness of a semiconductor device.

[0006] Embodiments of this disclosure provide pad structures for test circuits and crack detection circuits disposed in a chip region.

[0007] Embodiments of this disclosure provide a way to connect test circuitry and crack detection circuitry to a pad structure without structural and physical losses due to the guard ring structure.

[0008] According to one embodiment of this disclosure, a semiconductor device includes: a substrate having a chip region and a protective ring region surrounding the chip region; a protective ring structure and a crack detection circuit structure disposed on the substrate and in the protective ring region; a crack detection pad structure disposed on the substrate and in the chip region; and a crack detection pad connection member embedded in the substrate to electrically connect the crack detection circuit structure to the crack detection pad structure passing through a portion of the protective ring structure. The crack detection pad connection member includes a crack detection pad connection buried electrode and a crack detection pad connection buried cover layer disposed on the crack detection pad connection buried electrode.

[0009] According to one embodiment of this disclosure, a semiconductor device includes: a substrate having a chip region defined by scribe lines and a guard ring region, wherein the guard ring region is configured to surround the chip region; a guard ring structure disposed on the substrate and in the guard ring region; a test circuit structure disposed on the substrate and in at least one scribe line; a test pad structure disposed on the substrate and in the chip region; and a test pad connection component embedded in the substrate to electrically connect the test circuit structure to the test pad structure passing through the guard ring region. The test pad connection component includes a test pad connection buried electrode and a test pad connection buried cover layer disposed on the test pad connection buried electrode.

[0010] According to one embodiment of this disclosure, a semiconductor device includes: a substrate having a chip region defined by scribe lines and a guard ring region, the guard ring region being configured to surround the chip region; a guard ring structure disposed on the substrate and in the guard ring region; a circuit structure disposed on the substrate and in at least one scribe line or in the guard ring region; a pad structure disposed on the substrate and in the chip region; a pad connection component electrically connecting the circuit structure to the pad structure passing through the guard ring structure; and a cell structure disposed in the chip region. The pad connection component includes: a pad connection buried electrode embedded in the substrate; and a pad connection buried capping layer disposed above the pad connection buried electrode. The cell structure includes: a cell isolation region in the substrate for defining a cell active region, and a buried gate line embedded in the substrate. The buried gate line includes a buried gate electrode and a buried gate capping layer disposed above the buried gate electrode. The pad connection buried electrode and the buried gate electrode are disposed at the same level. The pad connection buried capping layer and the buried gate capping layer are disposed at the same level.

[0011] These and other features and advantages of the embodiments of this disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0012] Figure 1A This is a schematic diagram of a wafer according to an embodiment of the present disclosure. Figure 1B for Figure 1A A magnified view of region A in the middle.

[0013] Figures 2A to 2C To show Figure 1B The diagram shows an enlarged view of the protection ring area and part of the chip area.

[0014] Figures 3A to 3D A top view showing a portion of the swivel region, a portion of the guard ring region, a portion of the cell region in the chip region, and a portion of the peripheral circuit region in the chip region of a semiconductor device.

[0015] Figures 4 to 7 A longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown for illustrative purposes.

[0016] Figure 8A For along Figure 3A The longitudinal cross-section diagram taken from line I-I'. Figure 8B For along Figure 3A The longitudinal cross-section diagram taken from line V-V'.

[0017] Figure 9 For along Figure 3A The line VI-VI' or Figure 3B The longitudinal cross-section diagram taken from line VII-VII'.

[0018] Figure 10 For along Figure 3B The longitudinal cross-section diagram taken from line VIII-VIII'.

[0019] Figures 11A to 11D For along Figure 3B The longitudinal cross-section diagram taken by line IX-IX'. Detailed Implementation

[0020] The embodiments disclosed herein will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions of the particular embodiments are merely examples used to illustrate the technical concepts disclosed in this application. However, it should be understood that those skilled in the art can implement other examples or embodiments based on the technical concepts of this disclosure in various forms without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples or embodiments described.

[0021] All the crosshairs in the diagram represent corresponding or similar areas between the diagrams, rather than representing material related to those areas.

[0022] When one element is labeled "connected" or "coupled" to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between them. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or coupled to the other element, and there is no intermediate element between the two elements.

[0023] When one element is identified as being "above", "on top of", "below", or "under" another element, the two elements can be in direct contact, or an intermediate element can be placed between the two elements.

[0024] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “above,” “upper,” “side,” “upper part,” “topmost,” “lowest,” “front,” “back,” “left,” “right,” “column,” “row,” “horizontal,” and other terms indicating relative spatial relationships or directions are used for ease of description or reference to the accompanying drawings only and are not intended to be limiting. Other spatial relationships or directions not shown in the drawings or described in the specification are also possible within the scope of this disclosure.

[0025] Terms such as "first" and "second" are used to distinguish individual elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element might be referred to as the second element, while in another example, the second element might be referred to as the first element.

[0026] In the specification, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0027] The above concepts have been disclosed in conjunction with the examples and embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered exemplary, not restrictive. Therefore, the scope of this disclosure is not limited to the above description. All changes within the equivalent meaning and scope of the claims are included within its scope.

[0028] Figure 1A To illustrate a diagram of a wafer W according to an embodiment of the present disclosure, Figure 1B for Figure 1A A magnified view of region A in the image. (Reference) Figure 1A and Figure 1B The wafer W may include multiple semiconductor chips CH arranged in a matrix. The multiple semiconductor chips CH may be separated by scribes SL arranged in a grid. Each semiconductor chip CH may include a chip region CA and a guard ring region GR. The chip region CA may include a cell region and a peripheral circuit region. Memory cells may be disposed in the cell region, and peripheral circuits may be disposed in the peripheral circuit region. The guard ring region GR may be disposed adjacent to the scribes SL to surround the chip region CA.

[0029] Figures 2A to 2C for Figure 1B Enlarged view of the middle guard ring region and a portion of the chip region. (Reference) Figure 2AThe semiconductor chip CH may include a chip region CA defined by a scribe line SL and a guard ring region GR. The guard ring region GR may surround the chip region CA. The semiconductor chip CH may also include a test circuit TC disposed in the scribe line SL, and a first test pad TP1 and a second test pad TP2 disposed in the chip region CA. Both the first test pad TP1 and the second test pad TP2 are electrically connected to the test circuit TC. For example, the first test pad TP1 and the second test pad TP2 may correspond to portions of the test circuit TC, such as a first terminal and a second terminal, respectively. Therefore, a portion of the test circuit TC may pass through the guard ring region GR.

[0030] refer to Figure 2B The semiconductor chip CH may include an inner guard ring GRi, an outer guard ring GRo, and a crack detection circuit CDC disposed in a guard ring region GR, and may include a first crack detection pad CP1 and a second crack detection pad CP2 disposed in a chip region CA. The crack detection circuit CDC is configured to monitor cracks or defects (including fine lines, sidewall cracks, internal cracks, or back-side cracks) during the manufacturing process of the semiconductor chip CH. The inner guard ring GRi, the outer guard ring GRo, and the crack detection circuit CDC may all be in the form of a rectangular frame in a top view. The crack detection circuit CDC may be disposed between the inner guard ring GRi and the outer guard ring GRo. The first crack detection pad CP1 and the second crack detection pad CP2 may be disposed in the chip region CA. The first crack detection pad CP1 and the second crack detection pad CP2 may be electrically connected to the crack detection circuit CDC. For example, the first crack detection pad CP1 and the second crack detection pad CP2 may respectively correspond to portions of the crack detection circuit CDC, such as a first terminal and a second terminal. Therefore, a portion of the crack detection circuit CDC can pass through the inner protection ring GRi to be electrically connected to the first crack detection pad CP1 and the second crack detection pad CP2, respectively.

[0031] refer to Figure 2C The semiconductor chip CH may include a chip region CA defined by a scribe line SL and a guard ring region GR. The guard ring region GR may surround the chip region CA. The semiconductor chip CH may include a test circuit TC disposed in the scribe line SL, an inner guard ring GRi, an outer guard ring GRo, and a crack detection circuit CDC disposed in the guard ring region GR, and a first crack detection pad CP1, a second crack detection pad CP2, a first test pad TP1, and a second test pad TP2 disposed in the chip region CA. A portion of the crack detection circuit CDC may pass through the inner guard ring GRi, and a portion of the test circuit TC may pass through the inner guard ring GRi, the outer guard ring GRo, and the crack detection circuit CDC.

[0032] Figures 3A to 3DIt is a top view showing a portion of the swivel SL of a semiconductor device, a portion of the guard ring region GR, a portion of the cell region in the chip region CA, and a portion of the peripheral circuit region in the chip region CA.

[0033] refer to Figure 3A The semiconductor device may include a test circuit TC disposed in a scribe line SL, a guard ring structure GSa, test pads TP1 and TP2 disposed in a chip region CA, and test pad connection components 25 and 26 disposed in a guard ring region GR. The guard ring structure GSa may include a plurality of guard rings spaced apart from each other in a first horizontal direction X and extending parallel to each other in a second horizontal direction Y. Test pad connection components 25 and 26 may pass through the guard ring structure GSa. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other.

[0034] refer to Figure 3B The semiconductor device may include a guard ring structure GSb disposed in a guard ring region GR, crack detection pads CP1 and CP2 disposed in a chip region CA, and crack detection pad connection components 23 and 24 passing through a portion of the guard ring region GR and a portion of the chip region CA. The guard ring structure GSb may include an inner guard ring structure GSi, an outer guard ring structure GSo, and a crack detection circuit structure CDS located between the inner guard ring structure GSi and the outer guard ring structure GSo, which are spaced apart from each other in a first horizontal direction X and extend parallel to each other in a second horizontal direction Y. Both the inner guard ring structure GSi and the outer guard ring structure GSo may include multiple parallel guard rings. The crack detection pad connection components 23 and 24 may pass through the inner guard ring structure GSi.

[0035] refer to Figure 3C The semiconductor device may include a cell structure CS in a cell region of a chip region CA. The cell structure CS may include a cell active region 8, buried gate lines 28, and bit lines 38. The cell active region 8 may be defined by a cell isolation (e.g., shallow trench isolation) region 18. Each cell active region 8 may be a segment shape extending diagonally. The buried gate lines 28 may extend parallel to each other to pass through the cell active region 8 in a first horizontal direction X. Two buried gate lines 28 may pass through one cell active region 8. The buried gate lines 28 may be cell word lines. Each bit line 38 may extend parallel to each other to pass through the center of each cell active region 8 in a second horizontal direction Y.

[0036] refer to Figure 3DThe semiconductor device may include a peripheral transistor structure TS in a peripheral circuit region of a chip region CA. The peripheral transistor structure TS may include a peripheral active region 9, a peripheral gate electrode 39, and peripheral interconnects 99. The peripheral active region 9 may be defined by a peripheral isolation (e.g., shallow trench isolation, STI) region 19. The peripheral gate electrode 39 may be configured to pass through the peripheral active region 19. The peripheral interconnects 99 may extend in the form of lines along a second horizontal direction Y to overlap a portion of the peripheral active region 9.

[0037] Figures 4 to 7 A longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown for illustrative purposes. Figure 4 For along Figure 3A The longitudinal cross-section diagram taken from line I-I' in the diagram. Figure 5 For along Figure 3B The longitudinal cross-section diagram taken from line II-II' in the figure. Figure 6 For along Figure 3C The longitudinal cross-section diagram taken from line III-III' in the figure. Figure 7 For along Figure 3D The longitudinal cross-section diagram taken from line IV-IV' in the figure.

[0038] refer to Figure 4 The semiconductor device may include a guard ring structure GSa, a test circuit structure TCS, a test pad structure TPS, and a test pad connection component 25. The semiconductor device may also include a lower interlayer insulating layer I1, a middle-lower interlayer insulating layer I2, a middle-upper interlayer insulating layer I3, and an upper interlayer insulating layer I4.

[0039] In the vertical direction Z, the guard ring structure GSa may include a lower guard ring electrode 30, a lower guard ring plug 40, a lower guard ring pad 50, a middle guard ring plug 60, a middle guard ring pad 70, an upper guard ring plug 80, and an upper guard ring pad 90.

[0040] The lower guard ring electrode 30 can be directly disposed on the substrate Sub. The vertical direction Z can be perpendicular to the first horizontal direction X and the second horizontal direction Y. The lower guard ring electrode 30 can be directly formed on the surface of the substrate Sub. The lower guard ring electrode 30 may include an insulating lower layer, a conductive intermediate layer, and an insulating upper layer. The lower guard ring plug 40 can be disposed on the lower guard ring electrode 30 to pass perpendicularly through the lower interlayer insulating layer I1. The lower guard ring plug 40 can pass perpendicularly through the insulating upper layer of the lower guard ring electrode 30 to be electrically connected to the conductive intermediate layer of the lower guard ring electrode 30. The lower guard ring pad 50 can be disposed on the lower guard ring plug 40 and the lower interlayer insulating layer I1. The lower guard ring pad 50 can be perpendicularly overlapped with and electrically connected to the lower guard ring plug 40. The middle guard ring plug 60 can pass perpendicularly through the upper middle interlayer insulating layer I3 and the lower middle interlayer insulating layer I2 to be perpendicularly overlapped with and electrically connected to the lower guard ring pad 50. The guard ring intermediate pad 70 can be disposed on the guard ring intermediate plug 60 and the upper interlayer insulation layer I3. The guard ring intermediate pad 70 can be perpendicularly overlapped with and electrically connected to the guard ring intermediate plug 60. The guard ring upper plug 80 can be perpendicularly passed through the upper interlayer insulation layer I4 to be perpendicularly overlapped with and electrically connected to the guard ring intermediate pad 70. The guard ring upper pad 90 can be disposed on the guard ring upper plug 80 and the upper interlayer insulation layer I4. The guard ring upper pad 90 can be perpendicularly overlapped with and electrically connected to the guard ring upper plug 80.

[0041] The lower guard ring electrode 30, lower guard ring pad 50, middle guard ring pad 70, and upper guard ring pad 90 can all have a line shape extending along a first horizontal direction X or a second horizontal direction Y. The lower guard ring plug 40, middle guard ring plug 60, and upper guard ring plug 80 can all have a wall shape extending along a second horizontal direction Y and a vertical direction Z. The lower guard ring electrode 30, lower guard ring plug 40, lower guard ring pad 50, middle guard ring plug 60, middle guard ring pad 70, upper guard ring plug 80, and upper guard ring pad 90 can all include conductors, such as metals, metal alloys, or metal nitrides.

[0042] The Test Circuit Structure (TCS) may include a lower test circuit contact plug 45, a lower test circuit contact pad 55, an upper test circuit contact plug 65, and an upper test circuit contact pad 75. The lower test circuit contact plug 45 may pass vertically through the lower interlayer insulation layer I1 for physical and electrical connection with the test pad connection component 25. The lower test circuit contact pad 55 may be disposed on the lower test circuit contact plug 45 and the lower interlayer insulation layer I1, perpendicularly overlapping and electrically connected to the lower test circuit contact plug 45. The upper test circuit contact plug 65 may pass vertically through the upper middle interlayer insulation layer I3 and the lower middle interlayer insulation layer I2 for electrical connection with the lower test circuit contact pad 45. The upper test circuit contact pad 75 may be disposed on the upper test circuit contact plug 65 and the upper middle interlayer insulation layer I3, perpendicularly overlapping and electrically connected to the upper test circuit contact plug 65. Both the lower test circuit contact pad 55 and / or the upper test circuit contact pad 75 may be in the shape of a horizontally elongated segment. The components of the Test Circuit Structure (TCS) may include at least one of a capacitor structure, a resistor structure, a transistor structure, or a bridge structure. The lower contact plug 45, the lower contact pad 55, the upper contact plug 65, and the upper contact pad 75 may all include conductors, such as metals, metal alloys, or metal nitrides.

[0043] The test pad structure TPS may include a lower test pad contact plug 46, a lower test pad contact pad 56, a middle test pad contact plug 66, a middle test pad contact pad 76, an upper test pad contact plug 86, and an upper test pad contact pad 96. The lower test pad contact plug 46 may pass vertically through the lower interlayer insulation layer I1 for physical and electrical connection with the test pad connection component 25. The lower test pad contact pad 56 may be disposed on the lower test pad contact plug 46 and the lower interlayer insulation layer I1, perpendicularly overlapping and electrically connected to the lower test pad contact plug 46. The middle test pad contact plug 66 may pass vertically through the upper middle interlayer insulation layer I3 and the lower middle interlayer insulation layer I2, perpendicularly overlapping and electrically connected to the lower test pad contact pad 56. The middle test pad contact pad 76 may be disposed on the middle test pad contact plug 66 and the upper middle interlayer insulation layer I3. The test pad center contact pad 76 can be perpendicularly overlapped and electrically connected to the test pad center contact plug 66. The test pad upper contact plug 86 can be perpendicularly passed through the upper interlayer insulation layer I4 to be perpendicularly overlapped and electrically connected to the test pad center contact pad 76. The test pad upper contact pad 96 can be disposed on the test pad upper contact plug 86 and the upper interlayer insulation layer I4. The test pad upper contact pad 96 can be perpendicularly overlapped and electrically connected to the test pad upper contact plug 86. The test pad upper contact pad 96 can correspond to Figure 2A , 2CThe first test pad TP1 in 3A. The lower test pad 56, the middle test pad 76, and the upper test pad 96 may have a segmental shape extending along a first horizontal direction X or a second horizontal direction Y. The lower test pad plug 46, the middle test pad plug 66, and the upper test pad plug 86 may have a column shape extending along a vertical direction Z. The lower test pad plug 46, the lower test pad plug 56, the middle test pad plug 66, the middle test pad plug 76, the upper test pad plug 86, and the upper test pad plug 96 may all include a conductor, such as a metal, a metal alloy, or a metal nitride.

[0044] Test pad connection component 25 may be embedded in a guard ring isolation (shallow trench isolation, STI) region 10 formed in the substrate Sub. Test pad connection component 25 may include a test pad connection embedded electrode 25a and a test pad connection embedded cover layer 25b. Test pad connection embedded electrode 25a may include a conductor, such as a metal, metal alloy, or metal nitride. Test pad connection embedded cover layer 25b may include a silicon nitride layer. The test circuit lower contact plug 45 and the test pad connection embedded electrode 25a of test pad connection component 25 may include the same material. Therefore, the test circuit lower contact plug 45 and test pad connection component 25 can be bonded very firmly compared to materials that are different from each other. A lower interlayer insulating layer I1 may be disposed on the substrate Sub to surround the sides of the guard ring lower electrode 30, guard ring lower plug 40, test circuit lower contact plug 45, and test pad lower contact plug 46. The middle and lower interlayer insulation layer I2 can be disposed on the lower interlayer insulation layer I1 to surround the sides of the lower pad 50 of the protection ring, the middle plug 60 of the protection ring, the lower contact pad 55 of the test circuit, the middle contact plug 65 of the test circuit, the lower contact pad 56 of the test pad, and the middle contact plug 66 of the test pad.

[0045] The upper-middle interlayer insulation layer I3 can be disposed on the lower-middle interlayer insulation layer I2 to surround the sides of the middle plug 60 of the guard ring, the upper contact plug 65 of the test circuit, and the middle contact plug 66 of the test pad. The upper interlayer insulation layer I4 can be disposed on the upper-middle interlayer insulation layer I3 to surround the sides of the middle pad 70 of the guard ring, the upper plug 80 of the guard ring, the upper contact pad 75 of the test circuit, the middle contact pad 76 of the test pad, and the upper contact plug 86 of the test pad.

[0046] The pads 90 on the guard ring of the guard ring structure GSa can correspond to the uppermost metal layer of the semiconductor device and can contact probes for testing. The guard ring structure GSa can have a lossless connection structure from the substrate Sub surface to the uppermost metal layer. Therefore, the guard ring structure GSa can prevent moisture penetration and crack propagation from the scribe line SL to the chip region CA.

[0047] refer to Figure 5 The semiconductor device may include a guard ring structure GSb, a crack detection pad structure CPS, and a crack detection pad connection component 23. The guard ring structure GSb may include an inner guard ring structure GSi, an outer guard ring structure GSo, and a crack detection circuit structure CDS. The semiconductor device may also include a lower interlayer insulating layer I1, a middle-lower interlayer insulating layer I2, a middle-upper interlayer insulating layer I3, and an upper interlayer insulating layer I4.

[0048] The inner guard ring structure GSi may include an inner guard ring lower electrode 31, an inner guard ring lower plug 41, an inner guard ring lower pad 51, an inner guard ring intermediate plug 61, an inner guard ring intermediate pad 71, an inner guard ring upper plug 81, and an inner guard ring upper pad 91. The inner guard ring lower electrode 31 may be directly formed on the surface of the substrate Sub. The inner guard ring lower electrode 31 may include an insulating lower layer, a conductive intermediate layer, and an insulating upper layer. The inner guard ring lower plug 41 may perpendicularly pass through the lower interlayer insulating layer I1 and may be disposed on the inner guard ring lower electrode 31. The inner guard ring lower plug 41 may perpendicularly pass through the insulating upper layer of the inner guard ring lower electrode 31 to be electrically connected to the conductive intermediate layer of the inner guard ring lower electrode 31. The inner guard ring lower pad 51 may be disposed on the inner guard ring lower plug 41 and the lower interlayer insulating layer I1. The inner guard ring lower pad 51 may perpendicularly overlap with and be electrically connected to the inner guard ring lower plug 41. The inner protective ring's intermediate plug 61 can pass vertically through the upper and middle interlayer insulation layers I3 and I2, so as to vertically overlap and electrically connect with the lower pad 51 of the inner protective ring. The inner protective ring's intermediate pad 71 can be disposed on the inner protective ring's intermediate plug 61 and the upper and middle interlayer insulation layers I3. The inner protective ring's intermediate pad 71 can vertically overlap and electrically connect with the inner protective ring's intermediate plug 61. The inner protective ring's upper plug 81 can pass vertically through the upper interlayer insulation layer I4, so as to vertically overlap and electrically connect with the inner protective ring's intermediate pad 71. The inner protective ring's upper pad 91 can be disposed on the inner protective ring's upper plug 81 and the upper interlayer insulation layer I4. The inner protective ring's upper pad 91 can vertically overlap and electrically connect with the inner protective ring's upper plug 81. The lower electrode 31, lower pad 51, middle pad 71, and upper pad 91 of the inner protective ring can all be segmented in shape extending along the first horizontal direction X and linear in shape extending along the second horizontal direction Y. The lower plug 41, middle plug 61, and upper plug 81 of the inner protective ring can all be wall-shaped extending along the vertical direction Z. The lower electrode 31, lower plug 41, lower pad 51, middle plug 61, middle pad 71, upper plug 81, and upper pad 91 of the inner protective ring can all include conductors such as metal, metal alloy, or metal nitride.

[0049] The outer guard ring structure GSo may include a lower outer guard ring plug 42, a lower outer guard ring pad 52, a middle outer guard ring plug 62, a middle outer guard ring pad 72, an upper outer guard ring plug 82, and an upper outer guard ring pad 92. The lower outer guard ring plug 42 may perpendicularly pass through the lower interlayer insulating layer I1. The guard ring isolation region 10 in the substrate Sub may define the guard ring active region 3. The lower outer guard ring pad 52 may be disposed on the lower outer guard ring plug 42 and the lower interlayer insulating layer I1. The lower outer guard ring pad 52 may perpendicularly overlap and be electrically connected to the lower outer guard ring plug 42. The middle outer guard ring plug 62 may perpendicularly pass through the upper middle interlayer insulating layer I3 and the lower middle interlayer insulating layer I2 to perpendicularly overlap and be electrically connected to the lower outer guard ring pad 52. The middle outer guard ring pad 72 may be disposed on the middle outer guard ring plug 62 and the upper middle interlayer insulating layer I3. The outer protective ring intermediate pad 72 can be perpendicularly overlapped and electrically connected to the outer protective ring intermediate plug 62. The outer protective ring upper plug 82 can be perpendicularly passed through the upper interlayer insulation layer I4 to be perpendicularly overlapped and electrically connected to the outer protective ring intermediate pad 72. The outer protective ring upper pad 92 can be disposed on the outer protective ring upper plug 82 and the upper interlayer insulation layer I4. The outer protective ring upper pad 92 can be perpendicularly overlapped and electrically connected to the outer protective ring upper plug 82. The outer protective ring lower pad 52, the outer protective ring intermediate pad 72, and the outer protective ring upper pad 92 can all have a segment shape extending along the first horizontal direction X and a line shape extending along the second horizontal direction Y. The outer protective ring lower plug 42, the outer protective ring intermediate plug 62, and the outer protective ring upper plug 82 can all have a wall shape extending along the vertical direction Z. The lower plug 42 of the outer protection ring, the lower pad 52 of the outer protection ring, the middle plug 62 of the outer protection ring, the middle pad 72 of the outer protection ring, the upper plug 82 of the outer protection ring, and the upper pad 92 of the outer protection ring may all include conductors, such as metals, metal alloys, or metal nitrides.

[0050] The crack detection circuit structure CDS may include a lower contact plug 43, a lower contact pad 53, a middle contact plug 63, a middle contact pad 73, an upper contact plug 83, and an upper contact pad 93. The lower contact plug 43 can pass vertically through the lower interlayer insulation layer I1 to achieve physical and electrical connection with the crack detection pad connection component 23. The lower contact pad 53 can be disposed on the lower contact plug 43 and the lower interlayer insulation layer I1. The lower contact pad 53 can vertically overlap and be electrically connected to the lower contact plug 43. The middle contact plug 63 can vertically pass through the upper-middle interlayer insulation layer I3 and the lower-middle interlayer insulation layer I2 to vertically overlap and be electrically connected to the lower contact pad 53. The intermediate contact pad 73 of the crack detection circuit can be disposed on the intermediate contact plug 63 of the crack detection circuit and the upper interlayer insulation layer I3. The intermediate contact pad 73 of the crack detection circuit can be perpendicularly overlapped with and electrically connected to the intermediate contact plug 63 of the crack detection circuit. The upper contact plug 83 of the crack detection circuit can pass perpendicularly through the upper interlayer insulation layer I4 to be perpendicularly overlapped with and electrically connected to the intermediate contact pad 73 of the crack detection circuit. The upper contact pad 93 of the crack detection circuit can be disposed on the upper contact plug 83 of the crack detection circuit and the upper interlayer insulation layer I4. The upper contact pad 93 of the crack detection circuit can be perpendicularly overlapped with and electrically connected to the upper contact plug 83 of the crack detection circuit. The lower contact pad 53, the intermediate contact pad 73, and the upper contact pad 93 of the crack detection circuit can all be in the shape of a segment extending along the first horizontal direction X or the second horizontal direction Y. The lower contact plug 43, the intermediate contact plug 63, and the upper contact plug 83 of the crack detection circuit can all be cylindrical in shape, extending along the vertical direction Z. The lower contact plug 43, the lower contact pad 53, the intermediate contact plug 63, the intermediate contact pad 73, the upper contact plug 83, and the upper contact pad 93 of the crack detection circuit can all include conductors, such as metals, metal alloys, or metal nitrides.

[0051] The crack detection pad structure CPS may include a lower contact plug 44, a lower contact pad 54, a middle contact plug 64, a middle contact pad 74, an upper contact plug 84, and an upper contact pad 94. The lower contact plug 44 can pass vertically through the lower interlayer insulation layer I1 to achieve physical and electrical connection with the crack detection pad connection component 23. The lower contact pad 54 can be disposed on the lower contact plug 44 and the lower interlayer insulation layer I1, perpendicularly overlapping and electrically connected to the lower contact plug 44. The middle contact plug 64 can pass vertically through the upper middle interlayer insulation layer I3 and the lower middle interlayer insulation layer I2 to perpendicularly overlap and electrically connect to the lower contact pad 54. The crack detection pad intermediate contact pad 74 can be disposed on the crack detection pad intermediate contact plug 64 and the upper interlayer insulation layer I3. The crack detection pad intermediate contact pad 74 can be perpendicularly overlapped with and electrically connected to the crack detection pad intermediate contact plug 64. The crack detection pad upper contact plug 84 can be perpendicularly passed through the upper interlayer insulation layer I4 and perpendicularly overlapped with and electrically connected to the crack detection pad intermediate contact pad 74. The crack detection pad upper contact pad 94 can be disposed on the crack detection pad upper contact plug 84 and the upper interlayer insulation layer I4. The crack detection pad upper contact pad 94 can be perpendicularly overlapped with and electrically connected to the crack detection pad upper contact plug 84. The crack detection pad lower contact pad 54, the crack detection pad intermediate contact pad 74, and the crack detection pad upper contact pad 94 can all be in the shape of a segment extending along the first horizontal direction X or the second horizontal direction Y. The lower contact plug 44, the middle contact plug 64, and the upper contact plug 84 of the crack detection pad can all be cylindrical in shape, extending Z-direction vertically. The lower contact plug 44, the lower contact pad 54, the middle contact plug 64, the middle contact pad 74, the upper contact plug 84, and the upper contact pad 94 of the crack detection pad can all include a conductor, such as a metal, a metal alloy, or a metal nitride.

[0052] The crack detection connection component 23 may be embedded in the protective ring isolation region 10 formed in the substrate Sub. The crack detection pad connection component 23 may include a crack detection pad connection buried electrode 23a and a crack detection pad connection buried cover layer 23b. The crack detection pad connection buried electrode 23a may include a conductor, such as a metal, metal alloy, or metal nitride. The crack detection pad connection buried cover layer 23b may include a silicon nitride-based insulating layer. The crack detection circuit under-contact plug 43, the crack detection pad under-contact plug 44, and the crack detection pad connection buried electrode 23a of the crack detection pad connection component 23 may include the same material. Therefore, compared to materials that are different from each other, the adhesion and bonding between the crack detection circuit under-contact plug 43 and the crack detection pad connection buried electrode 23a, and the adhesion and bonding between the crack detection pad under-contact plug 44 and the crack detection pad connection buried electrode 23a, can be very strong.

[0053] The pads 91 on the inner guard ring and 92 on the outer guard ring of the guard ring structure GSb can correspond to the uppermost metal layer of the semiconductor device and can contact a probe used for crack detection. The inner guard ring structure GSi and the outer guard ring structure GSo of the guard ring structure GSb can have a lossless connection structure from the substrate Sub surface to the uppermost metal layer. Therefore, the guard ring structure GSb can prevent moisture penetration and crack propagation from the scribe line SL to the chip region CA.

[0054] refer to Figure 6 A semiconductor device according to one embodiment of the present disclosure may include a cell structure CS. The cell structure CS may include a cell isolation region 18 and a buried gate line 28 located in a substrate Sub, and bit line contact plugs 37, bit lines 38, memory contact plugs 48, memory contact pads 58, and memory electrodes 68 located on the substrate Sub in the vertical direction Z. The semiconductor device may also include a lower interlayer insulating layer I1, a middle lower interlayer insulating layer I2, a middle upper interlayer insulating layer I3, and an upper interlayer insulating layer I4. The cell isolation region 18 may define a cell active region 8. The cell isolation region 18 may include an insulating material. The buried gate line 28 may include a buried gate electrode 28a and a buried gate capping layer 28b formed in a buried gate trench Tb. The buried gate electrode 28a may include a conductor, such as a metal, a metal alloy, or a metal nitride. The buried gate electrode 28a may be formed larger and deeper in the cell isolation region 18 than in the cell active region 8. The buried gate line 28 may be formed with the same structure and level as the crack detection pad connection components 23a and 24a and the test pad connection components 25a and 26a, and may include the same material.

[0055] Bit line contact plug 37 may be in the form of a pillar electrically connected to the central portion of the active region 8 of the cell. Bit line contact plug 37 may include at least one of doped silicon, metal silicide, metal nitride, metal, or metal alloy. Bit line 38 may be electrically connected to bit line contact plug 37 and extend in a horizontal direction. Bit line 38 may include an insulating lower layer, a conductive intermediate layer, and an insulating upper layer. The conductive intermediate layer of bit line 38 may be directly connected to the upper surface of bit line contact plug 37. Bit line contact plug 37 may pass through the insulating lower layer to be electrically connected to the conductive intermediate layer.

[0056] All storage contact plugs 48 may be cylindrical in shape, perpendicularly passing through the lower interlayer insulating layer I1, to electrically connect to portions on both sides of the active region 8 of the cell. Storage contact plugs 48 may include at least one of doped silicon, metal silicide, metal nitride, metal, or metal alloy. Storage contact pads 58 may be disposed on the lower interlayer insulating layer I1, between the storage contact plugs 48 and the storage electrode 68, and electrically connected to both the storage contact plugs 48 and the storage electrode 68. Storage contact pads 58 may include at least one of doped silicon, metal silicide, metal nitride, metal, or metal alloy. Storage electrode 68 may perpendicularly pass through the middle and lower interlayer insulating layer I2 and may be disposed on the storage contact pads 58. Storage electrode 68 may include at least one of doped silicon, metal silicide, metal nitride, metal, or metal alloy.

[0057] The lower interlayer insulating layer I1 may surround the sides of the bit line contact plug 37, bit line 38, and storage contact plug 48. The lower interlayer insulating layer I1 may surround a portion of the lower surface and the upper surface of the bit line 38. The middle lower interlayer insulating layer I2 may surround the sides of the storage contact pad 58 and the storage electrode 68. The middle lower interlayer insulating layer I2 may cover a portion of the upper surface of the storage contact pad 58. The middle upper interlayer insulating layer I3 may be disposed on the upper surface of the storage electrode 68. That is, the middle upper interlayer insulating layer I3 may not surround the sides of the storage electrode 68.

[0058] refer to Figure 7A semiconductor device according to one embodiment of the present disclosure may include a peripheral transistor structure TS. The peripheral transistor structure TS may include, in the vertical direction Z, a peripheral isolation region 19 in a substrate Sub, and a peripheral gate electrode 39, a peripheral lower contact plug 49, a peripheral lower contact pad 59, a peripheral upper contact pad 79, a peripheral upper contact plug 89, and a peripheral interconnect 99 on the substrate Sub. The peripheral isolation region 19 may define a peripheral active region 9. The peripheral isolation region 19 may include an insulating material. The peripheral gate electrode 39 may include a conductor. The peripheral gate electrode 39 may have the same structure as the bit line 38 of the cell structure CS. For example, the peripheral gate electrode 39 may include an insulating lower layer, a conductive intermediate layer, and an insulating upper layer, respectively corresponding to features of the bit line 38 of the cell structure CS. The peripheral lower contact plug 49 may pass vertically through the interlayer insulating layer I1 and be physically and electrically connected to the peripheral active region 9 of the substrate Sub. The peripheral lower contact pad 59 may be disposed on the peripheral lower contact plug 49 and the interlayer insulating layer I1. The peripheral lower contact pad 59 can be perpendicularly overlapped and electrically connected to the peripheral lower contact plug 49. The peripheral intermediate contact plug 69 can be perpendicularly passed through the upper-middle interlayer insulation layer I3 and the lower interlayer insulation layer I2 to be perpendicularly overlapped and electrically connected to the peripheral lower contact pad 59. The peripheral intermediate contact pad 79 can be disposed on the peripheral intermediate contact plug 69 and the upper-middle interlayer insulation layer I3. The peripheral intermediate contact pad 79 can be perpendicularly overlapped and electrically connected to the peripheral intermediate contact plug 69. The peripheral upper contact plug 89 can be perpendicularly passed through the upper interlayer insulation layer I4 to be perpendicularly overlapped and electrically connected to the peripheral intermediate contact pad 79. The peripheral upper contact pad 99 can be disposed on the peripheral upper contact plug 89 and the upper interlayer insulation layer I4. The peripheral upper contact pad 99 can be perpendicularly overlapped and electrically connected to the peripheral upper contact plug 89.

[0059] Figure 8A For along Figure 3A The longitudinal cross-section diagram taken from line I-I' in the diagram. Figure 8B For along Figure 3A The longitudinal cross-section diagram taken by line V-V' in the figure. (Reference) Figure 8A and Figure 8BThe semiconductor device may include a guard ring structure GSa, a test circuit structure TCS, a test pad structure TPS, and a test pad connection component 25. The guard ring structure GSa may be disposed on a guard ring isolation region 10 formed in a substrate Sub. The lower guard ring electrode 30 may be electrically insulated from the guard ring active region 3 through the guard ring isolation region 10. The lower guard ring electrode 30 may be electrically insulated from the test pad connected buried cover layer 25b through the test pads to the buried electrode 25a. The lower guard ring electrode 30 may be electrically insulated from the lower guard ring electrode 3 through the guard ring isolation region 10. The test pad connection component 25 may pass through the guard ring isolation region 10 in a first horizontal direction X. A portion of the test pad connected to the buried electrode 25a in the guard ring isolation region 10 may be formed deeper and larger than a portion of the test pad connected to the buried electrode 25a in the guard ring active region 3.

[0060] Figure 9 It is along Figure 3A The line VI-VI' in the middle or Figure 3B The longitudinal cross-section diagram taken from line VII-VII' in the figure. (See figure) Figure 9 As shown, the guard ring structures GSa and GSi may include lower guard ring electrodes 30 and 31, lower guard ring plugs 40 and 41, lower guard ring pads 50 and 51, middle guard ring plugs 60 and 61, middle guard ring pads 70 and 71, upper guard ring plugs 80 and 81, and upper guard ring pads 90 and 91. Crack detection pad connection components 23 and 24 and / or test pad connection components 25 and 26 may pass through the lower part of the guard ring structures GSa and GSi.

[0061] The lower guard ring electrodes 30 and 31, as well as the upper contact pads 90 and 91, can all have a line shape extending along the second horizontal direction Y. The lower guard ring electrodes 30 and 31, the lower guard ring pads 50 and 51, the middle guard ring pad 70, and the upper guard ring pads 90 and 91 can all have a wall shape extending along the second direction Y and the vertical direction Z.

[0062] Crack detection pad connection components 23 and 24 and / or test pad connection components 25 and 26 may be embedded in the guard ring isolation region 10 in the substrate Sub. The lower electrodes 30 and 31 of the guard ring may be connected to the buried cover layers 23b and 24b via crack detection pads and / or the buried cover layers 25b and 26b via test pads, and the buried electrodes 23a and 24a and / or the buried electrodes 25a and 26a via crack detection pads, providing electrical insulation.

[0063] Figure 10 It is along Figure 3B The longitudinal cross-section diagram taken from line VIII-VIII' in the figure. (Reference) Figure 10The outer guard ring structure GSo may include a lower outer guard ring plug 42, a lower outer guard ring pad 52, a middle outer guard ring plug 62, a middle outer guard ring pad 72, an upper outer guard ring plug 82, and an upper outer guard ring pad 92. The guard ring isolation region 10 may define the active region 3 of the guard ring. The lower guard ring plug 42 may be adjacent to the active region 3 of the guard ring and the guard ring isolation region 10.

[0064] Figures 11A to 11D For along Figure 3B The longitudinal cross-section taken by line IX-IX' in the diagram. (Reference) Figures 11A to 11D Each semiconductor device may include a crack detection circuit structure CDS and crack detection pad connection components 23 and 24.

[0065] refer to Figure 11A The crack detection circuit structure CDS may include a lower contact plug 43, a lower contact pad 53, a middle contact plug 63, a middle contact pad 73, an upper contact plug 83, and an upper contact pad 93. Crack detection pad connection components 23 and 24 may be embedded in the protective ring isolation region 10 of the substrate Sub.

[0066] The lower contact pad 53 of the crack detection circuit can be spaced apart from the substrate Sub in the vertical direction Z and can be disposed on the lower interlayer insulating layer I1. Each lower contact pad 53 of the crack detection circuit can be in the shape of a segment extending along the second horizontal direction Y. The lower contact pad 53 of the crack detection circuit can be electrically connected to the intermediate contact plug 63 of the crack detection circuit that is adjacent to each other along the second horizontal direction Y.

[0067] The lower contact pad 53 and the upper contact pad 93 of the crack detection circuit can be staggered. In the second horizontal direction Y, the lower contact pad 53 of the crack detection circuit can electrically connect the odd-numbered lower contact plugs 43 and even-numbered lower contact plugs 43 of the crack detection circuit to each other. In the second horizontal direction Y, the upper contact pad 93 of the crack detection circuit can electrically connect the even-numbered upper contact plugs 83 and odd-numbered upper contact plugs 83 of the crack detection circuit to each other.

[0068] Some crack detection circuit lower contact pads 53 may not extend or elongate in the second horizontal direction Y. Each crack detection circuit lower contact plug 43 may be perpendicular to and electrically connected to the crack detection circuit lower contact pad 53 that does not extend to one of the crack detection pad connection components 23 and 24. Crack detection pad connection components 23 and 24 may include a first crack detection pad connection component 23 and a second crack detection pad connection component 24. The first and second crack detection pad connection components 23 and 24 may respectively include first and second crack detection pad connection buried electrodes 23a and 24a and first and second crack detection pad connection buried capping layers 23b and 24b. Therefore, the crack detection circuit lower contact plug 43 may be electrically connected to the first and second crack detection pad connection buried electrodes 23a and 24a, respectively.

[0069] refer to Figure 11B The crack detection circuit structure CDS may include a lower electrode 33, a lower contact plug 43, a lower contact pad 53, an intermediate contact plug 63, an intermediate contact pad 73, an upper contact plug 83, and an upper contact pad 93. Crack detection pad connection components 23 and 24 may be embedded in the protective ring isolation region 10 of the substrate Sub. The lower electrode 33 may be disposed on the substrate Sub, and each lower electrode 33 has a segment shape extending along the second horizontal direction Y. Crack detection pad connection components 23 and 24 may be embedded in the protective ring isolation region 10 of the substrate Sub.

[0070] Some of the crack detection circuit lower contact plugs 43 can electrically connect the crack detection circuit lower contact pads 53 to the crack detection circuit lower electrode 33. The remaining parts of the crack detection circuit lower contact plugs 43 can electrically connect the crack detection circuit lower contact pads 53 to the crack detection pad connection parts 23 and 24.

[0071] The lower electrode 33 and the upper contact pad 93 of the crack detection circuit can be staggered. In the second horizontal direction Y, the lower electrode 33 of the crack detection circuit can electrically connect the odd-numbered and even-numbered lower contact plugs 43 of the crack detection circuit to each other. In the second horizontal direction Y, the upper contact pad 93 of the crack detection circuit can electrically connect the even-numbered and odd-numbered upper contact plugs 83 of the crack detection circuit to each other.

[0072] Crack detection pad connection components 23 and 24 may include a first crack detection pad connection component 23 and a second crack detection pad connection component 24. The first and second crack detection pad connection components 23 and 24 may each include first and second crack detection pad connection buried electrodes 23a and 24a, and first and second crack detection pad connection buried overlays 23b and 24b, respectively. Therefore, the remaining portion of the lower contact plug 33 of the crack detection circuit may be electrically connected to the first and second crack detection pad connection buried electrodes 23a and 24a, respectively.

[0073] refer to Figure 11C and Figure 11D The crack detection circuit structure CDS may include a crack detection circuit embedded interconnect 20, a crack detection circuit lower contact plug 43, a crack detection circuit lower contact pad 53, a crack detection circuit intermediate contact plug 63, a crack detection circuit upper contact plug 83, and a crack detection circuit upper contact pad 93. The crack detection circuit embedded interconnect 20 may be embedded in a protective ring isolation region 10 in the substrate Sub. The crack detection circuit embedded interconnect 20 may include a crack detection circuit embedded electrode 20a and a crack detection circuit embedded cover layer 20b. The crack detection circuit embedded interconnect 20 may have the same structure as the crack detection pad connection components 23 and 24. The crack detection circuit lower contact plug 43 may be directly electrically connected to the crack detection circuit embedded electrode 20a of the crack detection circuit embedded interconnect 20. The crack detection circuit embedded interconnect 20 and the crack detection circuit upper contact pad 93 may be staggered. Figure 11C As shown, the protective ring isolation area 10 can be integrally formed to surround the crack detection circuit and embed the interconnect 20. Figure 11D As shown, multiple protective ring isolation zones 10 can be formed to surround a crack detection circuit with embedded interconnects 20.

[0074] The crack detection circuit embedded interconnect 20, crack detection pad connection components 23 and 24, test pad connection components 25 and 26, and embedded gate electrode 28a can be formed simultaneously and can be formed at the same level to have the same structure. The crack detection circuit embedded electrode 20a, the crack detection pad connection embedded electrodes 23a and 24a, the test pad connection embedded electrodes 25a and 26a, the embedded gate electrode 28a, the guard ring lower plug 40, the inner guard ring lower plug 41, the outer guard ring lower plug 42, the crack detection circuit lower contact plug 43, the crack detection pad lower contact plug 44, the test circuit lower contact plug 45, and the test pad lower contact plug 46 may include the same metal. Therefore, by using the same material, adhesion and bonding strength can be improved.

[0075] The lower electrode 30 of the guard ring, the lower electrode 31 of the inner guard ring, the lower electrode 33 of the crack detection circuit, and the peripheral gate electrode 39 may have the same structure. For example, the lower electrode 30 of the guard ring, the lower electrode 31 of the inner guard ring, the lower electrode 33 of the crack detection circuit, and the peripheral gate electrode 39 may have a gate structure comprising an insulating lower layer, a conductive intermediate layer, and an insulating upper layer. The insulating lower layer may comprise at least one of a silicon oxide-based insulating layer, a metal oxide-based insulating layer, or a silicon nitride-based insulating layer. The conductive intermediate layer may comprise at least one of a metal (e.g., tungsten), a metal nitride (e.g., titanium nitride), and a metal silicide (e.g., cobalt silicide). The insulating upper layer may comprise a silicon nitride layer based on the insulating layer.

[0076] The lower electrode 30 of the protective ring, the lower electrode 31 of the inner protective ring, the lower electrode 33 of the crack detection circuit, and the outer gate electrode 39 can be formed simultaneously in the same process.

[0077] According to embodiments of this disclosure, the protective ring structure can maintain structural stability and physical robustness.

[0078] According to embodiments of this disclosure, the pad structures for the test circuit and the crack detection circuit can be disposed in the chip area.

[0079] According to embodiments of this disclosure, the test circuit and crack detection circuit can be connected to the pad structure without causing structural or physical damage to the guard ring structure.

[0080] Although this disclosure has been described in conjunction with specific embodiments, those skilled in the art will understand that various modifications and improvements can be made without departing from the concept of the technology disclosed and the scope of protection defined by the claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: A substrate having a chip region and a protective ring region surrounding the chip region; A protective ring structure and a crack detection circuit structure are disposed on the substrate and in the protective ring region; A crack detection pad structure is disposed on the substrate and in the chip region; and A crack detection pad connection component, embedded in the substrate, electrically connects the crack detection circuit structure to the crack detection pad structure by passing through a portion of the guard ring structure. The crack detection pad connection component includes a crack detection pad connection embedded electrode and a crack detection pad connection embedded cover layer disposed on the crack detection pad connection embedded electrode.

2. The semiconductor device according to claim 1, further comprising a unit structure disposed in the chip region, in, The unit structure includes: Cell isolation regions are disposed in the substrate to define cell active regions; and A buried gate line is embedded in the substrate, the buried gate line including a buried gate electrode and a buried gate capping layer disposed above the buried gate electrode. Wherein, the crack detection pad connecting the buried electrode and the buried gate electrode are arranged at the same level, and The crack detection pad is connected to the buried cover layer and the buried gate cover layer at the same level.

3. The semiconductor device according to claim 1, in, The protective ring structure includes an inner protective ring structure and an outer protective ring structure. The crack detection circuit structure is disposed between the inner protective ring structure and the outer protective ring structure. The crack detection pad connection component is configured to pass through the inner protective ring structure.

4. The semiconductor device according to claim 3, in, The inner protective ring structure includes: The lower electrode of the inner protective ring is disposed on the substrate. A lower plug for the inner protective ring is disposed above the lower electrode of the inner protective ring; The upper plug of the inner protective ring is disposed above the lower plug of the inner protective ring; and The pads on the inner protective ring are positioned above the plug on the inner protective ring. Each of the lower electrodes of the inner protective ring and each of the upper pads of the inner protective ring have a line shape extending in the horizontal direction, and Each of the lower plugs of the inner protective ring and each of the upper plugs of the inner protective ring have a wall shape that extends in the vertical direction.

5. The semiconductor device of claim 4, further comprising a peripheral transistor structure disposed in the chip region. in, The peripheral transistor structure includes: A peripheral isolation region is disposed in the substrate to define a peripheral active region; and The peripheral gate electrode is disposed above the peripheral active region, and The outer gate electrode and the inner protective ring lower plug are positioned at the same level.

6. The semiconductor device according to claim 3, in, The outer protective ring structure includes: The lower plug of the outer protective ring is electrically connected to the substrate; The upper plug of the outer protective ring is disposed above the lower plug of the outer protective ring; and The solder pads on the outer protective ring are positioned above the plug on the outer protective ring. Each of the lower plugs of the outer protective ring and each of the upper plugs of the outer protective ring have a wall shape extending in the vertical direction, and Each of the outer protective rings has a pad with a line shape extending in the horizontal direction.

7. The semiconductor device of claim 6, further comprising a guard ring isolation region disposed in the substrate to define a guard ring active region. in, The lower plug of the outer protection ring is electrically connected to the active area of ​​the protection ring, and The crack detection pad connection component is embedded in the isolation area of ​​the protective ring.

8. The semiconductor device according to claim 7, in, The crack detection circuit structure includes: Lower contact plug of crack detection circuit; The crack detection circuit has a lower contact pad, which is configured to be spaced apart from the substrate in the vertical direction; The crack detection circuit has an intermediate contact plug, which is positioned above the lower contact pad of the crack detection circuit. A contact plug is provided on the crack detection circuit, positioned above the intermediate contact plug in the crack detection circuit; and The contact pads on the crack detection circuit are positioned above the contact plugs on the crack detection circuit. The lower contact plug of the crack detection circuit is connected to the embedded electrode of the crack detection pad. The contact pads on the crack detection circuit electrically connect adjacent contact plugs on the crack detection circuit to each other. The lower contact plug of the crack detection circuit and the embedded electrode connected to the crack detection pad are made of the same metal.

9. The semiconductor device according to claim 8, in, Some of the lower contact pads of the crack detection circuits electrically connect the intermediate contact plugs of two adjacent crack detection circuits to each other, and In this embodiment, at least one of the lower contact pads of the crack detection circuit is electrically connected to the lower contact plug of the crack detection circuit.

10. The semiconductor device according to claim 8, in, The crack detection circuit structure also includes: The lower electrode of the crack detection circuit is disposed on the substrate; and An additional lower contact plug for the crack detection circuit connects the lower contact pad of the crack detection circuit to the lower electrode of the crack detection circuit. The lower electrode of the crack detection circuit electrically connects two adjacent lower contact plugs of the additional crack detection circuit to each other.

11. The semiconductor device according to claim 8, in, The crack detection circuit structure also includes embedded interconnects of crack detection circuits embedded in the isolation area of ​​the protective ring. The crack detection circuit embedded interconnect includes: Crack detection circuit with embedded electrodes; and A cover layer is embedded in the crack detection circuit, which is disposed above the embedded electrodes of the crack detection circuit. The crack detection circuit structure further includes: an additional lower contact plug for the crack detection circuit, which connects the lower contact pad of the crack detection circuit to the buried electrode of the crack detection circuit; and The embedded electrodes of the crack detection circuit electrically connect the two adjacent lower contact plugs of the additional crack detection circuit to each other.

12. The semiconductor device according to claim 8, in, The crack detection pad structure includes: Crack detection pad under contact plug; The crack detection pad is a lower contact pad, which is disposed above the crack detection pad lower contact plug; A middle contact plug for crack detection pads is disposed above the lower contact pad of the crack detection pads; A contact plug on the crack detection pad, which is disposed above the middle contact plug of the crack detection pad; and The contact pad on the crack detection pad is positioned above the contact plug on the crack detection pad. The contact plug under the crack detection pad is electrically connected to the embedded electrode connected to the crack detection pad. The contact plug under the crack detection pad and the buried electrode connected to the crack detection pad are made of the same metal.

13. A semiconductor device, comprising: A substrate having a chip region defined by scribe lines and a guard ring region, the guard ring region being configured to surround the chip region; A protective ring structure is disposed on the substrate and in the protective ring region; A test circuit structure is disposed on the substrate in at least one of the scribe lines; Test the pad structure, which is disposed on the substrate and in the chip area; and A test pad connection component, embedded in the substrate, passes through the guard ring region to electrically connect the test circuit structure to the test pad structure. The test pad connection component includes a test pad connection buried electrode and a test pad connection buried cover layer disposed on the test pad connection buried electrode.

14. The semiconductor device of claim 13, further comprising a unit structure disposed in the chip region. in, The unit structure includes: Cell isolation regions are formed in the substrate to define cell active regions; and A buried gate line is embedded in the substrate, the buried gate line including a buried gate electrode and a buried gate capping layer disposed above the buried gate electrode. The test pad connecting the buried electrode and the buried gate electrode are positioned at the same level. The test pads are connected to the buried cover layer and the buried gate cover layer at the same level.

15. The semiconductor device according to claim 13, in, The protective ring structure includes: A lower electrode with a protective ring is disposed on the substrate; A lower plug for the protective ring is disposed above the lower electrode of the protective ring; The upper plug of the protective ring is disposed above the lower plug of the protective ring; and The pads on the guard ring are positioned above the plug on the guard ring. The lower electrode of the protective ring electrically connects two adjacent lower plugs of the protective ring to each other. The pads on the protection ring electrically connect two adjacent plugs on the protection ring to each other.

16. The semiconductor device of claim 15, further comprising a peripheral transistor structure disposed in the chip region. in, The peripheral transistor structure includes: A peripheral isolation region, which defines a peripheral active region within the substrate; and The peripheral gate electrode is disposed above the peripheral active region, and The peripheral gate electrode and the lower plug of the protective ring are arranged at the same level to have the same structure.

17. The semiconductor device according to claim 15, in, The test pad structure includes: Test the contact plug under the pad; The test pad is a contact pad located below the test pad and is positioned above the test pad contact plug. A test pad contact plug is positioned above the lower contact pad of the test pad; and The test pads are contact pads positioned above the contact plugs on the test pads. The test pad under-contact plug is connected to the test pad to connect to the buried electrode, and The contact plug under the crack detection pad and the buried electrode connected to the crack detection pad are made of the same metal.

18. The semiconductor device according to claim 17, in, The lower plug of the protective ring and the lower contact plug of the test pad are positioned at the same level. The plug on the protective ring and the contact plug on the test pad are positioned at the same level. The pads on the protective ring and the contact pads on the test pad are set at the same level.

19. The semiconductor device according to claim 13, in, The test circuit structure includes: Test the contact plug under the circuit; The test lower contact pad is positioned above the lower contact plug of the test circuit. The test circuit has a contact plug positioned above the lower contact pad of the test circuit; and The test circuit has contact pads that are positioned above the contact plugs on the test circuit. The lower contact plug of the test circuit is electrically connected to the buried electrode connected to the test pad. The lower contact plug of the crack detection circuit and the embedded electrode connected to the crack detection pad are made of the same metal.

20. A semiconductor device, comprising: A substrate having a chip region defined by scribe lines and a guard ring region, the guard ring region being configured to surround the chip region; A protective ring structure is disposed on the substrate and in the protective ring region; A circuit structure disposed on the substrate, in at least one of the scribe lines, or in the guard ring region; A pad structure disposed on the substrate in the chip region; A pad connection component that passes through the protective ring structure to electrically connect the circuit structure to the pad structure; and A unit structure is disposed in the chip region. The pad connection component includes a pad connection buried electrode embedded in the substrate, and a pad connection buried cover layer disposed on the pad connection buried electrode. The cell structure includes a cell isolation region in the substrate to define a cell active region, and a buried gate line embedded in the substrate. The buried gate line includes a buried gate electrode and a buried gate capping layer disposed on the buried gate electrode. Wherein, the pad connecting the buried electrode and the buried gate electrode are arranged at the same level, and The pads connecting the buried cover layer and the buried gate cover layer are positioned at the same level.

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