SRAM array detection method and SRAM array detection device

Abstract

The present application relates to a kind of SRAM array detection method and a kind of SRAM array detection device.The SRAM array detection method and the SRAM array detection device, current test is carried out to SRAM array in core grain, at least one of the first current flowing from the first node connected to the body region of NMOS transistor and the ratio of the first current and the second current flowing from the second node connected to the source of pull-down transistor is obtained, according to the result of the current test, whether at least one of the first current and the ratio of the first current and the second current is in the range indicating high aging risk, if yes, it is determined that the corresponding SRAM array has high aging risk, it is convenient to screen out the core grain of SRAM array with high aging risk on device wafer, not only can improve the reliability of screened core grain, but also can reduce the demand for increasing SRAM array aging margin in production process, help to increase process window and production yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an SRAM array detection method and an SRAM array detection device. Background Technology

[0002] SRAM (Static Random-Access Memory) can retain its internal data without a refresh circuit and has a fast storage speed. It is now widely used in electronic products such as computers, mobile phones, digital cameras and multimedia players.

[0003] The SRAM in a chip typically consists of multiple 6T memory cells arranged in an array. Each 6T memory cell includes six transistors and is used to store one bit of data. These six transistors include two pull-up transistors (PU transistors), two pull-down transistors (PD transistors), and two transmission gate transistors (PG transistors). Each pull-up transistor is connected to the gate of one pull-down transistor to form an inverter, and the two inverters form an interlock structure.

[0004] Research has found that during normal read / write or hold operations, the transistors inside the SRAM array cells age, causing a shift in the minimum pass voltage for read / write operations. This leads to decreased reliability or even failure of the SRAM array. To reduce the risk of reliability failure, some technical solutions control the aging margin of the SRAM array during production; however, this reduces the process window and production yield. Summary of the Invention

[0005] This invention provides an SRAM array detection method and an SRAM array detection device.

[0006] On one hand, the present invention provides an SRAM array detection method, the SRAM array detection method comprising:

[0007] Obtain a device wafer, the device wafer comprising multiple chips forming an SRAM array, the SRAM array comprising multiple 6T memory cells, multiple word lines and multiple bit lines connected to the multiple 6T memory cells, a first node connected to the body region of the NMOS transistors in the multiple 6T memory cells, and a second node connected to the source of the pull-down transistors in the multiple 6T memory cells;

[0008] A current test is performed on the SRAM array in the die, wherein the plurality of word lines and the plurality of bit lines are connected to a high potential, and the first node and the second node are connected to a low potential, to obtain at least one of a first current flowing out of the first node and the ratio of the first current to a second current flowing out of the second node; and

[0009] Based on the results of the current test, determine whether at least one of the first current and the ratio of the first current to the second current is within the range indicating a high risk of aging. If so, determine that the corresponding SRAM array has a high risk of aging.

[0010] Optionally, the SRAM array detection method further includes:

[0011] If the initial value of the minimum pass voltage for write operations of an SRAM array with high aging risk exceeds a first preset value, the corresponding chip is determined to be a failed chip. If not, the current minimum pass voltage for write operations of the SRAM array with high aging risk is further detected, and it is determined whether the sum of the current minimum pass voltage for write operations and the maximum offset that meets the reliability requirements exceeds a second preset value. If so, the corresponding chip is determined to be a failed chip.

[0012] Optionally, the device wafer undergoes CP testing, and the chip used for the current test is a chip that has passed the CP test.

[0013] Optionally, in the device wafer, the die has an MBIST test circuit connected to the corresponding SRAM array, wherein, during the current test, the MBIST test circuit is used to connect the multiple word lines and the multiple bit lines to a high potential, and to connect the first node and the second node to a low potential.

[0014] Optionally, the first current has a first correspondence with the offset of the minimum pass voltage of the write operation of the corresponding SRAM array under set aging conditions, wherein when the offset is greater than the maximum offset that meets the reliability requirements, the corresponding first current is in the range indicating a high aging risk.

[0015] Optionally, the ratio of the first current to the second current and the offset of the minimum pass voltage of the write operation of the corresponding SRAM array under set aging conditions have a second correspondence, wherein when the offset is greater than the maximum offset that meets the reliability requirements, the corresponding ratio of the first current to the second current is in the range indicating a high aging risk.

[0016] Optionally, the SRAM array detection method further includes:

[0017] Obtain a test die with the same SRAM array as the die in the device wafer;

[0018] The current test is performed on the SRAM array in the test chip to detect the first current and the second current;

[0019] An aging test is performed on the SRAM array in the test die, wherein multiple read and write operations are performed during the aging test, and before the multiple read and write operations, the minimum pass voltage of the first write operation corresponding to the SRAM array in the test die is detected, and after the multiple read and write operations, the minimum pass voltage of the second write operation corresponding to the SRAM array in the test die is detected.

[0020] Calculate the difference between the minimum pass voltage of the second write operation and the minimum pass voltage of the first write operation to obtain the corresponding offset;

[0021] The current test and aging test are performed using multiple test chips to obtain data on the first current, the second current, and the offset. Using this data, a first correspondence is obtained between the first current and the offset of the minimum pass voltage for write operations of the SRAM array under set aging conditions, and / or a second correspondence is obtained between the ratio of the first current to the second current and the offset of the minimum pass voltage for write operations of the SRAM array under set aging conditions; and

[0022] Based on the first correspondence and / or the second correspondence, obtain the range of the first current and / or the ratio of the first current to the second current that represent high aging risk when the offset is greater than the maximum offset that meets the reliability requirements.

[0023] Optionally, during the aging test, a power-on aging test is performed before the multiple read / write operations are performed, and after the power-on aging test is completed, the minimum pass voltage for the first write operation corresponding to the SRAM array in the test die is detected.

[0024] Optionally, after performing the SRAM current test and before performing the aging test, the minimum pass voltage for write operations at the initial moment corresponding to the SRAM array in the test die is detected, and the aging test is performed only if the minimum pass voltage for write operations at the initial moment does not exceed a first set value.

[0025] On the other hand, the present invention provides an SRAM array testing device for testing an SRAM array in a die. The SRAM array includes multiple 6T memory cells, multiple word lines and multiple bit lines connected to the multiple 6T memory cells, a first node connected to the body region of an NMOS transistor in the multiple 6T memory cells, and a second node connected to the source of a pull-down transistor in the multiple 6T memory cells. The SRAM array testing device includes an SRAM current testing module and a data processing module. The SRAM current testing module is configured to perform a current test on the SRAM array, wherein the multiple word lines and multiple bit lines of the SRAM array are connected to a high potential, and the first node and the second node are connected to a low potential, to obtain at least one of a first current flowing out of the first node and a ratio of the first current to a second current flowing out of the second node. The data processing module is configured to determine, based on the results of the SRAM current test, whether at least one of the first current and the ratio of the first current to the second current for each die is within a range indicating a high aging risk; if so, the corresponding SRAM array is determined to have a high aging risk.

[0026] Optionally, the SRAM array testing device further includes an MBIST test circuit disposed in the chip and connected to the corresponding SRAM array. The SRAM current testing module uses the MBIST test circuit to connect the multiple word lines and the multiple bit lines to a high potential, and to connect the first node and the second node to a low potential.

[0027] Optionally, the MBIST test circuit includes:

[0028] I / O unit, including current test control terminal; and

[0029] A control circuit is connected to the I / O unit and configured to connect the multiple word lines and the multiple bit lines to a high potential when the current test control terminal is connected to a high potential, so as to perform the current test.

[0030] Optionally, the I / O unit further includes a first test terminal and a second test terminal; the P-type substrate port is connected to the first node of the corresponding SRAM array, and the power ground port is connected to the second node of the corresponding SRAM array.

[0031] Using the SRAM array detection method and SRAM array detection device provided by this invention, current testing can be performed on the SRAM array in the chip to obtain at least one of the first current flowing out from the first node connected to the body region of the NMOS transistor and the ratio of the first current to the second current flowing out from the second node connected to the source of the pull-down transistor. Based on the results of the current test, it is determined whether the first current and at least one of the ratio of the first current to the second current are within the range indicating high aging risk. If so, the corresponding SRAM array is determined to have high aging risk, which facilitates the screening of chips with high aging risk of SRAM arrays, reduces the risk of SRAM array reliability failure in later use, not only improves the reliability of the screened chips, but also reduces the need to increase the aging margin of the SRAM array during the production process, which helps to increase the process window and production yield. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a 6T storage unit in one embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of an SRAM macrocell in one embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of an SRAM array and an MBIST test circuit connected to the SRAM array in one embodiment of the present invention.

[0035] Figure 4 This is a circuit diagram of a current test signal controlling a word line in one embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram illustrating the steps of obtaining a first correspondence, a second correspondence, and a range representing a first current and / or the ratio of the first current to the second current that indicates a high risk of aging, according to an embodiment of the present invention.

[0037] Figure 6 This is a schematic diagram illustrating the second correspondence between the ratio of the first current to the second current of the SRAM array and the offset of the minimum pass voltage for a write operation under set aging conditions in one embodiment of the present invention.

[0038] Figure 7 This is a schematic diagram of the steps of an SRAM array detection method according to an embodiment of the present invention. Detailed Implementation

[0039] The SRAM array detection method and SRAM array detection apparatus of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in this specification are in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0040] Reference Figure 1 The 6T memory cell in the SRAM array has 6 transistors and is used to store 1 bit of data. Two pull-up transistors (PU1, PU2) and two pull-down transistors (PD1, PD2) form two interlocked inverters. Transmission gate transistor PG1 is connected to the junction point Q of pull-up transistor PU1 and pull-down transistor PD1, and transmission gate transistor PG2 is connected to the junction point QB of pull-up transistor PU2 and pull-down transistor PD2. Taking the storage of "0" in the 6T memory cell as an example, node Q is at a low potential, and node QB is at a high potential. During data reading, bit lines BL and BLB have completed pre-charging before word line WL becomes high, thus having a high potential. After word line WL is charged to a high potential, transmission gate transistors PG1, PD1, PG2, and pull-up transistor PU2 are turned on, while pull-up transistors PU1 and PD2 are turned off. The charge on word line BL is discharged to the power supply ground (VSS) through transmission gate transistors PG1 and PD1, forming a discharge current (I). read ).

[0041] In the aforementioned 6T memory cell, the two pull-up transistors (PU1, PU2) are typically PMOS transistors. These two PMOS transistors are formed, for example, corresponding to the same N-type substrate region, such as an N-well. Their bulk connection point is the lead-out terminal of the N-well. The two pull-down transistors and two transmission gate transistors are typically NMOS transistors. These four NMOS transistors are formed, for example, corresponding to the same P-type substrate region, such as a P-well. The bulk connection point of these four NMOS transistors (corresponding to...) Figure 1 The connection end B shown is the lead-out end of the P-well.

[0042] Reference Figure 2 In some embodiments, the die on the wafer may be formed with at least one SRAM macrocell (i.e., SRAM instance), the capacity of which can be set as needed. The SRAM macrocell, for example, includes at least one SRAM array defined by a deep N-well (DNW) and a plurality of P-well leads 11 (corresponding to voltage V) disposed around the SRAM array. PW ) and multiple N-well leads 12 (corresponding to voltage V) NWEach SRAM array includes multiple 6T memory cells as described above. As an example, the SRAM macrocell includes two SRAM arrays, each SRAM array including n 6T memory cells (n is a positive integer). Therefore, this SRAM macrocell has 2n 6T memory cells, which includes 8n NMOS transistors and 4n PMOS transistors. Each P-well lead 11 is connected to the body region of at least one NMOS transistor in a 6T memory cell to apply a voltage to the body region of the corresponding NMOS transistor; each N-well lead 12 is connected to the body region of at least one PMOS transistor in a 6T memory cell to apply a voltage to the body region of the corresponding PMOS transistor. It should be noted that... Figure 2 For illustrative purposes only, the SRAM macrocell may also include other connections and circuitry. For example, the sources of all pull-down transistors in the SRAM macrocell may be connected to the same node (such as power ground (VSS)). Figure 2 (Not shown). When the SRAM macrocell is tested, depending on the connection of the test terminals of the SRAM array, at least one SRAM array can be tested independently or all SRAM arrays can be tested as a whole array.

[0043] Research has found that during the read and write operations of a 6T memory cell, the degradation of read and write performance is related to the aging of the NMOS transistors (especially the transfer transistors PG1 and PG2, which have relatively high drain-source voltages (Vds)). When the electrical performance of the NMOS transistors degrades, causing the threshold voltage (Vt) to increase, the minimum pass voltage Vt for write operations of the corresponding SRAM array decreases. min_write (This refers to the minimum power supply voltage required for all 6T memory cells in the SRAM array to successfully complete a write operation.) This voltage increases, causing a shift. Further research revealed that when the transfer transistors PG1 and PG2 in the SRAM array are turned on, the ratio of the current flowing from the node connecting the body region of the NMOS transistor to the discharge current from the source of the pull-down transistor corresponds to the shift of the minimum pass voltage for the write operation of the SRAM array after aging.

[0044] In the SRAM array testing method and apparatus described in the following embodiments, the aging risk of the NMOS transistors and SRAM array is characterized by the ratio of the current flowing out from a first node in the SRAM array that connects to the body region of an NMOS transistor and / or the current flowing out from a second node that connects to the source of a pull-down transistor. The first node is connected to the body region of the NMOS transistors of multiple 6T memory cells in the SRAM array. The first node includes a P-well lead 11 or other type of P-type substrate connection terminal connecting to the body region. The second node is connected to the source of the pull-down transistors of multiple 6T memory cells in the SRAM array. The second node includes, for example, a power ground connection terminal (such as a VSS terminal) connected to the source. The current flowing out from the first node can be detected at the test terminal corresponding to the first node, and the current flowing out from the second node can be detected at the test terminal corresponding to the second node. For convenience, the current flowing out from the first node is denoted as the first current I. sub The current flowing out from the second node is denoted as the second current I. read .

[0045] In this embodiment, the first current I is utilized. sub and the first current I sub With the second current I read At least one of the ratios is related to the minimum pass voltage V of the write operation after SRAM array aging. min_write The correspondence between the offsets is set to indicate the first current I mentioned above, which has a high risk of aging. sub Range and / or first current I sub With the second current I read The ratio, based on the first current I sub and / or the first current I sub With the second current I read The ratio result is used to estimate the minimum pass voltage V for write operations after SRAM array aging. min_write The offset is used to determine whether the corresponding SRAM array has a high aging risk. This facilitates the screening of SRAM chips with high aging risk on the device wafer, reducing the risk of reliability failure of the SRAM array in later use. It eliminates the need for lengthy aging tests and can be used in mass production. This helps ensure the reliability of the remaining chips on the device wafer after screening and also reduces the requirements for increasing transistor aging margins during production, thus helping to increase the process window and production yield. Further explanation follows.

[0046] Based on the first current I sub and / or the first current I sub With the second current I readBefore determining whether the SRAM array in the die on the device wafer has a high aging risk, the ratio of the test die to the test die can be used to perform current testing and aging testing on a test die with the same SRAM array as the die on the device wafer to obtain the I / O value of the SRAM array. sub and I sub / I read At least one of them is related to the SRAM array after aging V min_write The correspondence between the offsets. The test chip, for example, comes from a test wafer.

[0047] The test die is identical to the SRAM array in the die to be screened on the device wafer. The SRAM array includes multiple 6T memory cells, and the 6T memory cells include, for example... Figure 1 The diagram shows pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and transmission gate transistors PG1 and PG2. PU1 and PU2 are PMOS transistors with their sources connected to the power supply voltage VDD. PD1, PD2, PG1, and PG2 are NMOS transistors. The drain of PD1 is connected to the drain of PU1 and the source of PG1. The gates of PU1 and PD1 are connected to the source of PG2. The drains of PD2 and PU2 are connected to the source of PG2. The gates of PU2 and PD2 are connected to the source of PG1. The sources of PD1 and PD2 are connected to a second node (e.g., power ground (VSS)). The drains of PG1 and PG2 are connected to bit lines BL and BLB, respectively. The gates of PG1 and PG2 are connected to word line WL.

[0048] Reference Figure 1 and Figure 3 In order to detect the aforementioned first current I sub In the test die and the die on the device wafer, the SRAM array has a first node 10 (e.g., a P-type substrate connection terminal connected to the corresponding body region) connected to the body region of the NMOS transistor therein. The first node 10 is used to set the potential of the body region of the NMOS transistor and test the first current I. sub The first node 10 is independent of devices other than those connected to the SRAM array. The SRAM array, for example, also has a second node 20 (e.g., a power / ground connection to the corresponding source) connected to the sources of pull-down transistors PD1 and PD2 in a plurality of 6T memory cells. Using this second node 20, the potentials of the sources of pull-down transistors PD1 and PD2 can be set, and the discharge current (i.e., the second current I) formed by the discharge of charge on bit lines BL and BLB through the corresponding transmission gate transistors and pull-down transistors to the second node 20 can be tested. read The second node 20 is independent of the device settings outside the connected SRAM array.

[0049] The test chip and the chip to be screened on the device wafer may also have an MBIST test circuit connected to the corresponding SRAM array, which can be used to test the connected SRAM array.

[0050] Reference Figure 3 In some embodiments, the MBIST test circuit includes an I / O unit, a clock unit CLK, and control circuitry connected to the I / O unit and the clock unit CLK. The control circuitry can control the SRAM array to perform testing based on signals from the I / O unit and the clock unit CLK, without limiting the specific implementation circuit. As an example, the peripheral circuitry of the control circuitry may include a WL selection unit, a WL decoding unit, a BL selection unit, a BL decoding unit, an execution circuit, and a data storage module (e.g., a register set), where "WL" represents a word line and "BL" represents a bit line. The control circuitry can send corresponding control commands to the peripheral circuitry based on signals from the I / O unit and the clock unit CLK to control the SRAM array to perform testing. In other embodiments, in addition to the above components, the peripheral circuitry of the control circuitry may also include a WL full select unit and / or a BL full select unit. In this MBIST test circuit, the WL all-select unit is configured to make all word lines of the connected SRAM array high or low according to the instructions of the control circuit; the BL all-select unit is configured to make all bit lines of the connected SRAM array high or low according to the instructions of the control circuit; and the execution circuit is configured to control the MBIST test circuit to perform read operations, write operations, retention states, or current tests according to the instructions of the control circuit. The connection between the MBIST test circuit and the SRAM array, as well as the circuit implementation of the above modules, can be achieved using known techniques.

[0051] The I / O units are used to generate the input and output signals of the MBIST test circuit. (Refer to...) Figure 3 In some embodiments, the I / O unit includes a first test terminal, a second test terminal, and a current test control terminal; wherein the first test terminal is connected to a first node 10 of the corresponding SRAM array, and the second test terminal is connected to a second node 20 of the corresponding SRAM array. As an example, the first test terminal includes a port connected to the first node 10, such as a specially configured P-type substrate port P. sub However, this is not the only possibility. In some embodiments, the port connecting the first node 10 may also be compatible with other ports. As an example, the second test terminal includes a port connected to the second node 20 of the corresponding SRAM array, such as a dedicated power ground port P. VSSHowever, this is not the only possibility; in some embodiments, the port connecting the second node 20 may also be compatible with other ports. The current test control terminal is connected to the aforementioned control circuit, and the current test control terminal, for example, uses a dedicated current test port P for current testing. SRAM However, this is not the only possibility; in some embodiments, the current test control terminal may also be compatible with other functions. The aforementioned P-type substrate port P... sub and power ground port P VSS This is a power supply GPIO port, current test port P. SRAM This is a signal-type GPIO port.

[0052] The first node 10 of the SRAM array is connected to the P-type substrate port P. sub The second node 20 is connected to the power ground port P. VSS Furthermore, the current test control terminal is the current test port P. SRAM For example, P-type substrate port P sub The signal is used to input and control the potential of the first node 10 and to detect the current flowing out of the first node 10 when the transmission gate transistor in the SRAM array is turned on (i.e., the first current I). sub Power ground port P VSS This is used to input the potential of the second node 20 and detect the current flowing out of the second node 20 when the transmission gate transistor in the SRAM array is turned on (i.e., the second current I). read Current test control port P SRAM This is used to input a signal regarding whether to perform the current test on the corresponding SRAM array.

[0053] Table 1 shows the potential states of the SRAM array in one embodiment for the clock signal CLK, chip enable signal CEN, write enable signal WEN, hold signal RET, and current test signal BI in four operating states (read operation, write operation, hold state, and current test). (H represents high potential, L represents low potential, and X represents uncorrelated).

[0054] Table 1

[0055]

[0056] Referring to Table 1, the potential state of the current test signal BI is determined by the current test port P. SRAM This is generated as an analog signal. When the current test signal BI is high, the test equipment supplies power to the P-type substrate port P. sub and power ground port P VSS Apply a voltage and test the magnitude of the current at both ports, via the P-type substrate port P. sub The first current I is obtained sub From the power ground port PVSS The second current I is obtained read .

[0057] As an example, the control circuit at the current test port P SRAM When connected to a high potential (i.e., the current test signal BI is at a high potential L), the WL and BL full-select units are controlled to connect all word lines and all bit lines of the SRAM array under test to a high potential, and the execution circuit is controlled to put the SRAM array into a current test state. During read, write, and hold operations, the current test port P... SRAM For example, a low potential.

[0058] Figure 4 A circuit is shown that uses a current test signal BI to control a word line. (Refer to...) Figure 4 In this circuit, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are located on the input side of the driver stage 30. The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the positive power supply voltage VDDE, and their drains are connected to the drains of the first NMOS transistor N1 and the third NMOS transistor N3. The source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, and the sources of the second NMOS transistor N2 and the third NMOS transistor N3 are connected to the power supply ground VSSE. The gates of the first PMOS transistor P1 and the first NMOS transistor N1 are connected to the first row select signal ROWSEL1, the gates of the second PMOS transistor P2 and the second NMOS transistor N2 are connected to the second row select signal ROWSEL2, and the gate of the third NMOS transistor N3 is connected to the current test signal BI. Using this circuit, when the current test signal BI becomes high, the corresponding word line WL is fixed at a high level, thereby enabling the P-type substrate port P... sub and power ground port P VSS Apply a voltage signal and test the corresponding current, P-type substrate port P sub and power ground port P VSS The current can be measured simultaneously or separately.

[0059] It should be noted that in the above embodiments, the current test is triggered by making the current test signal BI high, but it is not limited to this. For example, in some other embodiments, the trigger signal of the current test can also be designed as other signal waveforms generated by the current test control terminal, such as rising edge, falling edge, pulse level for a certain time or a certain number of times, sine wave or cosine wave, etc.

[0060] Figure 5This is a schematic diagram illustrating the steps of obtaining a first correspondence, a second correspondence, and a range representing a first current and / or the ratio of the first current to the second current indicating a high aging risk, according to an embodiment of the present invention. (Refer to...) Figure 5 As an example, the offset of the minimum pass voltage for a write operation during SRAM aging is obtained, along with the aforementioned first current I. sub First current I sub With the second current I read The corresponding relationship between the ratios and the corresponding first current I representing high aging risk sub and / or the first current I sub With the second current I read The ratio can include the following process.

[0061] First, obtain test chips that have the same SRAM array as the chips in the device wafer. For example, multiple test chips can be obtained through at least one test wafer. For each test chip, perform the following current test and aging test.

[0062] Next, a current test is performed on the SRAM array in the test die. During the current test, the MBIST test circuit described above can be used, with the source of the pull-up transistor of each 6T memory cell in the corresponding SRAM array connected to the power supply voltage VDD, each word line and each bit line connected to a high potential, and the first node 10 and the second node 20 connected to a low potential. The current is then measured by detecting the P-type substrate port P. sub The current is obtained by the first current I flowing out from the first node 10. sub Additionally, when it is necessary to obtain the first current I sub With the second current I read When determining the relationship between the ratio and the minimum pass voltage offset of write operations after SRAM array aging, the power supply ground port P is also detected. VSS The current is obtained by the second current I flowing out from the second node 20. read By performing the aforementioned current test, the first current I corresponding to the SRAM array under test in the test die can be obtained. sub With the second current I read .

[0063] In some embodiments, after the current test is performed on the SRAM array in the test die and before the aging test, the minimum pass voltage for write operations of the corresponding SRAM array is measured, i.e., the minimum pass voltage for write operations V at the initial time (t0). min_write0 And determine the minimum pass voltage V for the write operation at the initial moment. min_write0 If the first set value is exceeded, the SRAM array does not meet the aging test requirements, and the following aging test will not be performed: if the minimum pass voltage V for the write operation at time t0 is... min_write0If the value does not exceed the first set value, then the following aging test will be performed. The first set value is, for example, 0.9 * VDD, where VDD is... Figure 1 The power supply voltage VDD is shown.

[0064] Next, an aging test is performed on the SRAM array in the test die. During the aging test, multiple read and write operations are performed, and before each of the multiple read and write operations, the minimum pass voltage V of the first write operation of the corresponding SRAM array is detected. min_write1 After the multiple read and write operations, the minimum pass voltage V for the write operation of the SRAM array is then detected. min_write2 .like Figure 5 As shown, in some embodiments, the SRAM array is first subjected to power-on aging for a first duration, for example, using a High Temperature Operating Life (HTOL) aging test platform. The first duration is, for example, 1000 hours. After the power-on aging ends, i.e., after the first duration of aging, the minimum pass voltage for write operations of the SRAM array is detected to obtain the first minimum pass voltage V for write operations. min_write1 Afterward, a second aging period (e.g., 1000 hours) is continued, during which normal read and write tests are performed. Upon completion, the minimum pass voltage for write operations of the SRAM array is detected to obtain the second minimum pass voltage V for write operations. min_write2 The minimum pass voltage for the second write operation is V. min_write2 For example, greater than the minimum pass voltage V of the first write operation. min_write1 .

[0065] The minimum pass voltage V for the first write operation is obtained. min_write1 The minimum pass voltage V for the second write operation min_write2 Then, calculate V. min_write2 With V min_write1 The difference is used to obtain the offset ΔV of the minimum pass voltage for the write operation corresponding to the tested SRAM array under the above aging conditions. min_write .

[0066] As can be seen, by using the above steps, the first current I corresponding to the SRAM array of the test chip can be obtained. sub Second current I read With offset ΔV min_write To obtain the minimum pass voltage offset and the first current I during SRAM array aging. sub and the first current I sub With the second current I read The corresponding relationship between the ratios can be obtained by performing the above steps using SRAM arrays in multiple test chips to obtain multiple sets of first current I. sub Second current I read and offset ΔV min_writeData, based on the first current I sub and offset ΔV min_write From the data, the first current I can be obtained. sub With offset ΔV min_write The first correspondence between them; in addition, based on the first current I in each set of data. sub With the second current I read The first current I can be obtained. sub With the second current I read The ratio (i.e., I) sub / I read ), using multiple sets of first current I sub With the second current I read The ratio and offset ΔV min_write The data can be used to obtain I. sub / I read With offset ΔV min_write The second correspondence between them. Figure 6 As an example, the first current I is shown. sub With the second current I read The ratio (i.e., I) sub / I read ) and offset ΔV min_write The second correspondence, wherein the results obtained from multiple test cores are derived from I. sub / I read With offset ΔV min_write The coordinates of the location fall within the area of ​​the dashed circle.

[0067] According to some embodiments of the present invention, the first current I sub and the first current I sub With the second current I read At least one of the ratios can be used to characterize the expected aging rate of the NMOS transistors in the corresponding SRAM array. (Refer to...) Figure 5 After obtaining the above-mentioned first correspondence and / or second correspondence, the first current I representing a high aging risk can be further obtained. sub The range and / or I indicating a high risk of aging sub / I read The scope, that is, based on the above first correspondence and / or second correspondence, can be defined as I with high aging risk. sub and / or I sub / I read The boundary, that is, when the first current I sub The data is located at the first current I, which indicates a high risk of aging. sub Within the range, and / or the first current I sub With the second current I readWhen the ratio data is within the range indicating high aging risk, the offset ΔV of the minimum pass voltage for write operations of the corresponding SRAM array under set aging conditions (such as the HTOL aging conditions mentioned above) is... min_write It is expected to exceed the maximum allowable offset ΔV required to meet reliability requirements. min_write_max The maximum offset ΔV min_write_max The settings can be customized according to the reliability requirements under the given aging conditions. For example, refer to... Figure 6 The minimum pass voltage V for the write operation at time t0 mentioned above. min_write0 For example, given a value of 0.9*VDD, after 2000 hours of HTOL aging, the maximum offset ΔV of the SRAM array that meets reliability requirements. min_write_max For example, if it is 0.05*VDD, when the offset ΔV min_write When the following equation (1) is satisfied, the corresponding first current I sub and / or the first current I sub With the second current I read The ratio falls within the range indicating a high risk of aging:

[0068] ΔV min_write > 0.95*VDD - 0.9*VDD (1)

[0069] Using the aforementioned first and second setting relationships, and the first current I representing a high aging risk. sub The range and / or I indicating a high risk of aging sub / I read The range allows for the estimation of the minimum pass voltage offset for write operations on the SRAM array on the device wafer during aging, thereby enabling the selection of chips.

[0070] Figure 7 This is a schematic diagram of the steps of an SRAM array detection method in one embodiment of the present invention. Using this SRAM array detection method, it is possible to detect whether the SRAM array in the chip on the device wafer has a high aging risk. Chips with SRAM arrays with high aging risk can be screened out, reducing the risk of SRAM array reliability failure in later use.

[0071] Reference Figure 1 , Figure 3 as well as Figure 7According to an embodiment of the present invention, an SRAM array detection method includes step S1, acquiring a device wafer, the device wafer including multiple chips on which an SRAM array is formed, wherein the SRAM array includes multiple 6T memory cells arranged in an array, multiple word lines and multiple bit lines connected to the multiple 6T memory cells, a first node 10 connected to the body region of the NMOS transistors in the multiple 6T memory cells, and a second node 20 connected to the source of the pull-down transistors in the multiple 6T memory cells. The chips on which the SRAM array is formed have, for example, as shown in the figure... Figure 1 and Figure 3 The structure shown. The first node 10 includes, for example, a P-type substrate connection terminal connected to the body region of the NMOS transistor in the corresponding SRAM array, and the second node 20 includes, for example, a power ground connection terminal connected to the source of the pull-down transistor in the corresponding SRAM array.

[0072] In some embodiments, before performing the current test in step S2, a CP test (i.e., chip probe test) is performed on the device wafer to obtain CP-test-qualified chips. The plurality of chips mentioned in step S1 are CP-test-qualified chips. The present invention is not limited thereto; in other embodiments, the CP test may not be performed before performing the current test on the SRAM array.

[0073] Next, step S2 is performed to test the current of the SRAM array in the chip.

[0074] The current testing of the SRAM array in the die on the device wafer is performed using the same method as the current testing of the aforementioned test die. During the current test, the source of the pull-up transistor of each 6T memory cell in the corresponding SRAM array is connected to the power supply voltage VDD, each word line and bit line is connected to a high potential, and the aforementioned first node 10 and second node 20 are connected to a low potential. The die in the device wafer that forms the SRAM array has, for example, the aforementioned MBIST test circuit connected to the corresponding SRAM array (see reference). Figure 3 During the current test, the MBIST test circuit can be used to receive external detection signals, so that all word lines and all bit lines of the SRAM array being tested are connected to a high potential.

[0075] The first current I flowing out of the first node 10 can be detected by the current test. sub The second current I flowing out from the second node 20 read And the first current I was calculated. sub With the second current I read The ratio (I) sub / I read ).

[0076] In this embodiment, Isub and I sub / I read At least one of them is the offset ΔV of the minimum pass voltage for a write operation after SRAM array aging. min_write This correspondence can be used to predict the minimum pass voltage offset ΔV of an SRAM array under set aging conditions (such as the HTOL aging conditions mentioned above). min_write Does it exceed the maximum allowable offset to meet reliability requirements?

[0077] Reference Figure 7 Then, step S3 is executed, and based on the result of the current test, the first current I is determined. sub and the first current I sub With the second current I read If at least one of the ratios is within the range indicating a high risk of aging, then the corresponding SRAM array is determined to have a high risk of aging.

[0078] Based on the first and / or second correspondences mentioned above, the first current I representing high aging risk can be obtained. sub The range, and / or the first current I representing a high risk of aging. sub With the second current I read The range of the ratio can be set, for example, based on the first correspondence and / or the second correspondence mentioned above, by setting I. sub and / or I sub / I read The high aging risk boundary, if I sub and / or I sub / I read If the data exceeds the corresponding boundary, it means that the corresponding SRAM array has a high risk of aging.

[0079] In some embodiments, after obtaining an SRAM array with a high risk of aging, the SRAM array detection method further includes the following process:

[0080] Determine the initial value of the minimum pass voltage for write operations on SRAM arrays with high aging risk (such as V mentioned above). min_write0 If the initial value of the minimum pass voltage for the write operation of the SRAM array is too large, it indicates that the corresponding chip (i.e., the chip in which the SRAM array with high aging risk is located) is a failed chip.

[0081] If the initial value of the minimum pass voltage for write operations of an SRAM array with a high risk of aging does not exceed the first set value, it indicates that the initial value of the minimum pass voltage for write operations of the corresponding SRAM array is qualified. Then, the current minimum pass voltage V for write operations of the corresponding SRAM array is further detected. min_write ;

[0082] The minimum pass voltage V for the current write operation is obtained. min_write Then, determine the minimum pass voltage V for the current write operation. min_write The maximum offset ΔV of the minimum pass voltage for a write operation when reliability requirements are met under set aging conditions. min_write_max If the sum exceeds the second set value, it is estimated that the reliability of the corresponding SRAM array will fail after aging under the set aging conditions, and the corresponding chip is determined to be a failed chip.

[0083] The first setting value is, for example, 0.9*VDD, the second setting value is, for example, 0.95*VDD, and the maximum offset ΔV min_write_max For example, it is 0.05*VDD. The minimum pass voltage V for determining the current write operation is... min_write The maximum offset ΔV of the minimum pass voltage for a write operation when reliability requirements are met under set aging conditions. min_write_max When the sum exceeds the second set value, it is determined whether the following equation (2) is true:

[0084] ΔV min_write_max + V min_write > 0.95*VDD (2)

[0085] In some embodiments, the minimum pass voltage V of the current write operation is determined. min_write The maximum offset ΔV of the minimum pass voltage for a write operation when reliability requirements are met under set aging conditions. min_write_max If the sum exceeds the second set value, and the result is no, the core can be retained for subsequent processes instead of being treated as a failed core.

[0086] At least a portion of the SRAM array detection method described in the above embodiments can be converted into computer-executable instructions and stored in a memory (such as a hard disk, random access memory (RAM), external storage medium, storage device with communication lines, registers, etc.) for execution by a processor.

[0087] Some embodiments of the present invention relate to an SRAM array testing apparatus for testing SRAM arrays formed in a die. (See also...) Figures 1 to 7 The SRAM array includes multiple 6T memory cells arranged in an array, multiple word lines and multiple bit lines connected to the multiple 6T memory cells, a first node 10 connected to the body region of the NMOS transistors in the multiple 6T memory cells, and a second node 20 connected to the source of the pull-down transistors in the multiple 6T memory cells. The SRAM array detection device can perform the above-described SRAM array detection method.

[0088] In some embodiments, the SRAM array detection device includes an SRAM current testing module and a data processing module.

[0089] The SRAM current testing module is configured to perform the aforementioned current test on the SRAM array. During the current test, the word lines and bit lines of the corresponding SRAM array are connected to a high potential, while the first node 10 and the second node 20 are connected to a low potential. The first current I flowing out from the first node 10 can then be detected. sub and the first current I sub With the second current I flowing out from the second node 20 read The ratio (I) sub / I read At least one of the following.

[0090] Minimum voltage offset ΔV for write operations of an SRAM array under set aging conditions min_write With the first current I sub For example, given the first correspondence mentioned above, and / or, the minimum pass voltage offset ΔV of the SRAM array under set aging conditions for write operations. min_write With the first current I sub With the second current I read The ratio, for example, has the second correspondence described above. Referring to the description of the above embodiments, the first and second correspondences can be obtained by performing the above-described current test and aging test on multiple test chips, and a first current I representing a high aging risk can also be obtained. sub The range and / or I indicating a high risk of aging sub / I read The range.

[0091] The data processing module is configured to determine the first current I based on the result of the current test. sub and the first current I sub With the second current I read If at least one of the ratios is within the range indicating a high risk of aging, then the corresponding SRAM array is determined to have a high risk of aging.

[0092] Reference Figure 3 In some embodiments, the SRAM array detection device further includes an MBIST test circuit disposed in each chip forming the SRAM array and connected to the corresponding SRAM array. The SRAM current test module inputs a signal for SRAM current detection to the MBIST test circuit and uses the MBIST test circuit to control the corresponding SRAM array to perform the aforementioned current test. The features of the MBIST test circuit can be referred to the description of the above embodiments.

[0093] The SRAM current testing module and the data processing module can be implemented in software, such as by using a software program in conjunction with a device or equipment. However, all or part of them can also be implemented in hardware. Regardless of whether they are implemented in software or hardware, the specific parts can be implemented by those familiar with the fields of electronics and software. Therefore, the details will not be elaborated in this specification.

[0094] Using the SRAM array detection method and SRAM array detection device described in the above embodiments, a current test can be performed on the SRAM array in the chip, and based on the result of the current test, a first current I corresponding to the SRAM array can be determined. sub and the first current I sub With the second current I read If at least one of the ratios is within the range indicating high aging risk, then the corresponding SRAM array is determined to have high aging risk. This facilitates the screening of SRAM array chips with high aging risk on the device wafer, reduces the risk of SRAM array reliability failure during later use, improves the reliability of the screened chips, and can also reduce the need to increase the aging margin of the SRAM array during the production process, which helps to increase the process window and production yield.

[0095] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

[0096] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for detecting SRAM arrays, characterized in that, include: Obtain a device wafer, the device wafer comprising multiple chips forming an SRAM array, the SRAM array comprising multiple 6T memory cells, multiple word lines and multiple bit lines connected to the multiple 6T memory cells, a first node connected to the body region of the NMOS transistors in the multiple 6T memory cells, and a second node connected to the source of the pull-down transistors in the multiple 6T memory cells; A current test is performed on the SRAM array in the chip, wherein the multiple word lines and the multiple bit lines are connected to a high potential, and the first node and the second node are connected to a low potential, to obtain at least one of a first current flowing out of the first node and the ratio of the first current to a second current flowing out of the second node. as well as Based on the results of the current test, it is determined whether at least one of the first current and the ratio of the first current to the second current is within the range indicating a high aging risk. If so, the corresponding SRAM array is determined to have a high aging risk. Furthermore, using the minimum pass voltage of the write operation of the SRAM array with a high aging risk, it is determined whether the corresponding chip is a failed chip.

2. The SRAM array detection method as described in claim 1, characterized in that, Also includes: If the initial value of the minimum pass voltage for write operations of an SRAM array with high aging risk exceeds a first preset value, the corresponding chip is determined to be a failed chip. If not, the current minimum pass voltage for write operations of the SRAM array with high aging risk is further detected, and it is determined whether the sum of the current minimum pass voltage for write operations and the maximum offset that meets the reliability requirements exceeds a second preset value. If so, the corresponding chip is determined to be a failed chip.

3. The SRAM array detection method as described in claim 1, characterized in that, The device wafer undergoes CP testing, and the chip used for the current test is a chip that has passed the CP test.

4. The SRAM array detection method as described in claim 1, characterized in that, In the device wafer, the chip has an MBIST test circuit connected to the corresponding SRAM array. During the current test, the MBIST test circuit is used to connect the multiple word lines and the multiple bit lines to a high potential, and to connect the first node and the second node to a low potential.

5. The SRAM array detection method as described in claim 1, characterized in that, The first current has a first correspondence with the offset of the minimum pass voltage of the write operation of the corresponding SRAM array under set aging conditions, wherein when the offset is greater than the maximum offset that meets the reliability requirements, the corresponding first current is in the range that indicates a high aging risk.

6. The SRAM array detection method as described in claim 1, characterized in that, The ratio of the first current to the second current and the offset of the minimum pass voltage of the write operation of the corresponding SRAM array under set aging conditions have a second correspondence, wherein when the offset is greater than the maximum offset that meets the reliability requirements, the ratio of the first current to the second current is in the range that indicates a high aging risk.

7. The SRAM array detection method as described in claim 1, characterized in that, Also includes: Obtain a test die with the same SRAM array as the die in the device wafer; The current test is performed on the SRAM array in the test chip to detect the first current and the second current; An aging test is performed on the SRAM array in the test die, wherein multiple read and write operations are performed during the aging test, and before the multiple read and write operations, the minimum pass voltage of the first write operation corresponding to the SRAM array in the test die is detected, and after the multiple read and write operations, the minimum pass voltage of the second write operation corresponding to the SRAM array in the test die is detected. Calculate the difference between the minimum pass voltage of the second write operation and the minimum pass voltage of the first write operation to obtain the corresponding offset; The current test and aging test are performed using multiple test chips to obtain data on the first current, the second current, and the offset. Using this data, a first correspondence is obtained between the first current and the offset of the minimum pass voltage for write operations of the SRAM array under set aging conditions, and / or a second correspondence is obtained between the ratio of the first current to the second current and the offset of the minimum pass voltage for write operations of the SRAM array under set aging conditions; and Based on the first correspondence and / or the second correspondence, obtain the range of the first current and / or the ratio of the first current to the second current that represent high aging risk when the offset is greater than the maximum offset that meets the reliability requirements.

8. The SRAM array detection method as described in claim 7, characterized in that, During the aging test, a power-on aging test is performed before the multiple read / write operations are performed. After the power-on aging test is completed, the minimum pass voltage of the first write operation corresponding to the SRAM array in the test die is detected.

9. The SRAM array detection method as described in claim 7, characterized in that, After the current test and before the aging test, the minimum pass voltage for write operation at the initial moment corresponding to the SRAM array in the test die is detected. The aging test is performed only if the minimum pass voltage for write operation at the initial moment does not exceed a first set value.

10. An SRAM array detection device, characterized in that, Used for testing SRAM arrays in a die, the SRAM array including multiple 6T memory cells, multiple word lines and multiple bit lines connected to the multiple 6T memory cells, a first node connected to the body region of the NMOS transistors in the multiple 6T memory cells, and a second node connected to the source of the pull-down transistors in the multiple 6T memory cells; The SRAM array detection device includes: An SRAM current testing module is configured to perform a current test on the SRAM array, wherein the plurality of word lines and the plurality of bit lines of the SRAM array are connected to a high potential, and the first node and the second node are connected to a low potential, obtaining at least one of a first current flowing out of the first node and the ratio of the first current to a second current flowing out of the second node; and The data processing module is configured to determine, based on the result of the current test, whether at least one of the first current and the ratio of the first current to the second current is within a range indicating high aging risk; if so, determine that the corresponding SRAM array has high aging risk; and, using the minimum pass voltage of the write operation of the SRAM array with high aging risk, determine whether the corresponding chip is a failed chip.

11. The SRAM array detection device as described in claim 10, characterized in that, It also includes an MBIST test circuit disposed in the chip and connected to the corresponding SRAM array. The SRAM current test module uses the MBIST test circuit to connect the multiple word lines and the multiple bit lines to a high potential, and to connect the first node and the second node to a low potential.

12. The SRAM array detection device as described in claim 11, characterized in that, The MBIST test circuit includes: I / O unit, including current test control terminal; and A control circuit is connected to the I / O unit and configured to connect the multiple word lines and the multiple bit lines to a high potential when the current test control terminal is connected to a high potential, so as to perform the current test.

13. The SRAM array detection device as described in claim 12, characterized in that, The I / O unit further includes a first test terminal and a second test terminal; the first test terminal includes a port connected to the first node of the corresponding SRAM array, and the second test terminal includes a port connected to the second node of the corresponding SRAM array.

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