Method of manufacturing a co-packaged optical structure and co-packaged optical structure

Abstract

The embodiment of the present application provides a preparation method of a co-encapsulated optical structure and the co-encapsulated optical structure, relates to the chip packaging technical field, and first forms a base dielectric layer on a substrate, and then punches and cuts to form a base pattern opening. Then, a base metal layer is formed by electroplating. Then, a wiring combination layer is formed on the base metal layer, a plurality of heterogeneous chips are attached on the wiring combination layer, and a plastic encapsulation layer covering the plurality of heterogeneous chips is formed. Finally, the substrate is removed by grinding, and a solder ball is formed on the base dielectric layer. Compared with the prior art, the embodiment of the present application punches and cuts the base dielectric layer by using a specially designed cutting jig, so that the base pattern opening is formed, the cost is lower, and the negative influence caused by etching liquid is avoided. Meanwhile, the new electroplating process is used to realize multi-point injection, so that the electroplating liquid is more uniformly distributed, the wiring uniformity is greatly improved, the plating leakage phenomenon is effectively avoided, and then the conductivity of the wiring structure and the interlayer bonding force are ensured.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a method for preparing a co-packaging optical structure and the co-packaging optical structure itself. Background Technology

[0002] Existing chiplet technology can package chips with different functions together, such as photonic engine chips, memory chips, and / or processing chips, to form a heterogeneous integrated co-packaged optical structure. However, as chip input / output density increases and the number of chips integrated into a single package increases significantly, multi-chip packaging solutions typically improve their transmission performance through multi-layer wiring processes.

[0003] In conventional techniques, wiring processes typically require etching openings across the entire circuit layer before electroplating around these openings on the wafer. This electroplating process often results in poor uniformity, leading to inconsistent wiring layer thickness and consequently affecting conductivity and interlayer adhesion. Furthermore, traditional electroplated wiring layers require connecting leads around the wafer periphery to form a metal layer. Finally, micro-etching is used to remove these leads, but this process can lead to over-etching, causing uneven thickness and again impacting conductivity and interlayer adhesion. Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing a co-encapsulated optical structure and the co-encapsulated optical structure, which can use novel opening and electroplating processes to significantly improve the uniformity of the wiring layer, making the thickness of the electroplated metal layer consistent, thereby ensuring the conductivity and interlayer bonding of the wiring layer.

[0005] The embodiments of the present invention are implemented through the following methods: In one aspect, embodiments of the present invention provide a method for fabricating a co-encapsulated optical structure, comprising: A substrate dielectric layer is formed on the substrate; The substrate dielectric layer is punched and cut using a cutting fixture to form a substrate pattern opening on the substrate dielectric layer. The surface of the cutting fixture is provided with a cutting head protrusion for cutting to form the substrate pattern opening. The cutting head protrusion is also provided with an electroplating opening, and the electroplating opening is movably sealed with a cap. A base metal layer is formed by electroplating in the opening of the base pattern using the cutting fixture, wherein the electroplating solution flows into the base pattern opening from the electroplating opening. A wiring assembly layer is formed on the substrate dielectric layer, wherein the wiring assembly layer is electrically connected to the substrate metal layer; Multiple heterogeneous chips are mounted on the wiring assembly layer; A molding compound layer is formed on the wiring assembly layer, and the molding compound layer covers the plurality of heterogeneous chips; The substrate is removed by grinding, exposing the substrate dielectric layer; Solder balls are formed on the substrate dielectric layer, wherein the solder balls are electrically connected to the substrate metal layer.

[0006] In an optional embodiment, the step of punching and cutting the substrate dielectric layer using a cutting fixture includes: The cutting fixture is used to perform lamination and stamping cutting with the side of the cutting head protruding towards the substrate medium. The cutting fixture is separated to form a substrate pattern opening on the substrate medium layer.

[0007] In an optional embodiment, prior to the step of electroplating to form a base metal layer in the substrate pattern opening using the cutting fixture, the method further includes: Open the cap and chemically clean the opening of the substrate pattern, wherein the cleaning solution flows into the opening of the substrate pattern corresponding to the electroplating opening; The cutting fixture has a receiving cavity that is connected to the electroplating opening and is used to receive cleaning solution or electroplating solution.

[0008] In an optional embodiment, the step of electroplating a base metal layer in the substrate pattern opening using the cutting fixture includes: The cutting fixture is attached to the substrate medium layer so that the blade protrusion extends into the substrate pattern opening; Open the cap and inject the electroplating solution into the patterned opening of the substrate; The cutting fixture is separated to form a base metal layer in the opening of the base pattern.

[0009] In an optional embodiment, after the step of electroplating to form a base metal layer in the substrate pattern opening using the cutting fixture, the method further includes: The thickness of the base metal layer is measured using the cutting fixture, wherein the cap contacts the base metal layer, and the thickness of the base metal layer is obtained by measuring the resistivity of the base metal layer.

[0010] In an optional embodiment, the step of grinding to remove the substrate and expose the substrate dielectric layer includes: Using the substrate dielectric layer as the grinding stop layer, the substrate is ground until the substrate dielectric layer is exposed; The substrate dielectric layer is ground to reduce its thickness.

[0011] In an optional embodiment, the step of forming a wiring assembly layer on the substrate dielectric layer includes: Multiple wiring dielectric layers and multiple wiring metal layers are formed on the substrate dielectric layer, wherein the multiple wiring metal layers are disposed within the multiple wiring dielectric layers.

[0012] In an optional embodiment, the step of forming a wiring assembly layer on the substrate dielectric layer includes: A multilayer wiring dielectric layer, a multilayer wiring metal layer, and an optical module are formed on the substrate dielectric layer, wherein the multilayer wiring metal layer is disposed in the multilayer wiring dielectric layer, and the optical module is embedded in the multilayer wiring dielectric layer.

[0013] In an optional embodiment, the step of forming a wiring assembly layer on the substrate dielectric layer includes: A first dielectric layer and a first metal layer are formed on the substrate dielectric layer, wherein the first metal layer is located in the first dielectric layer; A structural chip is mounted on the first dielectric layer; A protective layer is formed on the first dielectric layer, wherein the protective layer covers the structure chip; Conductive pillars are formed in the protective layer, wherein the conductive pillars are electrically connected to the first metal layer; A second dielectric layer and a second metal layer are formed on the protective layer, wherein the second metal layer is located in the first dielectric layer and is electrically connected to the conductive pillar; The structure chip is electrically connected to the first metal layer or the second metal layer.

[0014] In an optional implementation, the step of mounting multiple heterogeneous chips on the wiring assembly layer includes: A first chip and a second chip are mounted on the wiring assembly layer, with the second chip located on both sides of the first chip.

[0015] In an optional embodiment, the step of mounting the first chip and the second chip on the wiring assembly layer includes: A first chip, a second chip, and an optical module are mounted on the wiring assembly layer, with the second chip located on one side of the first chip and the optical module located on the other side of the first chip.

[0016] On the other hand, embodiments of the present invention provide a co-packaged optical structure, which is fabricated using the aforementioned method for fabricating a co-packaged optical structure, the co-packaged optical structure comprising: The substrate dielectric layer has a substrate pattern opening on one side surface and solder balls on the other side surface. A base metal layer is disposed in the opening of the base pattern and is electrically connected to the solder ball; A wiring assembly layer is disposed on the substrate dielectric layer and electrically connected to the substrate metal layer; Multiple heterogeneous chips are mounted on the wiring assembly layer; A molding layer is disposed on the wiring assembly layer and covers the plurality of heterogeneous chips.

[0017] In an optional implementation, the plurality of heterogeneous chips includes a first chip and a second chip, with the second chip located on either side of the first chip.

[0018] In an optional implementation, the plurality of heterogeneous chips include a first chip, a second chip, and an optical module, wherein the second chip is located on one side of the first chip, and the optical module is located on the other side of the first chip.

[0019] In an optional embodiment, the optical module includes a photonic chip and an electronic chip, the photonic chip having a photosensitive area, and the electronic chip disposed on the photonic chip and offset from the photosensitive area.

[0020] In an optional embodiment, the optical module further includes a transparent adhesive layer disposed on the photonic chip and covering the photosensitive area, and the transparent adhesive layer is exposed outside the molding compound.

[0021] In an optional embodiment, the molding layer is grooved to form a clearance notch, which is configured to expose the transparent adhesive layer.

[0022] In an optional embodiment, the optical module includes a photonic chip, an electron chip, a transparent adhesive layer, a molding compound, and a structural substrate. The photonic chip has a photosensitive area extending to the sidewall of the photonic chip. The electron chip is disposed on the photonic chip and offset from the photosensitive area. The transparent adhesive layer is disposed on the photonic chip and covers the photosensitive area. The structural substrate is disposed on the transparent adhesive layer. The molding compound is disposed on the photonic chip and encapsulates the electron chip. The molding compound also contains an electrical post, one end of which is connected to a pad on the surface of the photonic chip, and the other end is exposed outside the molding compound.

[0023] In an optional embodiment, the wiring combination layer includes multiple wiring dielectric layers and multiple wiring metal layers, wherein the multiple wiring metal layers are disposed within the multiple wiring dielectric layers.

[0024] In an optional embodiment, the wiring combination layer includes multiple wiring dielectric layers, multiple wiring metal layers, and an optical module, wherein the multiple wiring metal layers are disposed in the multiple wiring dielectric layers, and the optical module is embedded in the multiple wiring dielectric layers.

[0025] In an optional embodiment, the wiring combination layer includes a first dielectric layer, a first metal layer, a structural chip, a protective layer, a second dielectric layer, and a second metal layer. The first dielectric layer is disposed on the substrate dielectric layer, the first metal layer is located in the first dielectric layer, the structural chip is mounted on the first dielectric layer, the protective layer is disposed on the first dielectric layer and covers the structural chip, and conductive pillars are formed in the protective layer. The conductive pillars are electrically connected to the first metal layer. The second dielectric layer is disposed on the protective layer, the second metal layer is disposed in the second dielectric layer and is electrically connected to the conductive pillars, wherein the structural chip is electrically connected to either the first metal layer or the second metal layer.

[0026] The beneficial effects of the embodiments of the present invention include: The method for fabricating a co-packaged optical structure and the co-packaged optical structure provided in this invention first form a substrate dielectric layer on a substrate. Then, a dicing fixture is used to punch and cut the substrate dielectric layer, thereby forming a substrate pattern opening on the substrate dielectric layer. The dicing fixture has a protruding cutting head on its surface, which also has an electroplating opening, and the electroplating opening is movably sealed with a cap. Then, a substrate metal layer is directly electroplated in the substrate pattern opening using the dicing fixture, wherein the electroplating solution flows into the substrate pattern opening corresponding to the electroplating opening. Next, a wiring assembly layer is formed on the substrate metal layer, and multiple heterogeneous chips are mounted on the wiring assembly layer, forming a molding compound layer covering the multiple heterogeneous chips. Finally, the substrate is removed by grinding, and solder balls are formed on the substrate dielectric layer.

[0027] Compared to existing technologies, this invention utilizes a specially designed cutting fixture to punch and cut the substrate dielectric layer, thereby forming an opening in the substrate pattern. This novel opening process replaces the conventional etching process, resulting in lower costs and avoiding the negative impacts of etching solutions. Simultaneously, electroplating solutions can be directly injected into the substrate pattern openings using the electroplating openings on the cutting fixture, forming a substrate metal layer. This novel electroplating process achieves multi-point injection while ensuring more uniform distribution of the electroplating solution, significantly improving wiring uniformity, effectively preventing incomplete plating, and ensuring consistent electroplated metal layer thickness. This, in turn, guarantees the conductivity and interlayer adhesion of the wiring structure. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart illustrating the steps of a method for fabricating a co-encapsulated optical structure according to the first embodiment of the present invention. Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 5 This is a schematic diagram of the cutting fixture used in steps S2 and S3 of the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 6 This is a schematic diagram of the structure corresponding to step S4 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 7 This is a schematic diagram of the structure corresponding to step S5 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention; Figure 8 This is a schematic diagram of the structure corresponding to step S6 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 9 This is a schematic diagram of the structure corresponding to step S7 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 10 This is a schematic diagram of the structure corresponding to step S8 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 11a This is a schematic diagram of the common packaging optical structure provided in the first embodiment of the present invention; Figure 11b This is a schematic diagram of the upper plate structure of the common packaging optical structure provided in the first embodiment of the present invention; Figure 12 This is a top view of the common packaging optical structure provided in the first embodiment of the present invention; Figure 13This is a schematic diagram of the common packaging optical structure provided in the second embodiment of the present invention; Figure 14a This is a schematic diagram of the optical module structure in the second embodiment of the present invention; Figure 14b This is a schematic diagram of the front-end fabrication process of the optical module in the second embodiment of the present invention; Figure 14c This is a schematic diagram of the back-end fabrication process of the optical module in the second embodiment of the present invention; Figure 15a This is a schematic diagram of another common packaging optical structure provided in the second embodiment of the present invention; Figure 15b This is a schematic diagram of another optical module in the second embodiment of the present invention; Figure 16 A schematic diagram of the common packaging optical structure provided in the third embodiment of the present invention; Figure 17 This is a schematic diagram of the common packaging optical structure provided in the fourth embodiment of the present invention.

[0030] Icons: Common package optical structure 100; Substrate dielectric layer 110; Substrate pattern opening 111; Solder ball 112; Substrate metal layer 120; Wiring assembly layer 130; Wiring dielectric layer 131; Wiring metal layer 132; First dielectric layer 133; First metal layer 134; Protective layer 135; Conductive pillar 136; Second dielectric layer 137; Second metal layer 138; Structure chip 139; Heterogeneous chip 140; First chip 141 Second chip 142; Optical module 143; Photonic chip 144; Electron chip 145; Transparent adhesive layer 146; Photosensitive area 147; Molded body 148; Electrical pillar 1481; Structural substrate 149; Molded layer 150; Clearance notch 151; Substrate 200; Cutting fixture 300; Blade protrusion 310; Electroplating opening 311; Receiving cavity 312; Cover 313; Substrate 400; Fiber optic module 410; Carrier 500. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0033] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0034] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0035] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0036] As disclosed in the background section, existing chiplet technology can package chips with different functions together, such as photonic engine chips, memory chips, and / or processing chips, to form a co-packaged optoelectronic structure. However, existing wiring processes typically require etching openings across the entire wiring layer before electroplating the wafer pattern openings. This electroplating uniformity is poor, leading to inconsistent wiring layer thickness, which affects conductivity and interlayer adhesion. Furthermore, traditional electroplated wiring layers require lead wires designed around the wafer periphery to connect the plating points, forming a metal layer. Finally, micro-etching is used to remove the electroplated lead wires. This micro-etching process is prone to over-etching, easily causing the wiring layer to be eroded, resulting in uneven thickness, which also affects conductivity and interlayer adhesion.

[0037] Furthermore, conventional etching processes for opening are costly and energy-intensive. Additionally, etching solution residue is easily left after etching, causing irregular ripples at the edge of the dielectric layer at the opening due to the residual liquid. This can lead to uneven stress on the sidewalls of the dielectric layer and the formation of brittle points from moisture, making it prone to fracture.

[0038] To address the aforementioned problems, embodiments of the present invention provide a novel method for preparing a co-encapsulated optical structure and the co-encapsulated optical structure itself. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0039] First Embodiment Please see Figure 1 This invention provides a method for preparing a co-encapsulated optical structure 100. This method can use novel opening and electroplating processes to significantly improve the uniformity of the wiring layer, making the electroplated metal layer thickness consistent, thereby ensuring the conductivity and interlayer bonding of the wiring layer.

[0040] The method for fabricating the co-encapsulated optical structure 100 provided in this embodiment of the invention includes the following steps: S1: Form a substrate dielectric layer on the substrate.

[0041] See also Figure 2 Specifically, a substrate 200 can be taken first, and a liquid dielectric material can be directly spin-coated onto the surface of the substrate 200 using a coating machine. Then, the substrate can be soft-baked and shaped into a film using a hot plate to form a base dielectric layer 110. The substrate 200 can be made of materials such as glass, silicon oxide, or metal, and the dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc.

[0042] S2: Use a cutting fixture to punch and cut the substrate medium layer to form a substrate pattern opening on the substrate medium layer.

[0043] See Figure 3 The surface of the cutting fixture 300 is provided with a cutting head protrusion 310 for cutting to form a base pattern opening 111. The cutting head protrusion 310 is also provided with an electroplating opening 311, and the electroplating opening 311 is movably sealed with a cap 313.

[0044] Specifically, the cutting fixture 300 with the blade protrusion 310 can be pressed together with the substrate medium layer 110 to achieve stamping and cutting. Then the cutting fixture 300 can be separated to form a substrate pattern opening 111 on the substrate medium layer 110.

[0045] It should be noted that after the stamping and cutting are completed, the substrate pattern opening 111 also needs to be cleaned. Specifically, the cover 313 can be opened, and the substrate pattern opening 111 can be chemically cleaned, wherein the cleaning solution flows into the substrate pattern opening 111 corresponding to the electroplating opening 311; wherein, a receiving cavity 312 is formed in the cutting fixture 300, the receiving cavity 312 is connected to the electroplating opening 311, and is used to receive the cleaning solution or electroplating solution. It is worth noting that the depth of the substrate pattern opening 111 here is less than the thickness of the substrate dielectric layer 110, thereby preventing the substrate pattern opening 111 from penetrating the substrate dielectric layer 110.

[0046] In actual preparation, a stamping and cutting method can be used first to press the protruding blade 310 towards the substrate dielectric layer 110 to form a substrate pattern opening 111. Then, a cleaning process is performed. First, a cleaning solution is filled into the receiving cavity 312. Then, the cap 313 is opened, and the cleaning solution is injected into the substrate pattern opening 111 through the electroplating opening 311 to achieve cleaning, removing residues and foreign matter from the substrate pattern opening 111. The cleaning solution can be a combination of triethanolamine, tetrahydrofurfuryl alcohol, benzotriazole, chloride, surfactants, and other alcohol-based cleaning solutions. Because multiple electroplating openings 311 are used to clean the substrate pattern openings 111 at different locations, cleaning of a single opening is achieved, the cleaning solution distribution is more uniform, and the degree of saponification and emulsification reactions is significantly improved, thus greatly enhancing the cleaning effect.

[0047] S3: Electroplating is performed in the opening of the substrate pattern using a cutting fixture to form a base metal layer.

[0048] See Figure 4 The electroplating solution flows into the substrate pattern opening 111 through the electroplating opening 311. Specifically, the cutting fixture 300 is first attached to the substrate dielectric layer 110, so that the cutting head protrusion 310 extends into the substrate pattern opening 111. Then, the cap 313 is opened, and the electroplating solution is injected into the substrate pattern opening 111 for electroplating. Finally, the cutting fixture 300 is separated, so that a substrate metal layer 120 is formed in the substrate pattern opening 111. This electroplating method can directly perform multi-point electroplating at the location of the substrate pattern opening 111, which greatly improves the uniformity of the metal layer.

[0049] It should be noted that the cutting fixture 300 here is made entirely of conductive material, so there is no need to arrange additional electroplating leads.

[0050] It is worth noting that after the electroplating of the substrate metal layer 120 is completed, the thickness of the substrate metal layer 120 can be measured. Specifically, the thickness of the substrate metal layer 120 can be measured using a cutting fixture 300, wherein the cap 313 contacts the substrate metal layer 120, and the thickness of the substrate metal layer 120 is obtained by measuring the resistivity of the substrate metal layer 120. In actual measurement, the cap 313 can contact the substrate metal layer 120, and the resistivity of the substrate metal layer 120 is measured under power-on conditions to determine its thickness. Here, the thickness measurement of a single substrate metal layer 120 can be achieved separately, greatly improving the measurement accuracy. Traditional measurement methods select and measure multiple areas to determine the thickness of the wiring metal, which has measurement errors and omissions. Specifically, in existing processes, the wiring of the substrate 200 to be measured needs to be placed on a separate inspection machine for thickness measurement, such as generating a three-dimensional outline of the circuit through 3D scanning and directly reading the height (thickness) of the copper wiring protrusion, which has a large measurement error.

[0051] It should be noted that the thickness of the electroplated layer can be measured by resistivity, and it satisfies the following formula: t = ρ * L / R * W; Where t: copper wiring thickness (cm), converted to μm; ρ: copper resistivity, pure copper at 20℃: ρ = 1.72 × 10⁻⁶ 6 Ω cm; L: Actual length of the trace (cm); W: Trace width (cm); R: Actual DC resistance (Ω).

[0052] See also Figure 5 The cutting fixture 300 is described in detail below: The cutting fixture 300 has an internal receiving cavity 312, which communicates with an electroplating opening 311 and can hold cleaning solution or electroplating solution. Multiple blade protrusions 310 are integrally formed on one side surface of the cutting fixture 300, and each blade protrusion 310 has an electroplating opening 311 on its surface. A cover 313 is also movably disposed at the electroplating opening 311, and the cover 313 can open or close the electroplating opening 311.

[0053] In practical use, the substrate dielectric layer 110 can first be punched and cut using the protrusion 310 of the cutting head to form a substrate pattern opening 111. Then, a cleaning process is performed, with the cleaning solution entering the substrate wiring opening through the electroplating opening 311 to remove residues and foreign matter from the substrate pattern opening 111. Next, the electroplating solution is replaced in the receiving cavity 312, and injected directly into the substrate pattern opening 111 through the electroplating opening 311. Electroplating is then performed at the substrate pattern opening 111 to form a substrate metal layer 120, significantly improving the uniformity of the electroplated metal layer. Finally, the thickness of the substrate metal layer 120 is measured, improving measurement accuracy and enabling timely detection of whether the thickness and thickness uniformity are up to standard.

[0054] S4: Form a wiring assembly layer on the substrate dielectric layer.

[0055] See Figure 6 The wiring assembly layer 130 is electrically connected to the substrate metal layer 120. Specifically, the wiring assembly layer 130 includes a multilayer wiring dielectric layer 131 and a multilayer wiring metal layer 132, wherein the multilayer wiring metal layer 132 is disposed within the multilayer wiring dielectric layer 131. In actual fabrication, the wiring dielectric layer 131 can be formed on the substrate dielectric layer 110, and then the wiring metal layer 132 can be formed by opening, cleaning, and electroplating using a cutting fixture 300. This process is repeated to form the multilayer wiring dielectric layer 131 and the multilayer wiring metal layer 132. Alternatively, conventional wiring processes can be used to form the multilayer wiring dielectric layer 131 and the multilayer wiring metal layer 132.

[0056] S5: Multiple heterogeneous chips are mounted on the wiring assembly layer.

[0057] See Figure 7 Specifically, the plurality of heterogeneous chips 140 includes a first chip 141 and a second chip 142. In actual mounting, the first chip 141 and the second chip 142 can be mounted on the wiring combination layer 130, with the second chip 142 located on both sides of the first chip 141. Preferably, the first chip 141 and the second chip 142 can be flip-chip bonded to the structural pads of the wiring combination layer 130, and then an underfill adhesive can be applied to form a filler adhesive layer to protect the soldering structure of the flip-chip.

[0058] S6: Form a molding layer on the wiring assembly layer.

[0059] See Figure 8 The molding compound 150 covers multiple heterogeneous chips 140. Specifically, the molding compound 150 can be formed by printing or pressure injection molding. The molding compound 150 can cover the first chip 141 and the second chip 142, and also cover the filler adhesive layer, thus providing protection.

[0060] In some other preferred embodiments, the molding compound 150 can be thinned by grinding to expose the back sides of the first chip 141 and the second chip 142, thereby improving heat dissipation characteristics and reducing package height.

[0061] S7: Grind to remove the substrate and expose the base dielectric layer.

[0062] See Figure 9 Specifically, the substrate 200 can be polished first, using the substrate dielectric layer 110 as a polishing stop layer, until the substrate dielectric layer 110 is exposed. Then, the substrate dielectric layer 110 is further polished to thin it. It should be noted that the substrate dielectric layer 110 does not expose the substrate metal layer 120 after planarization. By removing the substrate 200 through chemical polishing, and using the substrate dielectric layer 110 as a polishing stop layer to continue polishing to a certain thickness, excessive polishing can be avoided to prevent damage to the substrate metal layer 120.

[0063] It should be noted that the substrate 200 is removed here by a grinding process, which avoids the debonding removal process in traditional technology, thus avoiding the generation of residual adhesive.

[0064] S8: Form solder balls on the substrate dielectric layer.

[0065] See Figure 10The solder ball 112 is electrically connected to the base metal layer 120. Specifically, an opening can be made on the back side of the base dielectric layer 110 through a stamping and cutting process to expose the base metal layer 120. Then, a solder ball 112 is formed in the opening through an electroplating process. The solder ball 112 can be at least one of Ti, Wu, Ni, Sn, Ag, and Cu, which can improve solderability. Furthermore, the stamping and cutting method used here can avoid damage to the base metal layer 120 by laser opening or traditional etching opening, and can ensure consistent opening depth, thereby ensuring uniform electroplating. Finally, it is cut into individual products.

[0066] See Figure 11a and Figure 12 This invention also provides a co-packaged optical structure 100, fabricated using the aforementioned method. The co-packaged optical structure 100 includes a substrate dielectric layer 110, a substrate metal layer 120, a wiring assembly layer 130, multiple heterogeneous chips 140, and a molding compound layer 150. One surface of the substrate dielectric layer 110 has a substrate pattern opening 111, and the other surface has solder balls 112. The substrate metal layer 120 is disposed in the substrate pattern opening 111 and electrically connected to the solder balls 112. The wiring assembly layer 130 is disposed on the substrate dielectric layer 110 and electrically connected to the substrate metal layer 120. Multiple heterogeneous chips 140 are mounted on the wiring assembly layer 130. The molding compound layer 150 is disposed on the wiring assembly layer 130 and encapsulates the multiple heterogeneous chips 140.

[0067] In this embodiment, the wiring combination layer 130 includes a multilayer wiring dielectric layer 131 and a multilayer wiring metal layer 132, with the multilayer wiring metal layer 132 correspondingly disposed in the multilayer wiring dielectric layer 131.

[0068] In this embodiment, the plurality of heterogeneous chips 140 includes a first chip 141 and a second chip 142, with the second chip 142 located on both sides of the first chip 141. The first chip 141 and the second chip 142 can be any combination of control chips, logic chips, or memory chips.

[0069] See Figure 11b In actual use, the co-packaged optical structure 100 can be mounted on a substrate 400. An optical module 143 and an optical fiber module 410 can be disposed on the substrate 400. The optical module 143 is spaced apart from the co-packaged optical structure 100, and the optical fiber module 410 is coupled to the optical module 143.

[0070] In summary, the fabrication method and the co-packaged optical structure 100 provided in this embodiment of the invention first form a substrate dielectric layer 110 on a substrate 200, and then use a cutting fixture 300 to punch and cut the substrate dielectric layer 110, thereby forming a substrate pattern opening 111 on the substrate dielectric layer 110. The cutting fixture 300 has a protruding cutting head 310 on its surface, which also has an electroplating opening 311, and a cap 313 is movably sealed to the electroplating opening 311. Then, the cutting fixture 300 directly electroplats a substrate metal layer 120 in the substrate pattern opening 111, wherein the electroplating solution flows into the substrate pattern opening 111 through the electroplating opening 311. Next, a wiring assembly layer 130 is formed on the substrate metal layer 120, and multiple heterogeneous chips 140 are mounted on the wiring assembly layer 130, forming a molding compound 150 covering the multiple heterogeneous chips 140. Finally, the substrate 200 is removed by grinding, and solder balls 112 are formed on the substrate dielectric layer 110. Compared with the prior art, this embodiment of the invention uses a specially designed cutting fixture 300 to punch and cut the substrate dielectric layer 110, thereby forming a substrate pattern opening 111. This novel opening process replaces the conventional etching opening process, resulting in lower costs and avoiding the negative impact of etching solution. At the same time, electroplating solution can be directly injected into the substrate pattern opening 111 using the electroplating opening 311 on the cutting fixture 300 to form a substrate metal layer 120. This novel electroplating process achieves multi-point injection while making the electroplating solution distribution more uniform, significantly improving wiring uniformity, effectively avoiding incomplete plating, and ensuring a consistent thickness of the electroplated metal layer, thereby guaranteeing the conductivity and interlayer bonding of the wiring structure.

[0071] Second Embodiment See Figure 13 This embodiment of the invention provides a co-encapsulated optical structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0072] The co-packaged optical structure 100 includes a substrate dielectric layer 110, a substrate metal layer 120, a wiring assembly layer 130, multiple heterogeneous chips 140, and a molding compound layer 150. One surface of the substrate dielectric layer 110 has a substrate pattern opening 111, and the other surface has solder balls 112. The substrate metal layer 120 is disposed in the substrate pattern opening 111 and electrically connected to the solder balls 112. The wiring assembly layer 130 is disposed on the substrate dielectric layer 110 and electrically connected to the substrate metal layer 120. Multiple heterogeneous chips 140 are mounted on the wiring assembly layer 130. The molding compound layer 150 is disposed on the wiring assembly layer 130 and encapsulates the multiple heterogeneous chips 140.

[0073] In this embodiment, the plurality of heterogeneous chips 140 include a first chip 141, a second chip 142 and an optical module 143. The second chip 142 is located on one side of the first chip 141 and the optical module 143 is located on the other side of the first chip 141.

[0074] Among them, see Figure 14a The optical module 143 includes a photonic chip 144, an electron chip 145, and a transparent adhesive layer 146. The photonic chip 144 has a photosensitive area 147. The electron chip 145 is disposed on the photonic chip 144 and offset from the photosensitive area 147. The transparent adhesive layer 146 is disposed on the photonic chip 144 and covers the photosensitive area 147. A groove is formed in the molding compound 150 to create an clearance notch 151, which is configured to expose the transparent adhesive layer 146.

[0075] Furthermore, an optical fiber module 410 (FAU) can be installed in the clearance notch 151 to achieve optical fiber coupling. During the process of creating the clearance notch 151, the transparent adhesive layer 146 can protect the photosensitive area 147 and prevent it from being damaged. At the same time, the slot can increase the heat dissipation area, thereby improving the heat dissipation effect. The optical fiber module 410 can be installed in the clearance notch 151, which can reduce the overall packaging height.

[0076] The following is a detailed description of the specific fabrication process of the optical module 143: First, such as Figure 14b A wafer can be provided, on which the transistor fabrication of the photonic die 144 is pre-done. The wafer has pads and optical areas formed on its front side, and electrical connection bumps formed on its back side. The pads on the front side and the electrical connection bumps on the back side are electrically connected. The back side of the wafer is then mounted on a carrier 500, and a transparent adhesive layer 146 is attached to the front side of the wafer. Then, grooves are cut into the transparent adhesive layer 146 to expose the pads. See [link to relevant documentation]. Figure 14c Then, the electron die 145 is flip-mounted and bonded to the pad in the slot, and filler adhesive is applied to the bottom of the electron die 145. Then, a molding compound 148 is formed, and the transparent adhesive layer 146 is ground to expose it. Finally, the carrier 500 is removed and cut to form a single optical module 143.

[0077] Of course, the encapsulation 148 can be omitted here, and a single optical module 143 can be directly cut. In other preferred embodiments of the present invention, the transparent adhesive layer 146 can be omitted, and the electron chip 145 can be directly mounted on the surface of the photonic chip 144. Alternatively, in other preferred embodiments of the present invention, the bottom of the electron chip 145 can be protected directly by the encapsulation 148 without the filler adhesive.

[0078] See Figure 15aIn other preferred embodiments of the present invention, the molding layer 150 may also expose the transparent adhesive layer 146 by grinding.

[0079] See Figure 15b In other preferred embodiments of the present invention, another optical module 143 is provided, which includes a photonic chip 144, an electron chip 145, a transparent adhesive layer 146, a molding compound 148, and a structural substrate 149. The photonic chip 144 has a photosensitive area 147 extending to the sidewall of the photonic chip 144. The electron chip 145 is disposed on the photonic chip 144 and offset from the photosensitive area 147. The transparent adhesive layer 146 is disposed on the photonic chip 144 and covers the photosensitive area 147, thereby enabling side light emission. The structural substrate 149 is disposed on the transparent adhesive layer 146. The molding compound 148 is disposed on the photonic chip 144 and encapsulates the electron chip 145. The molding compound 148 also includes an electrical post 1481. One end of the electrical post 1481 is connected to a pad on the surface of the photonic chip 144, while the other end is exposed outside the molding compound 148 and forms a solder ball at the end, thus achieving electrical connection between the photonic chip 144 and the outside. Unlike the aforementioned optical module 143, this module is mounted in an inverted manner, with the back of the electron chip 145 facing the wiring assembly layer 130, thereby achieving electrical connection between the photonic chip 144 and the wiring assembly layer 130 through the electrical post 1481.

[0080] Furthermore, the molding compound 148 here can improve its heat dissipation performance and reduce the package height by grinding to expose the back side of the die 145 and the surface of the structural substrate 149.

[0081] The structural substrate 149 may include elemental semiconductors such as silicon and germanium and / or compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide, or the structural substrate 149 may also include metals (such as copper / aluminum).

[0082] It should be noted that the first chip 141 can be high-bandwidth memory (HBM), DRAM, HBF (High-bandwidth Flash) flash memory, DDR random access memory, etc.; the second chip 142 can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, etc.; and the optical module 143 can be a photonic engine chip, whose photonic integrated circuit design is used to utilize the unique properties of light, providing advantages such as high bandwidth, low power consumption and faster data transmission speed compared to its electronic counterpart.

[0083] This invention provides a method for preparing a co-encapsulated optical structure 100. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0084] The method for fabricating the co-encapsulated optical structure 100 provided in this embodiment of the invention includes the following steps: S1: A substrate dielectric layer 110 is formed on the substrate 200.

[0085] S2: The substrate medium layer 110 is punched and cut using a cutting fixture 300 to form a substrate pattern opening 111 on the substrate medium layer 110.

[0086] S3: Using a cutting fixture 300, a base metal layer 120 is formed by electroplating in the base pattern opening 111.

[0087] S4: A wiring assembly layer 130 is formed on the substrate dielectric layer 110.

[0088] S5: Attach multiple heterogeneous chips 140 on the wiring combination layer 130.

[0089] Specifically, the multiple heterogeneous chips 140 include a first chip 141, a second chip 142, and an optical module 143. In actual chip mounting, the first chip 141, the second chip 142, and the optical module 143 can be mounted on the wiring combination layer 130. The second chip 142 is located on one side of the first chip 141, and the optical module 143 is located on the other side of the first chip 141.

[0090] S6: Form a molding layer 150 on the wiring assembly layer 130.

[0091] S7: Grind to remove substrate 200 and expose substrate dielectric layer 110.

[0092] S8: Solder balls 112 are formed on the substrate dielectric layer 110.

[0093] It should be noted that the molding layer 150 partially exposes the optical module 143, thus facilitating coupling with the external fiber optic module 410. By integrating the optical module 143 onto the wiring assembly layer 130, a CPO packaging structure can be achieved, realizing the optical module function and improving the functional characteristics and integration of the heterogeneous packaging structure.

[0094] Third Embodiment See Figure 16This invention provides a co-encapsulated optical structure 100, which is prepared using the aforementioned method for preparing a co-encapsulated optical structure 100. Its basic structure, principle, and technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0095] The co-packaged optical structure 100 includes a substrate dielectric layer 110, a substrate metal layer 120, a wiring assembly layer 130, multiple heterogeneous chips 140, and a molding compound layer 150. One surface of the substrate dielectric layer 110 has a substrate pattern opening 111, and the other surface has solder balls 112. The substrate metal layer 120 is disposed in the substrate pattern opening 111 and electrically connected to the solder balls 112. The wiring assembly layer 130 is disposed on the substrate dielectric layer 110 and electrically connected to the substrate metal layer 120. Multiple heterogeneous chips 140 are mounted on the wiring assembly layer 130. The molding compound layer 150 is disposed on the wiring assembly layer 130 and encapsulates the multiple heterogeneous chips 140.

[0096] In this embodiment, the wiring combination layer 130 includes a multilayer wiring dielectric layer 131, a multilayer wiring metal layer 132, and an optical module 143. The multilayer wiring metal layer 132 is disposed in the multilayer wiring dielectric layer 131, and the optical module 143 is embedded in the multilayer wiring dielectric layer 131. The side of the optical module 143 is exposed outside the multilayer wiring dielectric layer 131, thereby realizing side light entry / exit.

[0097] In this embodiment, the plurality of heterogeneous chips 140 includes a first chip 141 and a second chip 142, with the second chip 142 located on both sides of the first chip 141. The first chip 141 and the second chip 142 can be any combination of control chips, logic chips, or memory chips.

[0098] It should be noted that the basic structure of the optical module 143 here is the same as in the second embodiment, except that the transparent adhesive layer 146 can be relatively thicker, thereby increasing the size of the photosensitive cavity, reducing the curvature of the light wave propagation, and avoiding strong bending radiation loss in small-radius waveguides. Simultaneously, it can increase the natural convection heat dissipation channel, increase the contact area between the upper and lower surfaces of the waveguide and the air, enhance convection heat transfer, and significantly reduce the peak temperature of hot spots. Furthermore, it can improve the sidewall bonding strength and enhance the photosensitivity of the photosensitive area 147 and the waveguide efficiency of the transparent adhesive layer 146.

[0099] In practical use, the co-encapsulated optical structure 100 can be mounted on a substrate 400. An optical fiber module 410 can be disposed on the substrate 400. The optical fiber module 410 is disposed adjacent to the optical module 143, thereby achieving lateral coupling.

[0100] This invention provides a method for preparing a co-encapsulated optical structure 100. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0101] The method for fabricating the co-encapsulated optical structure 100 provided in this embodiment of the invention includes the following steps: S1: A substrate dielectric layer 110 is formed on the substrate 200.

[0102] S2: The substrate medium layer 110 is punched and cut using a cutting fixture 300 to form a substrate pattern opening 111 on the substrate medium layer 110.

[0103] S3: Using a cutting fixture 300, a base metal layer 120 is formed by electroplating in the base pattern opening 111.

[0104] S4: A wiring assembly layer 130 is formed on the substrate dielectric layer 110.

[0105] Specifically, the wiring combination layer 130 includes a multilayer wiring dielectric layer 131, a multilayer wiring metal layer 132, and an optical module 143, wherein the multilayer wiring metal layer 132 is disposed in the multilayer wiring dielectric layer 131, and the optical module 143 is embedded in the multilayer wiring dielectric layer 131. In actual manufacturing, the optical module 143 can be avoided by using a special cutting fixture 300.

[0106] S5: Attach multiple heterogeneous chips 140 on the wiring combination layer 130.

[0107] S6: Form a molding layer 150 on the wiring assembly layer 130.

[0108] S7: Grind to remove substrate 200 and expose substrate dielectric layer 110.

[0109] S8: Solder balls 112 are formed on the substrate dielectric layer 110.

[0110] This invention provides a method for fabricating a co-packaged optical structure 100 and the co-packaged optical structure 100. By embedding the optical module 143 in a multilayer wiring dielectric layer 131, side light emission is achieved and the packaging height is reduced, which is beneficial to the miniaturization of the packaging structure.

[0111] Fourth embodiment See Figure 17 This embodiment of the invention also provides a co-encapsulated optical structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0112] The co-packaged optical structure 100 includes a substrate dielectric layer 110, a substrate metal layer 120, a wiring assembly layer 130, multiple heterogeneous chips 140, and a molding compound layer 150. One surface of the substrate dielectric layer 110 has a substrate pattern opening 111, and the other surface has solder balls 112. The substrate metal layer 120 is disposed in the substrate pattern opening 111 and electrically connected to the solder balls 112. The wiring assembly layer 130 is disposed on the substrate dielectric layer 110 and electrically connected to the substrate metal layer 120. Multiple heterogeneous chips 140 are mounted on the wiring assembly layer 130. The molding compound layer 150 is disposed on the wiring assembly layer 130 and encapsulates the multiple heterogeneous chips 140.

[0113] The wiring assembly layer 130 includes a first dielectric layer 133, a first metal layer 134, a structural chip 139, a protective layer 135, a second dielectric layer 137, and a second metal layer 138. The first dielectric layer 133 is disposed on the substrate dielectric layer 110, the first metal layer 134 is located in the first dielectric layer 133, the structural chip 139 is mounted on the first dielectric layer 133, the protective layer 135 is disposed on the first dielectric layer 133 and covers the structural chip 139, and conductive pillars 136 are formed in the protective layer 135. The conductive pillars 136 are electrically connected to the first metal layer 134. The second dielectric layer 137 is disposed on the protective layer 135, the second metal layer 138 is disposed in the second dielectric layer 137 and is electrically connected to the conductive pillars 136. The structural chip 139 is electrically connected to either the first metal layer 134 or the second metal layer 138, preferably the structural chip 139 is electrically connected to the second metal layer 138.

[0114] In practical use, the co-encapsulated optical structure 100 can be mounted on a substrate 400. An optical fiber module 410 can be disposed on the substrate 400. The optical fiber module 410 is disposed adjacent to the optical module 143. The optical module 143 extends outward and is coupled to the optical fiber module 410 from the top side.

[0115] This invention provides a method for preparing a co-encapsulated optical structure 100. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0116] S1: A substrate dielectric layer 110 is formed on the substrate 200.

[0117] S2: The substrate medium layer 110 is punched and cut using a cutting fixture 300 to form a substrate pattern opening 111 on the substrate medium layer 110.

[0118] S3: Using a cutting fixture 300, a base metal layer 120 is formed by electroplating in the base pattern opening 111.

[0119] S4: A wiring assembly layer 130 is formed on the substrate dielectric layer 110.

[0120] Specifically, the wiring assembly layer 130 includes a first dielectric layer 133, a first metal layer 134, a structural chip 139, a protective layer 135, a second dielectric layer 137, and a second metal layer 138. In actual fabrication, the first dielectric layer 133 and the first metal layer 134 can be formed first on the substrate dielectric layer 110, with the first metal layer 134 located within the first dielectric layer 133. Then, the structural chip 139 is mounted on the first dielectric layer 133. Next, a protective layer 135 is formed on the first dielectric layer 133, covering the structural chip 139. Then, conductive pillars 136 are formed in the protective layer 135, electrically connected to the first metal layer 134. Finally, the second dielectric layer 137 and the second metal layer 138 are formed on the protective layer 135, with the second metal layer 138 located within the first dielectric layer 133 and electrically connected to the conductive pillars 136. The structural chip 139 is electrically connected to the first metal layer 134 or the second metal layer 138, preferably the structural chip 139 is electrically connected to the second metal layer 138.

[0121] S5: Attach multiple heterogeneous chips 140 on the wiring combination layer 130.

[0122] S6: Form a molding layer 150 on the wiring assembly layer 130.

[0123] S7: Grind to remove substrate 200 and expose substrate dielectric layer 110.

[0124] S8: Solder balls 112 are formed on the substrate dielectric layer 110.

[0125] It should be noted that the structure chip 139 here can be at least one of a control chip, a logic chip, and a memory chip. By further integrating the packaged structure chip 139 within the wiring combination layer 130, the chip packaging density can be increased. Meanwhile, the protective layer 135 here can also be a dielectric material, which, while protecting the structure chip 139, also acts as a buffer, effectively mitigating warpage and stress concentration in the multi-layer wiring structure. The conductive pillar 136 can be a metal pillar, such as a copper pillar, which enables electrical connection between upper and lower layers of wiring structures, improving transmission efficiency.

[0126] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a co-encapsulated optical structure, characterized in that, include: A substrate dielectric layer is formed on the substrate; The substrate dielectric layer is punched and cut using a cutting fixture to form a substrate pattern opening on the substrate dielectric layer. The surface of the cutting fixture is provided with a cutting head protrusion for cutting to form the substrate pattern opening. The cutting head protrusion is also provided with an electroplating opening, and the electroplating opening is movably sealed with a cap. A base metal layer is formed by electroplating in the opening of the base pattern using the cutting fixture, wherein the electroplating solution flows into the base pattern opening from the electroplating opening. A wiring assembly layer is formed on the substrate dielectric layer, wherein the wiring assembly layer is electrically connected to the substrate metal layer; Multiple heterogeneous chips are mounted on the wiring assembly layer; A molding compound layer is formed on the wiring assembly layer, and the molding compound layer covers the plurality of heterogeneous chips; The substrate is removed by grinding, exposing the substrate dielectric layer; Solder balls are formed on the substrate dielectric layer, wherein the solder balls are electrically connected to the substrate metal layer.

2. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of punching and cutting the substrate dielectric layer using a cutting fixture includes: The cutting fixture is used to perform lamination and stamping cutting with the side of the cutting head protruding towards the substrate medium. The cutting fixture is separated to form a substrate pattern opening on the substrate medium layer.

3. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, Prior to the step of electroplating to form a base metal layer in the opening of the substrate pattern using the cutting fixture, the method further includes: Open the cap and chemically clean the opening of the substrate pattern, wherein the cleaning solution flows into the opening of the substrate pattern corresponding to the electroplating opening; The cutting fixture has a receiving cavity that is connected to the electroplating opening and is used to receive cleaning solution or electroplating solution.

4. The method for fabricating the co-encapsulated optical structure according to claim 2, characterized in that, The step of electroplating a base metal layer in the opening of the substrate pattern using the cutting fixture includes: The cutting fixture is attached to the substrate medium layer so that the blade protrusion extends into the substrate pattern opening; Open the cap and inject the electroplating solution into the patterned opening of the substrate; The cutting fixture is separated to form a base metal layer in the opening of the base pattern.

5. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, After the step of electroplating to form a base metal layer in the opening of the substrate pattern using the cutting fixture, the method further includes: The thickness of the base metal layer is measured using the cutting fixture, wherein the cap contacts the base metal layer, and the thickness of the base metal layer is obtained by measuring the resistivity of the base metal layer.

6. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of grinding to remove the substrate and expose the substrate dielectric layer includes: Using the substrate dielectric layer as the grinding stop layer, the substrate is ground until the substrate dielectric layer is exposed; The substrate dielectric layer is ground to reduce its thickness.

7. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of forming a wiring assembly layer on the substrate dielectric layer includes: Multiple wiring dielectric layers and multiple wiring metal layers are formed on the substrate dielectric layer, wherein the multiple wiring metal layers are disposed within the multiple wiring dielectric layers.

8. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of forming a wiring assembly layer on the substrate dielectric layer includes: A multilayer wiring dielectric layer, a multilayer wiring metal layer, and an optical module are formed on the substrate dielectric layer, wherein the multilayer wiring metal layer is disposed in the multilayer wiring dielectric layer, and the optical module is embedded in the multilayer wiring dielectric layer.

9. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of forming a wiring assembly layer on the substrate dielectric layer includes: A first dielectric layer and a first metal layer are formed on the substrate dielectric layer, wherein the first metal layer is located in the first dielectric layer; A structural chip is mounted on the first dielectric layer; A protective layer is formed on the first dielectric layer, wherein the protective layer covers the structure chip; Conductive pillars are formed in the protective layer, wherein the conductive pillars are electrically connected to the first metal layer; A second dielectric layer and a second metal layer are formed on the protective layer, wherein the second metal layer is located in the first dielectric layer and is electrically connected to the conductive pillar; The structure chip is electrically connected to the first metal layer or the second metal layer.

10. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of mounting multiple heterogeneous chips on the wiring assembly layer includes: A first chip and a second chip are mounted on the wiring assembly layer, with the second chip located on both sides of the first chip.

11. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of mounting the first chip and the second chip on the wiring assembly layer includes: A first chip, a second chip, and an optical module are mounted on the wiring assembly layer, with the second chip located on one side of the first chip and the optical module located on the other side of the first chip.

12. A co-packaged optical structure, fabricated using the method for fabricating a co-packaged optical structure as described in claim 1, characterized in that, The common packaging optical structure includes: The substrate dielectric layer has a substrate pattern opening on one side surface and solder balls on the other side surface. A base metal layer is disposed in the opening of the base pattern and is electrically connected to the solder ball; A wiring assembly layer is disposed on the substrate dielectric layer and electrically connected to the substrate metal layer; Multiple heterogeneous chips are mounted on the wiring assembly layer; A molding layer is disposed on the wiring assembly layer and covers the plurality of heterogeneous chips.

13. The co-encapsulated optical structure according to claim 12, characterized in that, The plurality of heterogeneous chips include a first chip and a second chip, with the second chip located on both sides of the first chip.

14. The co-packaged optical structure according to claim 12, characterized in that, The plurality of heterogeneous chips include a first chip, a second chip, and an optical module, wherein the second chip is located on one side of the first chip, and the optical module is located on the other side of the first chip.

15. The co-packaged optical structure according to claim 14, characterized in that, The optical module includes a photonic chip and an electronic chip. The photonic chip has a photosensitive area, and the electronic chip is disposed on the photonic chip and offset from the photosensitive area.

16. The co-packaged optical structure according to claim 15, characterized in that, The optical module also includes a transparent adhesive layer, which is disposed on the photonic chip and covers the photosensitive area, and the transparent adhesive layer is exposed outside the molding layer.

17. The co-encapsulated optical structure according to claim 16, characterized in that, The molding layer has grooves to form clearance notches, which are configured to expose the transparent adhesive layer.

18. The co-packaged optical structure according to claim 14, characterized in that, The optical module includes a photonic chip, an electron chip, a transparent adhesive layer, a molding compound, and a structural substrate. The photonic chip has a photosensitive area that extends to the sidewall of the photonic chip. The electron chip is disposed on the photonic chip and is offset from the photosensitive area. The transparent adhesive layer is disposed on the photonic chip and covers the photosensitive area; the structural substrate is disposed on the transparent adhesive layer; the encapsulation body is disposed on the photonic chip and encapsulates the electron chip; wherein, the encapsulation body is further provided with an electrical post, one end of which is connected to a pad on the surface of the photonic chip, and the other end is exposed outside the encapsulation body.

19. The co-packaged optical structure according to claim 12, characterized in that, The wiring combination layer includes multiple wiring dielectric layers and multiple wiring metal layers, wherein the multiple wiring metal layers are disposed within the multiple wiring dielectric layers.

20. The co-packaged optical structure according to claim 12, characterized in that, The wiring combination layer includes multiple wiring dielectric layers, multiple wiring metal layers, and an optical module, wherein the multiple wiring metal layers are disposed in the multiple wiring dielectric layers, and the optical module is embedded in the multiple wiring dielectric layers.

21. The co-packaged optical structure according to claim 12, characterized in that, The wiring assembly layer includes a first dielectric layer, a first metal layer, a structural chip, a protective layer, a second dielectric layer, and a second metal layer. The first dielectric layer is disposed on the substrate dielectric layer, the first metal layer is located in the first dielectric layer, the structural chip is mounted on the first dielectric layer, the protective layer is disposed on the first dielectric layer and covers the structural chip, and conductive pillars are formed in the protective layer. The conductive pillars are electrically connected to the first metal layer. The second dielectric layer is disposed on the protective layer, the second metal layer is disposed in the second dielectric layer and is electrically connected to the conductive pillars. The structural chip is electrically connected to either the first metal layer or the second metal layer.

Images