Packaging structure and electronic device

Abstract

The embodiments of the present disclosure provide a packaging structure and an electronic device in the technical field of semiconductor packaging. The packaging structure includes a substrate, a device assembly, a filling layer and an encapsulation layer. The device assembly is located on a first side of the substrate and electrically connected to the substrate, and includes a first semiconductor structure and a second semiconductor structure which are adjacent and spaced apart. The encapsulation layer is arranged on the first side of the substrate and at least partially arranged on the sidewall of the first semiconductor structure. The filling layer includes a first part between the device assembly and the substrate and a second part between the sidewall of the second semiconductor structure and the encapsulation layer. In a direction parallel to the main surface of the substrate, a part of the encapsulation layer is located between the second part of the filling layer and the first semiconductor structure. The encapsulation layer has a groove between the first semiconductor structure and the second semiconductor structure, the groove extends from the surface of the encapsulation layer away from the substrate into the encapsulation layer, and is spaced apart from the filling layer to reduce the possibility of cracking of the filling layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of semiconductor packaging technology, and in particular to a packaging structure and electronic device. Background Technology

[0002] In semiconductor packaging technology, chips are packaged to provide protection, physical and / or electrical connections, etc. Multiple chips can be integrated together through packaging technology; for example, system-on-a-chip (SoC) and memory chips can be integrated to achieve high-performance computing. However, cracking of the film layers in the packaging structure can affect its reliability. Summary of the Invention

[0003] This invention application provides at least one embodiment of a packaging structure and an electronic device.

[0004] This invention application provides at least one embodiment of a packaging structure. The packaging structure includes: a substrate having opposing first and second sides; a device assembly located on the first side of the substrate and electrically connected to the substrate, including a first semiconductor structure and at least one second semiconductor structure disposed adjacent to each other and spaced apart; an encapsulation layer disposed on the first side of the substrate and at least partially disposed on the sidewall of the first semiconductor structure; a filler layer including a first portion located between the device assembly and the substrate and a second portion located between the sidewall of the at least one second semiconductor structure and the encapsulation layer; wherein, in a direction parallel to the main surface of the substrate, a portion of the encapsulation layer is located between the second portion of the filler layer and the first semiconductor structure; the encapsulation layer has a groove located between the first semiconductor structure and the at least one second semiconductor structure, the groove extending from the surface of the encapsulation layer on the side away from the substrate into the encapsulation layer and spaced apart from the filler layer.

[0005] For example, according to at least one embodiment of the present invention, the at least one second semiconductor structure includes a plurality of second semiconductor structures; the first semiconductor structure includes a first side and a second side connected together, a second semiconductor structure is disposed on one side of the first side, and another second semiconductor structure is disposed on one side of the second side; the groove is located between at least one of the first side and the second side and the second semiconductor structure.

[0006] For example, according to at least one embodiment of the present invention, in a direction parallel to the main surface of the substrate, the filler layer includes a first extension portion and a second extension portion that are connected to and intersect each other; the device assembly includes a first device structure and a second device structure located on both sides of the first extension portion; the first device structure includes an adjacent first semiconductor structure and a second semiconductor structure, and the second extension portion is located between the adjacent first semiconductor structure and the second semiconductor structure; the second device structure includes only the second semiconductor structure; the package structure is configured to satisfy at least one of the following conditions: the recess is located between the first extension portion and the first semiconductor structure; the recess is located between the second extension portion and the first semiconductor structure.

[0007] For example, according to at least one embodiment of the present invention, the second extension portion is located on one side of the first extension portion, and the extension direction of the second extension portion passes through the second semiconductor structure in the second device structure.

[0008] For example, according to at least one embodiment of the present invention, the second portion of the filling layer includes a first filling portion and a second filling portion located between and connected to the first semiconductor structure and the at least one second semiconductor structure, the first filling portion extending along a first direction and the second filling portion extending along a second direction; in a direction parallel to the main surface of the substrate, the groove is located between at least one of the first filling portion and the second filling portion and the first semiconductor structure; the first direction and the second direction intersect each other and are both parallel to the main surface of the substrate.

[0009] For example, according to at least one embodiment of the present invention, the groove includes a first groove portion extending along the first direction and a second groove portion extending along the second direction.

[0010] For example, according to at least one embodiment of the present invention, the first groove and the second groove are in communication with each other.

[0011] For example, according to at least one embodiment of the present invention, the first groove portion has a size of not less than 100 micrometers in the first direction, and the second groove portion has a size of not less than 100 micrometers in the second direction.

[0012] For example, according to at least one embodiment of the present invention, the at least one second semiconductor structure includes a plurality of second semiconductor structures, and the portion of the second portion of the filling layer located between adjacent second semiconductor structures is in contact with the adjacent second semiconductor structures respectively.

[0013] For example, according to at least one embodiment of the present invention, the spacing between the edges of adjacent first semiconductor structures and second semiconductor structures facing each other is a first dimension, and the width of the portion of the filling layer located between adjacent second semiconductor structures is a second dimension; the first dimension is larger than the second dimension.

[0014] For example, according to at least one embodiment of the present invention, the first size is 200 micrometers to 1000 micrometers, and the second size is 40 micrometers to 150 micrometers.

[0015] For example, according to at least one embodiment of the present invention, the encapsulation layer includes an encapsulation structure surrounding and encapsulating the first semiconductor structure, the encapsulation structure being integrally formed with the first semiconductor structure; the groove is formed on the encapsulation structure.

[0016] For example, according to at least one embodiment of the present invention, the packaging structure has a device component region, the device component region including the first semiconductor structure, the encapsulation structure surrounding and encapsulating the first semiconductor structure, and the at least one second semiconductor structure; the encapsulation layer further includes an encapsulation portion, at least a portion of which surrounds the device component region in the circumferential direction.

[0017] For example, according to at least one embodiment of the present invention, the distance between the outer edge of the opening of the groove and the outer edge of the encapsulation structure is 10 micrometers to 900 micrometers in a direction parallel to the main surface of the substrate.

[0018] For example, according to at least one embodiment of the present invention, in a direction parallel to the main surface of the substrate, the distance between the outer edge of the opening of the groove and the edge of the first semiconductor structure is 10 micrometers to 900 micrometers.

[0019] For example, according to at least one embodiment of the present invention, on the main surface of the substrate, the orthographic projection of the groove surrounds a portion of the orthographic projection of the first semiconductor structure in the circumferential direction.

[0020] For example, according to at least one embodiment of the present invention, the groove is a discontinuous structure and includes a plurality of sub-grooves spaced apart along a direction parallel to the main surface of the substrate.

[0021] For example, according to at least one embodiment of the present invention, in a direction perpendicular to the main surface of the substrate, the depth of the groove is less than or equal to 1 / 2 of the thickness of the encapsulation layer.

[0022] For example, according to at least one embodiment of the present invention, the first semiconductor structure includes a first chip, and the at least one second semiconductor structure includes at least one of a second chip, a capacitor structure, and a dummy structure.

[0023] For example, according to at least one embodiment of the present invention, the first chip is a memory chip and the second chip is a logic chip.

[0024] For example, according to at least one embodiment of the present invention, the coefficient of thermal expansion of the filling layer is greater than the coefficient of thermal expansion of the first semiconductor structure and the coefficient of thermal expansion of the at least one second semiconductor structure, and less than the coefficient of thermal expansion of the encapsulation layer.

[0025] For example, according to at least one embodiment of the present invention, the encapsulation structure further includes: an additional filler layer filling the groove of the encapsulation layer, wherein the coefficient of thermal expansion of the additional filler layer is less than the coefficient of thermal expansion of the encapsulation layer.

[0026] This invention application provides an electronic device according to at least one embodiment. The electronic device includes the packaging structure of any of the above embodiments.

[0027] According to at least one embodiment of the packaging structure and electronic device provided in this application, the packaging structure can reduce or even eliminate the possibility of cracking of the filler layer. As a result, the yield of the packaging structure is improved, and it can maintain good packaging performance under more extreme operating conditions (such as high temperature, high humidity, high and low temperature cycling, etc.), thereby improving the reliability of the packaging structure. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0029] Figure 1A A schematic plan view of an encapsulation structure is shown.

[0030] Figure 1B The schematic diagram illustrates the surface morphology of a packaging structure after a planarization process.

[0031] Figure 2 This is a schematic plan view of an example of an encapsulation structure provided in at least one embodiment of the present disclosure.

[0032] Figure 3 for Figure 2 The diagram shows a schematic cross-sectional view of the encapsulation structure taken along line AA'.

[0033] Figure 4A for Figure 2 A magnified view of a portion of point P1.

[0034] Figure 4B for Figure 2A magnified view of a portion of point P2.

[0035] Figure 5 This is a schematic cross-sectional view of the packaging structure provided as an example in at least one embodiment of the present disclosure.

[0036] Figures 6 to 9 This is a schematic plan view of the packaging structure provided for different examples in at least one embodiment of the present disclosure.

[0037] Figure 10 This is a schematic diagram of an electronic device provided as an example in at least one embodiment of the present disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0040] The terms "parallel," "perpendicular," and "identical" as used in this disclosure include the strictly defined meanings of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include some degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. In embodiments of this disclosure, "center" can include a strictly geometrically centered location and an approximate center location within a small area surrounding the geometrically centered location. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0041] Chip on wafer on substrate (CoWoS) packaging is an advanced packaging technology that enables high-density circuitry between multiple chips and high-speed data transmission. CoWoS packaging is a 2.5D chip packaging widely used in fields such as artificial intelligence (AI). This packaging structure includes a chip on wafer (CoW) module and a packaging substrate. The CoW module typically includes silicon-based structures such as chips, filler layers, molding compound, adapters, and conductive terminals.

[0042] In the manufacturing process of CoWoS packaging, the packaging process of the CoW module is first completed, followed by the assembly of the flip chip ball grid array (FCBGA) to mount the CoW module onto the packaging substrate to form the CoWoS packaging structure.

[0043] Figure 1A A schematic plan view of an encapsulation structure is shown. Figure 1B The schematic diagram illustrates the surface morphology of a packaging structure after a planarization process.

[0044] During the research, the inventors of this application discovered that, referring to Figure 1A and Figure 1B The filler layer 003 covering the corner of the silicon-based structure 001 will inevitably come into contact with the molding compound 004 and another silicon-based structure 002. For example... Figure 1A As indicated by the middle arrow, the molding compound 004 will continue to undergo chemical shrinkage at high temperatures. Due to the combined effects of thermal expansion and contraction, stress concentration is likely to occur at the corner 001C of the silicon-based structure 001. Under extreme conditions such as high temperature, high humidity, and high-low temperature cycling, different materials will experience varying degrees of thermal expansion due to the mismatch in their coefficients of thermal expansion. Therefore, the filler layer 003 covering the corner 001C of the silicon-based structure 001 is likely to crack. Figure 1A and Figure 1B The CK point shown indicates that the packaging structure failed.

[0045] In response, at least one embodiment of this disclosure provides a packaging structure that can reduce or even eliminate the possibility of cracking in the filler layer. This improves the yield of the packaging structure and allows it to maintain good packaging performance under more extreme operating conditions (such as high temperature, high humidity, and high / low temperature cycling), thereby enhancing the reliability of the packaging structure.

[0046] At least one embodiment of this disclosure provides a packaging structure and an electronic device. The packaging structure includes a substrate, a device assembly, a filler layer, and an encapsulation layer. The substrate has opposing first and second sides; the device assembly is located on the first side of the substrate and electrically connected to the substrate, and includes a first semiconductor structure and at least one second semiconductor structure disposed adjacent to each other and spaced apart; the encapsulation layer is disposed on the first side of the substrate and is at least partially disposed on the sidewall of the first semiconductor structure; the filler layer includes a first portion located between the device assembly and the substrate and a second portion located between the sidewall of the second semiconductor structure and the encapsulation layer; in a direction parallel to the main surface of the substrate, a portion of the encapsulation layer is located between the second portion of the filler layer and the first semiconductor structure; the encapsulation layer has a groove located between the first semiconductor structure and the at least one second semiconductor structure, the groove extending from the surface of the encapsulation layer away from the substrate into the encapsulation layer and spaced apart from the filler layer.

[0047] In the packaging structure and electronic device provided in at least one embodiment of this disclosure, by providing a groove in the encapsulation layer and designing the groove opening position between the first semiconductor structure and the second semiconductor structure, the structural continuity of the encapsulation layer can be broken at locations prone to stress concentration. In cases where the encapsulation layer undergoes chemical shrinkage or thermal expansion and contraction due to factors such as high temperature, the groove between the first and second semiconductor structures can be used to alleviate stress. As a result, the stress on the second portion of the fill layer located between the sidewall of the second semiconductor structure and the encapsulation layer is correspondingly reduced, thereby reducing or even eliminating the possibility of cracking in the fill layer. Consequently, the yield of the packaging structure is improved, and better packaging performance can be maintained under more extreme operating conditions (such as high temperature, high humidity, and high and low temperature cycling), thus improving the reliability of the packaging structure.

[0048] The packaging structure and electronic device are described below with reference to the accompanying drawings and through some embodiments.

[0049] Figure 2 This is a schematic plan view of the packaging structure provided in at least one embodiment of the present disclosure. Figure 3 for Figure 2 The diagram shows a schematic cross-sectional view of the encapsulation structure taken along line AA'. It should be understood that... Figure 2 The positions of the two vertices of line AA' in the X direction are shown, and... Figure 3 The two edges of the cross-section shown are in one-to-one correspondence in the X direction.

[0050] refer to Figure 2 and Figure 3 The packaging structure includes a substrate 10, a device assembly 100, a filler layer 200, and an encapsulation layer 300. For example... Figure 3As shown, the substrate 10 has opposing first sides 10a and second sides 10b. For example, the first sides 10a and second sides 10b are located at... Figure 3 The components are opposite each other in the Z direction. The device assembly 100 is located on the first side 10a of the substrate 10 and is electrically connected to the substrate 10. The device assembly 100 includes adjacent and spaced-apart first semiconductor structures 101 and at least one (such as one or more) second semiconductor structures 102.

[0051] It should be understood that the term "adjacent" as used above means that, among the multiple semiconductor structures included in the device assembly, no other semiconductor structures are disposed between the first semiconductor structure and the second semiconductor structure. However, adjacent does not mean that the first semiconductor structure and the second semiconductor structure are in close proximity (such as being in direct contact). Other structures, such as encapsulation layers, filling layers, etc., may exist between them.

[0052] refer to Figure 2 and Figure 3 The filling layer 200 includes a first portion 210 located between the device assembly 100 and the substrate 10, and a second portion 220 located between the sidewall of the second semiconductor structure 102 and the encapsulation layer 300. For example, the first portion 210 of the filling layer 200 fills the space between the device assembly 100 and the substrate 10, and the second portion 220 of the filling layer 200 covers the sidewall of the second semiconductor structure 102. Figure 3 The second portion 220, located between the sidewall of the second semiconductor structure 102 and the encapsulation layer 300, is schematically outlined with a dashed box.

[0053] refer to Figure 2 and Figure 3 An encapsulation layer 300 is disposed on a first side 10a of the substrate 10, and at least partially disposed on the sidewall of the first semiconductor structure 101. In a direction parallel to the main surface of the substrate 10, a portion of the encapsulation layer 300 is located between the second portion 220 of the fill layer 200 and the first semiconductor structure 101. For example, the encapsulation layer 300 may be in direct contact with the fill layer 200. For example, the main surface of the substrate 10 may be the top surface of the substrate 10, such as the surface of the first side 10a of the substrate 10.

[0054] For example, Figure 2 and Figure 3 The schematic diagram shows that the direction parallel to the main surface of the substrate 10 can be the direction indicated by the X-direction arrow and the direction opposite to the direction indicated by the arrow, or it can be... Figure 2 The arrow in the Y direction is shown in both directions and directions opposite to the arrow. However, this disclosure is not limited thereto, and directions parallel to the main surface of the substrate 10 may also be other directions intersecting the X and / or Y directions, which are not limited herein.

[0055] refer to Figure 3 The encapsulation layer 300 has a groove 310 located between the first semiconductor structure 101 and the second semiconductor structure 102. For example, the orthographic projection of the groove 310 on the substrate 10 lies between the orthographic projection of the first semiconductor structure 101 on the substrate 10 and the orthographic projection of the second semiconductor structure 102 on the substrate 10. For example, in a direction parallel to the substrate 10, the groove 310 may be located between the first semiconductor structure 101 and the second semiconductor structure 102.

[0056] refer to Figure 3 The groove 310 extends from the surface of the encapsulation layer 300 away from the substrate 10 into the encapsulation layer 300 and is spaced apart from the filler layer 200. For example, in a direction perpendicular to the substrate 10, there is a gap between the bottom wall of the groove 310 and the filler layer 200. For example, the groove 310 extends toward the filler layer 200 but does not expose the filler layer 200. Thus, the encapsulation layer 300 can be used to protect the device assembly 100, preventing damage to the device assembly 100 during the formation of the groove 310, and also helping to ensure the structural stability of the encapsulation layer 300 and the overall package.

[0057] It should be understood that the aforementioned direction perpendicular to the substrate can be a direction perpendicular to the main surface of the substrate, for example, it can be... Figure 3 The direction indicated by the Z-direction arrow or the direction opposite to the direction indicated by the arrow.

[0058] refer to Figure 2 and Figure 3 In the packaging structure provided in this embodiment, by providing a groove 310 in the encapsulation layer 300 and designing the groove 310's opening position between the first semiconductor structure 101 and the second semiconductor structure 102, the structural continuity of the encapsulation layer 300 can be broken at locations prone to stress concentration. In cases where the encapsulation layer 300 undergoes chemical shrinkage or thermal expansion and contraction due to factors such as high temperature, the groove 310 between the first semiconductor structure 101 and the second semiconductor structure 102 can be used to alleviate stress. As a result, the stress on the second portion 220 of the filler layer 200 covering the sidewall of the second semiconductor structure 102 is correspondingly reduced, thereby reducing or even eliminating the possibility of cracking in the filler layer 200. Therefore, the yield of the packaging structure is improved, and it can maintain good packaging performance under more extreme operating conditions (such as high temperature, high humidity, and high and low temperature cycling), thus improving the reliability of the packaging structure.

[0059] Specifically, refer to Figure 2 The sidewall of the second semiconductor structure 102 is covered with a second portion 220 of the filling layer 200, and a portion of the encapsulation layer 300 extends between the second portion 220 and the first semiconductor structure 101. Figure 1A and Figure 1B According to the relevant description, when an angle is formed between the edges of two second semiconductor structures 102, and a first semiconductor structure 101 is disposed at this angle, an encapsulation layer 300 and a filler layer 200 exist between the first semiconductor structure 101 and the adjacent second semiconductor structure 102. Because the encapsulation layer 300 and the filler layer 200 are made of different materials, there is a mismatch in their coefficients of thermal expansion. After the encapsulation layer 300 contracts at high temperatures and generates thermal stress, it covers the corner of the second semiconductor structure 102 (e.g., ...). Figure 2 Stress concentration is likely to occur in the filler layer 200 outside the corners C1 and C2 shown. By slotting the encapsulation layer 300 near the corners of the second semiconductor structure 102, the stress at the corners of the second semiconductor structure 102 can be effectively reduced, thereby preventing cracking of the filler layer 200.

[0060] refer to Figure 3 For example, the package structure may also include a plurality of conductive terminals 400 disposed on a second side 10b of the substrate 10. For example, the conductive terminals 400 and the device assembly 100 may be disposed on opposite sides of the substrate 10. For example, the conductive terminals 400 may include solder balls, such as or include controlled collapsed chip connection (C4) bumps.

[0061] refer to Figure 3 For example, substrate 10 can be an adapter plate. For example, the adapter plate can be a silicon-based adapter plate and includes a substrate 11, an interconnect structure 12, and a substrate via 13. Substrate 11 can be or include a semiconductor substrate such as a silicon substrate. A substrate via 13 (TSV) is provided in substrate 11 to provide electrical connections between conductive members located on opposite sides of substrate 11. For example, interconnect structure 12 includes an inorganic dielectric structure and a conductive structure (not shown). The inorganic dielectric structure can be a single-layer or multi-layer structure and may include inorganic dielectric materials such as silicon oxide and silicon nitride. The conductive structure is embedded in the inorganic dielectric structure and may include one or more layers of conductive traces and conductive vias. The conductive structure is electrically connected to the substrate via 13 and is used to provide electrical connections between multiple devices in device assembly 100 and between device assembly 100 and conductive terminal 400.

[0062] It should be understood that the substrate can also be other structures, as long as it enables the bonding of device components and conductive terminals to the structure to achieve electrical interconnection, and this disclosure does not limit this.

[0063] refer to Figure 2For example, device assembly 100 may include multiple semiconductor devices, such as chips. Device assembly 100 may also include other devices such as capacitors or dummy structures, which will be discussed later.

[0064] For example, multiple chips in a device assembly may include chips of the same or different types. The number and type of chips can be selected according to product requirements; for example, the aforementioned multiple chips may include one or more of the following: system on chip (SoC), digital signal processor (DSP) chip, graphics processing unit (GPU), application specific integrated circuit (ASIC) chip, high bandwidth memory (HBM) and other memory chips, central processing unit (CPU), tensor processing unit (TPU), neural network processing unit (NPU), deep learning processing unit (DPU), accelerated processing unit (APU), general-purpose computing on graphics processing unit (GPGPU), and chiplet.

[0065] refer to Figure 2 In some examples, the first semiconductor structure 101 includes a first chip. For example, device assembly 100 may include one or more first chips. For example, the first chip may be a memory chip, such as an add-on chip. For example, the first chip may be HBM.

[0066] refer to Figure 2 In some examples, the second semiconductor structure 102 includes a second chip. For example, device assembly 100 may include one or more second chips. For example, the second chip may be a logic chip, such as a main chip. For example, the second chip may be a System-on-a-Chip (SoC). For example, the second chip may be other types of chips, such as chips with specific functions, such as input / output dies (IO dies).

[0067] refer to Figure 2In some examples, the second semiconductor structure 102 may also include at least one of a capacitor structure (Cap) and a dummy structure (dummy). For example, the second semiconductor structure 102 may include either a capacitor structure or a dummy structure. For example, the second semiconductor structure 102 may include both a capacitor structure and a dummy structure. For example, the dummy structure may include structures such as a dummy die, and this disclosure is not limiting in this regard.

[0068] For example, the material of at least one of the first semiconductor structure and the second semiconductor structure may include silicon.

[0069] refer to Figure 2 and Figure 3 In some examples, the coefficient of thermal expansion (CTE) of the filler layer 200 is greater than that of the first semiconductor structure 101 and greater than that of the second semiconductor structure 102, but less than that of the encapsulation layer 300. The CTE of the filler layer 200 lies between the CTE of the semiconductor structures in the device assembly 100 and that of the encapsulation layer 300, thus mitigating the thermal stress mismatch between the device assembly 100 and the encapsulation layer 300.

[0070] Figure 4A for Figure 2 A magnified view of a portion of point P1. Figure 4B for Figure 2 A magnified view of a portion of point P2.

[0071] Below, in conjunction with Figures 2 to 4B The following explanation will be based on the example of a first semiconductor structure being HBM and a second semiconductor structure including silicon.

[0072] In packaging structures, multiple chips (including actual chips and dummy chips) and capacitors are typically arranged on the substrate. Regardless of the arrangement method, a silicon-HBM-silicon arrangement is unavoidable. For example... Figure 4A and Figure 4B As shown, the first semiconductor structure 101 has at least a portion of the second semiconductor structure 102 on both one side in the X direction and one side in the Y direction, thereby forming the aforementioned silicon-HBM-silicon arrangement. In this arrangement, the filler layer 200 formed between the first semiconductor structure 101 and the second semiconductor structure 102 has a local structure that is roughly "T" shaped, which covers the corner of the second semiconductor structure 102 (as shown in the upper right corner of the figure).

[0073] from Figure 3As can be seen in the schematic cross-sectional view shown, a portion of the fill layer 200 (i.e., the second portion 220 of the fill layer 200) covers the sidewall of the second semiconductor structure 102, and a portion of the encapsulation layer 300 extends between the second portion 220 of the fill layer 200 and the sidewall of the first semiconductor structure 101. (Reference) Figure 3 and Figure 4A Because the groove 310 in the encapsulation layer 300 breaks the structural integrity of the encapsulation layer 300, the groove 310 can act as a stress buffer structure to release stress under high temperature conditions. As a result, the stress concentration problem at the T-shaped structure is alleviated, thereby reducing or even eliminating the possibility of the filling layer 200 cracking at the corner of the second semiconductor structure 102.

[0074] refer to Figure 2 and Figure 3 In some examples, the encapsulation layer 300 includes an encapsulation structure 301 surrounding and encapsulating the first semiconductor structure 101, the encapsulation structure 301 being integrally formed with the first semiconductor structure 101. For example, when the first semiconductor structure 101 is a stacked device, the encapsulation structure 301 can be used to encapsulate the stacked device. For example, when the first semiconductor structure 101 is an HBM, the first semiconductor structure 101 having a multilayer chip stack structure can be encapsulated, thereby forming an encapsulation structure 301 integrally formed with the first semiconductor structure 101 between the chip layers and on the periphery of the first semiconductor structure 101.

[0075] It should be understood that when the first semiconductor structure 101 and the encapsulation structure 301 are integrally formed, a portion of the filler layer 200 is located between the integrally formed structure and the substrate 10. That is, a portion of the filler layer 200 may be filled between the encapsulation structure 301 and the substrate 10.

[0076] For example, the material of the encapsulation structure 301 may include molding compound, such as epoxy molding compound (EMC), and may be formed by molding process.

[0077] However, this disclosure is not limited thereto, and the encapsulation structure may also include a material substantially the same as or identical to that of the filler layer. It should be understood that although the material of the encapsulation structure may be substantially the same as or identical to that of the filler layer 200, the two may be formed using different processes, such as the encapsulation structure being formed using a molding process.

[0078] refer to Figure 2In some examples, the package structure has a device assembly region CR, where the device assembly 100 includes a first semiconductor structure 101, an encapsulation structure 301 surrounding the corresponding first semiconductor structure 101, and a second semiconductor structure 102. For example, the device assembly region CR includes a region where the device assembly 100 is disposed and a region overlapping that region in the Z direction. For example, a recess 310 is located within the device assembly region CR, thereby mitigating stress concentration problems occurring within the device assembly region CR.

[0079] refer to Figure 2 In some examples, the encapsulation layer 300 also includes an encapsulation portion 302. At least a portion of the encapsulation portion 302 surrounds the device assembly region CR in the circumferential direction. Figure 2 As shown, the encapsulation portion 302 can surround the device assembly region CR, thereby covering the outer wall of the second semiconductor structure 102 and the outer wall of the encapsulation structure 301 to achieve reliable packaging. It should be understood that, as Figure 2 As shown, the encapsulation portion 302 surrounding the device assembly region CR may also cover the sidewalls of the filling layer 200.

[0080] For example, the outline of the device assembly region CR can be defined by the lines connecting the outer walls of multiple devices. It should be understood that, in the case where the first semiconductor structure is HBM, the encapsulation structure and HBM can be formed as a single integral structure, thus being considered as a single device. Therefore, the outline of the device assembly region CR can be jointly defined by the lines connecting the outer walls of the devices other than the first semiconductor structure (i.e., the second semiconductor structure) and the outer walls of the encapsulation structure within the device assembly.

[0081] For example, the outer sidewall of a device refers to the sidewall of that device that is not adjacent to or faces other devices, and correspondingly, the inner sidewall of that device refers to the sidewall that is adjacent to or faces other devices. It is understood that, in conjunction with the foregoing examples, when the device assembly includes chips and other devices (such as capacitor structures, dummy structures, etc.), the outline of the aforementioned device assembly region CR is jointly defined by the chips and other devices.

[0082] refer to Figure 2 ,For example, Figure 2 The diagram schematically shows the entire encapsulation portion 302 disposed circumferentially around the device assembly region CR. However, this disclosure is not limited thereto, and the encapsulation portion 302 may also include a portion covering the side surface of the filler layer 200 away from the substrate 10, as will be described later.

[0083] refer to Figure 2For example, the material of the encapsulation portion 302 may include a molding compound, such as an epoxy molding compound (EMC), and may be formed through a molding process. For example, the encapsulation portion 302 may include a base material and a filler. The base material may include organic materials such as epoxy resin, and the filler is dispersed in the organic material, and may include semiconductor materials, inorganic insulating materials, etc., such as silicon, alumina, etc.

[0084] refer to Figure 2 For example, the material of the encapsulation portion 302 may be the same as or different from the material of the encapsulation structure 301. This disclosure does not impose any restrictions on this.

[0085] refer to Figure 2 For example, the package structure also has a peripheral region PR. The peripheral region PR is the area outside the device component region CR, and may, for example, surround the device component region CR in a direction parallel to the main surface of the substrate. Figure 2 and Figure 3 As shown, for example, substrate 10 also has a plurality of terminal regions, each of which may be provided with one or more conductive terminals (such as the conductive terminal 400 in the aforementioned example). A terminal region includes an area on the substrate where conductive terminals are provided, and includes a region overlapping that area in the Z direction perpendicular to the main surface of the substrate. For example, the terminal region may overlap with the device assembly region CR, or may also overlap with a portion of the peripheral region PR. For example, the orthographic projection of the plurality of conductive terminals 400 on the main surface of the substrate overlaps with the orthographic projection of the device assembly 100 on the main surface of the substrate, or may also overlap with the orthographic projection of the encapsulation layer located in the peripheral region on the main surface of the substrate.

[0086] refer to Figure 2 and Figure 3 For example, device assembly 100 may be mounted (e.g., flip-chip mounted) to a first side 10a of substrate 10. For example, a plurality of conductive bumps 110 are provided between device assembly 100 and substrate 10, and one or more chips in device assembly 100 may be electrically connected to substrate 10 via corresponding conductive bumps 110. For example, conductive bumps 110 may include conductive materials such as metal and / or solder, and may be, for example, micro-bumps.

[0087] For example, each chip may include a chip substrate, a device layer, and conductive connectors; the chip substrate is a semiconductor substrate and may be or include a silicon substrate, or may include other semiconductor materials such as germanium; the device layer is disposed on one side of the chip substrate and may include active devices (e.g., transistors), passive devices (e.g., capacitors, inductors, etc.) or combinations thereof, and chip interconnect structures, the various devices being connected through the chip interconnect structures; the conductive connectors are located on the side of the device layer away from the substrate and can be electrically connected to various devices on the chip substrate through the chip interconnect structures; the conductive connectors serve as external connection points for the chip to provide electrical connections between the chip and other components (e.g., the substrate). The side of the chip closest to the device layer (e.g., the side with the conductive connectors) may be referred to as the front side or active side of the chip, and the side of the chip where the substrate is located (i.e., the side opposite to the front side) may be referred to as the back side. For example, each chip may be flip-chip mounted on a substrate such that its front side faces the substrate.

[0088] refer to Figure 2 and Figure 3 After the device assembly 100 is bonded to the substrate 10, a filler layer 200 can be formed by an underfill process, such as by a dispensing process. The colloidal material used to form the filler layer 200 can fill the space between the device assembly 100 and the substrate 10, and can extend to cover the sidewalls of each device. For example, in the case where the first semiconductor structure 101 is covered by an encapsulation structure 301, the colloidal material can extend to cover the sidewalls of the encapsulation structure 301, thereby forming a filler layer 200. Figure 3 The second portion 220 shown is located between the encapsulation structure 301 and the second semiconductor structure 102.

[0089] refer to Figure 3 For example, the material of the filler layer 200 may include organic materials such as epoxy resin.

[0090] refer to Figure 3 For example, the filler layer 200 fills the space between the device assembly 100 and the substrate 10, and surrounds and protects a plurality of conductive bumps 110. For example, a portion of the filler layer 200 may be covered by an encapsulation layer 300, and is spaced apart from the recesses 310 in a direction perpendicular to the substrate 10, i.e., the recesses 310 do not expose the filler layer 200. For example, the filler layer 200 may also extend to cover the sidewalls (including inner and / or outer sidewalls) of the device assembly 100. For example, combined with... Figure 2 and Figure 3 As shown, the extended portion of the fill layer 200 can extend beyond the device assembly region CR and into the peripheral region PR. For example, the sidewalls of the extended portion of the fill layer 200 in the peripheral region can be covered (e.g., completely covered) by the encapsulation layer 300, thus ensuring the overall structural stability of the package structure.

[0091] refer to Figure 2 and Figure 3 For example, the gap between the encapsulation structure 301 and the second semiconductor structure 102 can be filled by at least one of the fill layer 200 and the encapsulation portion 302, such as substantially completely filled. For example, Figure 3 The diagram schematically shows that the gap between the encapsulation structure 301 and the second semiconductor structure 102 is completely filled by the filling layer 200. That is, the surface of the filling layer 200 that is filled between the encapsulation structure 301 and the second semiconductor structure 102 (such as the second portion 220) away from the substrate 10 is approximately flush with the surface of the device in the device assembly 100 away from the substrate 10. For example, the surface formed by the second portion 220 of the filling layer 200 away from the substrate 10, the surface of the first semiconductor structure 101 away from the substrate 10, the surface of the second semiconductor structure 102 away from the substrate 10, and the surface of the encapsulation layer 300 away from the substrate 10 can be approximately parallel to the main surface of the substrate 10.

[0092] However, this disclosure is not limited thereto. For example, the spacing between adjacent devices in a device assembly may be partially filled by a filling layer and partially filled by an encapsulation portion in an encapsulation layer, etc., and this disclosure does not limit this.

[0093] For example, the above-mentioned complete filling means that there are no grooves in the gap between adjacent devices, that is, there are no grooves extending downward from the surface in the encapsulation layer and / or filling layer therein, but the filling layer and / or encapsulation layer therein may contain acceptable small pores or holes formed by the underfill process and / or encapsulation process.

[0094] It should be understood that during the formation of the encapsulation layer, the intermediate material layer used to form the encapsulation portion can cover the surface of the device assembly away from the substrate, the sidewalls of each device, and the sidewalls of the filler layer. In the case of a device in which the first semiconductor structure and the encapsulation structure are integrally formed, the intermediate material layer is correspondingly encapsulated outside the encapsulation structure.

[0095] For example, after forming the intermediate material layer, a planarization process can be used to remove the portion of the intermediate material layer located on the side of the device assembly away from the substrate, thereby exposing the surface of the device assembly away from the substrate and forming a surface such as... Figure 2 The encapsulation portion 302 shown forms an encapsulation layer 300 comprising an encapsulation structure 301 and an encapsulation portion 302. For example, the planarization process described above may include a grinding process, such as a chemical mechanical polishing (CMP) process.

[0096] refer to Figure 2 and Figure 3In some examples, the groove 310 is formed on the encapsulation structure 301. This breaks the structural integrity of the encapsulation structure 301 and uses the groove 310 to release stress, preventing the filling layer 200 from cracking due to stress concentration.

[0097] refer to Figure 2 For example, the portion of the encapsulation structure 301 that covers the first semiconductor structure 101 and contacts the encapsulation portion 302 may not have a groove 310, thereby avoiding the need to open grooves 310 in unnecessary locations to ensure the encapsulation reliability of the encapsulation structure 301.

[0098] refer to Figure 2 and Figure 3 For example, a grooving process such as laser grooving can be used to create the groove 310. For example, a laser beam can be irradiated onto the area of ​​the encapsulation structure 301 where the groove 310 is to be formed, thereby removing a portion of the structure in that area to form the groove 310.

[0099] refer to Figure 3 For example, in the direction perpendicular to the main surface of the substrate 10, the depth h1 of the groove 310 is less than the thickness h2 of the encapsulation layer 300, meaning that the groove 310 will not expose the structure below the encapsulation layer 300, such as the filler layer 200. In some examples, the depth h1 of the groove 310 may be less than or equal to half the thickness h2 of the encapsulation layer 300, thereby ensuring reliable encapsulation of the encapsulation layer 300 while relieving stress using the groove 310, which is beneficial to improving the structural stability of the encapsulation structure.

[0100] refer to Figure 3 For example, the depth h1 of the groove 310 can be 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, 1 / 8, 1 / 9, 1 / 10 of the thickness h2 of the encapsulation layer 300. It should be understood that the depth h1 of the groove 310 can also be other values ​​less than or equal to 1 / 2 of the thickness h2 of the encapsulation layer 300, which will not be elaborated in this disclosure.

[0101] refer to Figure 3 For example, the depth h1 of the groove 310 can be no less than 20 micrometers, such as 20 micrometers, 21 micrometers, 22 micrometers, 23 micrometers, 24 micrometers, 25 micrometers, 26 micrometers, 27 micrometers, 28 micrometers, 29 micrometers, 30 micrometers, or greater than 30 micrometers. It should be understood that the depth h1 of the groove 310 can also be other values ​​no less than 20 micrometers, which will not be elaborated here.

[0102] refer to Figures 2 to 4AIn some examples, the distance L1 between the outer edge of the opening of the groove 310 and the outer edge of the encapsulation structure 301 in a direction parallel to the main surface of the substrate 10 is 10 micrometers to 900 micrometers. For example, this distance L1 can be the vertical distance between the outer edge of the opening of the groove 310 and the outer edge of the encapsulation structure 301. This reduces or even eliminates the possibility of damage to the encapsulation structure 301 caused by the grooving process. For example, the distance L1 can be 10 micrometers to 90 micrometers. For example, the distance L1 can be 20 micrometers to 80 micrometers. For example, the distance L1 can be 30 micrometers to 70 micrometers. For example, the distance L1 can be 40 micrometers to 60 micrometers. For example, the distance L1 can be approximately 50 micrometers. For example, the distance L1 can be 100 micrometers to 900 micrometers. For example, the distance L1 can be 200 micrometers to 800 micrometers. For example, the distance L1 can be 300 micrometers to 700 micrometers. For example, the distance L1 can be 400 micrometers to 600 micrometers. For example, the distance L1 can be approximately 500 micrometers. It should be understood that the spacing L1 can also be other values ​​ranging from 10 micrometers to 900 micrometers, which will not be elaborated in this disclosure.

[0103] refer to Figure 2 and Figure 3 In some examples, the spacing L2 between the outer edge of the opening of the groove 310 and the edge of the first semiconductor structure 101 in a direction parallel to the main surface of the substrate 10 is 10 micrometers to 900 micrometers. For example, the spacing L2 can be the vertical distance between the outer edge of the opening of the groove 310 and the edge of the first semiconductor structure 101. This reduces or even eliminates the possibility of damage to the first semiconductor structure 101 caused by the grooving process. For example, the spacing L2 can be 10 micrometers to 90 micrometers. For example, the spacing L2 can be 20 micrometers to 80 micrometers. For example, the spacing L2 can be 30 micrometers to 70 micrometers. For example, the spacing L2 can be 40 micrometers to 60 micrometers. For example, the spacing L2 can be approximately 50 micrometers. For example, the spacing L2 can be 100 micrometers to 900 micrometers. For example, the spacing L2 can be 200 micrometers to 800 micrometers. For example, the spacing L2 can be 300 micrometers to 700 micrometers. For example, the spacing L2 can be 400 micrometers to 600 micrometers. For example, the spacing L2 can be approximately 500 micrometers. It should be understood that the spacing L2 can also be other values ​​ranging from 10 micrometers to 900 micrometers, which will not be elaborated in this disclosure.

[0104] refer to Figure 2 and Figure 3 For example, the spacing L1 and the spacing L2 may be equal or unequal, and this disclosure does not impose any restrictions on this.

[0105] It should be understood that the outer edge of the opening of the aforementioned groove and the outer edge of the encapsulation structure are relative to the first semiconductor structure. Specifically, the outer edge of the encapsulation structure surrounding the first semiconductor structure refers to the edge of the encapsulation structure away from the first semiconductor structure, and the outer edge of the opening of the groove refers to the edge of the opening away from the first semiconductor structure.

[0106] refer to Figure 2 and Figure 4A In some examples, at least one second semiconductor structure 102 includes a plurality of second semiconductor structures 102. For example... Figure 4A As shown, the first semiconductor structure 101 includes a first side 1011 and a second side 1012 connected together. It should be understood that... Figure 4A The first side 1011 and the second side 1012 are shown schematically for ease of description only and are not limited to [the two sides]. Figure 4A These two sides are shown. It should be understood that the first side 1011 and the second side 1012 are connected to each other to form a corner of the first semiconductor structure 101.

[0107] refer to Figure 2 and Figure 4A A second semiconductor structure 102 is provided on one side of the first side 1011 (e.g., Figure 4A The diagram shows a second semiconductor structure 102 in the upper right corner, and another second semiconductor structure 102 is provided on one side of the second side 1012 (e.g., ...). Figure 4A The second semiconductor structure 102 is shown on the left side of the diagram. A groove 310 is located between at least one of the first side 1011 and the second side 1012 and the second semiconductor structure 102. For example, the groove 310 may be located between the first side 1011 and the second semiconductor structure 102. For example, the groove 310 may be located between the second side 1012 and the second semiconductor structure 102. For example, the groove 310 may be partially located between the first side 1011 and the second semiconductor structure 102, and another portion may be located between the second side 1012 and the second semiconductor structure 102.

[0108] In conjunction with the preceding text, in an encapsulation structure without grooves, stress concentration may occur in the portion of the encapsulation structure covering the corner formed by the connection of the first and second sides. (Reference) Figure 2 and Figure 4A By placing the groove 310 near the corner formed by the connection of the first side 1011 and the second side 1012, stress concentration can be relieved while unnecessary slotting of the encapsulation structure 301 is reduced, which helps to improve the encapsulation effect and prevent damage to the device assembly 100.

[0109] refer to Figure 2 , Figure 3 and Figure 4BIn some examples, in a direction parallel to the main surface of the substrate 10, the filler layer 200 includes a first extension 200a and a second extension 200b that are connected to and intersect each other. For example, Figure 4B The diagram schematically shows a first extension 200a extending along the Y direction and a second extension 200b extending along the X direction. However, this disclosure is not limited thereto, and in other areas of the package structure, such as areas other than P2, the first and second extensions may extend in other directions respectively.

[0110] refer to Figure 2 and Figure 4B In some examples, device assembly 100 includes a first device structure 100a and a second device structure 100b located on either side of the first extension 200a. The first device structure 100a includes adjacent first semiconductor structure 101 and second semiconductor structure 102, and the second extension 200b is located between adjacent first semiconductor structure 101 and second semiconductor structure 102. The second device structure 100b includes only the second semiconductor structure 102.

[0111] The first and second device structures described above can be understood as dividing the device assembly into two groups distributed on both sides of the first extension portion based on the positional relationship of the semiconductor structures within the device assembly relative to the first extension portion. Each group may contain only one semiconductor structure or multiple semiconductor structures. For example, Figure 4B The first device structure 100a shown includes two semiconductor structures, namely a first semiconductor structure 101 and a second semiconductor structure 102, while the second device structure 100b includes only one semiconductor structure, namely the second semiconductor structure 102. However, this disclosure is not limited thereto, and in other examples, there may be multiple semiconductor structures in each group, such as the second device structure may include two or more second semiconductor structures, which is not limited here.

[0112] refer to Figure 2 and Figure 4B In some examples, the groove 310 is located between the first extension 200a and the first semiconductor structure 101 and / or between the second extension 200b and the first semiconductor structure 101. It should be understood that when only the second semiconductor structure 102 is provided on one side of the first extension 200a of the filling layer 200, while adjacent first and second semiconductor structures 101 are provided on the other side, and the second extension 200b extends between the first and second semiconductor structures 101 and 102, the first extension 200a and the second extension 200b can be formed as follows: Figure 4BThe structure shown is a "T" shape. By designing the position of the groove 310, stress concentration can be alleviated while reducing unnecessary slotting of the encapsulation structure 301, thereby improving the encapsulation effect and preventing damage to the device assembly 100.

[0113] refer to Figure 2 and Figure 4B In some examples, the second extension 200b is located on one side of the first extension 200a, and the extension direction of the second extension 200b passes through the second semiconductor structure 102 of the second device structure 100b. For example, on a reference plane perpendicular to the X direction, the orthographic projections of the first semiconductor structure 101 of the first device structure 100a and the second semiconductor structure 102 of the first device structure 100a both overlap with the orthographic projection of the second semiconductor structure 102 of the same second device structure 100b. Figure 4B As shown, the overall structure of the second extension portion 200b is located between the first semiconductor structure 101 and the second semiconductor structure 102 in the first device structure 100a, thereby forming a "T"-shaped structure.

[0114] However, this disclosure is not limited thereto. When the second device structure includes two adjacent second semiconductor structures, the second extension may also extend to the other side of the first extension structure; that is, the second extension may connect to both sides of the first extension. For example, the second extension may include a portion located between adjacent first and second semiconductor structures, and a portion located between two adjacent second semiconductor structures. Thus, the first extension and the second extension may form a "+" shaped structure or a similar "+" shaped structure. A detailed description of this example will be given later. Figure 9 The relevant descriptions will be elaborated upon here, and will not be repeated here.

[0115] refer to Figure 2 and Figure 4A In some examples, the second portion 220 includes a first filling portion 201 and a second filling portion 202 located between and connected to the first semiconductor structure 101 and the second semiconductor structure 102. The first filling portion 201 extends along a first direction, and the second filling portion 202 extends along a second direction. The first direction and the second direction intersect each other and are both parallel to the main surface of the substrate 10.

[0116] For example, Figure 2 The schematic diagram shows the first direction as Figure 2 The X direction is shown, and the second direction is... Figure 2The Y direction is shown, and the X direction is perpendicular to the Y direction. However, this disclosure is not limited thereto. It should be understood that, depending on the arrangement or outline shape of the first semiconductor structure 101 and the second semiconductor structure 102, the first direction and the second direction can be other directions parallel to the main surface of the substrate 10, such as the first direction and the second direction intersecting but not perpendicular, and this disclosure does not limit them in this regard.

[0117] refer to Figure 2 and Figure 4A In some examples, the groove 310 is located between at least one of the first filling portion 201 and the second filling portion 202 and the first semiconductor structure 101 in a direction parallel to the main surface of the substrate 10. For example, the groove 310 may be located between the first filling portion 201 and the first semiconductor structure 101. For example, the groove 310 may be located between the second filling portion 202 and the first semiconductor structure 101. For example, the groove 310 may be partially located between the first filling portion 201 and the first semiconductor structure 101, and another portion may be located between the second filling portion 202 and the first semiconductor structure 101.

[0118] refer to Figure 2 and Figure 4A Based on the relative positional relationship between the first filling portion 201 and the second filling portion 202 and the first semiconductor structure 101 and the second semiconductor structure 102, it can be seen that by opening a groove 310 at a specific position of the encapsulation structure 301, stress concentration can be alleviated while reducing unnecessary slotting of the encapsulation structure 301, so as to improve the encapsulation effect and prevent damage to the device assembly 100.

[0119] Figure 2 and Figure 4A The illustration schematically shows that a first side 1011 of the first semiconductor structure 101 can extend along a first direction, and a second side 1012 of the first semiconductor structure 101 can extend along a second direction. However, this disclosure is not limited thereto.

[0120] refer to Figure 2 and Figure 4A In some examples, the groove 310 includes a first groove portion 311 extending in a first direction and a second groove portion 312 extending in a second direction. This allows for stress buffering in both directions (i.e., the first and second directions) to achieve better crack prevention. For example, the groove 310 can be generally L-shaped, which helps buffer stress at the corners of the encapsulation structure 301 and simplifies the manufacturing process.

[0121] It should be noted that "extending in a certain direction" as mentioned above refers to the overall tendency to extend in that direction. Taking the first groove portion 311 extending in the first direction as an example, Figure 2 and Figure 4A The illustration schematically shows the first groove portion 311 extending along the X direction with its center line being a straight line. However, this disclosure is not limited to this; for example, the center line of the first groove portion 311 may also be curved, such as the first groove portion 311 extending in an S-shape. It should be understood that this disclosure does not limit the specific shape of the structure, etc., as long as the overall trend can be presented.

[0122] refer to Figure 4A In some examples, the dimension L3 of the first groove 311 in the first direction is not less than 100 micrometers, such as greater than or equal to 100 micrometers. In some examples, the dimension L4 of the second groove 312 in the second direction is not less than 100 micrometers, such as greater than or equal to 100 micrometers. By designing the dimensions of the first groove 311 and the second groove 312, a better stress relief effect can be achieved, such that the filler layer 200 will basically not crack.

[0123] refer to Figure 4A For example, the dimension L3 of the first groove portion 311 in the first direction can be 100 micrometers, 150 micrometers, 200 micrometers, 250 micrometers, 300 micrometers, 350 micrometers, 400 micrometers, 450 micrometers, 500 micrometers, 550 micrometers, 600 micrometers, 650 micrometers, 700 micrometers, 750 micrometers, 800 micrometers, or greater than 800 micrometers. It should be understood that the dimension L3 of the first groove portion 311 in the first direction can also be other values ​​not less than 100 micrometers, which will not be elaborated upon here. For example, the dimension L4 of the second groove portion 312 in the second direction can be 100 micrometers, 150 micrometers, 200 micrometers, 250 micrometers, 300 micrometers, 350 micrometers, 400 micrometers, 450 micrometers, 500 micrometers, 550 micrometers, 600 micrometers, 650 micrometers, 700 micrometers, 750 micrometers, 800 micrometers, or greater than 800 micrometers. It should be understood that the dimension L4 of the second groove portion 312 in the second direction can also be other values ​​not less than 100 micrometers, which will not be elaborated in this disclosure.

[0124] refer to Figure 2 and Figure 4A For example, the dimension L3 of the first groove portion 311 in the first direction and the dimension L4 of the second groove portion 312 in the second direction may be the same or different, and this disclosure does not limit this.

[0125] refer to Figure 4AFor example, the width W1 of the first groove portion 311 can be not less than 20 micrometers, such as 20 micrometers, 25 micrometers, 30 micrometers, etc. For example, the width of the first groove portion 311 can be the distance between the two sidewalls of the first groove portion 311 in a direction perpendicular to its extension direction, such as the width of the first groove portion 311 being its dimension in the Y direction. It should be understood that the width W1 of the first groove portion 311 can also be other values ​​not less than 20 micrometers, which will not be elaborated upon here.

[0126] refer to Figure 4A For example, the width W2 of the second groove portion 312 can be not less than 20 micrometers, such as 20 micrometers, 25 micrometers, 30 micrometers, etc. For example, the width of the second groove portion 312 can be the distance between the two sidewalls of the second groove portion 312 in a direction perpendicular to its extension direction, such as the width of the second groove portion 312 being its dimension in the Y direction. It should be understood that the width W2 of the second groove portion 312 can also be other values ​​not less than 20 micrometers, which will not be elaborated upon here.

[0127] refer to Figure 4A Based on the aforementioned descriptions of spacing L1 and spacing L2, the parameter combinations of spacing L1, spacing L2, width W1 of the first groove portion 311, and width W2 of the second groove portion 312 can be jointly optimized as needed, and this disclosure does not impose any limitations on this.

[0128] refer to Figure 2 and Figure 4A In some examples, the first groove portion 311 and the second groove portion 312 are connected to each other to form a continuous groove 310 to improve the stress relief effect.

[0129] However, this disclosure is not limited to the above examples regarding the shape of the grooves. In other examples, where the groove includes a continuous structure, the groove may also extend along a direction parallel to the main surface of the substrate and intersecting the X and Y directions, respectively. For example, the extension direction of the groove may intersect the extension direction of the edge of the encapsulation structure and / or the first semiconductor structure. In still other examples, the groove may be a discontinuous structure, such as a groove comprising a plurality of sub-grooves spaced apart in a direction parallel to the main surface of the substrate. It should be understood that this disclosure does not limit the shape, structure, number of the grooves, or the shape, structure, number of the sub-grooves, as long as the grooves can be used to achieve stress relief at the corners of the encapsulation structure.

[0130] refer to Figure 2 and Figure 4AIn some examples, on the main surface of the substrate 10, the orthographic projection of the groove 310 surrounds a portion of the orthographic projection of the first semiconductor structure 101 circumferentially, thereby improving the stress buffering effect while ensuring the encapsulation reliability of the encapsulation structure 301. For example, the groove 310 may surround a portion of the first semiconductor structure 101 circumferentially, such as surrounding one corner of the first semiconductor structure 101, surrounding two or more corners of the first semiconductor structure 101, or surrounding 1 / 4, 1 / 2, or 3 / 4 of the first semiconductor structure 101, etc., and this disclosure does not limit this.

[0131] refer to Figures 2 to 4A In some examples, at least one second semiconductor structure 102 includes a plurality of second semiconductor structures 102. In the second portion 220 of the fill layer 200, the portion located between adjacent second semiconductor structures 102 is in contact with the adjacent second semiconductor structure 102, thereby reducing the likelihood of stress concentration at that location. For example, Figure 4A The portion 220a of the second part 220 located between adjacent second semiconductor structures 102 is outlined in the dashed box. For example, in the package structure, the encapsulation layer 300 may not extend between adjacent second semiconductor structures 102, or may extend only a small portion between adjacent second semiconductor structures 102. For example, in conjunction with the foregoing example, the encapsulation portion 302 in the encapsulation layer 300 may be filled between adjacent second semiconductor structures 102 as needed. For example, the contact area between the sidewalls of adjacent second semiconductor structures 102 facing each other and the encapsulation layer 300 may be very small or even non-contact, thus the stress caused by the shrinkage of the encapsulation layer 300 material is relatively small or even negligible.

[0132] refer to Figure 4A In some examples, the spacing between the edges of adjacent first semiconductor structures 101 and second semiconductor structures 102 facing each other is a first dimension D1, and the width of the portion of the filling layer 200 located between adjacent second semiconductor structures 102 is a second dimension D2. For example, the spacing between the edges of adjacent first semiconductor structures 101 and second semiconductor structures 102 facing each other can be the vertical spacing between the edges of adjacent first semiconductor structures 101 and second semiconductor structures 102 facing each other. The first dimension D1 is greater than the second dimension D2. For example, the spacing between the first semiconductor structure 101 and the second semiconductor structure 102 is larger, while the spacing between adjacent second semiconductor structures 102 is smaller.

[0133] refer to Figure 4AIt is understood that the portion of the filling layer 200 located between adjacent second semiconductor structures 102 (such as the second portion 220) contacts the two second semiconductor structures 102 respectively, so that the width of the portion can be the vertical distance between the edges of the two adjacent second semiconductor structures 102 facing each other.

[0134] It should be understood that the aforementioned first dimension D1 corresponds to the width of the structure located between adjacent first semiconductor structures 101 and second semiconductor structures 102. In conjunction with the foregoing description of the encapsulation structure material and the filling layer material, when the encapsulation structure material and the filling layer material are approximately the same or identical, the difference in their coefficients of thermal expansion may be relatively small. However, due to the difference between the first dimension D1 and the second dimension D2, i.e., the difference between the width of the structure located between adjacent first semiconductor structures 101 and second semiconductor structures 102 and the width of the structure located between adjacent second semiconductor structures 102, uneven stress may occur. Therefore, by setting the groove 310 as... Figure 4A The location shown is beneficial in mitigating stress concentration problems caused by the aforementioned factors.

[0135] refer to Figure 4A In some examples, the first size D1 can be from 200 micrometers to 1000 micrometers. For example, the first size D1 can be from 200 micrometers to 300 micrometers. For example, the first size D1 can be from 210 micrometers to 290 micrometers. For example, the first size D1 can be from 220 micrometers to 280 micrometers. For example, the first size D1 can be from 230 micrometers to 270 micrometers. For example, the first size D1 can be from 240 micrometers to 260 micrometers. For example, the first size D1 can be around 250 micrometers, etc. For example, the first size D1 can be from 300 micrometers to 1000 micrometers. For example, the first size D1 can be from 400 micrometers to 900 micrometers. For example, the first size D1 can be from 500 micrometers to 800 micrometers. For example, the first size D1 can be from 600 micrometers to 700 micrometers. For example, the first size D1 can be around 750 micrometers. Of course, the first size D1 can also be other values ​​from 200 micrometers to 1000 micrometers, and this disclosure is not limited to the above values, which will not be elaborated here.

[0136] refer to Figure 4AIn some examples, the second size D2 can be from 40 micrometers to 150 micrometers. For example, the second size D2 can be from 50 micrometers to 140 micrometers. For example, the second size D2 can be from 60 micrometers to 130 micrometers. For example, the second size D2 can be from 70 micrometers to 120 micrometers. For example, the second size D2 can be from 80 micrometers to 110 micrometers. For example, the second size D2 can be from 90 micrometers to 100 micrometers. For example, the second size D2 can be around 95 micrometers. Of course, the second size D2 can also be other values ​​within the above range, and this disclosure is not limited to the above values, which will not be elaborated here.

[0137] Figure 5 This is a schematic cross-sectional view of the packaging structure provided as an example in at least one embodiment of the present disclosure.

[0138] Figure 5 The packaging structure shown is similar to Figure 3 The differences in the packaging structures shown include Figure 5 An additional filling layer 500 is provided in the groove 310 of the encapsulation structure shown.

[0139] refer to Figure 5 The encapsulation structure also includes an additional filler layer 500. The additional filler layer 500 fills the groove 310 of the encapsulation layer 300, and its coefficient of thermal expansion is less than that of the encapsulation layer 300. By providing an additional filler layer 500 with a smaller coefficient of thermal expansion in the encapsulation layer 300, the structural continuity of the encapsulation layer 300 can be broken. Furthermore, the smaller coefficient of thermal expansion of the additional filler layer 500 helps alleviate stress concentration problems.

[0140] refer to Figure 5 For example, the surface of the additional filler layer 500 away from the substrate 10 may be substantially flush with the surface of the encapsulation layer 300 away from the substrate 10, such that the surface formed by the two layers is substantially parallel to the main surface of the substrate 10. In this case, the additional filler layer 500 can be considered to fill the groove 310. However, this disclosure is not limited thereto. For example, the additional filler layer 500 may also fill a portion of the groove 310, such that the surface of the additional filler layer 500 away from the substrate 10 may be closer to the main surface of the substrate 10 than the surface of the encapsulation layer 300 away from the substrate 10. It should be understood that this disclosure does not limit the material, structure, or placement of the additional filler layer 500, as long as the structural continuity of the encapsulation layer 300 can be disrupted by the additional filler layer 500.

[0141] Figures 6 to 9 This is a schematic plan view of the packaging structure provided for different examples in at least one embodiment of the present disclosure.

[0142] Figures 6 to 9 and Figure 2The differences include, Figures 6 to 9 The illustrations schematically depict different arrangements of the first semiconductor structure 101 and the second semiconductor structure 102 in device assembly 100. Correspondingly, the location of the recess 310 also differs from the foregoing example. In addition to the differences mentioned above, Figures 6 to 9 The structures shown can all be referred to in the relevant descriptions in the preceding examples, and will not be repeated hereafter. Below, in conjunction with... Figure 2 as well as Figures 6 to 9 Please provide an explanation.

[0143] refer to Figure 2 and Figure 6 ,For example, Figure 2 and Figure 6 The schematic diagram illustrates a package structure comprising two first semiconductor structures 101 and two second semiconductor structures 102. Both first semiconductor structures 101 can be first chips, such as HBMs, and each first semiconductor structure 101 is surrounded by an encapsulation structure 301. Each of the two second semiconductor structures 102 includes a second chip 1021 and a structure 1022. The second chip 1021 is, for example, a SoC, and the structure 1022 can be a capacitor structure or a dummy structure, etc.

[0144] like Figure 2 and Figure 6 As shown, the two first semiconductor structures 101 and 1022 are arranged in the Y direction and are located on the same side of the second chip 1021. Figure 2 and Figure 6 The difference is that, Figure 2 The intermediate structure 1022 is located between the two first semiconductor structures 101, while Figure 6 The two first semiconductor structures 101 are located on the same side of structure 1022.

[0145] refer to Figure 2 In a structure 1022, first semiconductor structures 101 are arranged on both sides in the Y direction, and a second chip 1021 is arranged on one side of the structure 1022 in the X direction. At the two corners of the structure 1022 closest to the second chip 1021 in the Y direction—namely, the upper left and lower left corners as shown in the figure—the filling layer 200 covering these two corners is susceptible to cracking due to stress concentration. Therefore, grooves 310 are provided on the encapsulation structures 301 surrounding the two first semiconductor structures 101. By providing grooves 310 in each encapsulation structure 301 located between the first semiconductor structure 101 and the second semiconductor structure 102, the stress generated by the shrinkage of the encapsulation structure 301 can be buffered, thereby reducing or even eliminating the risk of cracking of the filling layer 200.

[0146] refer to Figure 6 ,exist Figure 6In the arrangement shown, the first semiconductor structure 101 is arranged on one side of structure 1022 in the Y direction, which means that the filling layer 200 covering structure 1022 outside the upper left corner of the figure may crack due to stress concentration. Therefore, the groove 310 can be formed only on the encapsulation structure 301 of the two first semiconductor structures 101 closest to structure 1022.

[0147] refer to Figure 7 , Figure 7 The diagram schematically illustrates four first semiconductor structures 101 and three second semiconductor structures 102. Each of the four first semiconductor structures 101 can be a first chip, such as an HBM (Hardware Body Module). Each first semiconductor structure 101 is surrounded by an encapsulation structure 301. The three second semiconductor structures 102 include one second chip 1021 and two structures 1022. The second chip 1021 is, for example, a System-on-a-Chip (SoC), and the structures 1022 can be capacitor structures or dummy structures, etc.

[0148] like Figure 7 As shown, the second chip 1021 has two first semiconductor structures 101 and one structure 1022 on each side in the X direction, and the structure 1022 is located between the two first semiconductor structures 101 in the Y direction. The groove 310 on the encapsulation structure 301 outside the two first semiconductor structures 101 on the right side of the second chip 1021 is located at a position similar to... Figure 2 Similarly, in the two first semiconductor structures 101 located on the left side of the second chip 1021, the encapsulation structure 301 outside the upper first semiconductor structure 101 can have a groove 310 in the lower right corner, while the encapsulation structure 301 outside the lower first semiconductor structure 101 can have a groove 310 in the upper right corner.

[0149] refer to Figure 8 , Figure 8 The diagram schematically illustrates eight first semiconductor structures 101 and six second semiconductor structures 102. Each of the eight first semiconductor structures 101 can be a first chip, such as an HBM (Hardware Body Module). Each first semiconductor structure 101 is surrounded by an encapsulation structure 301. The six second semiconductor structures 102 include two second chips 1021 and four structures 1022. The second chips 1021 are, for example, a System-on-a-Chip (SoC), and the structures 1022 can be capacitor structures or dummy structures, etc.

[0150] exist Figure 8 The arrangement shown can be considered as including two groups of devices in the Y direction, and the arrangement of each group of devices is similar to... Figure 7 The arrangement shown is the same. Therefore, the location of the groove 310 can be referenced as described above. Figure 7 The relevant descriptions will not be repeated here.

[0151] refer to Figure 8 Taking two adjacent first semiconductor structures 101 located on the left side of the second chip 1021 in the figure as an example (i.e., the two first semiconductor structures 101 in the middle on the left side of the figure, with no structure 1022 between them), and in conjunction with the aforementioned description of the location of the groove 310, the encapsulation structure 301 is further explained as follows. In these two first semiconductor structures 101, the lower right corner of the encapsulation structure 301 covering the upper first semiconductor structure 101 in the figure may not have a groove 310, while the upper right corner of the encapsulation structure 301 covering the lower first semiconductor structure 101 in the figure may not have a groove 310.

[0152] refer to Figure 9 , Figure 9 and Figure 8 The differences include the different ways in which the grooves 310 on structure 1022 and encapsulation structure 301 are set. Figure 9 Six structures 1022 are schematically shown, each structure 1022 located between two adjacent first semiconductor structures 101 in the Y direction. Due to the change in the arrangement of the device assembly 100, the position of the recess 310 also changes accordingly. For example... Figure 9 As shown, a first semiconductor structure 101 located between two adjacent structures 1022 in the Y direction has two grooves 310 formed on an encapsulation structure 301 covering the first semiconductor structure 101.

[0153] refer to Figure 9 In conjunction with the aforementioned Figure 4B Related descriptions, Figure 9 The diagram also schematically illustrates a configuration where second extensions 200b are present on both sides of the first extension 200a. Figure 9 In the arrangement of the device assembly 100 shown, there are two second chips 1021 on the left side of the first extension portion 200a extending in the Y direction, and the second extension portion 200b extends between the two second chips 1021. Meanwhile, in the device on the right side of the first extension portion 200a, a structure 1022 directly opposite the second extension portion 200b in the X direction is located between two first semiconductor structures 101, thus the second extension portion 200b also extends between adjacent first semiconductor structures 101 and 1022.

[0154] It should be understood that, due to Figure 9At least one structure 1022 shown is directly opposite the second extension portion 200b, so that the second extension portions 200b on both sides of the first extension portion 200a in the X direction are misaligned, forming a structure similar to a "+" shape. However, this disclosure is not limited thereto. For example, the second extension portions 200b on both sides of the first extension portion 200a in the X direction may not be misaligned, that is, the second extension portions 200b on both sides may overlap in the X direction, thereby forming a "+" shape structure. In this case, Figure 9 The position of structure 1022, which is directly opposite the second extension 200b, will change, for example, it can be along... Figure 9 The Y-direction is shifted upward or downward as shown, so that one edge of the structure 1022 in the Y-direction is aligned with one edge of the second chip 1021 in the Y-direction.

[0155] It should be understood that Figures 2 to 9 This illustration only schematically shows the arrangement of the first semiconductor structure 101 and the second semiconductor structure 102 in some packaging structures, as well as the corresponding positions of the recesses 310, but this disclosure is not limited thereto. In conjunction with the description of the recesses 310 in the foregoing examples, in other packaging structures, the number, position, shape, etc. of the recesses 310 can be adjusted accordingly based on the actual arrangement.

[0156] For example, Figures 2 to 9 The packaging structure shown may be referred to as a CoW package, and the CoW package may be further mounted onto a packaging substrate. For example, any of the above packaging structures may also include a packaging substrate, which may be disposed on the side of the substrate 10 away from the device assembly 100 and electrically connected to the substrate 10 via a plurality of conductive terminals 400.

[0157] Figure 10 This is a schematic diagram of an electronic device provided as an example in at least one embodiment of the present disclosure.

[0158] At least one example of this disclosure also provides an electronic device 900. This electronic device includes the packaging structure 950 from any of the above examples. Since the electronic device 900 according to embodiments of this disclosure includes the packaging structure 950 from the above examples, it also has corresponding beneficial technical effects, which will not be elaborated upon here.

[0159] For example, the electronic device may be a Peripheral Component Interconnect Express (PCIe), an Open Compute Project Accelerator Module (OCP Accelerator Module, OAM) board, or a server, etc., and the embodiments disclosed herein are not limited thereto.

[0160] In at least one example of the packaging structure and electronic device provided in this disclosure, by providing grooves at specific locations in the encapsulation layer of the packaging structure, the structural continuity of the encapsulation layer can be broken at locations prone to stress concentration, thereby alleviating stress and reducing or even eliminating the possibility of cracking in the filler layer. As a result, the yield of the packaging structure is improved, and it can maintain good packaging performance under more extreme operating conditions (such as high temperature, high humidity, high and low temperature cycling), thus improving the reliability of the packaging structure.

[0161] The following points need to be explained:

[0162] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0163] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0164] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging structure, characterized in that, include: A substrate having a first side and a second side opposite to each other; The device assembly is located on the first side of the substrate and is electrically connected to the substrate, and includes a first semiconductor structure and at least one second semiconductor structure that are adjacent to each other and spaced apart. An encapsulation layer is disposed on the first side of the substrate and at least partially disposed on the sidewall of the first semiconductor structure; The filling layer includes a first portion located between the device assembly and the substrate, and a second portion located between the sidewall of the at least one second semiconductor structure and the encapsulation layer; Wherein, in a direction parallel to the main surface of the substrate, a portion of the encapsulation layer is located between the second portion of the filling layer and the first semiconductor structure; The encapsulation layer has a groove located between the first semiconductor structure and the at least one second semiconductor structure, the groove extending from the surface of the encapsulation layer away from the substrate into the encapsulation layer and spaced apart from the fill layer; The coefficient of thermal expansion of the filling layer is greater than that of the first semiconductor structure and the at least one second semiconductor structure, and less than that of the encapsulation layer.

2. The packaging structure according to claim 1, characterized in that, The at least one second semiconductor structure includes a plurality of second semiconductor structures; The first semiconductor structure includes a first side and a second side connected together, a second semiconductor structure is disposed on one side of the first side, and another second semiconductor structure is disposed on one side of the second side; The groove is located between at least one of the first side and the second side and the second semiconductor structure.

3. The packaging structure according to claim 1, characterized in that, In a direction parallel to the main surface of the substrate, the filler layer includes a first extension portion and a second extension portion that are connected to and intersect each other; The device assembly includes a first device structure and a second device structure located on both sides of the first extension portion; the first device structure includes an adjacent first semiconductor structure and a second semiconductor structure, and the second extension portion is located between the adjacent first semiconductor structure and the second semiconductor structure; The second device structure includes only the second semiconductor structure; The packaging structure is configured to satisfy at least one of the following conditions: The groove is located between the first extension portion and the first semiconductor structure; The groove is located between the second extension and the first semiconductor structure.

4. The packaging structure according to claim 3, characterized in that, The second extension is located on one side of the first extension, and the extension direction of the second extension passes through the second semiconductor structure in the second device structure.

5. The packaging structure according to claim 1, characterized in that, The second portion of the filling layer includes a first filling portion and a second filling portion located between the first semiconductor structure and the at least one second semiconductor structure and connected to each other, wherein the first filling portion extends along a first direction and the second filling portion extends along a second direction. In a direction parallel to the main surface of the substrate, the groove is located between at least one of the first filling portion and the second filling portion and the first semiconductor structure; The first direction and the second direction intersect each other and are both parallel to the main surface of the substrate.

6. The packaging structure according to claim 5, characterized in that, The groove includes a first groove portion extending along the first direction and a second groove portion extending along the second direction.

7. The packaging structure according to claim 6, characterized in that, The first groove and the second groove are connected to each other.

8. The packaging structure according to claim 6, characterized in that, The first groove portion has a dimension of not less than 100 micrometers in the first direction, and the second groove portion has a dimension of not less than 100 micrometers in the second direction.

9. The packaging structure according to claim 1, characterized in that, The at least one second semiconductor structure includes a plurality of second semiconductor structures, and in the second portion of the filling layer, the portion located between adjacent second semiconductor structures is in contact with the adjacent second semiconductor structures respectively.

10. The packaging structure according to claim 9, characterized in that, The spacing between the edges of adjacent first and second semiconductor structures facing each other is a first dimension, and the width of the portion of the filling layer located between adjacent second semiconductor structures is a second dimension; The first dimension is larger than the second dimension.

11. The packaging structure according to claim 10, characterized in that, The first size is 200 micrometers to 1000 micrometers, and the second size is 40 micrometers to 150 micrometers.

12. The packaging structure according to any one of claims 1-11, characterized in that, The encapsulation layer includes an encapsulation structure surrounding and encapsulating the first semiconductor structure, wherein the encapsulation structure and the first semiconductor structure are integrally formed. The groove is formed on the encapsulation structure.

13. The packaging structure according to claim 12, characterized in that, The packaging structure has a device component area, which includes the first semiconductor structure, the encapsulation structure surrounding and encapsulating the first semiconductor structure, and the at least one second semiconductor structure. The encapsulation layer further includes an encapsulation portion, at least a portion of which surrounds the device assembly region in the circumferential direction.

14. The packaging structure according to claim 12, characterized in that, In a direction parallel to the main surface of the substrate, the distance between the outer edge of the opening of the groove and the outer edge of the encapsulation structure is 10 micrometers to 900 micrometers.

15. The packaging structure according to claim 12, characterized in that, In a direction parallel to the main surface of the substrate, the distance between the outer edge of the opening of the groove and the edge of the first semiconductor structure is 10 micrometers to 900 micrometers.

16. The packaging structure according to any one of claims 1-11, characterized in that, On the main surface of the substrate, the orthographic projection of the groove surrounds a portion of the orthographic projection of the first semiconductor structure circumferentially.

17. The packaging structure according to any one of claims 1-11, characterized in that, The groove is a discontinuous structure and includes a plurality of sub-grooves spaced apart along a direction parallel to the main surface of the substrate.

18. The packaging structure according to any one of claims 1-11, characterized in that, In a direction perpendicular to the main surface of the substrate, the depth of the groove is less than or equal to 1 / 2 of the thickness of the encapsulation layer.

19. The packaging structure according to any one of claims 1-11, characterized in that, The first semiconductor structure includes a first chip, and the at least one second semiconductor structure includes at least one of a second chip, a capacitor structure, and a dummy structure.

20. The packaging structure according to claim 19, characterized in that, The first chip is a memory chip, and the second chip is a logic chip.

21. The packaging structure according to any one of claims 1-11, characterized in that, Also includes: An additional filler layer is provided to fill the groove in the encapsulation layer, and the coefficient of thermal expansion of the additional filler layer is less than that of the encapsulation layer.

22. An electronic device, characterized in that, Includes the packaging structure according to any one of claims 1-21.

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