Robot multi-axis motion task time consistency deterministic scheduling method and device and storage medium

Abstract

The application relates to the field of robot motion control, and provides a robot multi-axis motion task time consistency deterministic scheduling method, device and storage medium. The method comprises the following steps: acquiring a robot motion graph containing a plurality of semantic motion units and semantic relationships therebetween, and calculating time windows of the semantic motion units; quantizing the time windows of the semantic motion units into a timing execution time slot sequence sorted according to trigger time, and recording at least a semantic motion unit set to be triggered at an execution time section and synchronization axis group information; processing control instructions through a double-layer period buffer mechanism; for a timing execution time slot containing a synchronization semantic relationship, sending a synchronization pre-trigger instruction to all device adapters in the synchronization axis group before a target trigger time; receiving feedback information returned by the device adapters and containing a control instruction application time stamp, checking an execution result according to the feedback information, and performing abnormal processing on subsequent timing execution time slots according to the checking result.

Description

Technical Field

[0001] This application relates to the field of robot motion control, and in particular to a deterministic scheduling method, apparatus and storage medium for time consistency of multi-axis motion tasks of robots. Background Technology

[0002] With the rapid development of industrial automation and intelligent robotics, robot tasks are evolving from single, fixed actions to complex, flexible multi-axis collaborative operations. In such tasks, such as collaborative assembly with dual robotic arms, synchronized operation of a mobile chassis and robotic arms, or complex trajectory movements formed by interpolation of multiple servo axes, not only is it required that each axis accurately complete its own movement, but more importantly, that the actions between multiple axes maintain a high degree of consistency and determinism in the time dimension. This means that a motion plan generated by a higher-level task planning system, containing specific temporal logic (e.g., sequence, synchronization points, waiting conditions, etc.), must be accurately and predictably reproduced during the underlying physical execution. Any drift between the planned time and the actual execution time, or any phase difference between multi-axis movements, can lead to task failure, product damage, or even safety accidents.

[0003] Currently, common technical solutions for robot motion task scheduling include message communication and callback mechanisms based on robot operating systems (e.g., ROS / ROS2), scan cycle models of programmable logic controllers (PLCs), and task scheduling based on real-time operating systems (RTOS). ROS / ROS2 systems offer a robust software ecosystem and modular communication capabilities, but their task triggering time is affected by operating system thread scheduling, message queue latency, and network jitter, making it difficult to guarantee that instructions take effect at precise physical moments. PLC systems employ a periodic input-calculation-output scan pattern, exhibiting a certain degree of periodicity. However, for complex multi-axis tasks with rich time constraints (e.g., relative start time, synchronization barriers), a large amount of auxiliary logic typically requires hard coding, making it difficult to form a unified and expressible time-based execution plan. Real-time operating systems can provide priorities and timers, but their scheduling objects are general tasks or threads, rather than scheduling units directly bound to motion semantics, time windows, and synchronization groups. Developers still need to maintain complete time planning, instruction buffering, and synchronization verification logic at the application layer.

[0004] In summary, the existing technology has at least the following drawbacks: 1) The time specifications specified in the upper-level task planning are prone to drift with the actual instruction activation time of the lower-level executor, lacking a unified and mappable execution time profile; 2) The multi-axis synchronization requirements declared in the task semantic layer are difficult to guarantee that the instructions are applied in the same physical cycle during the process of issuing instructions to different physical device adapters, buses and drivers, resulting in synchronization failure; 3) The cycle of the upper-level scheduling loop is directly coupled with the cycle of the lower-level servo control, and the instantaneous delay or fluctuation of the upper-level scheduling will be directly transmitted to the lower level, destroying the uniformity and determinism of the instruction application time. Summary of the Invention

[0005] This application provides a time-consistent deterministic scheduling method, apparatus, and storage medium for robot multi-axis motion tasks. By using timed execution time slot planning, double-layer periodic buffering, and synchronous pre-triggering, the time consistency determinism of robot multi-axis motion between planning, scheduling, and physical execution is achieved.

[0006] On one hand, this application provides a time-consistent deterministic scheduling method for multi-axis motion tasks of robots, the method comprising: Step S1: Obtain a robot motion graph containing multiple semantic motion units and their semantic relationships, and calculate the time window of each semantic motion unit based on the time specifications of the semantic motion units and the constraints of the semantic relationships; Step S2: Quantize each time window into a timed execution slot sequence ordered by the trigger time. Each timed execution slot in the timed execution slot sequence represents an execution time section at a predetermined trigger time and records at least the semantic motion unit set and synchronization axis group information to be triggered in the execution time section. Step S3: Through a two-layer cycle buffer mechanism, in the upper-layer scheduling cycle, the control instruction corresponding to the target time slot is pre-written into the instruction buffer of the corresponding device adapter at the pre-write time of the target time slot. In the lower-layer execution cycle, the device adapter reads and applies the control instruction from the instruction buffer. Step S4: For time slots containing synchronous semantic relationships, before the target trigger time, send a synchronous pre-trigger command to all device adapters in the synchronous axis group to trigger each device adapter in the group to apply its pre-stored corresponding control command in the same target execution cycle. Step S5: Receive feedback information from each device adapter containing the application timestamp of the control command, verify the execution result based on the feedback information, and perform anomaly handling on subsequent time slots based on the verification result.

[0007] On the other hand, this application provides a deterministic scheduling device for time consistency of multi-axis motion tasks of robots, the device comprising: The acquisition module is used to acquire a robot motion graph containing multiple semantic motion units and their semantic relationships, and to calculate the time window of each semantic motion unit based on the time specifications of the semantic motion units and the constraints of the semantic relationships. The quantization module is used to quantize each of the time windows into a sequence of timed execution slots ordered by the trigger time. Each timed execution slot in the sequence represents an execution time section at a predetermined trigger time and records at least the semantic motion unit set and synchronization axis group information to be triggered in the execution time section. The instruction processing module is used to pre-write the control instruction corresponding to the target time slot into the instruction buffer of the corresponding device adapter during the pre-writing time of the target time slot in the upper-level scheduling cycle through a two-layer cycle buffer mechanism. In the lower-level execution cycle, the device adapter reads and applies the control instruction from the instruction buffer. The trigger module is used to send a synchronization pre-trigger command to all device adapters in the synchronization axis group before the target trigger time for timed execution slots containing synchronization semantic relationships, so as to trigger each device adapter in the group to apply its pre-stored corresponding control command in the same target execution cycle. The verification module is used to receive feedback information returned by each device adapter, which includes the application timestamp of the control command, verify the execution result according to the feedback information, and perform anomaly handling on subsequent time slots based on the verification result.

[0008] Thirdly, this application provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the technical solution of the above-described deterministic scheduling method for time consistency of multi-axis motion tasks of robots.

[0009] Fourthly, this application provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described deterministic scheduling method for time consistency of multi-axis motion tasks in robots.

[0010] Fifthly, this application provides a device adapter for robot motion control, comprising: The instruction buffer is used to receive and cache control instructions from the upper-level scheduling engine, the control instructions carrying a target execution cycle identifier; The synchronization pre-trigger receiving module is used to receive the synchronization pre-trigger instruction packet from the upper-layer scheduling engine. The synchronization pre-trigger instruction packet includes a synchronization group identifier, a target trigger timestamp, and a target execution cycle. The preloading module, in response to the synchronous pre-trigger instruction package, preloads the control instructions corresponding to the target execution cycle in the instruction buffer into the local register to be activated; The application execution module is used to read control instructions from the register to be activated and apply them to the connected physical actuator when the target execution cycle arrives; The timestamp recording module is used to record the actual application timestamp of the control command and return feedback information containing the actual application timestamp to the upper-layer scheduling engine.

[0011] As can be seen from the technical solution provided in this application, on the one hand, by quantifying the time window of the motion graph into a sequence of time slots ordered by the trigger time, and recording complete execution time profile information for each time slot, a clear mapping relationship is established between the upper-level planning time, the scheduling trigger time, and the lower-level target execution cycle. This transforms the originally abstract time planning result into a series of specific time-based scheduling units that can be directly processed by the scheduling engine, thus laying a structural foundation for the precise control of the effective time of instructions and helping to reduce the systematic drift between the planned time and the actual execution time. On the other hand, by adopting a two-layer cycle buffer mechanism, the upper-level scheduling cycle driven by the scheduling tick is decoupled from the lower-level execution cycle driven by the fixed control cycle. The pre-written instruction buffer is used as an intermediate bridge, allowing the upper-level scheduler to pre-set instructions for multiple future execution cycles within one scheduling cycle, while the lower-level device adapter consumes instructions according to its own stable high-frequency cycle. In this way, the instantaneous calculation delay or jitter that may exist in the upper-level scheduling cycle is absorbed by the buffer and no longer directly affects the cycle uniformity and time determinism of the lower-level instruction application, thereby significantly improving the overall efficiency. The system achieves several key improvements. First, it ensures the stability and predictability of the execution process. Second, by introducing synchronous pre-trigger instructions for timed execution slots containing synchronous semantic relationships, and triggering the application of pre-stored instructions by the device adapters within the same target execution cycle, it realizes closed-loop control of multi-axis synchronization from semantic declaration to physical execution. This not only sends a synchronization signal to each execution axis indicating "when it will take effect," but more importantly, it forces alignment of the instruction application points of each axis through the unified time reference of "the same target execution cycle," thereby effectively ensuring the consistency of the starting phase of multi-axis motion at the physical layer and solving the synchronization error problem caused by differences in device response or communication delays. Third, by receiving and verifying the execution results and handling anomalies based on feedback information such as the application timestamps of the control instructions returned by each device adapter, a closed loop from planning to scheduling to execution feedback is formed. This allows the system to proactively perceive the deviation between actual execution and the plan (e.g., synchronization error), and dynamically adjust or process subsequent plans based on the verification results. This enhances the system's fault tolerance and robustness in the face of non-ideal execution environments, achieving proactive maintenance of time consistency rather than passive dependence. In summary, the technical solution of this application achieves temporal consistency determinism between planning, scheduling and physical execution of multi-axis robot motion through timed execution slot planning, double-layer periodic buffering and synchronous pre-triggering. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of the time-consistent deterministic scheduling method for robot multi-axis motion tasks provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the robot multi-axis motion task time consistency deterministic scheduling device provided in the embodiments of this application; Figure 3 This is a schematic diagram of the device provided in the embodiments of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] In this specification, adjectives such as "first" and "second" are used only to distinguish one element or action from another, without necessarily requiring or implying any actual such relationship or order. Where circumstances permit, reference to an element or component or step (etc.) should not be construed as being limited to only one of the elements, components, or steps, but may be one or more of the elements, components, or steps, etc.

[0016] For ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale.

[0017] Currently, common technical solutions for robot motion task scheduling include message communication and callback mechanisms based on robot operating systems (e.g., ROS / ROS2), scan cycle models of programmable logic controllers (PLCs), and task scheduling based on real-time operating systems (RTOS). ROS / ROS2 systems offer a robust software ecosystem and modular communication capabilities, but their task triggering time is affected by operating system thread scheduling, message queue latency, and network jitter, making it difficult to guarantee that instructions take effect at precise physical moments. PLC systems employ a periodic input-calculation-output scan pattern, exhibiting a certain degree of periodicity. However, for complex multi-axis tasks with rich time constraints (e.g., relative start time, synchronization barriers), a large amount of auxiliary logic typically requires hard coding, making it difficult to form a unified and expressible time-based execution plan. Real-time operating systems can provide priorities and timers, but their scheduling objects are general tasks or threads, rather than scheduling units directly bound to motion semantics, time windows, and synchronization groups. Developers still need to maintain complete time planning, instruction buffering, and synchronization verification logic at the application layer. In summary, the existing technology has at least the following drawbacks: 1) The time specifications specified in the upper-level task planning are prone to drift with the actual instruction activation time of the lower-level executor, lacking a unified and mappable execution time profile; 2) The multi-axis synchronization requirements declared in the task semantic layer are difficult to guarantee that the instructions are applied in the same physical cycle during the process of issuing instructions to different physical device adapters, buses and drivers, resulting in synchronization failure; 3) The cycle of the upper-level scheduling loop is directly coupled with the cycle of the lower-level servo control, and the instantaneous delay or fluctuation of the upper-level scheduling will be directly transmitted to the lower level, destroying the uniformity and determinism of the instruction application time.

[0018] To address the aforementioned problems in the prior art, this application proposes a deterministic scheduling method for multi-axis motion tasks of robots, which can be applied to complex task scenarios performed by embodied intelligent systems (e.g., embodied intelligent robots). Its flowchart is attached. Figure 1 As shown, it mainly includes steps S1 to S5, which are detailed below: Step S1: Obtain a robot motion graph containing multiple semantic motion units and their semantic relationships, and calculate the time window of each semantic motion unit based on the time specifications of the semantic motion units and the constraints of the semantic relationships.

[0019] In this embodiment, a robot motion graph is a data structure used to describe complex robot tasks. It decomposes a complete task into a series of basic semantic motion units with clear semantics, and defines the logical and temporal relationships between these units through semantic relations. A semantic motion unit is the smallest schedulable action block of a task, and its types are diverse, including, for example, joint-space point-to-point motion (MOVJ), Cartesian space linear motion (MOVL), circular motion (MOVC), gripper opening and closing control, digital input / output (DI / DO) control, and synchronization waiting actions for verification, etc. Each semantic motion unit is accompanied by a time specification, which includes at least its expected duration (i.e., the theoretical time required to complete the action) and deadline (i.e., the latest time the action must be completed). Semantic relations define the constraints between units, mainly including but not limited to: sequential relations (one unit must finish before another unit can start, with an offset), parallel relations (multiple units can start simultaneously), synchronization relations (time consistency within a preset synchronization tolerance for multiple units), resource mutual exclusion relations (multiple units cannot occupy the same resource simultaneously), and timeout relations, etc. Robot motion graphs provide a high-level semantic description of a task, but they are not yet linked to specific scheduling times.

[0020] The purpose of calculating the time window is to transform the robot motion graph with temporal constraints into a feasible execution interval for each semantic motion unit on the time axis. In existing technologies, the handling of complex temporal constraints is often scattered throughout the program logic, lacking a unified and formalized temporal feasibility analysis, which easily leads to hidden temporal conflicts. This application solves this problem through systematic window calculation. Specifically, the calculation of the time window for each semantic motion unit can be achieved through the following steps S1.1 to S1.3: Step S1.1: Based on the constraint that the semantic relationship type is sequential, calculate the earliest start time of the target semantic motion unit that is no earlier than the sum of the planned end time and offset of its source semantic motion unit.

[0021] For example, if semantic motion unit B must start at least 50 milliseconds after unit A ends, and the planned end time of A is T_A_end, then the earliest start time of B is Earliest(B) = T_A_end + 50ms. This calculation propagates forward along the sequential relationship path of the motion graph, determining a lower bound for the start time of each unit, determined by the predecessor task.

[0022] Step S1.2: Calculate the latest start time that does not violate the deadline time according to the deadline time constraint of the semantic motion unit.

[0023] Assuming that the deadline of unit C is Deadline(C) and its expected duration is Duration(C), then its latest start time Latest(C) = Deadline(C) - Duration(C). This constraint ensures that the task can be completed within the specified time.

[0024] Step S1.3: Determine the planned start time between the earliest start time and the latest start time to form an effective time window.

[0025] The time window is defined as the [Earliest, Latest] interval. The scheduler can select a specific "planned start time" for a unit within this interval. This calculation process is essentially a time-based reasoning process based on constraint propagation. When the calculated earliest start time is later than the latest start time, it indicates an irreconcilable time constraint conflict. In this case, the system can perform at least one of the following operations: generate a time planning failure event and terminate the current scheduling process to prompt upstream rescheduling; or, attempt to automatically adjust the planned start time of the conflicting semantic motion unit (e.g., relax its deadline or offset within an allowable range) and recalculate the time window for subsequent semantic motion units. This approach adds feasibility verification and self-adjustment mechanisms to the planning phase. Generating failure events can promptly prompt upstream systems to replan, avoiding meaningless execution; automatic adjustment and recalculation attempt to self-optimize within constraints, potentially resolving some conflicts, improving the front-end robustness and intelligence of the entire scheduling system, and preventing the transmission of erroneous or unrealistic time plans to the execution layer.

[0026] Step S2: Quantize each time window into a timed execution slot sequence ordered by the trigger time. Each timed execution slot in the timed execution slot sequence represents an execution time section at a predetermined trigger time and records at least the semantic motion unit set and synchronization axis group information to be triggered at the execution time section.

[0027] In traditional scheduling methods, task triggering is often event-driven (e.g., completion of a preceding sequence) or based on coarse periodic scans, lacking a global, high-precision time reference. For example, event-triggered message queues send a message to trigger the next action when an action is completed. The drawback is that the triggering time depends entirely on the completion event of the preceding action and message communication delays; it is reactive and cannot achieve forward-looking, precise time planning, resulting in poor time determinism. Another example is a task list based on scan cycles, which checks the task list and executes tasks that meet the conditions in each scan cycle. However, this approach also has significant drawbacks: the task start time is anchored to the scan cycle boundary, the resolution is limited by the scan cycle, it cannot express sub-periodic precision triggering times, and complex timing relationships require extensive hard-coding of auxiliary logic, resulting in poor expressibility. Therefore, the technical solution adopted in this application is to quantize each time window into a sequence of timed execution slots ordered by triggering time. Each timed execution slot in the sequence represents an execution time segment at a predetermined triggering time and records at least the set of semantic motion units to be triggered and the synchronization axis group information at that execution time segment. This scheme creates a new type of scheduling unit called timed execution slot by quantization and sorting. It discretizes continuous time planning into a series of scheduling points with clear and unique trigger timestamps, and packages and records all actions (SMUs) that need to be triggered at the same time and their synchronization relationships. This transforms the fuzzy time window into a precise scheduling instruction table, providing a unique and clear time reference and operation object for all subsequent steps. It is the foundation and prerequisite for achieving time determinism in the entire scheme.

[0028] Specifically, quantifying each time window into a sequence of time slots ordered by trigger time can be achieved through steps S2.1 to S2.3, as detailed below: Step S2.1: Divide the planned start time of the timed execution slot by the preset scheduling cycle to obtain the corresponding trigger cycle number, and retain the trigger timestamp in nanoseconds.

[0029] The scheduling tick period is the basic time unit (e.g., 1 ms) for the scheduler's operation. This operation quantizes and aligns consecutive plan start times to discrete scheduling ticks. For example, if the plan start time is 150.2 ms and the scheduling tick is 1 ms, then the trigger tick number is 150, and the trigger timestamp is 150200000 nanoseconds. Retaining nanosecond-level timestamps is to maintain a high-precision time reference.

[0030] Step S2.2: Aggregate semantic motion units to be triggered at the same trigger time according to the order of trigger timestamps to generate timed execution slots.

[0031] All semantic motion units scheduled to start within the same scheduling tick will be aggregated together to form a timed execution slot. Each timed execution slot uniquely represents an execution time segment, that is, the set of all actions that the system needs to process when that precise scheduling tick arrives; the timed execution slot is the atomic unit of scheduling.

[0032] Step S2.3: Record multiple semantic motion units containing synchronous semantic relationships in the same synchronous axis group within the same timing execution slot.

[0033] Synchronization relationships are defined in the robot motion graph. When generating timed execution slots, units with synchronization relationships are not only grouped into the same timed execution slot, but also assigned to a specific synchronization axis group within that slot. A timed execution slot can contain multiple synchronization axis groups, and axes within each group need to be strictly synchronized. Units between different groups or outside the same group execute concurrently within the timed execution slot, but strict synchronization is not required. In the embodiments of this application, each timed execution slot contains a unique slot identifier, used to index the slot throughout the entire task lifecycle. The core fields of the slot include: trigger tick number, i.e., the scheduling tick number corresponding to the slot; trigger timestamp, the absolute trigger time expressed in nanoseconds; a list of semantic motion units to be triggered, recording the identifiers of all semantic motion units that need to be started at that time; and a list of synchronization axis groups, each containing a group identifier, the number of axes within the group, the identifiers of each axis, and the allowed preload confirmation time window length for that group. In addition, the time slot also includes a target execution cycle field, indicating in which hardware control cycle the lower-level device adapter should number the application instruction; a pre-write tick number, i.e., the scheduling tick number at which the scheduler begins writing instructions to the device adapter buffer; an instruction buffer index and a feedback buffer index, used to associate the time slot with the slot occupied in the circular buffer; a time slot status, used to mark the lifecycle stage of the time slot (e.g., pending scheduling, ready, triggered, completed, or failed); a synchronization tolerance, representing the maximum allowed synchronization deviation of the time slot in microseconds; and an error handling strategy, used to specify the response measures to be taken when the time slot execution is abnormal (e.g., pause, discard, or reschedule). All time slots are pre-allocated a fixed-size array before the task starts, and managed at runtime through read / write pointers and a state machine, without dynamic memory allocation, thus ensuring the real-time and deterministic nature of the scheduling process.

[0034] As can be seen from the above embodiments, the data structure of the timed execution slot is rich. In addition to recording the set of semantic motion units to be triggered and the information of the synchronization axis group, its data structure also includes a target execution cycle field, which is used to indicate the physical cycle number of the control command applied by the lower-level device adapter. Therefore, after step S2, the method further includes mapping the trigger timestamp of each timed execution slot to the value of the target execution cycle field. This is equivalent to establishing a digital bridge between the upper-level scheduling plan and the lower-level hardware execution, converting the nanosecond-level trigger timestamp into a cycle number that the device adapter can recognize. This allows each timed execution slot to not only know "when to trigger" but also to specify "in which hardware cycle to execute," thereby achieving an unambiguous and operable precise conversion from the planned time to the physical execution cycle, which is the foundation for ensuring that the time plan can be ultimately implemented.

[0035] The lower-level actuator (e.g., a servo driver) operates with a fixed control cycle (e.g., 250µs). This mapping converts the upper-level scheduling tick time into a cycle count for the lower-level actuator. For example, if the trigger timestamp corresponds to 150ms and the lower-level cycle is 250µs, then the target execution cycle = 150ms / 250µs = 600. This field is the key link in synchronizing the upper-level scheduling plan with the lower-level hardware clock.

[0036] Through step S2, the abstract task plan is transformed into a scheduling timetable with a clear time scale and explicit content, consisting of a sequence of time slots for scheduled execution. This timetable is the sole basis for all subsequent deterministic scheduling operations.

[0037] Step S3: Through a two-layer cycle buffer mechanism, in the upper-layer scheduling cycle, the control instructions corresponding to the target time slot are pre-written into the instruction buffer of the corresponding device adapter at the pre-write time of the target time slot. In the lower-layer execution cycle, the device adapter reads and applies the control instructions from the buffer.

[0038] Step S3 addresses the issue that the nondeterminism of the upper-level scheduling cycle (e.g., task scheduling delays, GC pauses) directly transmits and interferes with the lower-level highly deterministic execution cycle—the scheduling jitter propagation problem. It aims to isolate interference from different time domains, ensuring that the lower-level executor can accurately consume instructions at its inherent, stable, high-frequency cycle. In real-time systems such as robot control, the upper-level task scheduler and the lower-level hardware executor typically operate in different time domains and frequencies. Traditional "direct call" or "instant delivery" models directly transmit unavoidable computational fluctuations and operating system scheduling delays from the upper-level scheduling loop to the lower level, causing unpredictable jitter during instruction application and severely compromising time consistency. To address this issue, this application creatively introduces a "dual-layer cycle buffer" mechanism. The core idea is to decouple the "planned generation time" and "physical application time" of the instruction in both time and space. Specifically, the technical solution adopted in this application is as follows: through the dual-layer cycle buffer mechanism, in the upper-layer scheduling cycle, the control instruction corresponding to the target time slot is pre-written into the instruction buffer of the corresponding device adapter at the pre-write time of the target time slot. In the lower-layer execution cycle, the device adapter reads and applies the control instruction from the buffer. In this scheme, the two-layer cycle acknowledges the reality that scheduling and execution reside in different time domains. The buffer establishes a "reservoir" and "firewall" between the two, transforming the pressure of real-time and urgent instruction issuance into pre-emptive and deliberate instruction pre-positioning operations. The upper-layer scheduler only needs to ensure that the instruction is placed in the buffer before the deadline (trigger time) to be considered as task completion. The lower-layer executor is completely unaffected by upper-layer scheduling fluctuations and focuses only on retrieving and executing instructions from the buffer at its own pace. This fundamentally cuts off the propagation path of nondeterministic jitter from top to bottom and is the core architecture that ensures the determinism of the entire system's execution time.

[0039] Specifically, the two-layer cycle buffer mechanism includes the key implementation methods of the following examples S31 to S33: S31: Before the task starts, pre-allocate circular memory for the time slot sequence, instruction buffer, and feedback buffer to be executed periodically.

[0040] This operation is fundamental to ensuring real-time performance and determinism. By allocating the memory required for all critical data structures in one go during the initialization phase, dynamic memory allocation during high-speed task scheduling loops is avoided, thus completely eliminating the risks of random latency and fragmentation introduced by the unpredictable behavior of the memory manager.

[0041] S32: The upper-level scheduling cycle is driven by a hardware timer or a real-time operating system timer interrupt.

[0042] This means that each cycle of the Scheduling Engine (SCDE) is not determined by the task scheduler of a general-purpose operating system, but is triggered by a hardware clock source with high precision and predictable cycles, or a timer in the real-time kernel. This ensures that the upper-level scheduling itself has strict periodicity, with minimal error in its tick intervals, providing a stable and reliable time base for the entire scheduling process.

[0043] S33: The lower-level execution cycle is synchronized with the control cycle of the physical servo driver and the simulator.

[0044] As a direct interface to hardware (or emulator), the device adapter's operating cycle needs to be strictly phase-locked with the hardware's inherent control cycle (e.g., the current loop and position loop cycles of a servo drive). This synchronization is typically achieved through hardware interrupts, bus synchronization signals (e.g., EtherCAT's distributed clock), or high-precision software timing, ensuring that the device adapter consumes and applies commands at a fixed, uniform rhythm.

[0045] Based on the stable periodic framework described above, the scheduler performs a pre-write operation. Pre-writing the control command corresponding to the target time slot to the instruction buffer of the corresponding device adapter at the pre-write time of the target time slot can be achieved through the following steps S'31 and S'32: Step S'31: Calculate the number of remaining clock cycles until the trigger time based on the current scheduling clock cycle and the trigger clock cycle number of the timed execution slot.

[0046] In each scheduling tick, the scheduler iterates through the sequence of time slots that have not yet been triggered. Assuming the current scheduling tick is Current_Tick, and the trigger tick number of a target time slot is Target_Tick, then the remaining ticks Remaining = Target_Tick - Current_Tick.

[0047] Step S'32: When the remaining number of beats is less than or equal to the preset pre-write advance, determine that the pre-write time has been entered, and execute the generation and writing of control instructions.

[0048] The pre-write lead is a configurable parameter whose value must be greater than the maximum time required from instruction generation to writing to the buffer. For example, the lead is set to 2 scheduling ticks. When Remaining <= 2, the scheduler begins processing the target time slot. It first generates control instructions in real time based on the unit type and motion parameters of the semantic motion unit set in the timed execution slot. For example, for units of the "joint space point-to-point motion" type, the position / velocity instruction sequence required by the servo driver needs to be calculated based on its target joint angle and motion parameters (velocity, acceleration); or, for complex trajectory motion, the pre-written control instructions are read from the pre-calculated and stored interpolation point sequence buffer according to the target execution cycle index. Afterward, the scheduler finds the corresponding device adapter based on the semantic motion unit's device_binding and writes the generated or read instructions to its instruction buffer. The device adapter instruction buffer is a circular buffer, and the movement of its read / write pointer and the update of the instruction validity flag are synchronously maintained by the upper-level scheduling cycle and the lower-level execution cycle through a lock-free programming mechanism to avoid dynamic memory allocation. Lock-free mechanisms (e.g., single producer-single consumer queues using atomic operations) ensure that the scheduler (producer) and device adapter (consumer) can access the buffer safely and efficiently concurrently without the need for mutex locks, avoiding priority inversion and unpredictable delays caused by lock contention.

[0049] For ease of engineering implementation, the instruction buffer can adopt a circular queue structure. Each buffer entry contains the following information: a unique instruction identifier, used to associate with the semantic motion unit in the timed execution slot; a target execution axis identifier, indicating which actuator should process the instruction; the instruction type, such as position instruction, speed instruction, torque instruction, digital output instruction, or gripper instruction; the instruction payload, i.e., the specific control parameters (e.g., target position, speed value, torque limit, or switch status); the expected application timestamp, i.e., the nanosecond-level moment when the instruction is scheduled to take effect on the underlying hardware; the target execution cycle number, i.e., the sequence number of the lower-level hardware control cycle in which the instruction should be applied; an instruction validity flag, used to mark whether the entry contains a valid instruction; and a device adapter acknowledgment flag, used to indicate whether the device has completed receiving or preloading the instruction. The circular buffer is managed by two pointers: the write pointer is atomically incremented by the upper-level scheduler each time a pre-write occurs, and the read pointer is atomically incremented by the lower-level device adapter each time an instruction is consumed. The difference between the write pointer and the read pointer represents the number of instructions to be consumed in the buffer. When the difference equals the buffer capacity, the buffer is full and the scheduler should wait; when the difference is zero, the buffer is empty and the device adapter should wait. All pointer operations are implemented using atomic instructions (such as compare-and-swap), eliminating the need for mutexes and thus avoiding priority inversion and unpredictable context switching overhead.

[0050] At this point, the instructions have been safely "stored" in the target device's buffer. When the next execution cycle arrives, the device adapter reads the control instructions from the read pointer position of the circular buffer and applies them to drive the physical actuators (servo motors, grippers, etc.) to move. This "write-before-consume" model allows the upper-level scheduler to ensure that the writing is completed before the "deadline" for the instructions to take effect. Its own minor fluctuations are absorbed by the buffer and no longer affect the precise timing of the application of the underlying instructions, thus achieving excellent timing determinism.

[0051] Step S4: For time slots containing synchronous semantic relationships, before the target trigger time, send a synchronous pre-trigger command to all device adapters in the synchronous axis group to trigger each device adapter in the group to apply its pre-stored corresponding control command in the same target execution cycle.

[0052] The double-buffering mechanism in step S3 above ensures that instructions can be pre-issued and stably, but this alone is insufficient to guarantee strict synchronization. In actual hardware systems, even if instructions arrive simultaneously in the buffers of different device adapters, due to minor differences in the internal state machines, bus communication stacks, and driver readiness of each device, there may still be microsecond-level deviations between the time the instruction is read from the buffer and its final application to the physical axis, i.e., synchronization phase differences. To solve this deep-seated problem, this application adds a collaborative triggering step on top of pre-writing. The specific technical solution is as follows: For timed execution slots containing synchronization semantic relationships, before the target triggering time, a synchronization pre-triggering instruction is sent to all device adapters in the synchronization axis group to trigger each device adapter in the group to apply its pre-stored corresponding control instructions in the same target execution cycle. In this scheme, the synchronous pre-trigger command is a dedicated coordination signal carrying a unified timestamp (target execution cycle). It commands all relevant device adapters to prepare the pre-stored control commands upon receiving the signal and wait for a unified, future, precise moment (same target execution cycle) to execute them simultaneously. This is equivalent to unifying the "starting gun" for all asynchronously executing devices, thereby achieving forced alignment of multi-axis command application times at the physical execution level. It is a key enhancement method for achieving high-precision time consistency, especially multi-axis synchronization.

[0053] Specifically, for time slots containing synchronous semantic relationships, before the target trigger time, a synchronous pre-trigger command is sent to all device adapters in the synchronous axis group to trigger each device adapter in the group to apply its pre-stored corresponding control commands in the same target execution cycle. This can be achieved through steps S4.1 to S4.3, as detailed below: Step S4.1: At the preset synchronization pre-trigger advance time before the target trigger time, send a synchronization pre-trigger instruction packet containing the synchronization group identifier, the target trigger timestamp, and the target execution cycle to each device adapter in the synchronization axis group.

[0054] This instruction packet is a dedicated coordination signal, not the control instruction itself. The synchronization group identifier distinguishes different synchronization groups; the target trigger timestamp is the absolute time (nanosecond level) in the upper-level scheduling plan; the target execution cycle is the underlying hardware cycle number mapped from this timestamp. Δt_sync (synchronization pre-trigger lead) needs to be large enough to cover the network transmission latency of the instruction packet and the longest internal preparation time of each device adapter.

[0055] Step S4.2: Receive pre-loading confirmation information from each device adapter for the synchronization pre-trigger instruction packet.

[0056] Upon receiving the synchronization pre-trigger instruction packet, the device adapter immediately performs a critical operation: based on the target execution cycle in the instruction packet, it locates the corresponding control instruction in its instruction buffer and loads it into a special local "pending-effective buffer" or register dedicated to this synchronization action. This "pre-loading" operation pre-processes the transfer of instructions from the general buffer to the final application interface. Once pre-loading is complete, the device adapter immediately returns a pre-load confirmation message to the scheduler.

[0057] Step S4.3: Mark the status of the corresponding time slot as ready only when all device adapters in the same synchronous axis group return preload confirmation information within the preset confirmation time window.

[0058] The device adapter internally maintains a finite state machine to manage the synchronization pre-triggering process. The initial state is idle, where the adapter waits for instructions or synchronization pre-triggering instruction packets from the scheduling engine. Upon receiving a synchronization pre-triggering instruction packet, the adapter enters a pre-loading state. In this state, it searches for the corresponding control instruction in the instruction buffer based on the target execution cycle number in the instruction packet and copies it to a local dedicated register to be activated. After pre-loading is complete, the adapter returns a pre-loading confirmation message and enters a standby state, waiting for the target execution cycle to arrive. When the target execution cycle arrives, the adapter enters an execution state, reads the instruction from the register to be activated, and immediately applies it to the physical executor, while recording the instruction application timestamp. After execution is complete, the adapter enters a completed state, returns feedback information including the timestamp to the scheduling engine, and then resets back to the idle state to prepare for the next round of instructions. If the pre-loading process fails to complete within the preset confirmation time window in the pre-loading state, the adapter enters a failure state and returns a pre-loading failure error. If the adapter finds that the target execution cycle has expired without being triggered in the standby state, it also enters a failure state and returns a timeout error. If a hardware failure is detected during execution, the adapter immediately enters a failure state and returns a hardware error code. The scheduling engine then performs subsequent processing based on the returned error code and the preset error handling strategy.

[0059] The scheduler sets a confirmation timeout window. Only when all members in the synchronization group confirm that the instruction has been preloaded within this window does the scheduler consider the group ready for synchronization and set the time slot status to ARMED (ready). This constitutes the first safety check for synchronization. However, unexpected events can always occur in complex systems. Therefore, to address the problem of the entire synchronization axis group becoming "stuck" or inconsistent in status due to a single device malfunction (e.g., communication interruption, preload failure) during the synchronization pre-triggering process, and to provide fault tolerance during the synchronization preparation phase, step S4.3 above may further include: if any device adapter in the same synchronization axis group fails to return preload confirmation information within the preset confirmation time window, a synchronization preparation failure event is generated and processed according to the preset error handling strategy in the corresponding time slot. For example, the error handling strategy may be PAUSE (pause all axes), SKIP (skip this synchronization group and continue subsequent asynchronous tasks), or ABORT (abort the entire task). By introducing timeout judgment and failure event generation, the above solution enables the system to promptly detect the breakpoint of synchronous collaboration and intervene according to preset strategies (e.g., pause, alarm) to prevent global failure or safety accidents caused by local faults, thus significantly improving the reliability and safety of the multi-axis collaborative system.

[0060] When the synchronization group is in ARMED state and the underlying target execution cycle counter reaches a predetermined value, all device adapters within the group will apply their pre-stored corresponding control instructions in the same target execution cycle. This simultaneous application is typically guaranteed by a precise hardware clock or interrupt within the device adapter, thereby achieving forced alignment of the multi-axis instruction activation time at the physical level and eliminating random deviations introduced by software scheduling and bus communication.

[0061] Step S5: Receive feedback information from each device adapter, which includes the application timestamp of the control command. Verify the execution result based on the feedback information and handle any anomalies in subsequent timed execution slots according to the verification result.

[0062] Step S5 constitutes a complete technical closed loop from planning, scheduling, execution to verification, and is the ultimate guarantee for achieving "time consistency" in this application. Without feedback verification, any determinism in planning and scheduling is merely an open-loop assumption. This application, through precise timestamp feedback, enables the system to perceive the deviation between actual execution and the plan, and to make intelligent responses accordingly.

[0063] Step S5 may also include resource management for completed time slots. Specifically, after determining that the execution result meets the verification requirements, the status of the corresponding time slot is updated to "completed," and the buffer resources occupied by that time slot are released for reuse by subsequently generated time slots. This is an important optimization measure. During execution, time slots may occupy slots in the instruction buffer and feedback buffer. After all associated semantic motion units have been executed and passed verification, the system actively marks these slots as free and returns their indexes to the free resource pool. This allows the entire scheduling system to cyclically utilize fixed memory resources during long-term operation or continuous execution of multiple tasks, avoiding memory leaks and fragmentation, and ensuring long-term system stability and high performance.

[0064] First, the execution result is verified. Verification of the execution result based on the feedback information can be achieved through the following steps Sa51 to Sa54: Step Sa51: For the same synchronous axis group, extract the application timestamps of the control commands returned by each device adapter within the group.

[0065] After the instruction is applied to the hardware, the device adapter records the actual instruction application timestamp using a high-precision clock (such as a clock synchronized with the IEEE 1588 precision time protocol) and returns it along with the status information.

[0066] It should be noted that, in this embodiment, the specific content of the feedback information may include the following fields: instruction identifier, used to associate with the corresponding control instruction; execution axis identifier; instruction reception timestamp, i.e., the moment the device adapter reads the instruction from the buffer; instruction preload timestamp, i.e., the moment the device adapter loads the instruction into the local register to be activated; instruction application timestamp, i.e., the moment the instruction is actually applied to the physical actuator (this is key data for synchronization verification); arrival timestamp, i.e., the moment the actuator moves to the target position tolerance range; actual position, speed, and torque feedback values; digital input / output status; and error code. These feedback entries are written to the feedback buffer by the device adapter after each lower-level execution cycle, and the scheduling engine reads them in batches in subsequent upper-level scheduling cycles. For a synchronization axis group, the scheduling engine extracts the instruction application timestamps of all axes in the group, calculates the difference between the maximum and minimum values, and if the difference exceeds the preset synchronization tolerance of the time slot, a synchronization error event is determined to have occurred. For a single semantic motion unit, the scheduling engine compares the instruction application timestamp with the arrival timestamp to calculate the actual execution duration, and compares it with the expected duration in the unit's time specification to update the unit's execution status (e.g., normal completion, delayed completion, or timeout).

[0067] Step Sa52: Calculate the maximum difference between the timestamps of each application.

[0068] Step Sa53: Determine whether the maximum difference exceeds the preset synchronization tolerance in the time slot of the timed execution.

[0069] Each time slot can define a tolerance_us (synchronization tolerance, e.g., 50 microseconds), which is the maximum time deviation allowed for that synchronization.

[0070] Step Sa54: If the error exceeds the limit, a synchronization error event is determined to have occurred.

[0071] This event indicates that although the system attempted synchronization, the actual result did not meet the required accuracy.

[0072] As can be seen from the examples of steps Sa51 to Sa54 above, which verify the execution results based on feedback information, it effectively solves the global replanning problem of how to ensure that the temporal logic of all subsequent tasks remains correct and feasible after an anomaly occurs in the middle of the task flow execution (e.g., exceeding tolerance, missing a beat). Specifically, it provides a powerful dynamic global replanning capability, that is, instead of simply skipping or discarding subsequent tasks, it takes the current abnormal moment as a new starting point and re-derives the time window and time slot of the entire remaining task sequence based on the updated time reality (e.g., the actual application timestamp). This can maintain the temporal semantics and task integrity of the original motion graph to the greatest extent. While dealing with unexpected interference, it intelligently generates a new and feasible subsequent execution schedule, reflecting the high-order autonomy and resilience of the system.

[0073] Secondly, the feedback information can also include a command arrival timestamp. The device adapter records the command arrival timestamp when it detects that the actuator axis has reached the desired position (e.g., within the target position tolerance range). Figure 1 The example method, after step S5, may further include: calculating the actual execution duration of a single semantic motion unit based on the control instruction application timestamp and the instruction arrival timestamp; comparing the actual execution duration with the expected duration in the semantic motion unit's time specification, and updating the execution state of the semantic motion unit. For example, if the expected duration of a linear motion is 200ms, and the actual execution duration is 205ms, it indicates a slight delay in execution. The system can update the unit's state accordingly and provide more accurate time expectations for subsequent units that depend on it.

[0074] When verification reveals problems (e.g., synchronization errors, missed trigger ticks), the system cannot ignore them and must dynamically adjust subsequent plans. As one embodiment of this application, the specific handling of subsequent time slots based on the verification results for exceptions can be as follows: When a synchronization error occurs, according to a preset error handling strategy, at least one of the following operations is performed: pausing scheduling and waiting for external intervention; discarding affected subsequent time slots; and recalculating and generating the planned start time for subsequent time slots that have not yet been triggered based on the actual instruction application timestamp. These measures address the decision-making and execution problem of how the system should respond after detecting synchronization errors, providing a closed-loop path from "problem discovery" to "problem resolution," and endowing the system with structured response capabilities when synchronization is out of control. For example, by pausing to prevent damage from escalating, or by dynamically replanning subsequent tasks to adapt to the time deviation that has occurred. This allows the system not only to perceive inconsistencies but also to digest or process them, thereby enhancing the adaptability and completion rate of complex tasks in non-ideal execution environments.

[0075] In the above embodiments, recalculating and generating the planned start times of subsequent time slots that have not yet been triggered is an advanced automatic recovery capability. Furthermore, based on the verification results, anomaly handling is performed on subsequent time slots, including: when synchronization errors or missed trigger tick events occur, according to the preset error handling strategy in the affected time slots, recalculating and generating the planned start times of all subsequent time slots that have not yet been triggered, starting from the current abnormal time slot, and updating the time slot sequence. This means that the system does not simply adjust the next time slot, but uses the current actual time as the new time origin, based on the original semantic motion unit relationships and constraints, to re-execute the time planning and time slot quantization process from the current time to the end of the task. The newly generated time slot sequence will replace the unexecuted parts of the original plan, thus maintaining the temporal logic and integrity of the original task graph to the greatest extent possible even after deviations occur during task flow execution, demonstrating the system's powerful dynamic adjustment and self-recovery capabilities.

[0076] For intuitive display Figure 1The following example illustrates the time-dimensional operation of the method. Using a dual-axis synchronous capture task as an example, we assume the upper-level scheduling cycle is 1 millisecond and the lower-level execution cycle is 250 microseconds. After the task starts, the scheduling engine loads the motion graph and begins time planning in the first scheduling cycle (0 milliseconds), completes the time window calculation in the second scheduling cycle (1 millisecond), and generates the time slot sequence in the third scheduling cycle (2 milliseconds). A key time slot has a trigger cycle number of 6 (corresponding to 6 milliseconds) and contains a synchronous axis group (axis 1 and axis 2). In the fourth scheduling cycle (3 milliseconds), the scheduling engine detects that the remaining cycle number for this time slot is 3 (less than the preset pre-write advance of 4), and thus begins pre-writing the position command of axis 1 to the corresponding device adapter's command buffer. In the fifth scheduling cycle (4 milliseconds), the position command of axis 2 is pre-written to its buffer. In the sixth scheduling tick (5 milliseconds), the scheduling engine sends a synchronization pre-trigger instruction packet to both device adapters. This packet contains the target execution cycle number 24 (corresponding to 6 milliseconds divided by 250 microseconds). The two device adapters complete preloading and return acknowledgments at 5.1 milliseconds and 5.15 milliseconds respectively. After receiving all acknowledgments at 5.2 milliseconds, the scheduling engine marks the time slot as ready. When the underlying hardware clock counts to the 24th execution cycle (6 milliseconds), both device adapters simultaneously read instructions from their respective pending registers and apply them to the physical executors, then record the application timestamp and return. In the next scheduling tick (6 milliseconds), the scheduling engine processes the feedback information, calculates the difference between the two application timestamps to be 30 microseconds, which is less than the preset 50 microsecond synchronization tolerance. Therefore, it updates the time slot status to complete and releases the buffer resources it occupies. Throughout the process, minor fluctuations in the upper-level scheduling cycle (e.g., slight variations in the processing time of the fifth cycle) are absorbed by the instruction buffer and do not affect the precise application time of the sixth execution cycle, thus achieving deterministic scheduling with time consistency.

[0077] From the above Figure 1The example of a deterministic scheduling method for multi-axis robot motion tasks demonstrates that, on the one hand, by quantizing the motion graph's time window into a sequence of timed execution slots ordered by trigger times and recording complete execution time profile information for each slot, a clear mapping relationship is established between the upper-level planning time, scheduling trigger times, and the lower-level target execution cycle. This transforms the originally abstract time planning result into a series of concrete, time-defined scheduling units that can be directly processed by the scheduling engine, thus laying the structural foundation for the precise effective time of control instructions and helping to reduce the systematic drift between planned time and actual execution time. On the other hand, by employing a two-layer cycle buffer mechanism, the upper-level scheduling cycle driven by scheduling ticks is decoupled from the lower-level execution cycle driven by fixed control cycles. A pre-written instruction buffer serves as an intermediate bridge, allowing the upper-level scheduler to pre-set instructions for multiple future execution cycles within a single scheduling cycle, while the lower-level device adapter consumes instructions according to its own stable high-frequency cycle. In this way, the instantaneous computational delays or jitters that may exist in the upper-level scheduling loop are absorbed by the buffer and no longer directly affect the cycle uniformity and time determinism of the lower-level instruction application. The system significantly improves the timing stability and predictability of the entire execution process. Thirdly, by introducing synchronous pre-trigger instructions for time slots containing synchronous semantic relationships and triggering the application of pre-stored instructions by the device adapters within the group during the same target execution cycle, it achieves closed-loop control of multi-axis synchronization from semantic declaration to physical execution. This not only sends a synchronization signal to each execution axis indicating "when it will take effect," but more importantly, it forces alignment of the instruction application points of each axis through the unified time reference of "the same target execution cycle," thereby effectively ensuring the consistency of the starting phase of multi-axis motion at the physical layer and solving the synchronization error problem caused by differences in device response or communication delays. Fourthly, by receiving and verifying the execution results and handling anomalies based on feedback information such as the application timestamps of the control instructions returned by each device adapter, a closed loop from planning to scheduling to execution feedback is formed. This allows the system to proactively perceive deviations between actual execution and the plan (e.g., synchronization errors) and dynamically adjust or process subsequent plans based on the verification results. This enhances the system's fault tolerance and robustness in the face of non-ideal execution environments, achieving proactive maintenance of time consistency rather than passive dependence. In summary, the technical solution of this application achieves temporal consistency determinism between planning, scheduling and physical execution of multi-axis robot motion through timed execution slot planning, double-layer periodic buffering and synchronous pre-triggering.

[0078] Please see the appendix Figure 2 This application provides a deterministic scheduling device for the time consistency of multi-axis motion tasks of a robot. The device includes an acquisition module 201, a quantization module 202, an instruction processing module 203, a triggering module 204, and a verification module 205, which are described in detail below: The acquisition module 201 is used to acquire a robot motion graph containing multiple semantic motion units and their semantic relationships, and to calculate the time window of each semantic motion unit based on the time specifications of the semantic motion units and the constraints of the semantic relationships. The quantization module 202 is used to quantize the time window of each semantic motion unit into a timed execution slot sequence ordered by the trigger time. Each timed execution slot in the timed execution slot sequence represents an execution time section at a predetermined trigger time and records at least the set of semantic motion units to be triggered in the execution time section and the information of the synchronization axis group. The instruction processing module 203 is used to pre-write the control instruction corresponding to the target time slot into the instruction buffer of the corresponding device adapter during the pre-writing time of the target time slot in the upper-level scheduling cycle through a two-layer cycle buffer mechanism. In the lower-level execution cycle, the device adapter reads and applies the control instruction from the instruction buffer. The trigger module 204 is used to send a synchronization pre-trigger instruction to all device adapters in the synchronization axis group before the target trigger time for a time slot containing synchronization semantic relationship, so as to trigger each device adapter in the group to apply its pre-stored corresponding control instruction in the same target execution cycle. The verification module 205 is used to receive feedback information from each device adapter, which includes the application timestamp of the control command, verify the execution result based on the feedback information, and perform anomaly handling on subsequent time slots based on the verification result.

[0079] From the above Figure 2As illustrated by the example of a deterministic scheduling device for multi-axis robot motion tasks, on the one hand, by quantizing the time window of the motion graph into a sequence of timed execution slots ordered by trigger time, and recording complete execution time profile information for each slot, a clear mapping relationship is established between the upper-level planning time, scheduling trigger time, and the lower-level target execution cycle. This transforms the originally abstract time planning result into a series of concrete, time-based scheduling units that can be directly processed by the scheduling engine, thus laying the structural foundation for the effective time of precise control instructions and helping to reduce the systematic drift between planned time and actual execution time. On the other hand, by adopting a two-layer cycle buffer mechanism, the upper-level scheduling cycle driven by scheduling ticks is decoupled from the lower-level execution cycle driven by fixed control cycles. A pre-written instruction buffer serves as an intermediate bridge, allowing the upper-level scheduler to pre-set instructions for multiple future execution cycles within a single scheduling cycle, while the lower-level device adapter consumes instructions according to its own stable high-frequency cycle. Thus, the instantaneous computational delay or jitter that may exist in the upper-level scheduling cycle is absorbed by the buffer and no longer directly affects the cycle uniformity and time determinism of the lower-level instruction application. The system significantly improves the timing stability and predictability of the entire execution process. Thirdly, by introducing synchronous pre-trigger instructions for time slots containing synchronous semantic relationships and triggering the application of pre-stored instructions by the device adapters within the group during the same target execution cycle, it achieves closed-loop control of multi-axis synchronization from semantic declaration to physical execution. This not only sends a synchronization signal to each execution axis indicating "when it will take effect," but more importantly, it forces alignment of the instruction application points of each axis through the unified time reference of "the same target execution cycle," thereby effectively ensuring the consistency of the starting phase of multi-axis motion at the physical layer and solving the synchronization error problem caused by differences in device response or communication delays. Fourthly, by receiving and verifying the execution results and handling anomalies based on feedback information such as the application timestamps of the control instructions returned by each device adapter, a closed loop from planning to scheduling to execution feedback is formed. This allows the system to proactively perceive deviations between actual execution and the plan (e.g., synchronization errors) and dynamically adjust or process subsequent plans based on the verification results. This enhances the system's fault tolerance and robustness in the face of non-ideal execution environments, achieving proactive maintenance of time consistency rather than passive dependence. In summary, the technical solution of this application achieves temporal consistency determinism between planning, scheduling and physical execution of multi-axis robot motion through timed execution slot planning, double-layer periodic buffering and synchronous pre-triggering.

[0080] This application also provides a device adapter for robot motion control, comprising: The instruction buffer is used to receive and cache control instructions from the upper-level scheduling engine, which carry the target execution cycle identifier. The synchronization pre-trigger receiving module is used to receive synchronization pre-trigger instruction packets from the upper-layer scheduling engine. The synchronization pre-trigger instruction packets contain the synchronization group identifier, the target trigger timestamp, and the target execution cycle. The preloading module, in response to the synchronous pre-trigger instruction packet, preloads the control instructions corresponding to the target execution cycle from the instruction buffer into the local register to be activated; The application execution module is used to read control instructions from the register to be activated and apply them to the connected physical actuators when the target execution cycle arrives; The timestamp recording module is used to record the actual application timestamp of control commands and return feedback information containing the actual application timestamp to the upper-layer scheduling engine. Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example... Figure 3 As shown, the electronic device 3 in this embodiment mainly includes: a processor 30, a memory 31, and a computer program 32 stored in the memory 31 and executable on the processor 30, such as a program for a deterministic scheduling method for time consistency of robot multi-axis motion tasks. When the processor 30 executes the computer program 32, it implements the steps in the above-described embodiment of the deterministic scheduling method for time consistency of robot multi-axis motion tasks, for example... Figure 1 Steps S1 to S5 are shown. Alternatively, when processor 30 executes computer program 32, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 2 The functions of the acquisition module 201, quantization module 202, instruction processing module 203, triggering module 204, and verification module 205 are shown.

[0081] For example, the computer program 32 of the robot multi-axis motion task time consistency deterministic scheduling method mainly includes: acquiring a robot motion graph containing multiple semantic motion units and their semantic relationships, and calculating the time window of each semantic motion unit based on the constraints of the time specifications and semantic relationships of the semantic motion units; quantizing the time window of each semantic motion unit into a timed execution slot sequence ordered by trigger time, each timed execution slot in the timed execution slot sequence representing an execution time section at a predetermined trigger time, and recording at least the set of semantic motion units to be triggered at the execution time section and the information of the synchronization axis group; through a two-layer periodic buffer mechanism, in the upper-level scheduling cycle, at... The pre-writing time of the target time slot pre-writes the control instructions corresponding to the target time slot into the instruction buffer of the corresponding device adapter. In the next execution cycle, the device adapter reads and applies the control instructions from the instruction buffer. For time slots containing synchronization semantics, before the target trigger time, a synchronization pre-trigger instruction is sent to all device adapters in the synchronization axis group to trigger each device adapter in the group to apply its pre-stored corresponding control instructions in the same target execution cycle. Feedback information containing the application timestamp of the control instructions is received from each device adapter. The execution result is verified according to the feedback information, and exception handling is performed on subsequent time slots according to the verification result. The computer program 32 can be divided into one or more modules / units, which are stored in the memory 31 and executed by the processor 30 to complete this application. One or more modules / units can be a series of computer program instruction segments capable of performing specific functions. These instruction segments are used to describe the execution process of the computer program 32 in the electronic device 3.For example, computer program 32 can be divided into the functions of acquisition module 201, quantization module 202, instruction processing module 203, triggering module 204, and verification module 205 (a module in the virtual device). The specific functions of each module are as follows: Acquisition module 201 is used to acquire a robot motion graph containing multiple semantic motion units and their semantic relationships, and calculate the time window of each semantic motion unit based on the time specifications and semantic relationship constraints of the semantic motion units; Quantization module 202 is used to quantize the time window of each semantic motion unit into a timed execution slot sequence ordered by the trigger time. Each timed execution slot in the timed execution slot sequence represents an execution time section at a predetermined trigger time, and at least records the set of semantic motion units to be triggered at the execution time section and the information of the synchronization axis group; Instruction processing module 203 is used to pre-write the control instructions corresponding to the target time-based execution slot into the instruction buffer of the corresponding device adapter during the pre-write time of the target time-based execution slot in the upper-level scheduling cycle through a two-layer cycle buffer mechanism. In the lower-level execution cycle, the device adapter reads and applies the control instructions from the instruction buffer. Trigger module 204 is used to send a synchronization pre-trigger instruction to all device adapters in the synchronization axis group before the target trigger time for time-based execution slots containing synchronization semantics, so as to trigger each device adapter in the group to apply its pre-stored corresponding control instructions in the same target execution cycle. Verification module 205 is used to receive feedback information returned by each device adapter containing the application timestamp of the control instructions, verify the execution result according to the feedback information, and perform anomaly handling for subsequent time-based execution slots according to the verification result.

[0082] Electronic device 3 may include, but is not limited to, processor 30 and memory 31. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 3 and does not constitute a limitation on electronic device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device may also include input / output devices, network access devices, buses, etc.

[0083] The processor 30 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0084] The memory 31 can be an internal storage unit of the electronic device 3, such as a hard disk or RAM. The memory 31 can also be an external storage device of the electronic device 3, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 31 can include both internal and external storage units of the electronic device 3. The memory 31 is used to store computer programs and other programs and data required by the electronic device. The memory 31 can also be used to temporarily store data that has been output or will be output.

[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed. That is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above-described device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0087] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0088] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0089] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0090] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0091] If integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can also be implemented by a computer program instructing related hardware. The computer program of the robot multi-axis motion task time consistency deterministic scheduling method can be stored in a storage medium. When the computer program is executed by the processor, it can implement the steps of the above method embodiments, that is, obtain a robot motion graph containing multiple semantic motion units and their semantic relationships, and calculate the time window of each semantic motion unit based on the time specifications and semantic relationship constraints of the semantic motion units; quantize the time window of each semantic motion unit into a timed execution slot sequence ordered by the trigger time, each timed execution slot in the timed execution slot sequence represents an execution time section at a predetermined trigger time, and at least records the execution time section. The system includes a set of semantic motion units to be triggered and information on the synchronization axis group. Through a two-layer cycle buffer mechanism, in the upper-layer scheduling cycle, the control instructions corresponding to the target time-based execution slot are pre-written into the instruction buffer of the corresponding device adapter at the pre-write time of the target time-based execution slot. In the lower-layer execution cycle, the device adapter reads and applies the control instructions from the instruction buffer. For time-based execution slots containing synchronization semantic relationships, before the target trigger time, a synchronization pre-trigger instruction is sent to all device adapters in the synchronization axis group to trigger each device adapter in the group to apply its pre-stored corresponding control instructions in the same target execution cycle. Feedback information containing the application timestamps of the control instructions is received from each device adapter. The execution result is verified based on the feedback information, and exception handling is performed on subsequent time-based execution slots according to the verification result. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate form. Storage media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the contents of storage media can be appropriately added to or removed according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, storage media may not include electrical carrier signals and telecommunication signals.

[0092] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application. The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the protection scope of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for robot multi-axis motion task time-consistent deterministic scheduling, characterized in that, The method includes: Step S1: Obtain a robot motion graph containing multiple semantic motion units and their semantic relationships, and calculate the time window of each semantic motion unit based on the time specifications of the semantic motion units and the constraints of the semantic relationships; Step S2: Quantize each time window into a timed execution slot sequence ordered by the trigger time. Each timed execution slot in the timed execution slot sequence represents an execution time section at a predetermined trigger time and records at least the semantic motion unit set and synchronization axis group information to be triggered in the execution time section. Step S3: Through a two-layer cycle buffer mechanism, in the upper-layer scheduling cycle, the control instruction corresponding to the target time slot is pre-written into the instruction buffer of the corresponding device adapter at the pre-write time of the target time slot. In the lower-layer execution cycle, the device adapter reads and applies the control instruction from the instruction buffer. Step S4: For time slots containing synchronous semantic relationships, before the target trigger time, send a synchronous pre-trigger command to all device adapters in the synchronous axis group to trigger each device adapter in the group to apply its pre-stored corresponding control command in the same target execution cycle. Step S5: Receive feedback information from each device adapter containing the application timestamp of the control command, verify the execution result based on the feedback information, and perform anomaly handling on subsequent time slots based on the verification result; The step of quantizing each time window into a sequence of timed execution slots ordered by trigger time includes: Step S2.1: Dividing the planned start time of each timed execution slot by a preset scheduling cycle to obtain the corresponding trigger cycle number, and retaining the trigger timestamp in nanoseconds; Step S2.2: Aggregating semantic motion units to be triggered at the same trigger time according to the order of the trigger timestamps to generate timed execution slots; Step S2.3: Recording multiple semantic motion units containing synchronous semantic relationships in the same synchronous axis group of the same timed execution slot; The data structure of the timed execution slot also includes a target execution cycle field, which is used to indicate the physical cycle number of the control command applied by the lower-level device adapter. After step S2, the method further includes mapping the trigger timestamp of each timed execution slot to the value of the target execution cycle field. The dual-layer cycle buffer mechanism includes: pre-allocating ring memory for the time slot sequence, instruction buffer, and feedback buffer before the task starts; the upper-layer scheduling cycle is driven by a hardware timer or a real-time operating system timer interrupt; and the lower-layer execution cycle is synchronized with the control cycle of the physical servo driver and the simulator.

2. The method of claim 1, wherein, For time slots containing synchronous semantic relationships, before the target trigger time, a synchronous pre-trigger command is sent to all device adapters within the synchronous axis group to trigger each device adapter within the group to apply its pre-stored corresponding control commands in the same target execution cycle, including: Step S4.1: At the preset synchronization pre-trigger advance time before the target trigger time, send a synchronization pre-trigger instruction packet containing the synchronization group identifier, the target trigger timestamp, and the target execution cycle to each device adapter in the synchronization axis group; Step S4.2: Receive pre-loading confirmation information from each device adapter for the synchronization pre-trigger instruction packet; Step S4.3: Only when all device adapters in the same synchronous axis group return the preload confirmation information within the preset confirmation time window, mark the status of the corresponding time slot as ready.

3. The method of claim 2, wherein, Step S4.3 is followed by: If any device adapter in the same synchronous axis group fails to return preload confirmation information within the preset confirmation time window, a synchronization preparation failure event is generated and processed according to the preset error handling strategy in the corresponding time slot.

4. A device for robot multi-axis motion task time consistency deterministic scheduling, which implements the robot multi-axis motion task time consistency deterministic scheduling method according to any one of claims 1 to 3, characterized in that, The device includes: The acquisition module is used to acquire a robot motion graph containing multiple semantic motion units and their semantic relationships, and to calculate the time window of each semantic motion unit based on the time specifications of the semantic motion units and the constraints of the semantic relationships. The quantization module is used to quantize each of the time windows into a sequence of timed execution slots ordered by the trigger time. Each timed execution slot in the sequence represents an execution time section at a predetermined trigger time and records at least the semantic motion unit set and synchronization axis group information to be triggered in the execution time section. The instruction processing module is used to pre-write the control instruction corresponding to the target time slot into the instruction buffer of the corresponding device adapter during the pre-writing time of the target time slot in the upper-level scheduling cycle through a two-layer cycle buffer mechanism. In the lower-level execution cycle, the device adapter reads and applies the control instruction from the instruction buffer. The trigger module is used to send a synchronization pre-trigger command to all device adapters in the synchronization axis group before the target trigger time for timed execution slots containing synchronization semantic relationships, so as to trigger each device adapter in the group to apply its pre-stored corresponding control command in the same target execution cycle. The verification module is used to receive feedback information returned by each device adapter, which includes the application timestamp of the control command, verify the execution result according to the feedback information, and perform anomaly handling on subsequent time slots based on the verification result.

5. A device adapter for robot motion control, implementing the time-consistent deterministic scheduling method for multi-axis robot motion tasks as described in any one of claims 1 to 3, characterized in that, The device adapter includes: The instruction buffer is used to receive and cache control instructions from the upper-level scheduling engine, the control instructions carrying a target execution cycle identifier; The synchronization pre-trigger receiving module is used to receive the synchronization pre-trigger instruction packet from the upper-layer scheduling engine. The synchronization pre-trigger instruction packet includes a synchronization group identifier, a target trigger timestamp, and a target execution cycle. The preloading module, in response to the synchronous pre-trigger instruction package, preloads the control instructions corresponding to the target execution cycle in the instruction buffer into the local register to be activated; The application execution module is used to read control instructions from the register to be activated and apply them to the connected physical actuator when the target execution cycle arrives; The timestamp recording module is used to record the actual application timestamp of the control command and return feedback information containing the actual application timestamp to the upper-layer scheduling engine.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the time-consistent deterministic scheduling method for robot multi-axis motion tasks as described in any one of claims 1 to 3.

7. A storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the time-consistent deterministic scheduling method for robot multi-axis motion tasks as described in any one of claims 1 to 3.

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