Programmable dynamic load test circuit for power management chip, system and method thereof

Abstract

The application provides a programmable dynamic load test circuit for a power management chip, a system and a test method thereof, and belongs to the technical field of chip testing. The programmable dynamic load test circuit comprises a programmable logic unit, at least two pulse width modulators integrated in the programmable logic unit for generating pulse signals with respective frequencies and / or duty cycles, a frequency synthesizer integrated in the programmable logic unit, an input end of the frequency synthesizer being connected with an output end of each pulse width modulator, the frequency synthesizer receiving each pulse signal and performing synthesis to generate a composite synthesis signal, a filter, an input end of the filter being connected with an output end of the frequency synthesizer, the filter performing filtering processing on the composite synthesis signal, an output controller, an input end of the output controller being connected with an output end of the filter, a driver, an input end of the driver being connected with an output end of the output controller, and a power semiconductor switch, a control end of the power semiconductor switch being connected with an output end of the driver to output a dynamic load current. The application realizes complex dynamic load simulation with a simple and low-cost architecture.

Description

Technical Field

[0001] This invention relates to the technical field of chip testing, and in particular to a programmable dynamic load test circuit, system, and test method for power management chips. Background Technology

[0002] In the manufacturing and verification of computers and their peripherals, comprehensive functional and performance testing of power management chips (PMICs) is crucial. PMICs need to handle the complex, rapid, and variable current demands from load units such as CPUs, GPUs, and DDR memory in real-world application scenarios. To effectively verify the transient response, voltage stability, and protection functions of PMICs, the test equipment must be able to simulate highly realistic and diverse dynamic loads.

[0003] Existing technologies typically employ a multi-channel independent control architecture to achieve diverse load variations. The control chip within the test equipment incorporates multiple pulse width modulators (PWMs), each connected to an independent output controller, MOSFET driver, and power MOSFET switch. By controlling the on and off states of different MOSFETs, various load current steps can be combined to cover a wide range of load variation scenarios.

[0004] However, this approach has the following drawbacks: First, high hardware costs: Each additional load channel requires a complete set of MOSFETs, drivers, output controllers, and matching analog-to-digital converters, leading to a sharp increase in chip area, material costs, and PCB layout complexity. Second, insufficient testing flexibility: Existing solutions can only generate discrete, stepped load changes through switch combinations, making it difficult to generate continuous, nonlinear, or complex load waveforms involving multi-frequency coupling characteristics. For example, the high-frequency transient currents generated by concurrent operations such as DDR5 dual-channel independent read / write, DBI data flipping, background refresh, and ZQC calibration limit the test coverage and accuracy. Finally, poor scalability: To support more load combinations to cover more complex test scenarios, large-scale hardware modifications are required, resulting in long development cycles and high costs.

[0005] In view of this, a novel programmable dynamic load test circuit, system, and test method for power management chips are proposed to solve all or part of the above problems. Summary of the Invention

[0006] To address at least one of the aforementioned problems and deficiencies in the prior art, embodiments of the present invention provide a programmable dynamic load test circuit, system, and method for power management chips. It employs a many-to-one architecture of "multi-channel pulse width modulator (PWM) -> single frequency synthesizer -> single power MOSFET," replacing the traditional multi-channel independent load architecture, significantly reducing hardware costs and chip area. The frequency synthesizer supports both waveform synthesis and digital signal synthesis modes. Through logical superposition, arithmetic operations, or inverse fast Fourier transform (IFFT) combined with direct digital frequency synthesis (DDS) technology, multiple simple PWM signals are synthesized into complex dynamic load waveforms containing multi-frequency modulation components, resulting in higher test coverage. The programmable nature of the FPGA allows for increased load simulation complexity without hardware modifications, improving expansion flexibility. The present invention achieves a simple, low-cost, highly flexible, and highly reliable PMIC dynamic load test. The technical solution is as follows:

[0007] According to one aspect of the present invention, a programmable dynamic load test circuit for a power management chip is provided. The programmable dynamic load test circuit includes:

[0008] Programmable logic unit;

[0009] At least two pulse width modulators, integrated within a programmable logic unit, are used to generate pulse signals with their own frequencies and / or duty cycles;

[0010] A frequency synthesizer, integrated inside a programmable logic unit, has its input connected to the output of at least two pulse width modulators, and receives and synthesizes at least two pulse signals from the at least two pulse width modulators to generate a composite signal.

[0011] A filter, whose input is connected to the output of a frequency synthesizer, filters the composite signal.

[0012] The output controller has its input terminal connected to the output terminal of the filter;

[0013] The driver, whose input is connected to the output of the output controller; and

[0014] A power semiconductor switch whose control terminal is connected to the output terminal of the driver to output dynamic load current.

[0015] According to another aspect of the present invention, a programmable dynamic load testing system for a power management chip is provided, the programmable dynamic load testing system including a test machine, the control component of which integrates the programmable dynamic load testing circuit described above.

[0016] The test machine of the programmable dynamic load test system is equipped with a user interface, which is connected to the programmable logic unit. This user interface is used to receive external control signals to dynamically configure the parameters of each pulse width modulator of at least two pulse width modulators, select the operating mode of the frequency synthesizer, and set the threshold of the protection circuit.

[0017] According to another aspect of the present invention, a programmable dynamic load testing method for a power management chip is provided. The programmable dynamic load testing method includes:

[0018] Provides programmable logic units;

[0019] Pulse signals with their own frequencies and / or duty cycles are generated by at least two pulse width modulators integrated within a programmable logic unit.

[0020] A composite signal is generated by a frequency synthesizer integrated within a programmable logic unit, which receives and synthesizes at least two pulse signals generated by at least two pulse width modulators.

[0021] The composite signal is filtered to generate a driving signal;

[0022] The power semiconductor switch is driven by the drive signal through the output controller and driver, and the dynamic load current is output to the power management chip under test.

[0023] The programmable dynamic load test circuit, system, and test method for power management chips provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0024] (1) By using a multi-to-one architecture of at least two pulse width modulators -> frequency synthesizers -> single power semiconductor switches, the traditional solution eliminates the need for N-1 power semiconductor switches and their associated drivers, output controllers and analog devices such as digital-to-analog converters, which significantly reduces hardware costs and chip / PCB area and simplifies system integration.

[0025] (2) The frequency synthesizer can synthesize multiple simple PWM signals into arbitrarily complex dynamic load waveforms, including nonlinear load waveforms containing multi-frequency modulation components, which can more realistically simulate actual application scenarios, thereby greatly expanding the test coverage and accuracy of the test machine.

[0026] (3) The frequency and / or duty cycle parameters of each pulse width modulator can be dynamically configured through the user interface. The frequency and duty cycle of different PWM outputs can be the same or different to achieve free combination. Furthermore, by selecting the working mode of the frequency synthesizer and setting the threshold of the protection circuit, the complexity of increasing the load simulation can be achieved by simply increasing the number of PWM channels or modifying the synthesis algorithm inside the programmable logic unit without any hardware changes. It can easily adapt to more complex test requirements in the future.

[0027] (4) The integrated glitch filter effectively prevents the noise generated during the digital synthesis process from causing false triggering of the power semiconductor switch; and the high-efficiency single-channel protection circuit composed of the sampling resistor, amplifier, comparator, digital-to-analog converter and overcurrent latch can respond to overcurrent faults quickly and accurately, cut off the output in microseconds, and effectively protect the circuit safety.

[0028] (5) The frequency synthesizer supports waveform synthesis mode and digital signal synthesis mode. The waveform synthesis mode is suitable for quickly generating composite logic waveforms. The digital signal synthesis mode can generate high-precision arbitrary waveforms by combining fast Fourier inverse transform with direct digital frequency synthesis technology. It can be flexibly selected according to test requirements to meet diverse needs from conventional testing to high-precision complex waveform simulation. Attached Figure Description

[0029] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a schematic diagram of the principle structure of a programmable dynamic load test circuit according to an embodiment of the present invention;

[0031] Figure 2 This is a flowchart of a programmable dynamic load testing method according to an embodiment of the present invention. Detailed Implementation

[0032] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0033] The core of this invention lies in constructing a novel dynamic load synthesis architecture of "multi-channel pulse width modulator (PWM) -> single frequency synthesizer (FS) -> single power switch (MOSFET)". This programmable dynamic load test circuit and its testing method utilize multiple flexibly programmable PWM signals within a programmable logic unit (such as an FPGA chip) to perform high-degree-of-freedom time-domain synthesis or DDS digital synthesis via FS, thereby generating a high-fidelity complex load waveform incorporating features such as multi-frequency modulation. This achieves the simulation of dynamic loads most closely resembling real-world scenarios at very low hardware costs (i.e., eliminating N-1 MOSFET paths), fundamentally solving the technical contradictions and R&D challenges of existing solutions, such as high hardware costs, poor simulation flexibility, and insufficient scalability. It significantly improves the coverage and accuracy of power management chip (PMIC) testing.

[0034] See Figure 1 The diagram shows a schematic diagram of the principle structure of a programmable dynamic load test circuit 100 according to a preferred embodiment of the present invention.

[0035] like Figure 1 As shown, the programmable dynamic load test circuit 100 of the present invention (hereinafter referred to as test circuit 100) is packaged in a chip and integrated into the control component of the test machine. The core of the test circuit 100 is a programmable logic unit 110, namely a field-programmable gate array (FPGA), which integrates N (N is a positive integer ≥2) pulse width modulators 111 (PWM), a frequency synthesizer 112 (FS), a filter 113 (Glitch Filter, GF) and related control logic / circuits.

[0036] In one specific embodiment, the test circuit 100 comprises: a frequency synthesizer 112 (FS), a filter 113 (GF, preferably a glitch filter), N pulse width modulators 111 (PWM 1, PWM 2, ..., PWM N) within a programmable logic unit 110 (FPGA), a driver 120 (MOSFET Driver, MD) and its power semiconductor switch, an output controller 114 (Output Control, OC), an overcurrent latch 115 (Over Current Latch, OCL), an amplifier 130 (OPA), a comparator 140 (CMP), a digital-to-analog converter 150 (DAC), a sampling resistor 160 (RL), and output terminals V- and V+.

[0037] In the test circuit 100 of the present invention, the programmable logic unit 110 is preferably an FPGA chip. At least two pulse width modulators 111 are integrated inside the FPGA chip to generate pulse signals with their own frequencies and / or duty cycles. These pulse width modulators 111 are independent of each other and can be configured with different frequency and duty cycle parameters according to external control commands.

[0038] The frequency synthesizer 112 is also integrated inside the FPGA chip. Its input terminals are connected to the output terminals of all pulse width modulators 111, receiving pulse signals from these pulse width modulators 111 and synthesizing them to generate a composite signal. This "many-to-one" connection architecture is the key hardware configuration of this invention. Multiple pulse width modulators 111 share the same frequency synthesizer 112, and then drive a single power semiconductor switch through a shared channel, i.e., through a single driver 120, thereby significantly saving hardware resources.

[0039] Filter 113, preferably a glitch filter, has its input connected to the output of frequency synthesizer 112. It filters the composite signal to eliminate glitches and UHF interference that may be introduced during synthesis. Output controller 114 has its input connected to the output of filter 113 and controls the switching of the drive signal based on feedback from the protection circuit. Driver 120 has its input connected to the output of output controller 114 and converts the control signal to a level and drive capability suitable for driving the power semiconductor switch. The control terminal (gate) of the power semiconductor switch (preferably an N-channel power MOSFET) is connected to the output of driver 120. Its drain is connected to the positive output (V+) of the circuit and to the PMIC under test. Its source is grounded via sampling resistor 160 to output dynamic load current to the PMIC under test.

[0040] In one example, see Table 1, which provides a specific example of design parameters.

[0041] Table 1 Test Circuit Design Parameters

[0042]

[0043] The control logic of the test circuit 100 is as follows: The user sends a control signal to the FPGA through the user port of the test machine. The FPGA configures the frequency, duty cycle, and other parameters of each PWM according to the signal and selects the FS operating mode. The pulse signals output by each PWM are synthesized in the FS. The synthesized composite signal is filtered by the GF and then sequentially drives the power semiconductor switch MOSFET (Q1) through the OC and MOSFET drivers, thereby generating a controlled dynamic load current between V+ and V-, which is applied to the PMIC under test. Figure 1The circuit schematic is explained in detail below:

[0044] The internal signal processing chain of the programmable logic unit 110 is as follows: N independent pulse width modulators 111 (PWM 1-PWMN) serve as the basic signal source, outputting pulse signals with flexibly configurable frequency and duty cycle; these signals enter the frequency synthesizer 112 for digital domain synthesis to generate composite synthesized signals containing multi-frequency modulation characteristics; these composite synthesized signals are first filtered by the filter 113 to remove narrow pulse interference, and then the output controller 114 performs signal shaping and logic judgment, and finally outputs drive instructions.

[0045] External power and protection chain: The drive command output by the programmable logic unit 110 is amplified by the driver 120 to control the turn-on and turn-off of the power semiconductor switch MOSFET (Q1), thereby generating a dynamically changing load current between V+ and V-. At the same time, the sampling resistor 160 monitors the load current in real time. After being amplified by the amplifier 130, it is compared with the overcurrent threshold reference voltage output by the digital-to-analog converter 150. Once the overcurrent condition is triggered, the overcurrent latch 115 will immediately cut off the drive signal to achieve rapid circuit protection.

[0046] Multi-channel pulse width modulator 111: As a basic signal source, it supports independent configuration of the frequency and duty cycle of each PWM channel, and can flexibly combine to generate pulse signals with different characteristics, providing a variety of basic units for subsequent waveform synthesis.

[0047] Frequency synthesizer 112: This is the core component of the present invention, supporting two operating modes:

[0048] Time-domain synthesis mode: Perform logical operations (such as AND, OR, XOR) or arithmetic operations (such as weighted summation) on multiple PWM signals to directly generate a synthesized waveform with a specific envelope.

[0049] Digital signal synthesis mode: The PWM signal is used as a digital control word. After being processed by IFFT and combined with DDS technology, a continuous analog waveform of arbitrary shape is generated, which can accurately simulate the complex transient current of high-bandwidth loads such as DDR5.

[0050] Filter 113: The filtering logic is implemented through a shift register or counter. It only outputs a valid signal when a stable level is detected within multiple consecutive clock cycles. It can effectively filter out metastable glitches in the output signal of the frequency synthesizer 112 and prevent the power semiconductor switch from being triggered erroneously.

[0051] Overcurrent protection chain: A closed-loop protection circuit is formed by sampling resistor 160, amplifier 130, digital-to-analog converter 150, comparator 140, and overcurrent latch 115. The user can flexibly set the overcurrent threshold through digital-to-analog converter 150. When the load current is detected to exceed the threshold, comparator 140 output triggers overcurrent latch 115, immediately cutting off the drive signal to achieve microsecond-level circuit protection.

[0052] Signal generation and synthesis: The user configures the parameters of each pulse width modulator 111 inside the programmable logic unit 110 through an external interface to generate multiple basic pulse signals; the frequency synthesizer 112 synthesizes these signals according to a preset algorithm to generate a composite signal that meets the test requirements.

[0053] Signal filtering and driving: The composite signal is filtered by filter 113 to remove interference, and then the output controller 114 outputs a driving command; the driving command is amplified by driver 120 to control the conduction state of the power semiconductor switch and generate dynamic load current.

[0054] Real-time monitoring and protection: The sampling resistor 160 monitors the load current in real time. After being amplified by the amplifier 130 (i.e., operational amplifier), the current is compared with the threshold voltage output by the digital-to-analog converter 150. When the current exceeds the threshold, the overcurrent latch 115 triggers the protection mechanism to cut off the drive signal and ensure system safety.

[0055] In summary, the "multi-channel PWM -> single-frequency synthesizer -> single MOSFET switch" architecture of this invention has significant advantages over existing multi-channel independent control schemes:

[0056] Significantly reduced hardware costs: Eliminating N-1 sets of power switching devices, drivers, and associated analog circuits significantly reduces chip area and material costs;

[0057] Enhanced testing flexibility and accuracy: The frequency synthesizer can generate complex load waveforms that include multi-frequency modulation and nonlinear transient characteristics, which can accurately simulate the dynamic behavior of real loads and expand the scope of test scenarios.

[0058] Enhanced system scalability: No large-scale hardware modifications are required; different test scenarios can be switched solely through software configuration, improving testing efficiency and convenience.

[0059] In one example, the frequency synthesizer 112 supports two operating modes, which can be flexibly selected according to test requirements. Specifically:

[0060] (1) Waveform synthesis mode:

[0061] In waveform synthesis mode, frequency synthesizer 112 directly performs logical superposition or arithmetic operations on multiple PWM waveforms in the time domain to generate composite synthesized signals.

[0062] Taking two PWM signals as an example: PWM 1 outputs a square wave signal with a frequency of 100kHz and a duty cycle of 50%, and PWM 2 outputs a square wave signal with a frequency of 1MHz and a duty cycle of 25%. The frequency synthesizer 112 performs point-by-point logic operations on the two signals in the time domain. Commonly used logic operation types include:

[0063] Logical OR operation: If any PWM signal is high at the same time, the output is high, which is suitable for generating envelope superposition type composite waveforms;

[0064] Logical AND operation: A high level is output only when all PWM signals are high at the same time, which is suitable for generating narrow pulse composite waveforms;

[0065] The logical "XOR" operation: When two PWM signal levels are not at the same time, a high level is output, which is suitable for generating frequency multiplication type composite waveforms.

[0066] For example, by performing a logical OR operation on two signals, a composite signal containing a 100kHz carrier and a 1MHz envelope can be synthesized, which can simulate high-frequency transient scenarios, such as those experienced by a CPU under low-frequency load.

[0067] This mode is characterized by its simplicity, low latency, and suitability for real-time control, making it suitable for routine dynamic load testing scenarios that require rapid response.

[0068] (2) Digital signal synthesis mode:

[0069] In digital signal synthesis mode, multiple PWM signals are input as digital control words to frequency synthesizer 112. Frequency synthesizer 112 first processes the spectral data of the multiple PWM signals through inverse fast Fourier transform (IFFT), and then uses direct digital frequency synthesis (DDS) technology to generate high-precision arbitrary waveform signals.

[0070] Specifically, the synthesis process of this digital signal synthesis mode is illustrated as follows:

[0071] The first step is spectrum mapping: The programmable logic unit 110 internally maps N PWM control words (each corresponding to preset frequency and amplitude parameters) into frequency domain discrete spectrum data.

[0072] The second step is the IFFT operation: The frequency domain data is transformed using an IFFT to obtain a time-domain digital waveform sequence. The length of the IFFT (i.e., the number of points) determines the frequency resolution and accuracy of the synthesized waveform, and can be configured according to actual needs, such as using a 1024-point or 2048-point IFFT.

[0073] The third step is DDS synthesis: the time-domain waveform sequence output by IFFT is used as the waveform lookup table of the DDS engine. The waveform amplitude value is read by addressing with a high-frequency system clock (e.g., 200MHz) through a phase accumulator. Then, after digital-to-analog conversion (an external digital-to-analog converter 150 can be used if needed) and reconstruction filtering, a continuous arbitrary waveform signal is output.

[0074] For the parallel input of multiple PWM control words, the frequency synthesizer 112 adopts an FPGA-based multi-channel parallel IFFT architecture: multiple PWM control words correspond to different spectral components of the IFFT frequency point, and the FPGA performs complex multiplication and addition operations on all spectral lines in parallel within one IFFT operation cycle, converting the frequency domain data into a time domain waveform sequence in one go. This parallel architecture can complete the synchronous processing of multiple signals within a single system clock cycle, avoiding the phase error introduced by serial processing.

[0075] This digital signal synthesis mode can generate complex waveforms with high precision and low distortion, such as multi-frequency coupled transient current waveforms generated during DDR5 memory read and write operations, and is suitable for high-precision testing scenarios.

[0076] In one example, filter 113 is configured as a glitch filter to eliminate glitches and / or UHF interference components in the composite signal.

[0077] In programmable logic devices such as FPGAs, glitches are prone to occur in combinational logic outputs due to differences in signal transmission path delays and simultaneous changes in multiple signals. If these glitches directly drive power semiconductor switches, they may be mis-activated, causing abnormal output current or even damage to the devices. Therefore, this invention incorporates a glitch filter at the output of the frequency synthesizer 112.

[0078] The glitch filter can be implemented using digital filtering logic, and its filtering logic is illustrated below:

[0079] Let the input signal be S_in, the output signal be S_out, and the system clock be clk (e.g., 200MHz, corresponding to a 5ns clock cycle). The glitch filter internally uses a counter CNT and a preset pulse width threshold TH (e.g., TH=4, corresponding to 20ns). The counter samples the level of S_in at each rising edge of the clock.

[0080] When a change in the level of S_in is detected, the counter CNT is cleared and starts to accumulate;

[0081] When the counter CNT reaches the preset pulse width threshold TH, the level change is confirmed to be valid, and S_out toggles after S_in.

[0082] If the level of S_in changes again before the counter CNT reaches TH, it is determined to be a glitch, and S_out remains unchanged.

[0083] This design effectively filters out short-duration glitches with pulse widths smaller than a preset pulse width threshold. The preset pulse width threshold TH can be dynamically configured via a user interface based on the characteristics of the power semiconductor switch being driven. It is typically set to 1 / 3 to 1 / 2 of the minimum conduction pulse width of the MOSFET link to ensure effective glitches filtering without affecting the normal drive signal.

[0084] In one example, the glitch filter can optionally support two sub-modes: single-sided glitch filtering and double-sided glitch filtering. Single-sided glitch filtering only filters glitches in the positive (low->high) or negative (high->low) direction, suitable for applications sensitive to specific edges; double-sided glitch filtering filters glitches in both positive and negative directions simultaneously, suitable for scenarios requiring highly clean signal edges.

[0085] In one example, the test circuit 100 also includes a sampling resistor 160 connected between the source of the power semiconductor switch and ground to sample the dynamic load current flowing through the power semiconductor switch. The sampling resistor 160 is a low-inductance precision resistor, the value of which is selected based on the expected current range. For example, for a test current of 10A, a 0.01Ω sampling resistor 160 can be selected, generating a sampling voltage of 0.1V at 10A. The voltage across the sampling resistor 160 is proportional to the current flowing through the power semiconductor switch; by detecting this voltage, the magnitude of the load current can be monitored in real time.

[0086] In one example, the test circuit 100 also includes a complete overcurrent protection circuit, specifically comprising: an amplifier 130, a digital-to-analog converter 150, a comparator 140, and an overcurrent latch 115 (integrated within the FPGA). The specific connection and operating principle of this protection circuit are as follows:

[0087] The sampling resistor 160 is connected in series with the source of the power semiconductor switch to convert the load current I_load flowing through the power semiconductor switch into a voltage Vsense = I_load × RL, where RL is the sampling resistor 160.

[0088] Amplifier 130 is connected in parallel with sampling resistor 160 to amplify Vsense, resulting in an amplified voltage Vamp = Gain × Vsense. The amplification factor Gain can be configured according to the sampling resistor value and the expected current range, for example, Gain = 20.

[0089] The digital-to-analog converter 150 outputs a reference voltage Vref based on a preset safe current threshold. This reference voltage can be dynamically configured via a control signal through a user interface.

[0090] The first input terminal of comparator 140 is connected to the output terminal of amplifier 130, and the second input terminal is connected to the output terminal of digital-to-analog converter 150. It is used to compare the amplified voltage Vamp with the reference voltage Vref. When Vamp > Vref, the output of comparator 140 flips.

[0091] The input of the overcurrent latch 115 is connected to the output of the comparator 140, and the output is connected to the output controller 114. When the comparator 140 receives a toggle signal, the overcurrent latch 115 latches the fault state and outputs a shutdown signal to control the output controller 114 to cut off the output to the driver 120, thereby cutting off the drive signal of the power semiconductor switch within microseconds and protecting the circuit.

[0092] For example, the overcurrent latch 115 employs a latching logic design that locks the fault state once triggered, and can only resume normal operation after the system is reset (e.g., by sending a clear command through the user interface or by powering on again). This ensures that the output will not be repeatedly attempted to be restored during the fault period, thus avoiding cumulative damage caused by repeated conduction of the device in the overcurrent state.

[0093] In one example, embodiments of the present invention also provide a programmable dynamic load testing system for a power management chip, comprising a test unit whose control components integrate the test circuit 100 of the above embodiments. The test unit is provided with a user interface connected to a programmable logic unit 110, used to receive external control signals to dynamically configure parameters (including frequency, duty cycle, etc.) of each of at least two pulse width modulators 111, select the operating mode (waveform synthesis mode or digital signal synthesis mode) of the frequency synthesizer 112, and set thresholds for protection circuits (including the output reference voltage of the digital-to-analog converter 150, the threshold of the overcurrent latch 115, etc.).

[0094] For example, the user interface can be implemented in various ways, such as a standard communication interface (e.g., SPI, I2C, UART, etc.) or a dedicated control bus, to connect to a host computer (e.g., a test industrial control computer, microcontroller, etc.) to realize the automated control of the test program.

[0095] See Figure 2The flowchart of a programmable dynamic load testing method according to an embodiment of the present invention is shown.

[0096] In one example, the present invention also provides a programmable dynamic load testing method for a power management chip, specifically including the following steps:

[0097] Step S210: Provide a programmable logic unit;

[0098] Step S220: At least two pulse width modulators integrated in the programmable logic unit generate pulse signals with their own frequencies and / or duty cycles according to external control instructions, wherein the output frequencies of different pulse width modulators may be the same or different, and the output duty cycles may be the same or different.

[0099] Step S230: The frequency synthesizer integrated in the programmable logic unit receives and synthesizes the pulse signals generated by at least two pulse width modulators to generate a composite signal;

[0100] Step S240: Filter the composite signal to generate a driving signal. The filtering is specifically performed by a glitch filter to eliminate glitch and UHF interference components in the composite signal.

[0101] Step S250: The power semiconductor switch is driven by the drive signal through the output controller and driver to output dynamic load current to the power management chip under test.

[0102] The drive signal first enters the output controller, which then passes the signal directly to the MOSFET driver during normal operation. The MOSFET driver performs level conversion and power amplification on the control signal to drive the gate of the power semiconductor switch, controlling its on and off states, thereby generating a simulated dynamic load current between V+ and V-.

[0103] Taking the circuit design structure of the test circuit 100 in the above embodiment as an example.

[0104] In one example, the frequency synthesizer 112 uses a waveform synthesis mode to perform logical superposition or arithmetic operations on at least two pulse signals in the time domain to generate a composite signal.

[0105] In one example, the frequency synthesizer 112 can also employ a digital signal synthesis mode, using at least two pulse signals as digital control words and processing them through an inverse fast Fourier transform (IFFT) to generate a composite signal.

[0106] In one example, the test method also includes real-time monitoring of dynamic load current. When the dynamic load current exceeds a preset threshold, the drive signal is cut off to protect the circuit. The dynamic load current is a nonlinear load waveform that includes multi-frequency modulation components, such as the high-frequency transient waveform simulating DDR5 memory read / write operations, or the multi-frequency coupled current waveform simulating the CPU switching between different operating modes.

[0107] In one example, the specific steps for real-time monitoring of dynamic load current include:

[0108] Step 251: Sample the current flowing through the power semiconductor switch through the sampling resistor 160, and convert the current I_load into a voltage Vsense = I_load × RL;

[0109] Step 252: Amplify Vsense to Vamp = Gain × Vsense using amplifier 130. The amplification factor Gain needs to be reasonably selected based on the sampling resistor value and the preset overcurrent threshold to ensure the input voltage range of comparator 140 and the sampling accuracy of digital-to-analog converter 150;

[0110] Step 253: The digital-to-analog converter 150 outputs a reference voltage Vref according to the preset safe current threshold. The formula for calculating the reference voltage is: Vref = I_threshold × RL × Gain, where I_threshold is the preset overcurrent protection threshold current.

[0111] Step 254: Compare the amplified voltage Vamp with the reference voltage Vref using comparator 140;

[0112] Step 255: When the amplified voltage Vamp exceeds the reference voltage Vref, the output of comparator 140 flips, triggering the overcurrent latch 115;

[0113] Step 256: The overcurrent latch 115 controls the output controller 114 to cut off the drive signal output to the driver 120, thereby protecting the power semiconductor switch and the overall test circuit 100.

[0114] In one example, among the pulse signals output by at least two pulse width modulators 111, the frequencies output by the different pulse width modulators can be the same or different, and the duty cycles output by the different pulse width modulators can also be the same or different. This completely free parameter configuration capability allows users to flexibly combine the parameters of the output signals of each pulse width modulator according to the needs of the test scenario. For example:

[0115] Scenario 1: Simulating the superposition of periodic slow load changes and high-frequency noise.

[0116] PWM 1 outputs a low-frequency (e.g., 1kHz) square wave to simulate load cycle transitions, while PWM 2 outputs a high-frequency (e.g., 500kHz) narrow pulse to simulate high-frequency noise. After the two signals are combined in frequency synthesizer 112 by a logical "OR" operation, the load current exhibits a complex waveform with slow transitions and high-frequency ripple superimposed.

[0117] Scenario 2: Simulating a multi-level stepped load.

[0118] Multiple PWM outputs with the same frequency but different duty cycles are set up. After arithmetic summation in the frequency synthesizer 112, the outputs are driven by the driver 120 and the power semiconductor switch to obtain a multi-level stepped load current. This can be used to test the transient response characteristics of the PMIC when switching between different load current steps.

[0119] Scenario 3: Simulating concurrent operations in DDR memory read / write mode.

[0120] Three PWM channels are configured to correspond to the DDR5 read operation (frequency 5MHz, duty cycle 40%), write operation (frequency 5MHz, duty cycle 40%, phase offset 90°), and background refresh operation (frequency 500kHz, duty cycle 10%). The three signals are processed by IFFT-DDS in digital signal synthesis mode to synthesize a complex current waveform with multi-frequency coupling characteristics, which accurately simulates the load current changes of DDR5 memory during actual operation.

[0121] Furthermore, in some embodiments, the programmable dynamic load testing method further includes, prior to at least two pulse width modulators generating pulse signals with their respective frequencies and / or duty cycles:

[0122] Collect load current data of the power management chip under test in the working scenario;

[0123] Analyze the load current data to determine the target area where the transient rate of change of current and / or the current amplitude exceeds a preset threshold;

[0124] The target region is marked as the worst-case region. The target frequency and target duty cycle are extracted from the worst-case region. At least two pulse width modulators are configured with their respective frequencies and duty cycles based on the target frequency and target duty cycle.

[0125] Specifically, in the actual operating scenario of the power management chip (PMIC) under test, the test machine first acquires the load current data of the PMIC under operating conditions through a current sampling circuit. The load current data can be the time-domain current waveform sequence output by the PMIC when load units such as CPU, GPU, and DDR are working concurrently. Then, time-domain analysis is performed on the acquired load current data to calculate the current transient rate of change (di / dt) and peak detection is performed on the current amplitude. The region where the current transient rate of change and / or current amplitude exceeds a preset threshold is identified as the target region. The preset threshold can be set according to the rated operating parameters of the PMIC under test. For example, the preset threshold for the current transient rate of change can be set to 80-120% of the maximum di / dt allowed in the PMIC chip datasheet, and the preset threshold for the current amplitude can be set to 80-120% of the rated output current of the PMIC chip. Next, the target region is marked as the worst-case region, and the target frequency and target duty cycle are extracted from the waveform of the worst-case region. At least two pulse width modulators are then configured with their respective frequencies and duty cycles based on the target frequency and target duty cycle, ensuring that the subsequently generated pulse signals accurately reproduce the load characteristics of the worst-case region. Through these steps, the test parameters are directly derived from worst-case data in real-world application scenarios, ensuring that each test precisely targets the worst-case region and avoiding the loss of worst-case characteristics caused by blindly synthesizing PWM signals in traditional solutions.

[0126] Furthermore, in some embodiments, the at least three pulse width modulators are not bundled together, and each of the at least three pulse signals corresponds to an independent load source. After the frequency synthesizer generates the composite signal and before filtering, the programmable dynamic load testing method further includes:

[0127] The function generator integrated within the programmable logic unit receives the composite signal, reproduces the load waveform characteristics of the worst-case region based on the composite signal, and outputs the dynamic load current that reproduces the load conditions of the worst-case region by power semiconductor switching.

[0128] Specifically, regarding the independent configuration of the three pulse width modulators, at least the three pulse width modulators are not bundled together, and each of the three pulse signals corresponds to an independent load source. For example, the three pulse width modulators can be configured to correspond to the CPU load channel, GPU load channel, and DDR memory load channel, respectively, each independently generating a pulse signal corresponding to its load source. The three pulse signals are then combined by a frequency synthesizer. Because the pulse width modulators are not bundled together, the timing, frequency, and duty cycle of each load can be independently and precisely adjusted, avoiding the problem of worst-case characteristics being averaged when multiple signals are bundled into a unified signal.

[0129] Regarding the function generator's reproduction of the load waveform characteristics in the worst-case region, after the frequency synthesizer generates the composite signal and before filtering, the function generator, integrated within the programmable logic unit, receives the composite signal. Based on the composite signal, the function generator uses the digital amplitude sequence output by the frequency synthesizer as waveform lookup table data. It then uses a phase accumulator, addressed by the system clock (e.g., 200MHz), to read the waveform amplitude at the corresponding address, generating a continuous waveform signal and outputting it. A specific example illustrates the reproduction process:

[0130] Assuming the composite signal output by the frequency synthesizer contains frequency component A (100kHz, 50% duty cycle) and frequency component B (1MHz, 25% duty cycle), the function generator maps the aforementioned digital control word to an address sequence in a waveform lookup table. A phase accumulator accumulates the phase increment in each clock cycle, retrieving the corresponding amplitude data from the lookup table, and synthesizing a continuous waveform that simultaneously contains a 100kHz fundamental frequency and a 1MHz high-frequency transient. This continuous waveform accurately reproduces the load characteristics of the worst-case region, where a low-frequency load background superimposed with a high-frequency transient jump. The reproduced waveform is output to a glitch filter for filtering, and then the output controller and driver drive a power semiconductor switch, outputting a dynamic load current to the power management chip under test.

[0131] Therefore, the dynamic load current output by the power semiconductor switch accurately reproduces the load conditions in the worst-case region for each test, improving the coverage and relevance of the test.

[0132] The programmable dynamic load test circuit, system, and test method for power management chips provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0133] (1) By using a multi-to-one architecture of at least two pulse width modulators -> frequency synthesizers -> single power semiconductor switches, the traditional solution eliminates the need for N-1 power semiconductor switches and their associated drivers, output controllers and analog devices such as digital-to-analog converters, which significantly reduces hardware costs and chip / PCB area and simplifies system integration.

[0134] (2) The frequency synthesizer can synthesize multiple simple PWM signals into arbitrarily complex dynamic load waveforms, including nonlinear load waveforms containing multi-frequency modulation components, which can more realistically simulate actual application scenarios, thereby greatly expanding the test coverage and accuracy of the test machine.

[0135] (3) The frequency and / or duty cycle parameters of each pulse width modulator can be dynamically configured through the user interface. The frequency and duty cycle of different PWM outputs can be the same or different to achieve free combination. Furthermore, by selecting the working mode of the frequency synthesizer and setting the threshold of the protection circuit, the complexity of increasing the load simulation can be achieved by simply increasing the number of PWM channels or modifying the synthesis algorithm inside the programmable logic unit without any hardware changes. It can easily adapt to more complex test requirements in the future.

[0136] (4) The integrated glitch filter effectively prevents the noise generated during the digital synthesis process from causing false triggering of the power semiconductor switch; and the high-efficiency single-channel protection circuit composed of the sampling resistor, amplifier, comparator, digital-to-analog converter and overcurrent latch can respond to overcurrent faults quickly and accurately, cut off the output in microseconds, and effectively protect the circuit safety.

[0137] (5) The frequency synthesizer supports waveform synthesis mode and digital signal synthesis mode. The waveform synthesis mode is suitable for quickly generating composite logic waveforms. The digital signal synthesis mode can generate high-precision arbitrary waveforms by combining fast Fourier inverse transform with direct digital frequency synthesis technology. It can be flexibly selected according to test requirements to meet diverse needs from conventional testing to high-precision complex waveform simulation.

[0138] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A programmable dynamic load test circuit for a power management chip, characterized in that, The programmable dynamic load test circuit includes: Programmable logic unit; At least two pulse width modulators, integrated within the programmable logic unit, are used to generate pulse signals with their respective frequencies and / or duty cycles; A frequency synthesizer is integrated inside the programmable logic unit. The input terminal of the frequency synthesizer is connected to the output terminals of the at least two pulse width modulators respectively. It receives at least two pulse signals emitted by the at least two pulse width modulators and synthesizes them to generate a composite synthesized signal. The composite synthesized signal is a nonlinear load waveform signal including multi-frequency modulation components. A filter, the input of which is connected to the output of the frequency synthesizer, is used to filter the composite synthesized signal; An output controller, the input of which is connected to the output of the filter; A driver, the input of which is connected to the output of the output controller; and A power semiconductor switch, wherein the control terminal of the power semiconductor switch is connected to the output terminal of the driver, and outputs dynamic load current.

2. The programmable dynamic load test circuit according to claim 1, characterized in that, The frequency synthesizer is configured to: The waveform synthesis mode involves performing logical superposition or arithmetic operations on the at least two pulse signals in the time domain to generate the composite signal; or... The digital signal synthesis mode uses the at least two pulse signals as digital control words and generates the composite signal by processing them through inverse fast Fourier transform.

3. The programmable dynamic load test circuit according to claim 1, characterized in that, The filter is configured as follows: A glitch filter that eliminates glitches and / or ultra-high frequency interference components in the composite signal.

4. The programmable dynamic load test circuit according to any one of claims 1-3, characterized in that, The programmable dynamic load test circuit also includes a sampling resistor connected between the power semiconductor switch and ground to sample and obtain the dynamic load current.

5. The programmable dynamic load test circuit according to claim 4, characterized in that, The programmable dynamic load test circuit also includes: An amplifier, connected in parallel with the sampling resistor, amplifies the voltage across the sampling resistor; Digital-to-analog converter, output reference voltage; A comparator, wherein the first input terminal of the comparator is connected to the output terminal of the amplifier, and the second input terminal of the comparator is connected to the output terminal of the digital-to-analog converter, is used to compare the amplified voltage with the reference voltage; and An overcurrent latch is provided, the input of which is connected to the output of the comparator, and the output of which is connected to the output controller. The overcurrent latch is used to trigger and control the output controller to cut off the output when the amplified voltage exceeds the reference voltage.

6. A programmable dynamic load testing system for a power management chip, the programmable dynamic load testing system comprising a test machine, wherein the control component of the test machine integrates a programmable dynamic load testing circuit according to any one of claims 1-5, characterized in that, The testing machine is equipped with a user interface. The user interface is connected to the programmable logic unit and is used to receive external control signals to dynamically configure the parameters of each of the at least two pulse width modulators, select the operating mode of the frequency synthesizer, and set the threshold of the protection circuit; wherein, The frequency synthesizer operates in two modes: waveform synthesis mode and digital signal synthesis mode. In the waveform synthesis mode, the frequency synthesizer performs logical superposition or arithmetic operations on the at least two pulse signals in the time domain; In the digital signal synthesis mode, the frequency synthesizer uses the at least two pulse signals as digital control words and generates the composite signal by processing them through inverse fast Fourier transform.

7. A programmable dynamic load testing method for power management chips, characterized in that, The programmable dynamic load testing method includes: Provides programmable logic units; Pulse signals with their respective frequencies and / or duty cycles are generated by at least two pulse width modulators integrated within the programmable logic unit. The frequency synthesizer integrated within the programmable logic unit receives and synthesizes at least two pulse signals generated by the at least two pulse width modulators to generate a composite synthesized signal, which is a nonlinear load waveform signal including multi-frequency modulation components. The composite signal is filtered to generate a driving signal; The power semiconductor switch is driven by the drive signal through the output controller and driver, and the dynamic load current is output to the power management chip under test.

8. The programmable dynamic load testing method according to claim 7, characterized in that, The frequency synthesizer employs a waveform synthesis mode to perform logical superposition or arithmetic operations on the at least two pulse signals in the time domain to generate the composite signal.

9. The programmable dynamic load testing method according to claim 7, characterized in that, The frequency synthesizer uses a digital signal synthesis mode, taking the at least two pulse signals as digital control words and generating the composite signal after processing by inverse fast Fourier transform.

10. The programmable dynamic load testing method according to claim 7, characterized in that, The programmable dynamic load test method also includes real-time monitoring of the dynamic load current, and when the dynamic load current is detected to exceed a preset threshold, cutting off the drive signal to protect the circuit. The dynamic load current is a nonlinear load waveform that includes multi-frequency modulation components.

11. The programmable dynamic load testing method according to claim 10, characterized in that, The step of real-time monitoring of the dynamic load current includes: The current flowing through the power semiconductor switch is sampled by a sampling resistor and converted into voltage; The voltage is amplified and then compared with a reference voltage. When the amplified voltage exceeds the reference voltage, overcurrent protection is triggered.

12. The programmable dynamic load testing method according to any one of claims 7-11, characterized in that, In the at least two pulse signals output by the at least two pulse width modulators, Different pulse width modulators may output the same or different frequencies. Different pulse width modulators may output the same or different duty cycles.

13. The programmable dynamic load testing method according to claim 7, characterized in that, Before the at least two pulse width modulators generate pulse signals with their respective frequencies and / or duty cycles, the programmable dynamic load testing method further includes: Collect load current data of the power management chip under test in the working scenario; The load current data is analyzed to determine the target area where the transient rate of change of current and / or the current amplitude exceeds a preset threshold. The target region is marked as the worst-case region, and the target frequency and target duty cycle are extracted from the worst-case region. The frequency and duty cycle of each pulse width modulator are configured according to the target frequency and the target duty cycle.

14. The programmable dynamic load testing method according to claim 13, characterized in that, At least three pulse width modulators are integrated within the programmable logic unit. The at least three pulse width modulators are not bundled together, and each pulse signal generated by the at least three pulse width modulators corresponds to an independent load source. After the frequency synthesizer generates the composite signal and before the filtering process, the programmable dynamic load testing method further includes: The function generator integrated within the programmable logic unit receives the composite signal, reproduces the load waveform characteristics of the worst-case region based on the composite signal, and outputs it, so that the power semiconductor switch outputs a dynamic load current that reproduces the load conditions of the worst-case region.

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