An LCD drive chip interface compatibility test system and method

Abstract

The application discloses an LCD drive chip interface compatibility test system and method, and relates to the field of electric variable measurement.The system comprises an upper computer control module, a communication module, an FPGA interface behavior modeling module, a signal generation and output module, and a feedback and closed-loop evaluation module.The FPGA interface behavior modeling module is used for mapping test parameters into hardware control signals;the signal generation and output module generates non-ideal excitation signals with timing, electrical and analog electromagnetic disturbance characteristics accordingly, and physically outputs the signals to the measured chip;and the feedback and closed-loop evaluation module collects bottom layer feedback data and executes automatic determination and dynamic adjustment of test parameters.The application truly restores harsh electromagnetic working conditions, realizes high-precision, full-automatic multi-dimensional closed-loop extraction of chip interface limit electrical tolerance boundaries, and improves evaluation efficiency.

Description

Technical Field

[0001] This invention relates to the field of electrical variable measurement technology, and specifically to an LCD driver chip interface compatibility testing system and method. Background Technology

[0002] In the field of integrated circuit testing and electrical variable measurement technology, timing integrity and electrical characteristic testing of high-speed digital interfaces of semiconductor chips is a core means of quantitatively evaluating the physical reliability of electronic circuits. In recent years, with the rapid development of intelligent cockpits in new energy vehicles, in-vehicle multi-screen interactive systems have placed extremely high demands on the data transmission bandwidth and physical reliability of LCD driver chips. However, in the actual engineering application environment of new energy vehicles, due to the extremely harsh electromagnetic environment inside the vehicle (such as high-frequency switching noise of motor inverters and electromagnetic coupling of high-voltage battery packs), and the fact that in-vehicle display terminals usually need to be connected to domain controllers via long-distance cables (such as several meters long LVDS or in-vehicle high-speed serial harnesses), high-speed electrical signals inevitably experience severe electromagnetic coupling, impedance mismatch, and waveform distortion on the physical link.

[0003] The non-ideal electrical characteristics exhibited in automotive-grade applications manifest in several ways: long cable transmission leads to fixed or dynamic timing offsets between clock and data signals, and severe phase imbalances between differential interface transistors. Simultaneously, transient voltage fluctuations (such as transient voltage pulses and power supply ripple interference) generated by the vehicle's electrical network during rapid acceleration or energy recovery operations cause extreme instability in the output signal's voltage amplitude, drive capability, and edge rate under dynamic operating conditions. Furthermore, complex electromagnetic interference (EMI) in automotive applications often induces random or periodic jitter in high-speed electrical signal links. To address these stringent physical transmission link challenges, automotive-grade LCD driver chips (meeting standards such as AEC-Q100) must possess extremely high electrical redundancy and signal integrity (SI) tolerance.

[0004] However, traditional electrical variable measurement and chip testing equipment has revealed significant engineering shortcomings when dealing with the extreme tolerance testing of automotive chips:

[0005] First, existing testing equipment typically only supports the output of idealized electrical excitation signals with regular waveforms, lacking hardware circuit modulation methods to dynamically inject simulated transient ripples of the vehicle power grid and high-frequency EMI jitter of long cables into the physical electrical signal, thus failing to truly reproduce the harsh electromagnetic environment of the vehicle.

[0006] Second, the signal generation unit and electrical parameter adjustment circuit of traditional test benches are isolated from each other, making it impossible to achieve multi-dimensional linkage adjustment of interface time characteristic parameters and electrical characteristic parameters, and making it difficult to simulate the extreme boundary conditions of multiple physical quantities intertwined under the complex working conditions of new energy vehicles.

[0007] Third, the testing process usually relies on external oscilloscopes for manual waveform capture or static error logs for post-event analysis. It lacks a real-time physical closed-loop and fully automatic judgment mechanism based on the feedback of the underlying electronic circuit status, which cannot meet the high-throughput and high-reliability automated verification requirements of automotive-grade chips.

[0008] Fourth, due to the lack of an adaptive electrical parameter scanning strategy, existing technologies cannot efficiently and accurately quantify and extract the one-dimensional tolerance range and two-dimensional multi-dimensional stable working area boundary of the vehicle drive chip interface within a complex electrical variable coordinate space. This severely restricts the evaluation efficiency and accuracy of the localization substitution of core display components for new energy vehicles.

[0009] In summary, existing circuit testing technologies cannot effectively simulate the non-ideal electrical parameter distortion characteristics of the time and electrical domains intertwined in the real physical environment of new energy vehicles, nor can they achieve automated closed-loop quantitative measurement of the extreme electrical tolerance area of ​​automotive-grade chips. This directly limits the efficiency and accuracy of electrical redundancy evaluation of automotive display chips under complex electromagnetic and process fluctuation environments. Summary of the Invention

[0010] In view of this, one of the objectives of the present invention is to provide an LCD driver chip interface compatibility testing system to solve the problems mentioned in the background art.

[0011] The second objective of this invention is to provide a method for testing the interface compatibility of an LCD driver chip.

[0012] To achieve the aforementioned primary objective, the present invention provides the following technical solution:

[0013] An LCD driver chip interface compatibility testing system includes:

[0014] The host computer control module is used to configure test parameters and scanning strategies. The test parameters include interface parameters, time characteristic parameters, electrical characteristic parameters, and disturbance parameters.

[0015] The communication module is connected to the host computer control module;

[0016] The FPGA interface behavior modeling module is connected to the host computer control module through the communication module, and is used to map the test parameters into corresponding hardware control signals;

[0017] The signal generation and output module is connected to the FPGA interface behavior modeling module and is used to generate a test excitation signal with set timing characteristics, set electrical characteristics and set disturbance characteristics according to the hardware control signal, and physically output the test excitation signal to the LCD driver chip under test.

[0018] The feedback and closed-loop evaluation module is connected to the LCD driver chip under test and the communication module, respectively. It is used to collect the hardware feedback data output by the LCD driver chip under test in response to the test excitation signal, perform automatic judgment based on the hardware feedback data, dynamically adjust the test parameters according to the scanning strategy, and transmit the extracted tolerance evaluation results to the host computer control module via the communication module.

[0019] By adopting the above technical solution, the present invention will have the following beneficial effects:

[0020] I. Significantly improves the simulation fidelity of test excitation signals, effectively reproducing the complex electromagnetic operating conditions of new energy vehicles. Based on the cascaded architecture of the FPGA interface behavior modeling module and the signal generation and output module, this system can accurately convert the test parameters configured by the host computer control module into test excitation signals with set timing characteristics, set electrical characteristics, and set disturbance characteristics, and then physically output the test excitation signals. This overcomes the limitation of traditional test equipment that can only output ideal waveforms, and can realistically simulate the non-ideal electrical distortions under the long cable transmission and high-voltage coupling environments of new energy vehicles. It provides highly matched hardware excitation support for accurately evaluating the signal integrity of the tested LCD driver chip under harsh application scenarios.

[0021] Second, it achieves multi-dimensional coordinated adjustment of composite test parameters, adapting to on-board dynamic limit boundary testing. Global test parameters, including interface parameters, time characteristic parameters, electrical characteristic parameters, and disturbance parameters, are centrally configured through the host computer control module and transmitted to the FPGA interface behavior modeling module via the communication module, uniformly mapped to corresponding hardware control signals. This changes the traditional technical situation where signal generation units and electrical parameter adjustment circuits are isolated from each other. This mechanism can synchronously interweave multiple characteristic distortions on the same physical link, fully meeting the multi-physical quantity coupling test requirements of new energy vehicles under dynamic operating conditions, and providing a multi-dimensional system-level verification method for quantitatively evaluating interface electrical redundancy.

[0022] Third, a fully automated test closed loop based on underlying hardware-in-the-loop (HIL) was constructed, improving the efficiency and objectivity of tolerance boundary evaluation. The system utilizes a feedback and closed-loop evaluation module to collect hardware feedback data output by the tested LCD driver chip in response to the test stimulus signal in real time, and directly performs automatic judgment based on this hardware feedback data. Based on the judgment result, the system dynamically adjusts the test parameters in the underlying path according to a preset scanning strategy, triggering the next round of stimulus output locally. This automatic hardware iteration mechanism eliminates the reliance on manual waveform observation or post-event log analysis, significantly improving the execution efficiency and objectivity of interface tolerance extraction, and highly aligning with the industry demand for high-throughput and high-reliability verification of core display components in new energy vehicles.

[0023] To achieve the second objective mentioned above, the present invention also provides a testing method for the aforementioned LCD driver chip interface compatibility testing system, comprising the following steps:

[0024] S1: The host computer control module configures the test parameters and scanning strategy. The test parameters include interface parameters, time characteristic parameters, electrical characteristic parameters, and disturbance parameters.

[0025] S2: The host computer control module sends the configured test parameters to the FPGA interface behavior modeling module through the communication module;

[0026] S3: The FPGA interface behavior modeling module performs interface signal behavior modeling based on the received test parameters, and generates corresponding hardware control signals through the internal timing adjustment submodule, electrical characteristic adjustment submodule and disturbance injection submodule.

[0027] S4: The signal generation and output module generates a test excitation signal that conforms to the set timing characteristics, set electrical characteristics and set disturbance characteristics according to the hardware control signal, and physically outputs it to the LCD driver chip under test.

[0028] S5: The LCD driver chip under test processes the input test stimulus signal and outputs hardware feedback data, which includes CRC check value, data check code, status register status or error flag.

[0029] S6: The feedback and closed-loop evaluation module obtains the hardware feedback data and performs automatic judgment;

[0030] S7: The feedback and closed-loop evaluation module dynamically adjusts the test parameters according to the scanning strategy based on the automatic judgment result, and internally routes the adjusted test parameters to the FPGA interface behavior modeling module via the communication module to trigger the repeated execution of steps S3 to S6 until the parameter scan is completed. Then, the one-dimensional tolerance range or two-dimensional stable region of the LCD driver chip under test is extracted and output to the host computer control module via the communication module. Attached Figure Description

[0031] Figure 1 This is a general structural diagram of the LCD driver chip interface compatibility testing system according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the multi-dimensional tolerance region of the interface extracted in an embodiment of the present invention;

[0033] Figure 3 This is a flowchart of the LCD driver chip interface compatibility testing method according to an embodiment of the present invention.

[0034] The correspondence between the icon labels and component names in the diagram is as follows:

[0035] 1. Host computer control module; 2. Communication module; 3. FPGA interface behavior modeling module; 31. Interface parameter modeling unit; 32. Timing adjustment submodule; 33. Electrical characteristic adjustment submodule; 34. Disturbance injection submodule; 35. Test stimulus data generation unit; 36. Interface output control and buffering unit; 4. Signal generation and output module; 5. LCD driver chip under test; 6. Feedback and closed-loop evaluation module; 61. Feedback data acquisition unit; 62. Automatic judgment unit; 63. Tolerance evaluation unit. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] like Figure 1 As shown, this embodiment provides an LCD driver chip interface compatibility testing system. This system constructs a closed-loop test circuit using physical hardware entities to perform high-precision timing and electrical limit tolerance tests on the LCD driver chip 5 under test. Specifically, the system includes the following hardware modules connected via electrical signals or a data bus:

[0038] The host computer control module 1 is typically implemented using an industrial control computer or a high-performance general-purpose computer, running configuration and analysis control software to achieve global test control. The host computer control module 1 is mainly used to configure test parameters and scanning strategies, including interface parameters, time characteristic parameters, electrical characteristic parameters, and disturbance parameters.

[0039] The communication module 2 serves as a data interaction bridge between the host computer control module 1 and the underlying hardware. It is typically implemented using a USB 3.0 interface circuit, a UART serial bus circuit, or a PCIe bus interface card to achieve handshaking between signals, data packaging, data parsing, and real-time interaction.

[0040] The FPGA interface behavior modeling module 3 is composed of a high-clock-frequency field-programmable gate array (FPGA) chip. The FPGA interface behavior modeling module 3 is connected to the host computer control module 1 via the communication module 2, and is used to receive the test parameters and, within the programmable logic, precisely map the test parameters to corresponding hardware control signals through specific firmware configuration logic.

[0041] The signal generation and output module 4 consists of a high-speed digital interface circuit, a digitally controlled voltage regulation circuit, a high-speed digital-to-analog converter (DAC), and an impedance matching network, and is connected to the FPGA interface behavior modeling module 3. The signal generation and output module 4 is used to generate test excitation signals with set timing characteristics, set electrical characteristics, and set disturbance characteristics according to the hardware control signals, and physically outputs the test excitation signals to the input pins of the LCD driver chip 5 under test.

[0042] The feedback and closed-loop evaluation module 6 is connected to the LCD driver chip 5 under test and the communication module 2, respectively, thereby constructing a fully automated iterative test closed loop for the underlying hardware-in-the-loop. Figure 1 As shown, the feedback and closed-loop evaluation module 6 is further subdivided into a cascaded feedback data acquisition unit 61, an automatic judgment unit 62, and a tolerance evaluation unit 63. The feedback and closed-loop evaluation module 6 is used to capture in real time the hardware feedback data output by the tested LCD driver chip 5 in response to the test stimulus signal through the feedback data acquisition unit 61, and the automatic judgment unit 62 performs automatic judgment. During the closed-loop iterative test, the tolerance evaluation unit 63 dynamically calculates and adjusts the test parameters according to the scanning strategy, and routes the adjusted test parameters directly to the FPGA interface behavior modeling module 3 via the underlying control path of the communication module 2 to trigger the next round of stimulus output. After completing the global parameter scan, the tolerance evaluation unit 63 transmits the extracted final tolerance evaluation result back to the host computer control module 1 via the communication module 2 for display and analysis.

[0043] like Figure 1 As shown, this embodiment provides clear and specific structural constraints regarding the physical topology and signal flow connections of each unit and sub-module within the FPGA interface behavior modeling module 3. Its hardware architecture adopts a parallel distribution topology based on a programmable logic bus.

[0044] First, at the control level coupling, the signal input terminal of the interface parameter modeling unit 31 is connected to the host computer control module 1 via the communication module 2 to receive higher-level test parameters. The internal programmable logic bus of the interface parameter modeling unit 31 extends outwards to four independent control output pins, which are cascaded point-to-point to the register control input terminals of the timing adjustment submodule 32, the electrical characteristic adjustment submodule 33, the disturbance injection submodule 34, and the test excitation data generation unit 35, respectively. Through this structure, the interface parameter modeling unit 31 can distribute the parsed and mapped low-level hardware control signals (such as control words or enable levels) in parallel to each submodule, enabling independent configuration of each electrical variable.

[0045] Secondly, in the signal flow cascading, the clock / data phase shift output of the timing adjustment submodule 32, the voltage / drive configuration output of the electrical characteristic adjustment submodule 33, the noise superposition output of the disturbance injection submodule 34, and the original protocol packaged data output of the test stimulus data generation unit 35 converge backward on the programmable routing layer inside the FPGA and are physically connected to the corresponding signal input of the interface output control and buffer unit 36 ​​respectively.

[0046] Finally, the signal output terminal of the interface output control and buffer unit 36 ​​serves as the physical output pin of the entire FPGA interface behavior modeling module 3, spanning the FPGA chip boundary and physically connected to the external signal generation and output module 4 through the PCB controlled impedance trace network.

[0047] 1. Interface parameter modeling unit 31 and test stimulus data generation unit 35

[0048] The interface parameter modeling unit 31 includes a time domain model, an electrical domain model, and a disturbance model. It receives test parameters input from the communication module 2 and decomposes them into discrete configuration words for each hardware channel. The test stimulus data generation unit 35 is responsible for generating standard test stimulus data sequences (e.g., pseudo-random bit sequences conforming to a specific display resolution) and encapsulating them using interface protocols (e.g., encapsulating them as TTL timing protocol or LVDS differential protocol signals).

[0049] 2. Timing Adjustment Submodule 32

[0050] To create extremely small timing offsets on the test stimulus signal, timing adjustment submodule 32 employs three physical hardware circuit implementations:

[0051] Programmable delay unit: Using the IODELAY primitive inside the FPGA, the delay chain level can be configured to achieve independent and fine delay control of each data channel, with an adjustment range of -50ns to +50ns and a resolution of 5ps or 10ps.

[0052] Phase adjustment unit: Using a phase-shifted phase-locked loop (PLL) or a mixed-mode clock manager (MMCM), the clock signal is finely phase-adjusted from 0° to 360° to simulate timing inconsistencies between the clock and data channels.

[0053] Clock Reconstruction Unit: Dynamically changes the synthesized frequency of the clock to generate timing offset excitation under different frequency operating conditions.

[0054] The timing adjustment submodule 32 is used to adjust the multi-channel relative time delay and clock phase of the test excitation signal according to the hardware control signal, thereby physically adjusting the fixed or dynamic timing offset between the clock and data signals of the TTL interface or LVDS interface, the relative delay between data channels, and the phase offset between LVDS channels.

[0055] 3. Electrical characteristic adjustment submodule 33

[0056] Electrical characteristic adjustment submodule 33 is used to adjust the voltage amplitude, drive capability, edge rate, differential swing, or common-mode voltage of the test excitation signal according to the hardware control signal:

[0057] For the TTL interface: the electrical characteristic adjustment submodule 33 is equipped with an IO voltage configuration circuit, a drive capability adjustment circuit, and an edge rate control circuit. It utilizes the FPGA's programmable I / O standard configuration circuit to control the output voltage amplitude (physically switching between 1.8V / 2.5V / 3.3V); by adjusting the programmable output drive current control circuit, it changes the output drive capability (e.g., 4mA / 8mA / 12mA); and by controlling the I / O port's rise / falling edge slope control circuit (SLEW attribute), it switches the edge rate between Fast (steep edge) and Slow (flat edge).

[0058] For the LVDS interface: the electrical characteristic adjustment submodule 33 is equipped with a differential swing adjustment circuit, a common-mode voltage adjustment circuit, and a channel consistency adjustment circuit. It controls the constant current source bias current of the differential driver chip to adjust the differential swing (continuously adjustable between 200mV and 400mV); controls the DC component of the differential line end adder circuit to adjust the common-mode voltage (dynamically offset between 1.0V and 1.4V); and simultaneously, artificially creates an imbalance in the positive and negative voltage amplitudes between the transistors through the channel consistency adjustment circuit.

[0059] 4. Disturbance Injection Submodule 34

[0060] The disturbance injection submodule 34 is used to inject time-domain and voltage-domain disturbances into the test excitation signal according to the hardware control signal, so that it has dynamic instability characteristics to more closely resemble the actual system environment.

[0061] Time-domain perturbation injection includes random jitter injection (such as dynamically mixing Gaussian jitter in the range of ±100ps into the delay chain using high-speed modulation noise) and periodic jitter injection (such as mixing in sine or square wave jitter).

[0062] Voltage domain disturbance injection: This includes voltage fluctuation injection (such as adjustable LDO power supply at the control signal output terminal, superimposing frequency-controlled ripple on the high-speed output level to simulate the transient ripple of the vehicle power grid generated by the high-voltage battery pack and motor controller of new energy vehicles under rapid acceleration conditions), physical injection of ±5% power supply noise fluctuation and drive change injection (such as dynamic attenuation of drive capability).

[0063] 5. Interface output control and buffer unit 36

[0064] The interface output control and buffer unit 36 ​​is connected to the signal generation and output module 4. It uses physical hard primitives (such as ODDR toggle triggers and OBUF output buffers) to enable, map, and match the raw parallel / serial data after the above processing, and finally outputs it to the LCD driver chip 5 under test through controlled physical printed circuit board (PCB) traces.

[0065] like Figure 1 As shown in the figure, this embodiment specifically demonstrates how the feedback data acquisition unit 61, automatic judgment unit 62 and tolerance evaluation unit 63 inside the feedback and closed-loop evaluation module 6 realize the extraction of the fully automatic tolerance area.

[0066] 1. Physical data capture of feedback data acquisition unit 61

[0067] When the LCD driver chip 5 under test is excited by a test stimulus signal with non-ideal characteristics, its internal digital processing circuit performs decoding. The feedback data acquisition unit 61 reads and captures the hardware feedback data output by the LCD driver chip 5 under test in real time through a physical general-purpose serial interface bus (such as an SPI / I²C bus network) or a dedicated error pin of the chip. The hardware feedback data specifically includes: CRC check value, data check code, status register status or error flag.

[0068] 2. Compliance of the automatic judgment unit 62

[0069] The input of the automatic judgment unit 62 is cascaded to the output of the feedback data acquisition unit 61. The automatic judgment unit 62 performs the following compliance automatic judgment limits based on the returned hardware feedback data: when the CRC checksum is correct and no error flag is triggered, the automatic judgment unit 62 determines the test result under the current technical parameters to be normal (PASS); when the CRC checksum is incorrect, or the status register inside the tested LCD driver chip 5 is set with an error flag, or a timeout occurs without response, the automatic judgment unit 62 determines the current test result to be failed (FAIL). Simultaneously, the automatic judgment unit 62 also supports extended multi-frame error status statistics and error rate threshold determination.

[0070] 3. Adaptive scanning and multidimensional region extraction of tolerance assessment unit 63

[0071] The signal input terminal of the tolerance evaluation unit 63 is cascaded to the test result output terminal of the automatic judgment unit 62, and its data output terminal is physically connected to the host computer control module 1 through the communication module 2. The tolerance evaluation unit 63 is used to respond in real time to the PASS / FAIL status update signal issued by the automatic judgment unit 62, and in the underlying hardware loop-in-the-loop, it automatically executes the adaptive scanning mechanism and the multi-dimensional joint scanning mechanism to quantify and extract the limit tolerance boundary of the LCD driver chip 5 under test.

[0072] Specifically, the adaptive scanning mechanism and the multidimensional joint scanning mechanism are executed collaboratively within the tolerance evaluation unit 63 using a multi-layer nested loop control architecture. The adaptive scanning mechanism, as the inner-layer state iteration control, performs adaptive variable-step-size boundary fine-tuning on a single-dimensional parameter path; the multidimensional joint scanning mechanism, as the outer-layer control architecture, drives cross-dimensional step transitions of electrical parameters, thereby jointly constructing... Figure 2 The multidimensional orthogonal electrical parameter coordinate matrix is ​​shown.

[0073] (1) Inner layer iteration: Hardware variable step size execution logic of adaptive single-dimensional parameter scanning mechanism

[0074] In a fixed-dimensional section of a multidimensional orthogonal electrical parameter coordinate matrix (e.g., a fixed operating voltage of 2.8V, with only a one-dimensional scan of timing offset parameters), the inner-layer state iteration control is entirely driven by an adaptive scanning mechanism. Based on the current real-time automatic judgment result, the adaptive scanning mechanism dynamically switches the test step size within the time domain or electrical operating space. Its specific hardware switching logic is defined as follows:

[0075] First test step (coarse scan state): When the automatic judgment unit 62 consistently outputs a "test passed" (PASS) result for the current test point, it indicates that the LCD driver chip 5 under test is within the stable operating region. At this time, the tolerance evaluation unit 63 controls the system to maintain the first test step (a relatively large step, for example, a step size configured as 500ps) and rapidly increase it. Through this coarse scan state, the system can quickly skip the central redundant region without technical disputes with extremely high test throughput, significantly shortening the global traversal time.

[0076] Second test step (fine scan state): When the system advances to a certain test point, and the automatic judgment unit 62 detects the first error in the CRC check value in the hardware feedback data, or the first error flag set in the status register (i.e., a sudden change from PASS to FAIL), thus determining that the test point has entered the boundary region, the state machine inside the tolerance evaluation unit 63 immediately generates an interrupt and transitions to the fine scan state on the spot. At this time, the fully automatic control system of the tolerance evaluation unit 63 reduces the scan step size to the second test step size (a small step size, for example, the step size is automatically tightened to 50ps), and performs a high-density fine physical scan near the current critical point. Through this fine scan state, the system can accurately lock the boundary coordinates of the limit tolerance boundary with extremely high geometric resolution.

[0077] (2) Outer nesting: Spatiotemporal superposition and matrix traversal logic of multidimensional joint scanning mechanism

[0078] To fully extract the multidimensional tolerance profile spanning the time, electrical, and disturbance domains, the multidimensional joint scanning mechanism, based on the aforementioned inner-layer single-dimensional adaptive scanning, drives the coordinated response of multi-channel hardware through an outer-layer nested loop. Its specific spatiotemporal superposition and matrix traversal logic is defined as follows:

[0079] Spatial decoupling distribution of multidimensional discrete control words: The outer nested loop uses the set benchmark sequence period as the synchronization beat. When a multidimensional joint scan is started (such as a two-dimensional joint scan of timing offset and operating voltage, or a multidimensional joint scan of timing offset, jitter amplitude, and voltage ripple), the tolerance evaluation unit 63 converts the current multidimensional coordinate point (e.g., the current timing offset on the X-axis and the current operating voltage value on the Y-axis) into multiple spatially decoupled low-level hardware control words with different electrical dimensions.

[0080] Synchronous spatiotemporal superposition operation at the hardware layer: The underlying hardware control word is sent in parallel to the interface parameter modeling unit 31 via the communication module 2. On the same hardware clock plane, the interface parameter modeling unit 31 cascades and maps the first-dimensional control word to the timing adjustment submodule 32, controlling the programmable delay unit to change the physical circuit delay; simultaneously, it cascades and maps the second-dimensional control word to the electrical characteristic adjustment submodule 33, controlling the IO voltage configuration circuit to change the physical numerically controlled voltage amplitude; or it cascades and maps the third-dimensional control word to the disturbance injection submodule 34, controlling the superposition of physical noise. This ensures that the test excitation signal ultimately physically output by the signal generation and output module 4 to the LCD driver chip 5 under test synchronously carries multi-dimensional interleaved non-ideal distortion characteristics on the same physical link.

[0081] Cross-dimensional step transition and boundary extraction: After the inner loop completes the adaptive fine detection of the single-dimensional boundary in the current outer coordinate, it triggers the state reversal of the outer nested loop. The outer nested loop drives the electrical parameters of another dimension to cross a set step (e.g., increasing the operating voltage from 2.8V to 2.9V), and then triggers the inner loop again to re-execute the aforementioned adaptive variable step size scan on the new voltage profile.

[0082] (3) Tolerance envelope extraction and graphical rendering

[0083] During the aforementioned iteration process, the dynamic adjustment of test parameters by the feedback and closed-loop evaluation module 6 (specifically executed by the tolerance evaluation unit 63) does not require software intervention from the host computer control module 1. The tolerance evaluation unit 63 outputs the dynamically calculated updated test parameters to the communication module 2 in real time. The communication module 2 is internally configured with a low-level hardware routing control circuit (or local bus bridging logic). After receiving the updated test parameters, it does not send a software interrupt or bus request to the host computer control module 1. Instead, it directly writes the parameters into the configuration register of the FPGA interface behavior modeling module 3 with low hardware latency through the internal routing mechanism, thereby triggering repeated iterations of the inner or outer loop locally.

[0084] After the tolerance evaluation unit 63 completes the boundary approximation tracking of the entire multidimensional orthogonal electrical parameter coordinate matrix through a multi-layer nested loop, its internally integrated data encapsulation logic binds and stores the judgment state (PASS / FAIL) at each coordinate point with the hardware coordinates. The programmable logic of the tolerance evaluation unit 63 further performs envelope calculation and surface fitting on the stored set of closed critical boundary coordinates, thereby quantifying and extracting the one-dimensional tolerance range of the tested LCD driver chip 5 interface, and so on. Figure 2 The diagram shows the closed boundary of the two-dimensional stable region spanning the time and electrical domains. This complete beneficial tolerance assessment result is finally uploaded to the host computer control module 1 via communication module 2 after the scan is completed, allowing the client to perform highly visualized graphical output and chip redundancy evaluation.

[0085] like Figure 3 As shown, this embodiment also provides a method for testing the interface compatibility of an LCD driver chip based on the above-described physical system, which guides the specific physical testing process. The specific implementation steps include:

[0086] Step S1: The host computer control module 1 configures the test parameters and scanning strategy. The test parameters include interface parameters, time characteristic parameters, electrical characteristic parameters and disturbance parameters.

[0087] Those skilled in the art should understand that the "configuration" of the scanning strategy by the host computer control module 1 is limited to static parameter initialization and rule preset before test start; while the "dynamic adjustment" of the test parameters by the feedback and closed-loop evaluation module 6 (specifically executed by its internal tolerance evaluation unit 63) is limited to real-time closed-loop hardware feedback control during test operation. In the hardware-in-the-loop cycle, the tolerance evaluation unit 63 reads and, based on the scanning strategy rules pre-configured and issued by the host computer control module 1, automatically and locally switches between the first and second test step sizes according to the current PASS / FAIL judgment state. This allows for adaptive adjustment of closed-loop scanning parameters directly by the underlying hardware without the need for frequent interruption or reconfiguration commands from the host computer software layer. This "high-level configuration of rules, low-level dynamic execution" hardware-software collaborative architecture ensures the overall controllability of the test system and greatly improves the physical closed-loop response speed of extreme tolerance boundary measurements.

[0088] Step S2: The host computer control module 1 sends the configured test parameters to the FPGA interface behavior modeling module 3 through the communication module 2.

[0089] Step S3: The FPGA interface behavior modeling module 3 models the interface signal behavior based on the received test parameters, and performs hardware actions through the internal timing adjustment submodule 32, electrical characteristic adjustment submodule 33 and disturbance injection submodule 34 to generate corresponding hardware control signals.

[0090] Step S4: The signal generation and output module 4 generates a test excitation signal that conforms to the set timing characteristics, set electrical characteristics and set disturbance characteristics according to the hardware control signal, and physically outputs it to the LCD driver chip 5 under test.

[0091] Step S5: The LCD driver chip 5 under test processes the input test excitation signal and outputs hardware feedback data, which includes CRC check value, data check code, status register status or error flag.

[0092] Step S6: The feedback data acquisition unit 61 inside the feedback and closed-loop evaluation module 6 acquires the hardware feedback data, and the automatic judgment unit 62 performs automatic judgment to obtain the normal or abnormal test status result.

[0093] Step S7: The feedback and closed-loop evaluation module 6 dynamically adjusts the test parameters according to the scanning strategy based on the automatic judgment result, and internally routes the adjusted test parameters to the FPGA interface behavior modeling module 3 via the communication module 2 to trigger the system to automatically repeat steps S3 to S6. This hardware loop runs automatically at the bottom layer until the parameter scan is completed. Then, the tolerance evaluation unit 63 inside the feedback and closed-loop evaluation module 6 extracts the interface tolerance and outputs the one-dimensional tolerance range or two-dimensional stable region of the tested LCD driver chip 5 to the host computer control module 1 via the communication module 2.

[0094] To further verify the effectiveness and accuracy of the testing system described in this invention, four specific test scenario examples are provided below under different interface and scanning strategy conditions:

[0095] Example 1. Compatibility test of TTL interface with clock disturbance in vehicle-mounted long cable transmission environment.

[0096] In this embodiment, the reference operating frequency of the LCD driver chip 5 under test is limited to 65MHz in the test scheme configuration. In the time characteristic parameters configured by the host computer control module 1, the timing offset scan range between the clock signal and the data signal is set to ±2ns. After receiving the corresponding hardware control signal, the disturbance injection submodule 34 simulates complex automotive electromagnetic interference (EMI) and physically injects random jitter with an amplitude of ±100ps into the clock signal. The signal generation and output module 4 generates and outputs the corresponding test excitation signal. The hardware feedback data is collected in real time by the feedback data acquisition unit 61 and transmitted to the automatic judgment unit 62. After multiple rounds of scanning, the tolerance evaluation unit 63 finally extracts the one-dimensional tolerance range or stable operating region of the TTL interface that meets the PASS condition at a 65MHz operating frequency.

[0097] Example 2. Compatibility testing of LVDS interface and phase-locked loop capability

[0098] In this embodiment, the test scheme is configured with an LVDS interface. In the initial time characteristic parameters configured by the host computer control module 1, the relative phase offset between channels is artificially created and set to -3.5ns. The common-mode voltage adjustment circuit of the electrical characteristic adjustment submodule 33, according to the hardware control signal, causes the common-mode voltage of the output test excitation signal to dynamically change between 1.0V and 1.4V. The signal generation and output module 4 outputs a differential excitation signal with a fixed phase deviation of -3.5ns and dynamically changing common-mode voltage to the receiving pin of the LCD driver chip 5 under test. The feedback data acquisition unit 61 continuously reads data, and the automatic judgment unit 62 monitors the phase-locked loop (PLL) lock indicator bit in the internal status register of the LCD driver chip 5 under test, thereby allowing the tolerance evaluation unit 63 to verify with high precision the physical locking capability of the chip's internal PLL under non-ideal electrical and timing disturbance conditions.

[0099] Example 3. Adaptive Scan Test Based on Two-Level Step Size Switching

[0100] In this embodiment, the host computer control module 1 enables an adaptive scanning mechanism. After the test begins, when the tolerance evaluation unit 63 determines that it is currently within the stable working area, it controls the scanning parameters to perform a rapid coarse scan with a first test step size of 500 ps. When the automatic judgment unit 62 detects the first error in the CRC check value transmitted back by the feedback data acquisition unit 61, it determines that the test point has entered the boundary region and notifies the tolerance evaluation unit 63. At this time, in response to this determination, the tolerance evaluation unit 63 controls the system to automatically reduce the scanning step size to a second test step size of 50 ps and perform a high-density fine scan near the critical point, quickly and extremely accurately extracting the coordinates of the limit tolerance boundary.

[0101] Example 4. Joint scanning test in multidimensional parameter space

[0102] In this embodiment, the host computer control module 1 configures and initiates a multi-dimensional joint scanning mechanism. The system supports simultaneous collaborative cross-scanning of electrical parameters in two dissimilar dimensions within the same test sequence. In this embodiment, the selected joint scanning dual-dimensional parameters are specifically: timing offset parameter and interface output voltage amplitude parameter, which correspond to... Figure 2 The two-dimensional space test topology is shown. In each round of testing, the timing adjustment submodule 32 and the electrical characteristic adjustment submodule 33 adjust the physical excitation characteristics stepwise according to a two-dimensional coordinate matrix composed of two parameters. The feedback data acquisition unit 61 collects the hardware feedback data at each coordinate point, and the automatic judgment unit 62 projects the automatically judged PASS / FAIL result into a high-dimensional parameter space. The tolerance evaluation unit 63 finally extracts the complete stable working area boundary, and the host computer control module 1 prints it out as shown. Figure 2 The diagram shows the multidimensional tolerance and stable operating area of ​​the interface.

[0103] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An LCD driver chip interface compatibility testing system, characterized in that, include: The host computer control module (1) is used to configure test parameters and scanning strategies. The test parameters include interface parameters, time characteristic parameters, electrical characteristic parameters and disturbance parameters. The communication module (2) is connected to the host computer control module (1); The FPGA interface behavior modeling module (3) is connected to the host computer control module (1) through the communication module (2) and is used to map the test parameters into corresponding hardware control signals. The signal generation and output module (4) is connected to the FPGA interface behavior modeling module (3) and is used to generate a test excitation signal with set timing characteristics, set electrical characteristics and set disturbance characteristics according to the hardware control signal, and physically output the test excitation signal to the LCD driver chip under test (5). The feedback and closed-loop evaluation module (6) is connected to the LCD driver chip (5) under test and the communication module (2) respectively. It is used to collect the hardware feedback data output by the LCD driver chip (5) under test in response to the test excitation signal, and perform automatic judgment according to the hardware feedback data. It dynamically adjusts the test parameters according to the scanning strategy. The adjusted test parameters are directly internally routed to the FPGA interface behavior modeling module (3) through the underlying control path of the communication module (2) to trigger the next round of excitation output. After completing the global parameter scan, the extracted tolerance evaluation results are transmitted to the host computer control module (1) through the communication module (2).

2. The LCD driver chip interface compatibility testing system according to claim 1, characterized in that, The FPGA interface behavior modeling module (3) includes an interface parameter modeling unit (31), a timing adjustment submodule (32), an electrical characteristic adjustment submodule (33), a disturbance injection submodule (34), a test stimulus data generation unit (35), and an interface output control and buffering unit (36). The signal input terminal of the interface parameter modeling unit (31) is physically connected to the parameter output terminal of the host computer control module (1) via the communication module (2); the multiple control output terminals of the interface parameter modeling unit (31) are respectively connected point-to-point to the control input terminals of the timing adjustment submodule (32), the electrical characteristic adjustment submodule (33), the disturbance injection submodule (34) and the test stimulus data generation unit (35) for parallel distribution of the mapped underlying hardware control signals; the signal output terminals of the timing adjustment submodule (32), the electrical characteristic adjustment submodule (33), the disturbance injection submodule (34) and the test stimulus data generation unit (35) are collectively connected to the various signal input terminals of the interface output control and buffer unit (36); the signal output terminal of the interface output control and buffer unit (36) serves as the total output terminal of the FPGA interface behavior modeling module (3) and is physically connected to the input terminal of the signal generation and output module (4).

3. The LCD driver chip interface compatibility testing system according to claim 2, characterized in that, The timing adjustment submodule (32) includes a programmable delay unit, a phase adjustment unit and a clock reconstruction unit, which are used to physically adjust the fixed or dynamic timing offset between the clock and data signals of the TTL interface or LVDS interface, the relative delay between data channels and the phase offset between LVDS channels.

4. The LCD driver chip interface compatibility testing system according to claim 2, characterized in that, The electrical characteristic adjustment submodule (33) is equipped with an IO voltage configuration circuit, a drive capability adjustment circuit and an edge rate control circuit for the TTL interface; and a differential swing adjustment circuit, a common mode voltage adjustment circuit and a channel consistency adjustment circuit for the LVDS interface.

5. The LCD driver chip interface compatibility testing system according to claim 2, characterized in that, The time-domain disturbances injected by the disturbance injection submodule (34) include random jitter injection and periodic jitter injection; the voltage-domain disturbances injected include voltage fluctuation injection and drive change injection.

6. The LCD driver chip interface compatibility testing system according to claim 1, characterized in that, The hardware feedback data collected by the feedback and closed-loop evaluation module (6) includes CRC check value, data check code, status register status or error flag; the automatic judgment rules include: when the CRC check value is correct, the feedback and closed-loop evaluation module (6) determines that the test is passed; when the CRC check value is incorrect or there is no response after timeout, the feedback and closed-loop evaluation module (6) determines that the test is failed.

7. The LCD driver chip interface compatibility testing system according to claim 1, characterized in that, The scanning strategy includes an adaptive scanning mechanism and a multi-dimensional joint scanning mechanism; wherein... The specific execution logic of the adaptive scanning mechanism is as follows: the feedback and closed-loop evaluation module (6) determines that the LCD driver chip (5) under test is in a stable working area based on the automatic judgment result, and controls the system to perform a fast scan with a first test step size; when the LCD driver chip (5) under test is in a critical boundary area, the system automatically reduces the scanning step size to a second test step size to perform a high-density fine scan. The multidimensional joint scanning mechanism is defined as follows: a multidimensional orthogonal electrical parameter coordinate matrix is ​​constructed internally by the feedback and closed-loop evaluation module (6), the adaptive scanning mechanism is used as the inner loop control, and cross-dimensional electrical parameter step transitions are executed in the outer loop nest.

8. A method for testing the interface compatibility of an LCD driver chip, applied to the LCD driver chip interface compatibility testing system as described in any one of claims 1 to 7, comprising the following steps: S1: The host computer control module (1) configures the test parameters and scanning strategy, including interface parameters, time characteristic parameters, electrical characteristic parameters and disturbance parameters; S2: The host computer control module (1) sends the configured test parameters to the FPGA interface behavior modeling module (3) through the communication module (2); S3: The FPGA interface behavior modeling module (3) performs interface signal behavior modeling based on the received test parameters, and generates corresponding hardware control signals through the internal timing adjustment submodule (32), electrical characteristic adjustment submodule (33) and disturbance injection submodule (34); S4: The signal generation and output module (4) generates a test excitation signal that conforms to the set timing characteristics, set electrical characteristics and set disturbance characteristics according to the hardware control signal, and physically outputs it to the LCD driver chip under test (5). S5: The LCD driver chip (5) under test processes the input test excitation signal and outputs hardware feedback data, which includes CRC check value, data check code, status register status or error flag. S6: The feedback and closed-loop evaluation module (6) obtains the hardware feedback data and performs automatic judgment; S7: The feedback and closed-loop evaluation module (6) dynamically adjusts the test parameters according to the scanning strategy based on the automatic judgment result, and internally routes the adjusted test parameters to the FPGA interface behavior modeling module (3) via the communication module (2) to trigger the repeated execution of steps S3 to S6 until the global parameter scan is completed. Then, the one-dimensional tolerance range or two-dimensional stable region of the LCD driver chip (5) under test is extracted and output to the host computer control module (1) via the communication module (2).

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