A multi-dimensional feature criterion-based hierarchical open-circuit fault diagnosis method and system for a hybrid seven-level inverter

Abstract

The present application relates to the technical field of inverter fault diagnosis, especially to a mixed seven-level inverter graded open-circuit fault diagnosis method and system based on multi-dimensional feature criterion. The method comprises collecting original signals; constructing a dynamic voltage reference model based on the failure assumption of H-bridge unit, including the establishment of a normal operation model of the mixed seven-level inverter, the calculation of the controlled reconstruction logic and the equivalent switch function, and the adaptive cancellation of the flying capacitor ripple based on the mapping of the measured variables; extracting diagnostic characteristic quantities based on the original signals and the dynamic voltage reference model; and fusing the diagnostic characteristic quantities based on the improved Transform network. The present application provides a graded open-circuit fault diagnosis method for the mixed seven-level inverter, which innovatively constructs a dynamic reference model based on fault assumption and introduces a feature criterion strategy. Experimental results prove that the method has high robustness and accuracy under wide regulation and low power factor conditions.

Description

Technical Field

[0001] This invention relates to the field of inverter fault diagnosis technology, and in particular to a hierarchical open-circuit fault diagnosis method and system for hybrid seven-level inverters based on multi-dimensional feature criteria. Background Technology

[0002] Multilevel inverters have been widely used in high-voltage, high-power applications such as photovoltaic grid-connected power generation, motor drives, and flexible DC transmission due to their advantages such as high output voltage waveform quality, low electromagnetic interference, and low switching losses. Among them, the hybrid seven-level inverter, which consists of a front-end T-type three-level converter and a rear-end H-bridge unit cascaded together, combines the high efficiency of the T-type topology with the modular advantages of the H-bridge unit. It can output more levels with fewer isolated DC power supplies and has become a research hotspot in the field of power electronics in recent years.

[0003] However, hybrid seven-level inverters contain a large number of power switching devices (a single phase typically includes eight switching transistors and corresponding anti-parallel diodes). This increased system complexity significantly raises the probability of power device failures. Among these, open-circuit faults in the power switching transistors are one of the most common types of failure. Although open-circuit faults do not cause instantaneous system damage like short-circuit faults, they can lead to output voltage waveform distortion, DC-side capacitor voltage imbalance, and increased current harmonic content. If not detected promptly and appropriate fault-tolerant strategies are not implemented, this can result in severe system performance degradation and even secondary faults.

[0004] Currently, open-circuit fault diagnosis methods for multilevel inverters are mainly divided into signal analysis-based methods and model-based methods.

[0005] Signal analysis-based methods (such as the current-parking method and the current-average method) locate faults by analyzing the current characteristics after a fault occurs. These methods do not require precise system parameters, but they are slow to diagnose. Furthermore, under low-power or low-power-factor conditions, fault characteristics can be masked or significantly attenuated due to load current lag and dead-zone effects near zero-crossing points, easily leading to misdiagnosis or missed diagnosis. In addition, for hybrid topologies, fault characteristics from different modules (such as the T-type section and the H-bridge section) exhibit severe coupling and aliasing in the current domain, making accurate fault location difficult.

[0006] Model-based methods (such as hybrid logic dynamic models and voltage residual methods) diagnose faults by comparing the residuals of measured variables with those estimated by the observer. This requires the establishment of high-precision mathematical models, resulting in a heavy computational burden. In recent years, some scholars have proposed fault assumption strategies for three-level NPC inverters, constructing a baseline by assuming specific switch faults. However, directly applying this method to hybrid seven-level topologies faces significant challenges:

[0007] (1) Flying capacitor voltage fluctuation interference: The H-bridge unit in the hybrid topology contains a flying capacitor, and its voltage has inherent ripple. The traditional static model cannot cancel this ripple, resulting in a non-zero residual during normal operation, which can easily cause false alarms.

[0008] (2) Difficult to distinguish internal faults in H-bridge: When the four switches inside the H-bridge unit fail, especially the switches on the same side of the bridge arm, the effects on the output waveform are extremely similar, and they only manifest as a loss of level rather than waveform collapse. Existing methods cannot accurately distinguish them using a single variable.

[0009] Therefore, there is an urgent need for a hierarchical diagnostic method that can overcome the above-mentioned defects, maintain high robustness under wide operating range and low power factor conditions, clearly decouple the faults of the T-type converter and the H-bridge unit, and accurately locate the weak fault characteristics inside the H-bridge. Summary of the Invention

[0010] To address the aforementioned problems, this invention provides a hierarchical open-circuit fault diagnosis method and system for hybrid seven-level inverters based on multi-dimensional feature criteria. This solves the problems of severe feature coupling, poor robustness under low power factor, and difficulty in distinguishing weak faults within the H-bridge in existing hybrid topology fault diagnosis technologies.

[0011] In a first aspect, the present invention provides a hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria, which adopts the following technical solution:

[0012] A hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria includes:

[0013] Acquire raw signals, including the output voltage and current of the hybrid seven-level inverter and the flying capacitor voltage of the H-bridge unit;

[0014] A dynamic voltage reference model based on the failure assumption of H-bridge unit is constructed, including the establishment of normal operation model of hybrid seven-level inverter, calculation of controlled reconfiguration logic and equivalent switching function, and adaptive cancellation of flying capacitor ripple based on measured variable mapping.

[0015] Diagnostic features are extracted based on the original signal and dynamic voltage reference model;

[0016] Diagnostic feature fusion based on improved Transformer network;

[0017] Based on the characteristics of the fusion, determine whether the inverter output voltage is subject to hard clamping voltage;

[0018] Based on the judgment results, the faulty switching transistor was located using a dynamic voltage reference model.

[0019] Secondly, a hierarchical open-circuit fault diagnosis system for hybrid seven-level inverters based on multi-dimensional feature criteria includes:

[0020] The signal acquisition module is configured to acquire raw signals, including the output voltage and output current of the hybrid seven-level inverter and the flying capacitor voltage of the H-bridge unit.

[0021] The model building module is configured to build a dynamic voltage reference model based on the H-bridge unit failure assumption, including the establishment of a normal operation model of the hybrid seven-level inverter, the calculation of controlled reconfiguration logic and equivalent switching function, and adaptive cancellation of flying capacitor ripple based on measured variable mapping.

[0022] The feature extraction module is configured to extract diagnostic features based on the original signal and the dynamic voltage reference model;

[0023] The feature fusion module is configured to perform diagnostic feature fusion based on an improved Transformer network;

[0024] The clamping module is configured to determine whether a hard clamping voltage has occurred in the inverter output voltage based on the fused features.

[0025] The fault location module is configured to locate the faulty switching transistor based on the judgment result and using a dynamic voltage reference model.

[0026] Thirdly, the present invention provides a computer-readable storage medium storing a plurality of instructions adapted for loading and execution by a processor of a terminal device of the method for diagnosing hierarchical open-circuit faults in a hybrid seven-level inverter based on multidimensional feature criteria.

[0027] Fourthly, the present invention provides a terminal device, including a processor and a computer-readable storage medium, wherein the processor is used to implement various instructions; the computer-readable storage medium is used to store multiple instructions, the instructions being adapted to be loaded and executed by the processor to provide a hierarchical open-circuit fault diagnosis method for a hybrid seven-level inverter based on multi-dimensional feature criteria.

[0028] In summary, the present invention has the following beneficial technical effects:

[0029] 1. This invention provides a graded open-circuit fault diagnosis method for hybrid seven-level inverters, innovatively constructing a dynamic benchmark model based on fault assumptions and introducing a feature-based criterion strategy. Experimental results demonstrate extremely high robustness and accuracy under wide-range tuning and low power factor conditions.

[0030] 2. The hierarchical diagnostic strategy proposed in this invention can output digital fault flags accurate to specific switching transistors. This precise diagnostic result breaks through the limitation of ambiguous fault location in traditional hybrid multilevel topologies and can perfectly cooperate with subsequent pure software fault-tolerant strategies such as model prediction fault-tolerant control. After receiving the accurate fault flag, the system can achieve smooth fault-tolerant operation by directly re-constraining the switching state without adding extra hardware compensation circuits such as backup submodules or redundant bridge arms. This method significantly improves the overall reliability of the system while ensuring uninterrupted grid-connected operation, and significantly reduces the hardware manufacturing cost of the inverter and the system size.

[0031] 3. Most existing diagnostic and fault-tolerant methods typically employ a fault-tolerant strategy of directly bypassing and disconnecting the entire faulty unit (such as the entire H-bridge) after detecting a submodule fault. However, this invention, through deep fusion of three-dimensional characteristics such as flying capacitor voltage drift, ripple asymmetry, and voltage deviation integral, accurately distinguishes the specific faulty switching transistors within the T-type converter and H-bridge. Based on this precise device-level location, the fault-tolerant control system does not need to completely eliminate the faulty submodule; instead, it can continue to fully utilize the remaining healthy switching transistors within the faulty module. This allows the inverter to maintain as many output levels as possible even after experiencing single or multiple open-circuit faults, significantly improving the output voltage harmonic distortion rate after a fault, and ensuring high-quality power output and system stability even under severe fault conditions. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the hybrid seven-level inverter topology according to an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram showing the comparison and drift characteristics of the flying capacitor voltage ripple under an open-circuit fault of the forward discharge switch S5 of the H-bridge unit in an embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the inverted phase and negative drop characteristics of the flying capacitor voltage ripple under an open-circuit fault in the negative charging switch S6 of the H-bridge unit according to an embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of the local distortion and steady-state characteristics of the flying capacitor voltage ripple under an open-circuit fault of clamping switch S7 / S8 in the H-bridge unit according to an embodiment of the present invention.

[0036] Figure 5 This is a waveform diagram of the instantaneous voltage deviation of a T-type switch under high-modulus unity power factor operating conditions, as shown in this embodiment of the invention.

[0037] Figure 6 This is a simulation diagram of the integral characteristic response waveform of a T-type switch failure under high-modulus unity power factor conditions according to an embodiment of the present invention.

[0038] Figure 7 This is a response diagram of the correlation characteristics of H-bridge switch faults under high-modulus unity power factor conditions according to an embodiment of the present invention.

[0039] Figure 8 This is a waveform diagram of the instantaneous voltage deviation of a T-type switch under low-profile unit power factor operating conditions according to an embodiment of the present invention.

[0040] Figure 9 This is a simulation diagram of the integral characteristic response waveform of a T-type switch failure under low-profile unity power factor conditions, according to an embodiment of the present invention.

[0041] Figure 10 This is a response diagram of the correlation characteristics of H-bridge switch faults under low-power unity factor conditions according to an embodiment of the present invention.

[0042] Figure 11 This is a waveform diagram of the instantaneous voltage deviation of a T-type switch under low power factor conditions according to an embodiment of the present invention.

[0043] Figure 12 This is a simulation diagram of the integral characteristic response waveform of a T-type switch failure under low power factor conditions according to an embodiment of the present invention.

[0044] Figure 13 This is a response diagram of the correlation characteristics of H-bridge switch faults under low power factor conditions according to an embodiment of the present invention.

[0045] Figure 14 This is a flowchart illustrating the fault diagnosis process for a hybrid multilevel inverter topology according to an embodiment of the present invention. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to the accompanying drawings.

[0047] Example 1

[0048] Reference Figure 1 This embodiment of a hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria includes the following steps:

[0049] Step S1: Signal Acquisition

[0050] First, the inverter control system sampling circuit is used to collect the following key signals in real time: DC bus voltage V dc H-bridge unit flying capacitor voltage v f Three-phase output current i out and inverter bridge arm output voltage u invSince these signals are all necessary for closed-loop control, this method does not require additional sensor hardware costs.

[0051] Step S2: Construction of a dynamic benchmark system based on fault assumptions

[0052] Next, a dynamic voltage reference model that integrates measured state variables and switching states is constructed within the digital controller. This model overcomes the limitations of traditional static observers, and its core idea is "fault assumption" and "real-time variable mapping".

[0053] The specific model construction process includes the following sub-steps:

[0054] Establishment of the normal operation model for the S2.1 hybrid seven-level inverter:

[0055] First, define the ideal switching functions for the T-type converter and the H-bridge unit. Since a single phase of the hybrid seven-level inverter contains eight power switches (the T-type unit has...),... H-bridge unit is Let its driving signal be , where 1 indicates conduction and 0 indicates deactivation.

[0056] Define the real-time switching state function S of the T-type converter. T (t) is:

[0057] ,

[0058] Define the real-time switching state function S of the H-bridge unit. H (t) is:

[0059] ,

[0060] Under ideal, fault-free conditions, the theoretical value of the inverter's output phase voltage u inv_ideal (t) can be represented as a linear superposition of the T-type unit output and the H-bridge unit output:

[0061] ,

[0062] Among them, V dc (t) represents the measured total DC bus voltage, v f (t) represents the measured voltage across the flying capacitor of the H-bridge unit.

[0063] S2.2 Controlled Reconfiguration Logic and Equivalent Switching Function Calculation under the "Fault Assumption":

[0064] This invention utilizes a forward discharge switch (e.g., one that has the most representative effect on voltage) within the H-bridge unit preset inside the controller. Figure 1A baseline is established when an open-circuit fault occurs at S5. When an open-circuit fault is assumed at S5, the actual current path is affected by the load current i. out Strict physical constraints in the (t) direction.

[0065] Therefore, the current direction sign function sgn(i) is introduced. out (t)):

[0066] , Where i th It is a threshold for the dead zone of the current zero crossing, used to shield the jitter interference of the current sampling noise at the zero crossing point.

[0067] Based on the physical topology mechanism, the equivalent H-bridge switching function S after assuming S5 failure is derived. H S5 (t). Specifically: when the controller issues a raw command requiring S H (t)=1 (i.e., D5=1, D8=1), and at this time the load current i out (t) > 0 (i.e., current flows out of the inverter). At this time, the current should flow through S5 and S8, but since S5 is assumed to be open, the positive current is forced to transfer to the anti-parallel diode of the lower bridge arm for freewheeling, which causes the actual output of the H-bridge to be physically clamped to 0. When all other instruction combinations (such as output 0 level or negative level) or the current is reversed, the open circuit of S5 does not affect the normal current loop logic of the H-bridge.

[0068] Therefore, the equivalent switching function S H S5 (t) is mathematically defined as the following nonlinear piecewise logic expression:

[0069] .

[0070] S2.3 Discretized dynamic reference voltage output considering digital control delay

[0071] To ensure that the reference model is strictly synchronized with the actual inverter output when running in the actual digital signal processor, a one-step delay T inherent in the digital control system must be introduced. s and dead zone time T dead Compensation. Based on the above controlled reconstruction logic, the dynamic reference voltage u is calculated in real time in the discrete time domain. base The analytical model for (k) is:

[0072] ,

[0073] Where d is the inherent delay number of the hardware sampling and pulse width modulation update; u dead (k) is the dead zone voltage term based on current direction compensation.

[0074] S2.4 Adaptive Cancellation Mechanism of Cross-Capacitor Ripple Based on Measured Variable Mapping S2.4

[0075] In the calculation formula of this dynamic reference model, the multiplier terms of the H-bridge unit directly incorporate the measured real-time voltage v of the flying capacitor. f (k), rather than a constant DC reference value such as V dc / 4). The transient mathematical model of the voltage across the capacitor is: This formula includes the unavoidable low-frequency AC ripple component Δv. f_ripple (t). This means that the reference voltage waveform u calculated above... base Within (k), the capacitor voltage ripple characteristics and transient fluctuations that are completely consistent with the actual physical system have been automatically mapped and embedded. Therefore, in subsequent multi-dimensional feature extraction, such as calculating the measured output voltage u, inv (t) and reference voltage u base When integrating the difference of (t), the background ripple deviation caused by capacitor charging and discharging under normal operating conditions can be completely adaptively canceled by the algorithm at the mathematical level:

[0076] ,

[0077] This dynamic benchmark construction method based on the fusion of measured state variables fundamentally eliminates the severe coupling and aliasing between "inherent ripple of flying capacitors" and "weak fault characteristics" in the time and amplitude domains. It greatly improves the model's anti-interference capability under harsh conditions such as power grid fluctuations, nonlinear loads, and low power factors, and lays the core computational benchmark for the subsequent hierarchical decoupling of T-type faults and H-bridge weak faults.

[0078] Step S3: Extraction of multidimensional diagnostic features

[0079] This step aims to extract three sets of core characteristic quantities from the acquired raw signals and calculated reference voltage. These quantities are capable of keenly reflecting the nature of the fault and are insensitive to changes in operating conditions. The specific extraction process and its physical meaning are as follows:

[0080] Physical clamping features (U) used to capture hard boundaries of topological structures max U min Within a complete fundamental frequency cycle T0, the measured output voltage u of the inverter is captured in real time using a sliding window algorithm or a periodic reset mechanism. inv The maximum peak value of (t) U max and minimum valley value U min :

[0081] ,

[0082] In a hybrid seven-level topology, the T-type converter is directly connected to the high-voltage side of the DC bus. If a fault occurs in the T-type main arm or clamping branch, the output voltage will lose its level regulation capability within a specific half-cycle, being forcibly clamped to the DC bus voltage limit by physical diodes. This clamping effect is an inherent property of the topology and is unaffected by operating parameters such as load power factor and modulation ratio. Therefore, U max and U min It is the optimal indicator for distinguishing between T-type unit failures and H-bridge unit failures.

[0083] The energy deviation characteristic T used to quantify the degree of waveform distortion Flag2 First, calculate the measured voltage u. inv (t) and dynamic reference voltage u base The instantaneous residual Δu(t) is obtained from the energy deviation characteristic T. Then, this residual is subjected to half-cycle integration. Flag2 To eliminate integral drift, the integrator employs a reset mechanism based on the fundamental period.

[0084] ,

[0085] The instantaneous voltage residual reflects the moment the fault occurs, while the integral operation reflects the duration and severity of the fault. For a T-type main switch fault, due to the large-area level loss, the integral amplitude exhibits a maximized characteristic; for a T-type clamping switch fault, the level is lost only near the zero-crossing point, and the integral amplitude is relatively small. By quantifying the difference in the integral after the fault, this characteristic can achieve precise location of internal faults within the T-type circuit.

[0086] Capacitance-dependent features used to identify charge balance within the H-bridge. Flag This feature is not a simple amplitude comparison, but rather incorporates the concept of cross-correlation from signal processing. First, the measured flying capacitor voltage v is extracted separately. f and the reference model voltage v f_ref The AC ripple component of the DC bias is removed. Then, the cross-correlation integral of the two components within the sliding window is calculated:

[0087] ,

[0088] in T represents the ripple component after DC removal. wThe value represents the width of the sliding window. The four internal switches of the H-bridge control the charging and discharging circuits of the capacitor. A fault in S5 / S6 causes a phase reversal in the capacitor voltage ripple, manifested as a polarity reversal or loss of control in the correlation coefficient. A fault in S7 / S8 only results in a missing ripple within half a cycle; the correlation coefficient shows amplitude decay but unchanged polarity. This characteristic profoundly reveals the disruption mode of the capacitor's charge balance mechanism caused by the fault, and is key to solving the difficulty in distinguishing H-bridge faults.

[0089] Step S4: Multidimensional Feature Fusion and Precise Fault Localization Based on Lightweight Transformer Network

[0090] In traditional diagnostic methods, multidimensional features are often compared sequentially using rigid, fixed thresholds. This approach is prone to misjudgment when faced with sudden load changes, extremely low power factors, or nonlinear dead-zone effects due to feature distortion or blurred feature boundaries. To address this, this step introduces a lightweight Transformer network from deep learning. Through a self-attention mechanism, it performs deep nonlinear fusion and global mapping of the physical clamping features, energy deviation features, and capacitance correlation features extracted in step S3, achieving highly robust hierarchical fault diagnosis.

[0091] S4.1 Construction and Serialization Embedding of Multidimensional Feature Vectors:

[0092] First, the features extracted in step S3 are concatenated with the measured operating state to construct a comprehensive feature vector set covering the spatiotemporal information of the system. This is done within a sliding time window T. w Within the sample, the sequence is truncated according to the sampling step size to construct a multi-dimensional feature input matrix X. input :

[0093] ,

[0094] Where L is the sequence length within the sliding window, and d in For feature dimensions.

[0095] To adapt to the input format of the Transformer network, a linear projection layer is used to map the input matrix to a high-dimensional latent space, and positional encoding (PE) is superimposed to preserve time-series information, generating a feature token sequence E. input :

[0096] ,

[0097] Among them, W E ∈R L×dmodelFor the learnable embedding weight matrix, d model is the dimension of the hidden layer of the model; PE is the sine and cosine position encoding matrix.

[0098] S4.2 Feature fusion based on multi-head self-attention mechanism:

[0099] The generated feature token sequence E input The input is fed into a multi-layer Transformer encoder. Under different operating conditions, the characteristics of T-type converter faults and H-bridge faults in the hybrid seven-level inverter exhibit complex temporal coupling relationships. Through the multi-head self-attention (MHSA) mechanism, the model can adaptively calculate the dynamic correlation weights of each feature at different time steps, achieving deep fusion of multi-dimensional features.

[0100] In the h-th attention head, the query, key, and value matrices are calculated as follows:

[0101] ,

[0102] Among them, W Q h W K h W V h Let be the learnable parameter matrix of the h-th attention head.

[0103] Attention weight matrix for feature correlation h The calculation formula is:

[0104] ,

[0105] In the formula, d k The dimension of the key vector, divided by This is used to prevent gradient vanishing due to excessively large dot product values.

[0106] Subsequently, the outputs of multiple attention heads are concatenated and linearly mapped to obtain the hidden layer representation Z after multidimensional feature fusion. MHSA :

[0107] ,

[0108] By using residual connections and layer normalization, feature degradation in deep networks can be effectively prevented.

[0109] .

[0110] S4.3 Feedforward Neural Networks and High-Dimensional Nonlinear Mapping of Features:

[0111] The features Z' fused by the attention mechanism are fed into a two-layer fully connected feed-forward network (FFN) to further extract nonlinear electrical fault features. The FFN uses the GELU activation function.

[0112] ,

[0113] The final output features are corrected by layer-normalized residuals to obtain high-dimensional fused features:

[0114] ,

[0115] Through the aforementioned self-attention fusion and nonlinear mapping, the network has fully captured the hidden logical relationships such as "asymmetric ripple of flying capacitor under low power factor" and "transient energy deviation", effectively solving the problem of severe feature coupling near the zero crossing point in the traditional rule threshold method.

[0116] S4.4 Hierarchical Softmax Classifier and Fault Isolation Output:

[0117] The high-dimensional feature vector output by the Transformer encoder is compressed into a one-dimensional fault feature vector f by global average pooling. fused Subsequently, it is fed into a multilayer perceptron (MLP) classifier with a hierarchical structure. Based on the topological physical structure of the hybrid seven-level inverter, this invention designs a two-layer cascaded output mechanism:

[0118] Level 1 (Region Location): The Softmax function is used to output that the fault belongs to the T-type converter region (P...). T ) or H-bridge unit region (P H The probability distribution of ).

[0119] Level 2 (single tube location): After determining the area, further calculate the conditional probability of failure of each specific switch tube (S1~S4 or S5~S8) in the area.

[0120] The final fault category probability vector Y pred The calculation is as follows:

[0121] ,

[0122] in, This represents the normal probability of the system. This represents the probability of an open-circuit fault in the internal switching transistors S1 to S4 of the T-type converter. This represents the probability of an open-circuit fault in the internal switching transistors S5 to S8 of the H-bridge.

[0123] Set confidence threshold Pth (e.g., 0.90), when the probability y of a certain dimension in the probability vector... i >P th When the fault location flag for the corresponding switching transistor is displayed, the system outputs a fault location flag to complete a precise diagnosis.

[0124] S5. Determine whether a hard clamping voltage occurs in the inverter output voltage based on the fused features:

[0125] After completing the multi-dimensional feature fusion, the system inputs the extracted comprehensive feature indicators into the "physical guidance decision layer." This layer follows the topological clamping rules of the hybrid seven-level inverter, establishing a top-down calculation logic from global region partitioning to micro-device positioning. The specific calculation and diagnostic process is as follows:

[0126] S5.1 Adaptive Calculation of Dynamic Hard Clamp Threshold and First-Level Global Fault Offloading:

[0127] In a hybrid seven-level topology, the T-type converter is directly connected to the DC bus. If an open circuit occurs in the T-arm, the inverter output voltage will be clamped to the DC bus limit (i.e., half bus voltage ±V) by physical diodes. dc / 2). Due to the DC bus voltage V dc Fluctuations exist in actual operation; the system first calculates V based on real-time sampling. dc (t) Dynamic clamping discrimination threshold:

[0128] ,

[0129] , In the formula, α is a robustness margin coefficient that takes into account bus ripple, dead-zone voltage drop of switching transistors and sampling error. It is usually taken in the range of 0.85≤α≤0.95.

[0130] Subsequently, the Boolean logic discriminant function D for the first-level global fault shunting is constructed. upper and D lower :

[0131] ,

[0132] ,

[0133] Based on the Boolean discrimination results, complete the global fault area distribution:

[0134] 1. If D upper =1, indicating that physical hard clamping has occurred during the positive half-cycle of the output voltage, the fault is locked on the upper bridge arm of the T-type converter, and the process enters the secondary fine positioning of S5.2;

[0135] 2. If D lower=1, indicating that a physical hard clamping occurred during the negative half-cycle of the output voltage, the fault is locked in the lower bridge arm of the T-type converter, and the process enters the S5.2 secondary fine positioning.

[0136] 3. If D upper =0 and D lower =0, indicating that the output voltage has not reached the physical boundary of the DC bus and there is no hard clamping characteristic of the T-type bridge arm. The fault is locked in the H-bridge unit or the system is normal, and enter the S5.3 special diagnosis.

[0137] S5.2 Precise positioning of T-type internal switches based on fused energy deviation characteristics (second-level diagnosis):

[0138] After the fault region of the T-type converter is locked by the first-stage shunt, the voltage residual integral characteristic T obtained by fusion in step S4 is called. Flag2 By combining the differences in energy distortion polarity and amplitude of different switching transistor faults in the T-arm, accurate differentiation of single-transistor faults within the upper and lower arms can be achieved. The impact mechanisms of different open-circuit faults of switching transistors on inverter output energy loss and voltage distortion are significantly different, and a quantitative discrimination logic is established accordingly.

[0139] (1) Precise fault diagnosis of T-type upper arm (D upper =1):

[0140] The T-type upper bridge arm includes switches S2 and S3. An open-circuit fault in the lower main switch of S2 will cause a loss of negative half-cycle voltage, resulting in a positive drift in the energy integral characteristic. An open-circuit fault in the upper clamping switch of S3 mainly disrupts the midpoint freewheeling circuit, causing a continuous negative bias in the energy integral characteristic. A noise-reduction dead-time threshold ε is set. T To shield against minute sampling errors and ripple interference, the discrimination rules are as follows:

[0141] 1. If T Flag2 >ε T The fault was determined to be an open circuit fault in the S2 switch.

[0142] 2. If T Flag2 ≤-ε T The fault was determined to be an open circuit fault in the S3 switch.

[0143] (2) Precise fault diagnosis of T-type lower bridge arm (D lower =1):

[0144] The T-type lower bridge arm includes switches S1 and S4. An open circuit in the main switch S2 results in a complete loss of output energy during the positive half-cycle, leading to extremely large characteristic distortion amplitude. An open circuit in the auxiliary switch S4 only causes localized level distortion, with relatively weak characteristic deviation. To quantify the difference between the two, a reference characteristic quantity T under normal operating conditions is introduced. Flag2_nor Define the energy distortion rate characteristic ΔT ratio :

[0145] ,

[0146] Set a high distortion rate threshold γ th (Typical value 2.0), the discrimination rules are as follows:

[0147] 1. If ΔT ratio ≥γ th The fault was determined to be an open circuit fault in the S1 switch.

[0148] 2. If ΔT ratio <γ th The fault was determined to be an open circuit fault in the S4 switch.

[0149] S5.3 Precise localization of the H-bridge interior based on charge-correlation waveform asymmetry index (Level 3 diagnosis):

[0150] After the first-stage current shunting locks the fault region of the H-bridge unit, the fused capacitor charge correlation characteristic H is invoked. qiaoFlag To address the difficulty in distinguishing between the uncontrolled overt faults S5 and S6 and the subtle, concealed faults S7 and S8 in the H-bridge, a threshold-based qualitative judgment mechanism is constructed to achieve comprehensive and accurate location of faults in all four tubes of the H-bridge.

[0151] (1) Qualitative judgment of runaway overt faults:

[0152] Based on the ripple amplitude of the flyover capacitor under normal operating conditions, a preset H-bridge positive runaway threshold Thr is established. Hqiao_max Negative runaway threshold Thr Hqiao_min Rapidly identify severe faults by utilizing the characteristic quantity limit offset properties:

[0153] 1. If H qiaoFlag >Thr Hqiao_max The H-bridge forward charging and discharging circuit was determined to be cut off, and the voltage of the flying capacitor rose abnormally, indicating an open circuit fault in the S5 switch.

[0154] 2. If H qiaoFlag <Thr Hqiao_min The H-bridge negative circuit was determined to be abnormal, with the voltage of the flying capacitor dropping sharply and reversing, indicating an open circuit fault in the S6 switch.

[0155] (2) Quantitative judgment of hidden weak faults:

[0156] If the above-mentioned runaway threshold is not triggered, it is determined to be a weak, hidden fault, such as S7 or S8. These faults do not exhibit obvious voltage runaway characteristics, but only show waveform polarity asymmetry distortion. Extract H within a single sliding time window. qiaoFlag Absolute extreme value of characteristic quantity: Ψ max =|max(H qiaoFlag )|、Ψ min =|min(H qiaoFlagInnovative definition of waveform distortion asymmetry index I asym :

[0157] ,

[0158] Set the polarity bias threshold δ H Fault differentiation is achieved based on the sign and magnitude of the asymmetric exponent.

[0159] 1. If I asym ≥δ H The analysis indicates that the positive waveform distortion is dominant, which is a fault of open circuit in the S8 switch.

[0160] 2. If I asym <-δ H The analysis indicates that the negative waveform distortion is dominant, suggesting an open circuit fault in the S7 switch.

[0161] S5.4 Anti-interference sliding counter and fault-tolerant execution trigger

[0162] To completely shield instantaneous characteristic spikes caused by load step changes, power grid transient disturbances, and electromagnetic interference, and to eliminate false fault actions caused by single-point misjudgments, the DSP controller internally includes 8 power switching transistors (S). i (i=1,2,…,8) Configure independent fault status accumulators Count(S) respectively. i A multi-cycle false triggering verification mechanism is constructed. The discrete-domain sliding accumulation iteration formula is defined as follows:

[0163] If and only if the state accumulator of a certain switch satisfies Count(S) i When [k]≥3, the system officially latches the fault flag bit of the switch transistor, completing the final confirmation of the fault.

[0164] S6. Based on the judgment results and using the dynamic voltage reference model, locate the faulty switching transistor.

[0165] After step S5, which uses hard clamping features to initially divide the global fault region into T-type converter region or H-bridge unit region, this step performs a deep residual comparison between the actual operating state and the dynamic voltage reference model constructed in step S2 to achieve precise location of the specific faulty switching transistors (S1~S8). The specific execution logic is as follows:

[0166] S6.1: Real-time calculation and extraction of dynamic voltage residuals:

[0167] The actual output voltage uinv(t) of the inverter is acquired in real time using a digital controller. Combined with the real-time updated dynamic reference voltage ubase(t) constructed in step S2, the dynamic voltage residual between the two is calculated: Δu(t) = uinv(t) - ubase(t). Since the dynamic reference model in step S2 has adaptively embedded and canceled the normal AC ripple of the flying capacitor, the extracted residual Δu(t) at this time has filtered out background noise interference and contains only pure fault distortion information.

[0168] S6.2: Single-tube positioning inside the T-type converter (if step S5 determines that hard clamping has occurred):

[0169] When step S5 determines that the fault area is a T-type converter and that there is a hard clamping characteristic of the DC bus voltage, the fault types of the four switching transistors in the T-type bridge arm are further distinguished based solely on the integral polarity and amplitude characteristics of the fault residual Δu(t), combined with the distortion patterns of different switching transistor faults:

[0170] 1. Main switch fault location: If the residual integral of the positive half-cycle of voltage shows a significant negative missing maximum value, it is determined that the T-type upper bridge arm main switch S1 has an open circuit fault; if the residual integral of the negative half-cycle of voltage shows a positive missing maximum value, it is determined that the T-type lower bridge arm main switch S2 has an open circuit fault.

[0171] 2. Clamping switch fault location: If a small negative local residual integral appears only near the zero-crossing point of the load current, it is determined that the T-type upper bridge arm clamping switch S3 has an open circuit fault; if a small positive local residual integral appears near the zero-crossing point of the current, it is determined that the T-type lower bridge arm clamping switch S4 has an open circuit fault.

[0172] S6.3: Single tube positioning inside the H-bridge unit (if step S5 determines that no hard clamping has occurred):

[0173] When step S5 determines that there is no DC bus clamping characteristic and the fault is locked in the H-bridge unit, the distortion characteristics of the dynamic voltage residual Δu(t) and the drift direction of the flying capacitor voltage are combined to achieve hierarchical and precise positioning of the four switches of the H-bridge:

[0174] 1. Uncontrolled fault location: If the voltage of the flying capacitor is detected to be extremely divergent in the positive direction and Δu(t) shows a continuous positive deviation, it is determined that the H-bridge forward discharge switch S5 has an open circuit fault; if the voltage of the flying capacitor drops significantly in the negative direction, the output voltage phase flips, and Δu(t) shows a continuous negative deviation, it is determined that the H-bridge negative charging switch S6 has an open circuit fault.

[0175] 2. Concealed fault location: If the voltage across the capacitor does not exhibit global runaway divergence, but Δu(t) shows obvious waveform asymmetry distortion in the positive and negative half-cycles, the fault characteristic energy ratio in the positive and negative half-cycles is compared to determine the fault: if the deviation energy dominates in the positive half-cycle, the switch S8 on the same side is determined to have an open circuit fault; if the deviation energy dominates in the negative half-cycle, the switch S7 on the opposite side is determined to have an open circuit fault.

[0176] S6.4: Fault Confirmation and Fault Tolerance Command Issuance:

[0177] After completing device-level fault identification, the system generates and latches a precise fault digital flag, Flag=S. i (i∈{1,2,…,8}), accurately corresponds to the open-circuit fault state of the eight power switching transistors, and transmits the fault flag bit to the inverter main control system in real time.

[0178] Experimental verification

[0179] To intuitively demonstrate the physical meaning and distinguishing mechanism of this characteristic quantity, this invention extracts comparative waveforms of the measured ripple and the reference ripple:

[0180] like Figure 2 As shown, when S5 malfunctions, the forward discharge circuit is disconnected, and the measured voltage remains highly in phase with the reference ripple. More importantly, the measured voltage exhibits a sharp forward DC drift. This in-phase plus large amplitude characteristic will cause Hqiao... Flag It reaches an extremely high positive saturation value, which is significantly different from other faults.

[0181] like Figure 3 As shown, when S6 malfunctions, the measured ripple exhibits a clear inverse relationship with the reference ripple, accompanied by a negative voltage drop. This phase reversal and abnormal amplitude result in an abnormal correlation integral value (Hqiao). Flag The presence of extremely negative values ​​is a unique characteristic for identifying S6 faults.

[0182] like Figure 4 As shown, when S7 / S8 malfunctions, its Hqiao Flag The values ​​all fall within a middle range that is neither extremely large nor extremely small. Therefore, it is difficult to completely and reliably separate the two based solely on correlation integration under all operating conditions. At this point, the system will determine that the fault belongs to S7 / S8 and automatically activate the fourth-level diagnostic logic to achieve the final diagnosis.

[0183] For faults S7 and S8 that fall within the intermediate threshold range, this invention further proposes a fourth-level quantitative decision logic based on eigenvalue polarity bias. This logic utilizes the asymmetry of the H-bridge topology during positive and negative half-cycle operations, comparing the maximum absolute value of the eigenvalues ​​(|Hqiao...). Flag_max|) and minimum value (|Hqiao) Flag_min |) to achieve final separation. The specific separation principle is as follows: In the H-bridge unit of the hybrid seven-level inverter, S8 is the key switch in the positive loop. Its failure directly disrupts the waveform integrity of the positive half-cycle, leading to a loss of positive level or abnormal positive ripple, while having a smaller impact on the negative half-cycle. Therefore, the voltage deviation energy generated by it is mainly concentrated in the positive direction. Similarly, S7 is the key switch in the negative loop. Its failure directly disrupts the waveform integrity of the negative half-cycle, while having a smaller impact on the positive half-cycle. Therefore, the voltage deviation energy generated by it is mainly concentrated in the negative direction. Based on this, the absolute values ​​of the maximum and minimum values ​​of the characteristic values ​​are calculated and compared in real time. If |Hqiao Flag_max |>|Hqiao Flag_min The | indicates that the deviation caused by the fault is mainly shifted in the positive direction. This is highly consistent with the physical characteristics of the positive half-cycle waveform distortion caused by the S8 fault, thus confirming it as an S8 fault. Similarly, if |Hqiao Flag_max |<|Hqiao Flag_min The result indicates that the deviation caused by the fault is mainly shifted in the negative direction, which is highly consistent with the physical characteristics of the negative half-cycle waveform distortion caused by the S7 fault. Based on this, it can be diagnosed as an S7 fault.

[0184] To verify the effectiveness and robustness of the proposed hierarchical open-circuit fault diagnosis method based on multi-dimensional feature fusion, a hybrid seven-level inverter system model was built in the MATLAB / Simulink simulation platform. The main circuit parameters of the system are set as follows: DC bus voltage V dc =600V (i.e., the voltage of both the upper and lower DC voltage divider capacitors is 300V), DC side support capacitor C dc =2350uF, H-bridge unit flying capacitor C f =940uF. To comprehensively test the performance of the diagnostic algorithm under different operating conditions, the following two typical load conditions were set:

[0185] Operating condition 1 (unity power factor): Load resistance R = 26Ω, filter inductance L = 2mH. At this time, the phase angle PF ≈ 1.0, used to verify the basic performance of the algorithm under a standard resistive load.

[0186] Operating Condition 2 (Low Power Factor): Load resistance R = 20.8Ω, filter inductance L = 50mH. In this condition, the phase angle PF ≈ 0.8, used to verify the robustness of the algorithm under inductive load, severe current lag, and low power factor conditions.

[0187] Fault diagnosis verification under baseline operating conditions: such as Figure 5 , Figure 6 and Figure 7As shown, when a single open-circuit fault occurs in the internal switching transistor of the T-type converter, the voltage deviation and integral characteristic T are based on the fault assumption. Flag2 It exhibits significant differences. A fault in the main switch on S1 leads to a severe loss of energy during the positive half-cycle, resulting in a decrease in the integral value T. Flag2 The voltage drops to an extremely low negative value of approximately -2.58, with the largest amplitude. A fault in the main switch at S2 causes the integral polarity to reverse to a positive value of approximately 0.37. Faults in the upper clamping switch at S3 and the lower clamping switch at S4 only result in localized voltage distortion; although their integral values ​​are both negative (approximately -0.64 and -1.65 respectively), their amplitudes are significantly smaller than those of the S1 fault. Based on these amplitude multiples and polarity characteristics, the system successfully achieved precise positioning of the four transistors within the T-type circuit. Simultaneously, regarding internal faults in the H-bridge unit, the flying capacitor voltage u... f and correlation feature quantity Hqiao Flag The faults exhibit clear characteristics: S5 and S6 faults respectively cause a positive surge and a negative drop in capacitor voltage, and the characteristic quantity Hqiao Flag Rapid saturation to maximum and maximum negative values ​​triggers the runaway criterion; while S8 faults are characterized by predominantly positive amplitudes of the characteristic quantity, and S7 faults are characterized by predominantly negative amplitudes of the characteristic quantity. Based on this, the system utilizes waveform asymmetry to identify the internal structure of the H-bridge. Simulation results show that, under baseline conditions, the method of this invention can quickly and accurately isolate and locate all single-tube faults.

[0188] Fault diagnosis verification under low-profile system conditions: such as Figure 8 , Figure 9 and Figure 10 As shown, to verify the adaptability of the invention under non-rated operating conditions, the modulation index was reduced to M=1.8 while maintaining unity power factor. Although the reduction in output voltage amplitude slightly decreased the instantaneous value of voltage deviation, the integral characteristic T of the internal fault of the T-type inverter remained unchanged. Flag2 It maintained extremely high stability; the S2 fault remained the only type triggering integral polarity reversal, and the range of multiples between faults was not blurred by the reduction in modulation. Similarly, in the diagnosis of the H-bridge unit, the voltage runaway characteristics caused by the S5 and S6 faults remained significant, and the asymmetric characteristics of the correlation waveform between the positive bias of S8 and the negative bias of S7 remained obvious. This experimental example strongly demonstrates that the diagnostic criteria proposed in this invention have strong robustness to changes in the system operating point, and can achieve reliable diagnosis within a wide modulation range without dynamically adjusting the threshold.

[0189] Fault diagnosis verification under low power factor conditions: such as Figure 11 , Figure 12 and Figure 13As shown, to verify the reliability of the algorithm under inductive load conditions, the operating condition was further adjusted to M=1.8, with a low power factor phase angle of approximately 0.8. Under this condition, due to the severe lag of the load current, the fault characteristic range of the intermediate transistors S3 / S4 in the T-type converter is partially masked by the diode freewheeling effect, resulting in a significant attenuation of the instantaneous extreme value of the voltage deviation. However, the T-type fault criterion can still be successfully triggered. Meanwhile, for the H-bridge unit, although the ripple amplitude is reduced, the capacitor voltage drift characteristics of the S5 and S6 switches remain significant; for S7 / S8, the fourth-level polarity bias criterion proposed in this invention remains effective. This experimental example strongly demonstrates that the present invention still possesses extremely high robustness and anti-interference capability under extreme operating conditions.

[0190] First, the DC bus voltage V of the hybrid seven-level inverter is acquired by a sensor. dc Flying capacitor voltage v f and inverter output voltage u inv Subsequently, the following three key diagnostic characteristic quantities T are calculated in the digital controller. Flag1 (T-type clamping characteristic), T Flag2 (T-type integral characteristic), Hqiao Flag (H-bridge correlation characteristics), and then set diagnostic thresholds for each level according to the system voltage level.

[0191] like Figure 14 As shown, the fault diagnosis method proposed in this invention employs a top-down hierarchical decision-making strategy. By peeling away fault characteristics layer by layer, it achieves precise location of open-circuit faults in the eight power switches of a hybrid seven-level inverter. After the diagnostic process begins, a first-level global fault shunting is performed, aiming to lock the fault to the T-type converter region or the H-bridge unit region based on the physical clamping characteristics of the inverter output voltage. Specifically, the system determines in real time the maximum value T of the inverter output voltage within the current cycle. xingFlag1_Max Is it greater than the preset positive clamping threshold Thr? _TMax If this condition is met, it indicates that the output voltage is forcibly clamped to the positive terminal of the DC bus during the positive half-cycle. This phenomenon is caused only by a fault in the main switch or clamping switch of the upper arm of the T-type converter. Therefore, the system determines that the fault is located in the upper arm of the T-type converter and proceeds to the subsequent precise positioning branch. If this condition is not met, the system continues to determine the minimum output voltage T. xingFlag1_Min Is it less than the preset negative clamping threshold Thr? _TMin If the voltage is less than this threshold, it indicates that the negative half-cycle voltage is clamped to the negative terminal of the DC bus. The system determines that the fault is located in the lower arm of the T-type bridge and enters the corresponding subdivision process. If neither of the above two clamping conditions is met, it indicates that the inverter output voltage has not touched the DC bus boundary, the fault has not occurred in the T-type main energy channel, the system determines that the fault belongs to the internal fault of the H-bridge unit or the system is in normal operation, and then enters the H-bridge unit diagnostic branch.

[0192] For faults locked in the upper arm of the T-type bridge, the system utilizes the voltage deviation integral characteristic T. Flag2 The polarity is precisely located. Since a fault in S2 (lower main switch) typically causes severe voltage distortion or even polarity reversal during the negative half-cycle, the integral value exhibits a positive drift characteristic. A fault in S3 (upper clamp switch) mainly affects the midpoint freewheeling current; although the integral value decays, the polarity usually remains negative. Therefore, if T is detected... Flag2 If the value is greater than 0, it is determined that the S2 switch is open-circuited, and the counter t is incremented. 2x Conversely, if T Flag2 If the value is ≤0, it is determined that the S3 switch is open-circuited, and the counter t is incremented. 3x .

[0193] For faults locked in the lower T-arm, the system uses the amplitude multiple relationship of the integral characteristic quantity for differentiation. Considering that a fault in the main switch on S1 would result in a complete loss of positive half-cycle energy, the resulting integral deviation amplitude would be much greater than that of a fault in the clamping switch on S4. Therefore, the system compares the current integral value with the normal reference value T. Flag2_nor If the relationship is such that the amplitude increases significantly, then it is determined to be an S1 fault and t is accumulated. 1x Otherwise, it is judged as an S4 fault and t is accumulated. 4x .

[0194] Once the diagnostic process enters the H-bridge unit branch, the system first utilizes the characteristic quantity Hqiao of the flying capacitor voltage. Flag Qualitative analysis is performed on the threshold to identify runaway faults that severely impact the circuit. The system judges the maximum value of the characteristic quantity Hqiao. Flagmax Has the positive runaway threshold (Thr) been exceeded? _Hqiaomax If the voltage exceeds this value, it indicates that the discharge circuit of the flyaway capacitor has been cut off, causing the voltage to rise in the positive direction. The system directly determines that the S5 switch is faulty and accumulates t. 5x If it does not exceed the limit, the system continues to determine the minimum value of the feature quantity, Hqiao. Flagmin Is it below the negative runaway threshold Thr? _Hqiaomin If the value falls below this threshold, it indicates a failure in the capacitor charging circuit or a reverse phase, and the system determines that the S6 switch is faulty and accumulates t. 6x .

[0195] If none of the aforementioned runaway thresholds are triggered, it indicates that the capacitor voltage is under control, and the fault is a subtle, concealed fault, S7 / S8. In this case, the system executes quantitative decision logic based on waveform asymmetry, comparing the absolute values ​​of the maximum and minimum values ​​of the characteristic quantities. Since S8, as a fault of the same-side transistor, mainly causes positive half-cycle waveform distortion, resulting in a dominant positive deviation, while S7, as a fault of the opposite-side transistor, mainly causes negative half-cycle distortion, resulting in a dominant negative deviation, therefore, if |Hqiao Flagmax |≥|Hqiao Flagmin The system identifies an S8 fault and increments t. 8x Conversely, if | Hqiao Flagmax |<|Hqiao Flagmin |, then it is determined to be an S7 fault and t is accumulated. 7x .

[0196] To prevent false alarms caused by transient interference, the system is equipped with a fault confirmation mechanism. Only when the counter value (t) of one of the aforementioned faults is confirmed will the system confirm the fault. xx Only after continuously reaching the preset threshold, which is set to three cycles, will a definite fault code be finally output and the system protection or fault tolerance control action be triggered.

[0197] Example 2

[0198] This embodiment provides a hierarchical open-circuit fault diagnosis system for hybrid seven-level inverters based on multi-dimensional feature criteria.

[0199] A computer-readable storage medium storing a plurality of instructions adapted for loading and execution by a processor of a terminal device, the aforementioned method for diagnosing hierarchical open-circuit faults in a hybrid seven-level inverter based on multidimensional feature criteria.

[0200] A terminal device includes a processor and a computer-readable storage medium, the processor being used to implement various instructions; the computer-readable storage medium being used to store multiple instructions, the instructions being adapted to be loaded and executed by the processor as described in the "Hybrid Seven-Level Inverter Hierarchical Open-Circuit Fault Diagnosis Method Based on Multi-Dimensional Feature Criteria".

[0201] The above are all preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Therefore, all equivalent changes made in accordance with the structure, shape and principle of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria, characterized in that, include: Acquire raw signals, including the output voltage and output current of the hybrid seven-level inverter and the flying capacitor voltage of the H-bridge unit; A dynamic voltage reference model based on the failure assumption of H-bridge unit is constructed, including the establishment of normal operation model of hybrid seven-level inverter, calculation of controlled reconfiguration logic and equivalent switching function, and adaptive cancellation of flying capacitor ripple based on measured variable mapping. Diagnostic features are extracted based on the original signal and dynamic voltage reference model; Diagnostic feature fusion based on improved Transformer network; Based on the characteristics of the fusion, determine whether the inverter output voltage is subject to hard clamping voltage; Based on the judgment results, the faulty switching transistor was located using a dynamic voltage reference model; The normal operation model of the hybrid seven-level inverter is established, including defining the ideal switching functions of the T-type converter and the H-bridge unit. Based on the fact that a single phase of the hybrid seven-level inverter contains eight power switching transistors, its drive signal is assumed to be... Define the real-time switching state function S of the T-type converter. T (t) is: Define the real-time switching state function S of the H-bridge unit. H (t) is: Under ideal, fault-free conditions, the theoretical value of the inverter's output phase voltage u inv_ideal (t) represents the linear superposition of the T-type unit output and the H-bridge unit output: , Among them, V dc (t) represents the measured total DC bus voltage, v f (t) represents the measured voltage across the flying capacitor of the H-bridge unit; the controlled reconfiguration logic and equivalent switching function calculation includes the controlled reconfiguration logic and equivalent switching function calculation under fault assumptions: by pre-setting an open-circuit fault in the forward discharge switch S6, which has the most representative effect on voltage in the H-bridge unit, a benchmark model is constructed. When the assumption is defined that an open-circuit fault occurs in S5, its actual current path is affected by the load current i out Strict physical constraints on the direction of (t) are introduced, hence the introduction of the current direction sign function sgn(i out (t)): , Where i th A threshold is set for the dead zone band at the zero-crossing point of the current to shield against jitter interference from the current sampling noise at the zero-crossing point. Based on the physical topology mechanism, the equivalent H-bridge switching function S after assuming S5 failure is derived. H S5 (t), when the controller issues the raw command requiring S H (t)=1, and at this time the load current i out When (t) > 0, meaning current flows out of the inverter, the current should flow through S5 and S8. However, due to the assumption that S5 is open, the forward current is forced to transfer to the freewheeling diode in the lower bridge arm, causing the actual output of the H-bridge to be physically clamped to 0. Under all other instruction combinations or when the current is reversed, the open circuit of S5 does not affect the normal current loop logic of the H-bridge. Therefore, the equivalent switching function S... H S5 (t) is defined as a nonlinear piecewise logic expression: 。 2. The hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria according to claim 1, characterized in that, The adaptive cancellation of flying capacitor ripple based on measured variable mapping includes introducing a one-step delay T inherent in the digital control system to ensure that the reference model is synchronized with the actual inverter output when running in the actual digital signal processor. s and dead zone time T dead The compensation, based on controlled reconfiguration logic, calculates the dynamic reference voltage u in real time in the discrete-time domain. base The analytical model for (k) is: , Where d is the inherent delay number of the hardware sampling and pulse width modulation update; u dead (k) represents the dead-zone voltage term based on current direction compensation; in the analytical model calculation of the dynamic reference voltage, the multiplier term of the H-bridge unit is directly introduced into the measured real-time voltage v of the flying capacitor. f (k), instead of a constant DC reference value, the transient mathematical model for the flying capacitor voltage is: Based on the low-frequency AC ripple component Δv included in the formula f_ripple (t), to obtain the reference voltage waveform u base (k) Internally mapped and embedded with capacitor voltage ripple characteristics and transient fluctuations consistent with the actual physical system, thus calculating the measured output voltage u inv (t) and reference voltage u base When integrating the difference of (t), the background ripple deviation caused by capacitor charging and discharging under normal operating conditions is adaptively differentially canceled, as expressed as: .

3. The hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria according to claim 2, characterized in that, The method of extracting diagnostic features based on the original signal and dynamic voltage reference model includes extracting three sets of core features from the acquired original signal and calculated reference voltage that can keenly reflect the nature of the fault and are insensitive to changes in operating conditions. Specifically, these include physical clamping features (U) used to capture hard boundaries of the topological structure. max U min Within a complete fundamental frequency cycle T0, the measured output voltage u of the inverter is captured in real time using a sliding window algorithm or a periodic reset mechanism. inv The maximum peak value of (t) U max and minimum valley value U min : ; The energy deviation characteristic T used to quantify the degree of waveform distortion Flag2 First, the measured voltage u is calculated. inv (t) and dynamic reference voltage u base The instantaneous residual Δu(t) is obtained by performing a half-cycle integral on the residual, and then the energy deviation characteristic T is obtained. Flag2 To eliminate integral drift, the integrator employs a reset mechanism based on the fundamental period, expressed as: , For a T-type main switch fault, due to the large-area loss of voltage level, its integral amplitude exhibits a maximized characteristic. For T-type clamping switch faults, the level is lost only near the zero crossing point, and the integral amplitude is small; the capacitance-dependent characteristic Hqiao is used to identify the charge balance inside the H-bridge. Flag By introducing the concept of cross-correlation from signal processing, the measured flying capacitor voltage v is first extracted separately. f and the reference model voltage v f_ref The AC ripple component of the DC bias is removed, and then the cross-correlation integral of the two within the sliding window is calculated: ,in T represents the ripple component after DC removal. w The H-bridge has four internal switches that control the charging and discharging circuits of the capacitors, with the width of the sliding window being the limit. When S5 / S6 fails, the capacitor voltage ripple will undergo phase reversal, which manifests as a polarity reversal or loss of control of the correlation coefficient. When S7 / S8 fails, the ripple will only be missing for half a cycle, and the correlation coefficient will show a decrease in amplitude but no change in polarity.

4. The hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria according to claim 3, characterized in that, The diagnostic feature fusion based on the improved Transformer network includes first concatenating the extracted diagnostic features with the measured operating status to construct a comprehensive feature vector set covering the spatiotemporal information of the system, and then applying this feature vector set within a sliding time window T. w Within the sample, the sequence is truncated according to the sampling step size to construct a multi-dimensional feature input matrix X. input : ， Where L is the sequence length within the sliding window, and d in To determine the feature dimension, and to adapt to the input format of the Transformer network, a linear mapping layer is used to map the input matrix to a high-dimensional latent space, and positional encoding (PE) is superimposed to preserve time-series information, generating a feature token sequence E. input : Among them, W E ∈R L×dmodel For the learnable embedding weight matrix, d model PE is the dimension of the model's hidden layer; PE is the sine and cosine position encoding matrix; then the generated feature token sequence E is... input The input is fed into a multi-layer Transformer encoder. Under different operating conditions, the characteristics of T-type converter faults and H-bridge faults in the hybrid seven-level inverter exhibit complex temporal coupling relationships. Through the multi-head self-attention mechanism MHSA, the dynamic correlation weights of each feature at different time steps are adaptively calculated to achieve deep fusion of multi-dimensional features. In the h-th attention head, the query, key, and value matrices are calculated as follows: ， Among them, W Q h W K h W V h The learnable parameter matrix for the h-th attention head; the attention weight matrix representing the correlation between features. h The calculation formula is: In the formula, d k The dimension of the key vector, divided by To prevent gradient vanishing due to excessively large dot product values, the outputs of multiple attention heads are then concatenated and linearly mapped to obtain the hidden layer representation Z after multidimensional feature fusion. MHSA : Through residual connections and layer normalization, feature degradation in deep networks is effectively prevented. .

5. The hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria according to claim 4, characterized in that, The diagnostic feature fusion based on the improved Transformer network further includes feeding the fused features Z' through the attention mechanism into a two-layer fully connected feedforward neural network FFN to extract nonlinear electrical fault features. The FFN uses the GELU activation function. The final output features are corrected by layer-normalized residuals to obtain high-dimensional fused features: Through self-attention fusion and nonlinear mapping, the hidden logical relationships of the flying capacitor asymmetric ripple and transient energy deviation under low power factor are captured. Then, the high-dimensional feature vector output by the Transformer encoder is compressed into a one-dimensional fault feature vector f by global average pooling. fused Subsequently, it is fed into a multilayer perceptron (MLP) classifier with a hierarchical structure. Based on the topological physical structure of the hybrid seven-level inverter, a two-layer cascaded output mechanism is constructed: the first level is for region localization: using the Softmax function to output the fault location as region P of the T-type converter. T or H-bridge unit region P H The probability distribution; Second-level single-tube localization: After determining the area, further calculate the conditional probability of each specific switch tube in the area failing; The final fault category probability vector Y pred The calculation is as follows: , in, This represents the normal probability of the system. This represents the probability of an open-circuit fault in the internal switching transistors S1 to S4 of the T-type converter. This represents the probability of an open-circuit fault in the internal switching transistors S5 to S8 of the H-bridge.

6. The hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria according to claim 5, characterized in that, The feature-based determination of whether the inverter output voltage is subject to hard clamping includes adaptive calculation of the dynamic hard clamping threshold and first-level global fault shunting after multi-dimensional feature fusion. In the hybrid seven-level topology, the T-type converter is directly connected to the DC bus. When the T-arm is open-circuited, the inverter output voltage will be forcibly clamped to the DC bus limit by the physical diodes. Due to the DC bus voltage V... dc Fluctuations exist during operation; firstly, V is calculated based on real-time sampling. dc (t) Dynamic clamping discrimination threshold: ， , In the formula, α is the robustness margin coefficient, and then the Boolean logic discriminant function D for the first-level global fault shunting is constructed. upper and D lower : ， ， And by combining the Boolean discrimination results, the global fault area distribution is completed: if D upper =1, indicating a physical hard clamping occurred during the positive half-cycle of the output voltage, locking the fault to the upper bridge arm of the T-type converter, and entering secondary fine-tuning; if D lower =1, indicating a physical hard clamping occurred during the negative half-cycle of the output voltage, locking the fault in the lower bridge arm of the T-type converter, and entering secondary fine-tuning; if D upper =0 and D lower =0, indicating that the output voltage has not reached the physical boundary of the DC bus and there is no hard clamping characteristic of the T-type bridge arm. The fault is locked in the H-bridge unit or the system is normal, and special diagnosis is initiated.

7. The hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria according to claim 6, characterized in that, The feature-based determination of whether the inverter output voltage has experienced a hard clamping voltage also includes, after locking the fault region of the T-type converter through the first-stage shunt, calling the voltage residual integral feature T. Flag2 By combining the energy distortion polarity and amplitude differences of different switching transistor faults in the T-arm, the system achieves accurate differentiation of single-transistor faults within the upper and lower arms. First, a quantitative discrimination logic is established. The upper T-arm contains switching transistors S2 and S3, and a noise-reduction dead zone threshold ε is set. T To shield against minute sampling errors and ripple interference, the discrimination rule is: if T Flag2 >ε T The fault is determined to be an open circuit fault in switch S2; if T Flag2 ≤-ε T The fault was determined to be an open circuit fault in switch S3; the lower T-arm of the bridge includes switches S1 and S4, and the reference characteristic quantity T under normal operating conditions is introduced. Flag2_nor Define the energy distortion rate characteristic ΔT ratio : ， Set a high distortion rate threshold γ th The judgment rule is: if ΔT ratio ≥γ th The fault is determined to be an open circuit fault in switch S1; if ΔT ratio <γ th The fault was determined to be an open circuit fault in the S4 switch. Finally, after the first-stage shunt was used to locate the fault region in the H-bridge unit, the fused capacitor charge correlation characteristic H was invoked. qiaoFlag To address the difficulty in distinguishing between the uncontrolled overt faults (S5 and S6) and the subtle, concealed faults (S7 and S8) of the H-bridge, a threshold-based qualitative judgment mechanism is constructed to achieve comprehensive and accurate fault location across all four transistors in the H-bridge. Firstly, based on the amplitude of the flying capacitor ripple under normal operating conditions, a preset positive uncontrolled threshold Thr for the H-bridge is established. Hqiao_max Negative runaway threshold Thr Hqiao_min It can quickly identify severe faults by utilizing the characteristic limit offset characteristics. To shield the instantaneous characteristic spikes caused by load step changes, power grid transient disturbances, and electromagnetic interference, the DSP controller internally uses 8 power switching transistors (S). i For i=1,2,…,8, configure an independent fault status accumulator Count(S) for each. i A multi-period false triggering verification mechanism is constructed, and a discrete-domain sliding accumulation iteration formula is defined: , If and only if the state accumulator of a certain switch satisfies Count(S) i When [k]≥3, the system officially latches the fault flag bit of the switching transistor, completing the final confirmation of the fault.

8. The hierarchical open-circuit fault diagnosis method for hybrid seven-level inverters based on multi-dimensional feature criteria according to claim 7, characterized in that, The process of locating faulty switching transistors based on the judgment results and using a dynamic voltage reference model includes: after initially dividing the global fault region into T-type converter region or H-bridge unit region through hard clamping features, comparing the actual operating state with the constructed dynamic voltage reference model using deep residual comparison to achieve precise location of specific faulty switching transistors S1~S8. First, the actual output voltage uinv(t) of the inverter is acquired in real time using a digital controller, and combined with the real-time updated dynamic reference voltage ubase(t), the dynamic voltage residual between the two is calculated: Δu(t) = uinv(t) - ub ase(t); When the fault area is determined to be a T-type converter and there is a hard clamping characteristic of DC bus voltage, the fault residual Δu(t) is used to refine the differentiation of the fault types of the four switching transistors in the T-type bridge arm by combining the integral polarity and amplitude characteristics of the fault residual Δu(t) with the distortion law of different switching transistor faults; When there is no DC bus clamping characteristic and the fault is locked in the H-bridge unit, the distortion characteristics of the dynamic voltage residual Δu(t) and the drift direction of the flying capacitor voltage are combined to achieve hierarchical and accurate positioning of the four switching transistors in the H-bridge; After completing the device-level fault identification, a precise fault digital flag bit Flag=S is generated and latched. i , i∈{1,2,…,8}, accurately corresponds to the open-circuit fault state of the eight power switching transistors, and transmits the fault flag bit to the inverter main control system in real time.

9. A hierarchical open-circuit fault diagnosis system for a hybrid seven-level inverter based on multi-dimensional feature criteria, executing the hierarchical open-circuit fault diagnosis method for a hybrid seven-level inverter based on multi-dimensional feature criteria as described in claim 1, characterized in that, include: The signal acquisition module is configured to acquire raw signals, including the output voltage and output current of the hybrid seven-level inverter and the flying capacitor voltage of the H-bridge unit. The model building module is configured to build a dynamic voltage reference model based on the H-bridge unit failure assumption, including the establishment of a normal operation model of the hybrid seven-level inverter, the calculation of controlled reconfiguration logic and equivalent switching function, and adaptive cancellation of flying capacitor ripple based on measured variable mapping. The feature extraction module is configured to extract diagnostic features based on the original signal and the dynamic voltage reference model; The feature fusion module is configured to perform diagnostic feature fusion based on an improved Transformer network; The clamping module is configured to determine whether a hard clamping voltage has occurred in the inverter output voltage based on the fused features. The fault location module is configured to locate the faulty switching transistor based on the judgment result and using a dynamic voltage reference model.

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