Control circuit, parameter configuration method, chip and electronic device

Abstract

A control circuit, a parameter configuration method, a chip and an electronic device. The control circuit comprises a comparison module, a multiplexing module and a control module. The comparison module comprises N comparison units, and the N comparison units are respectively used for comparing a timing relationship or a numerical relationship between an actual value and a reference value of N operating parameters; an input end of the multiplexing module is connected with the N comparison units, and the multiplexing module outputs a comparison result of a first comparison unit corresponding to a selection signal in the N comparison units; and the control module is used for increasing or decreasing a numerical value of a control parameter according to the comparison result of the first comparison unit, wherein the control parameter is used for adjusting a first operating parameter corresponding to the first comparison unit in the N operating parameters. The control circuit can switch and adjust multiple operating parameters by using the same state machine circuit, and the circuit architecture is simplified.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a control circuit, a parameter configuration method, a chip, and an electronic device. Background Technology

[0002] Analog circuits, as a core component of modern electronic systems, are widely used in various fields such as communications, industrial control, and medical equipment. Their performance stability directly determines the reliability of the system. However, the performance of analog circuits is highly susceptible to changes in process, voltage, and temperature (PVT) parameters, which exacerbates the instability of circuit performance and poses challenges to analog circuit design.

[0003] To mitigate the adverse effects of PVT variations and enhance circuit robustness and flexibility, existing analog circuit designs typically include a controllable trim (calibration) circuit. This circuit, acting as an adjustable compensation unit, can precisely fine-tune key circuit parameters through external control or internal adjustment mechanisms, offsetting performance drift caused by PVT variations and adapting to different application scenarios. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a control circuit, including a comparison module, a multiplexing module, and a control module. The comparison module includes N comparison units, which are respectively used to compare the timing relationship or numerical relationship between the actual values ​​and reference values ​​of N kinds of operating parameters. The input terminal of the multiplexing module is connected to the N comparison units and outputs the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units. The control module is used to increase or decrease the value of a control parameter according to the comparison result of the first comparison unit, wherein the control parameter is used to adjust the first operating parameter corresponding to the first comparison unit among the N kinds of operating parameters, and N is an integer greater than or equal to 2.

[0005] For example, in the control circuit provided in at least one example of the above embodiments of this disclosure, the control module is configured to output the control parameters to the operating parameter adjustment circuit, so that the operating parameter adjustment circuit adjusts the first operating parameter corresponding to the first comparison unit among the N operating parameters according to the value of the control parameters.

[0006] For example, in the control circuit provided in at least one example of the above embodiments of this disclosure, any one of the N comparison units is a comparator or a phase detector. The comparator is used to compare the numerical relationship between the actual value and the reference value of the operating parameter, and the phase detector is used to compare the timing relationship between the actual value and the reference value of the operating parameter.

[0007] For example, in the control circuit provided in at least one example of the above embodiments of this disclosure, the N operating parameters include numerical parameters and phase parameters, wherein the numerical parameters include at least one of voltage, current and temperature; the comparator is used to compare the numerical parameters, and the phase detector is used to compare the phase parameters.

[0008] For example, in the control circuit provided in at least one example of the above embodiments of this disclosure, each of the N comparison units includes a first output terminal and a second output terminal, the first output terminal and the second output terminal output a differential signal, the differential signal representing the comparison result; the multiplexing module includes a first multiplexer and a second multiplexer, the first multiplexer being connected to the first output terminal of each comparison unit, and the second multiplexer being connected to the second output terminal of each comparison unit; the first multiplexer and the second multiplexer receive the selection signal and output a differential signal of the first comparison unit corresponding to the selection signal based on the selection signal.

[0009] For example, in the control circuit provided in at least one example of the above embodiments of this disclosure, the control module includes a plurality of cascaded parameter configuration units, each of the plurality of cascaded parameter configuration units outputs a counting signal representing a single digit of the control parameter, and the counting signals output by the plurality of cascaded parameter configuration units constitute the control parameter; the bit width of the control parameter is equal to the number of cascaded parameter configuration units.

[0010] For example, in the control circuit provided in at least one example of the above embodiments of this disclosure, each of the plurality of cascaded parameter configuration units includes a clock signal input terminal, a status signal input terminal, a carry signal input terminal, a borrow signal input terminal, a count signal output terminal, a carry signal output terminal, a borrow signal output terminal, and a current-level status signal output terminal; the clock signal input terminals of the plurality of cascaded parameter configuration units receive the same clock signal, and the carry signal output terminal, borrow signal output terminal, and current-level status signal output terminal of adjacent preceding parameter configuration units are respectively connected to the carry signal input terminal, borrow signal input terminal, and status signal input terminal of subsequent parameter configuration units; for each parameter configuration unit, when either the carry signal output terminal or the borrow signal output terminal outputs a valid level, the current-level status signal output terminal outputs a valid level; the count signal output terminal is used to output the count signal.

[0011] For example, in the control circuit provided in at least one example of the above embodiments of this disclosure, when the comparison result of the first comparison unit indicates that one of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the plurality of parameter configuration units causes the control parameter to increase in binary; when the comparison result of the first comparison unit indicates that the other of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the plurality of parameter configuration units causes the control parameter to decrease in binary.

[0012] At least one embodiment of this disclosure provides a parameter configuration method, comprising: using N comparison units to compare the timing or numerical relationship between the actual values ​​and reference values ​​of N kinds of operating parameters; using a multiplexing module to output the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units; and using a control module to increase or decrease the value of a control parameter according to the comparison result of the first comparison unit, wherein the control parameter is used to adjust the first operating parameter corresponding to the first comparison unit among the N kinds of operating parameters, wherein N is an integer greater than or equal to 2.

[0013] At least one embodiment of this disclosure provides a chip including a control circuit and an operating parameter adjustment circuit. The control circuit includes a comparison module, a multiplexing module, and a control module. The comparison module includes N comparison units, each used to compare the timing or numerical relationship between the actual values ​​and reference values ​​of N operating parameters. The input terminal of the multiplexing module is connected to the N comparison units and outputs the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units. The control module is used to increase or decrease the value of a control parameter according to the comparison result of the first comparison unit. The operating parameter adjustment circuit is configured to adjust the first operating parameter corresponding to the first comparison unit among the N operating parameters according to the value of the control parameter, where N is an integer greater than or equal to 2.

[0014] For example, in a chip provided in at least one example of the above embodiments of this disclosure, the operating parameter adjustment circuit is further configured to: adjust the first operating parameter in a first direction when the control parameter increases; and adjust the first operating parameter in a second direction when the control parameter decreases.

[0015] For example, in a chip provided in at least one example of the above embodiments of this disclosure, any one of the N comparison units is a comparator or a phase detector. The comparator is used to compare the numerical relationship between the actual value and the reference value of the operating parameter, and the phase detector is used to compare the timing relationship between the actual value and the reference value of the operating parameter.

[0016] For example, in a chip provided in at least one example of the embodiments of this disclosure, each of the N comparison units includes a first output terminal and a second output terminal, the first output terminal and the second output terminal output a differential signal, the differential signal representing the comparison result; the multiplexing module includes a first multiplexer and a second multiplexer, the first multiplexer being connected to the first output terminal of each comparison unit, and the second multiplexer being connected to the second output terminal of each comparison unit; the first multiplexer and the second multiplexer receive the selection signal and output a differential signal of the first comparison unit corresponding to the selection signal based on the selection signal.

[0017] For example, in a chip provided in at least one example of the above embodiments of this disclosure, the control module includes a plurality of cascaded parameter configuration units, wherein the counting signal output by each of the plurality of cascaded parameter configuration units represents a single bit of the control parameter, and the counting signals output by the plurality of cascaded parameter configuration units constitute the control parameter; the bit width of the control parameter is equal to the number of cascaded parameter configuration units.

[0018] At least one embodiment of this disclosure provides an electronic device including the chip described in any of the above embodiments.

[0019] In the control circuit, parameter configuration method, chip, and electronic device provided in at least one embodiment of this disclosure, a multiplexing module is used to switch the comparison results of different operating parameters to adjust different operating parameters in a time-sharing manner. In this way, multiple operating parameters are adjusted using the same state machine circuit, which simplifies the circuit architecture, reduces the circuit area occupied, and reuses the same control module in the adjustment process of multiple operating parameters, which improves the reusability of the module and is beneficial to chip mass production calibration and subsequent performance maintenance. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 A schematic diagram of a control circuit provided in at least one embodiment of the present disclosure is shown;

[0022] Figure 2 A schematic diagram of a control module provided in at least one embodiment of the present disclosure is shown;

[0023] Figure 3 A schematic diagram of a counting signal provided in at least one embodiment of the present disclosure is shown;

[0024] Figure 4A schematic diagram of the circuit structure of a parameter configuration unit provided in at least one embodiment of the present disclosure is shown;

[0025] Figure 5 A schematic diagram of a circuit for generating an initial state signal is shown, according to at least one embodiment of the present disclosure;

[0026] Figure 6 A flowchart of a parameter configuration method provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 7 A schematic diagram of a chip provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0030] This disclosure relates to a state machine circuit for controlling a trim circuit, which autonomously configures and optimizes the trim circuit. The state machine circuit receives key performance indicators of the circuit in real time and compares them with corresponding reference data for evaluation. Based on the comparison results, it controls the trim circuit to adjust the circuit's operating parameters until the actual operating data is close to or the same as the reference data. For example, the state machine circuit increases or decreases the value of the control parameter output to the trim circuit based on the comparison result of the actual operating data and the reference data. The trim circuit determines the adjustment direction of the circuit's operating parameters based on the change in the control parameter value. For example, when the actual voltage value of the circuit is less than the reference voltage value, the state machine circuit increases the value of the control parameter output to the trim circuit, and the trim circuit increases the circuit voltage in response to the increase in the control parameter. Therefore, the state machine circuit increases or decreases the value of the control parameters by comparing the actual operating data of the circuit with the reference data, thereby controlling the trim circuit to adjust the operating parameters in the expected direction until the optimal fine-tuning working state that fits the current working conditions is found, and the automatic configuration locking of the trim circuit is completed. No external human intervention is required for debugging. It can adaptively compensate for the circuit performance deviation caused by process, voltage and temperature fluctuations, and further improve the working stability and environmental adaptability of analog circuits.

[0031] In some implementations, multiple state machine circuits are set up for various operating parameters of the circuit. The operating parameters of the circuit include voltage, current, temperature, clock phase, etc. Setting up a state machine circuit for each of these operating parameters requires multiple state machine circuits, which will result in redundant and complex circuit architecture, large area occupation, excessive hardware resource consumption, low design reusability, and is not conducive to chip mass production calibration and subsequent performance maintenance.

[0032] At least one embodiment of this disclosure provides a control circuit, a parameter configuration method, a chip, and an electronic device. The control circuit includes a comparison module, a multiplexing module, and a control module. The comparison module includes N comparison units, each used to compare the timing or numerical relationship between the actual values ​​and reference values ​​of N operating parameters. The input terminal of the multiplexing module is connected to the N comparison units, and outputs the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units. The control module is used to increase or decrease the value of a control parameter according to the comparison result of the first comparison unit. The control parameter is used to adjust the first operating parameter corresponding to the first comparison unit among the N operating parameters, where N is an integer greater than or equal to 2.

[0033] This control circuit uses a multiplexer module to switch between comparison results of different operating parameters, and adjusts different operating parameters in a time-sharing manner. In this way, multiple operating parameters can be adjusted using the same state machine circuit, which simplifies the circuit architecture, reduces the circuit area, and reuses the same control module for the adjustment process of multiple operating parameters, improving the reusability of the module and facilitating chip mass production calibration and subsequent performance maintenance.

[0034] Figure 1 A schematic diagram of a control circuit provided in at least one embodiment of the present disclosure is shown.

[0035] like Figure 1 As shown, the control circuit includes a comparison module 110, a multiplexer module 120, and a control module 130. The comparison module 110 includes N comparison units, each used to compare the timing or numerical relationship between the actual values ​​and reference values ​​of N operating parameters. The input terminal of the multiplexer module 120 is connected to the N comparison units, and it outputs the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units. The control module 130 is used to increase or decrease the value of a control parameter based on the comparison result of the first comparison unit. The control parameter is used to adjust the first operating parameter corresponding to the first comparison unit among the N operating parameters. Here, N is an integer greater than or equal to 2.

[0036] For example, any one of the N comparison units can be a comparator or a phase detector. The comparator is used to compare the numerical relationship between the actual value and the reference value of the operating parameter, while the phase detector is used to compare the timing relationship between the actual value and the reference value of the operating parameter. The actual value of the operating parameter is acquired in real time during circuit operation, while the reference value of the operating parameter can be preset.

[0037] For example, operating parameters refer to parameters used to represent the performance and state of a chip during operation, such as voltage, current, temperature, and clock phase. A corresponding comparison unit is set up for each operating parameter.

[0038] For example, N operating parameters include numerical parameters and phase parameters, where the numerical parameters include at least one of voltage, current, and temperature. A comparator is used to compare the numerical parameters, and a phase detector is used to compare the phase parameters.

[0039] like Figure 1As shown, the comparison module 110 includes a comparator 111 and a phase detector 112. The comparator 111 compares the magnitude of the acquired actual voltage with that of the reference voltage, and the phase detector 112 compares the sequence of the acquired actual clock phase with that of the reference clock phase. The comparator can also be represented as COMPRATOR, the phase detector as PHASE DETECTOR, the actual voltage as TRAIN_VOLTAGE, the reference voltage as REF_VOLTAGE, the actual clock phase as TRAIN_CLK, and the reference clock phase as REF_CLK. Similarly, in some of the following embodiments, the English words or abbreviations in parentheses after the names represent alternative representations of the names.

[0040] For example, the multiplexing module 120 connects the comparator module 110 and the control module (COUNTER) 130, and is used to switch the output of comparison results of different comparator units to the control module 130 at different time periods. The multiplexing module 120 receives a selection signal, which indicates which line of the multiplexing module 120 is selected to output the comparison result of the first comparator unit. The first comparator unit refers to the comparator unit corresponding to the selection signal, that is, the comparator unit selected by the selection signal. The first comparator unit can be any one of N comparator units. For example, in the first time period, the line corresponding to comparator 111 is selected to output the comparison result of comparator 111 to the control module 130; in the second time period, the line corresponding to phase detector 112 is selected to output the comparison result of phase detector 112 to the control module 130.

[0041] For example, the control module 130 is configured to increase or decrease the value of the control parameter according to the comparison result of the first comparison unit, and output the value of the control parameter to the operating parameter adjustment circuit (trim circuit), so that the operating parameter adjustment circuit adjusts the first operating parameter corresponding to the first comparison unit among N operating parameters according to the value of the control parameter. The first operating parameter corresponding to the first comparison unit is the operating parameter compared by the first comparison unit, that is, the data received by the first comparison unit is the data of the first operating parameter (actual value and reference value).

[0042] For example, the control module 130 can be implemented as a counting module, where the counted value is the value of the control parameter. When the comparison result of the first comparison unit is a first result (e.g., the reference value is greater than the actual value), the count is increased; when the comparison result of the first comparison unit is a second result (e.g., the reference value is less than the actual value), the count is decreased. Correspondingly, when the count increases, the operating parameter adjustment circuit adjusts the first operating parameter in the first direction (e.g., increases the value or delays the timing); when the count decreases, the operating parameter adjustment circuit adjusts the first operating parameter in the first direction (e.g., decreases the value or advances the timing), thus adjusting the first operating parameter in the expected direction. The actual value of the adjusted first operating parameter is fed back to the comparison module, which then outputs the comparison result to the control module 130 via the multiplexing module. The control module 130 increases or decreases the control parameter again based on the comparison result to control the operating parameter adjustment circuit to readjust the first operating parameter. This cycle continues until the actual value of the adjusted first operating parameter is close to or equal to the reference value (e.g., adjusting the first operating parameter so that the comparator determines the actual value is equal to the reference value).

[0043] For example, if the actual voltage value is less than the reference value, the control module 130 receives this comparison result and increases the value of the control parameter to control the trim circuit to increase the voltage. The adjusted actual voltage value is fed back to the comparison module 110. If the actual value is still less than the reference value, the control module 130 further increases the value of the control parameter to control the trim circuit to further increase the voltage. This process is repeated until the actual value of the adjusted first operating parameter is determined by the comparator to be equal to the reference value.

[0044] For example, the control circuit can be a state machine circuit. The state machine circuit increases or decreases the value of the control parameter by comparing the actual data of the operating parameter with the reference data, thereby controlling the trim circuit to adjust the operating parameter in the expected direction until the optimal fine-tuning working state that fits the current working conditions is found, thus completing the automatic configuration of the trim circuit.

[0045] For example, once the first operating parameter is adjusted to the expected result, if another operating parameter needs to be adjusted, the selection signal can be updated. In response to the updated selection signal, the multiplexing module switches to output the comparison result of another comparison module, thus enabling the adjustment of another operating parameter.

[0046] According to at least one embodiment of this disclosure, a multiplexing module is used to switch the comparison results of different operating parameters to adjust different operating parameters in a time-sharing manner. In this way, multiple operating parameters can be adjusted using the same state machine circuit, which simplifies the circuit architecture, reduces the circuit area occupied, and reuses the same control module for the adjustment process of multiple operating parameters, which improves the reusability of the module and is beneficial to chip mass production calibration and subsequent performance maintenance.

[0047] For example, each of the N comparison units includes a first output terminal and a second output terminal. The first output terminal and the second output terminal output a differential signal, which represents the comparison result.

[0048] For example, such as Figure 1 As shown, comparator 111 outputs differential signals at its two output terminals. For example, when the actual value is less than the reference value, the first output terminal outputs a high level and the second output terminal outputs a low level; when the actual value is greater than the reference value, the first output terminal outputs a low level and the second output terminal outputs a high level. Phase detector 112 outputs differential signals at its two output terminals. When the actual phase of the clock lags behind the reference phase, the first output terminal outputs a high level and the second output terminal outputs a low level; when the actual phase of the clock leads the reference phase, the first output terminal outputs a low level and the second output terminal outputs a high level. In this way, by using the differential signals as the comparison result output, the control module can bidirectionally adjust the control parameters, and thus bidirectionally adjust the operating parameters.

[0049] For example, the multiplexing module 120 includes a first multiplexer 121 and a second multiplexer 122. The first multiplexer 121 is connected to the first output terminal of each comparison unit, and the second multiplexer 122 is connected to the second output terminal of each comparison unit. The first multiplexer 121 and the second multiplexer 122 receive a selection signal (IN_SEL) and output a differential signal of the first comparison unit corresponding to the selection signal IN_SEL.

[0050] For example, the state machine controls the input source of the multiplexing module through the IN_SEL signal. When the IN_SEL signal is 1'b0, the output of the multiplexing module is the comparison result of comparator 111; when the IN_SEL signal is 1'b1, the output of the multiplexing module is the comparison result of phase detector 112.

[0051] For example, the control module includes multiple cascaded parameter configuration units. The counting signal output by each of the multiple cascaded parameter configuration units represents a single bit of the control parameter. The counting signals output by the multiple cascaded parameter configuration units constitute the control parameter. The bit width of the control parameter is equal to the number of cascaded parameter configuration units.

[0052] Figure 2 A schematic diagram of a control module provided in at least one embodiment of the present disclosure is shown, wherein (a) is a schematic block diagram of the control module (COUNTER), and (b) shows a plurality of cascaded parameter configuration units (COUNTER_UNIT), which are also referred to as counter units in some of the following embodiments.

[0053] like Figure 2As shown, the control module includes multiple cascaded parameter configuration units, such as the first-level parameter configuration unit 201 to the fourth-level parameter configuration unit 204. These multiple parameter configuration units are connected in series. Each parameter configuration unit outputs a first counting signal (code signal) and a second counting signal (codeb signal) for its level. The codeb signal is the opposite of the code signal, thus implementing bidirectional counting control logic (addition / subtraction). The multiple levels of code / codeb signals constitute the control parameters, with each level representing one bit of the control parameter. The number of bits from the first level to the nth level increases sequentially from low to high, where n is an integer greater than 1. In this way, the number of parameter configuration units can be set according to the desired code bit width, thereby enabling various bit widths to adapt to different application scenarios.

[0054] For example, each parameter configuration unit in a series of cascaded parameter configuration units includes a clock signal input (CLK), a status signal input (IN), a carry signal input (UP), a borrow signal input (DOWN), a first count output (code), a second count output (codeb), a carry signal output (UP_OUT), a borrow signal output (DOWN_OUT), and a status signal output (OUT) for this stage. The carry signal input (UP) and borrow signal input (DOWN) of the first-stage parameter configuration unit receive the differential signal output from the first comparison unit selected by the multiplexing module. The status signal input (IN) of the first-stage parameter configuration unit receives the initial status signal (TIEL), which may be, for example, a low level. Multiple cascaded parameter configuration units receive the same clock signal (CLK) at their clock signal inputs. The carry signal output (UP_OUT) and borrow signal output (DOWN_OUT) of adjacent preceding parameter configuration units are connected to the carry signal input (UP) and borrow signal input (DOWN) of the following parameter configuration unit, respectively. The status signal output (OUT) of the preceding parameter configuration unit is connected to the status signal input (IN) of the following parameter configuration unit. For each parameter configuration unit, when either the carry signal output (UP_OUT) or the borrow signal output (DOWN_OUT) outputs a valid level (e.g., active high), the status signal output (OUT) of that unit outputs a valid level. The count signal outputs (code and codeb) are used to output the count signal.

[0055] For example, when the comparison result of the first comparison unit indicates that one of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the multiple parameter configuration units causes the control parameter to increase in binary form; when the comparison result of the first comparison unit indicates that the other of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the multiple parameter configuration units causes the control parameter to decrease in binary form.

[0056] Figure 3 A schematic diagram of a counting signal provided in at least one embodiment of the present disclosure is shown.

[0057] like Figure 3 As shown, the control parameter has a bit width of 4, and the first counting signal (code) of the first stage. <0> 0 indicates the first counting signal (code) from the first level to the fourth level. <3> , 3 indicates the fourth level) represent the first to fourth bits of the control parameter respectively, code <0> To code <3> The system uses binary. If the UP signal remains in the first state (e.g., high level), each time the clock signal goes high, the code output by the first-stage counter unit increases from its initial value of 0 by 1 until it reaches its maximum value (1 in binary). When the next clock cycle arrives, the code flips to its minimum value of 0, triggering the next-stage counter unit to increase its code from its initial value of 0 by 1, and so on, achieving a binary linear increase in the value of the control parameter (code value). For example, before the start of the first clock cycle, the initial value of the control parameter is 0000. If the UP signal remains high, when the rising edge of the first clock cycle arrives, the first-stage code increases from its initial value of 0 by 1, and the control parameter is updated to 0001; when the rising edge of the second clock cycle arrives, the first-stage code flips from 1 to 0, triggering the second-stage code to increase from its initial value of 0 by 1, and the control parameter is updated to 0010; when the rising edge of the third clock cycle arrives, the first-stage code increases from 0 to 1, and the control parameter is updated to 0011, and so on. If the UP signal remains high, the value of the control parameter will increase linearly in binary until the UP signal becomes 0 or low. Conversely, if the UP signal changes to the second state (such as low level) and remains there, the value of the control parameter decreases linearly in binary.

[0058] Figure 4 A schematic diagram of the circuit structure of a parameter configuration unit provided in at least one embodiment of the present disclosure is shown, wherein (a) is a schematic block diagram of the parameter configuration unit and (b) shows the circuit structure of the parameter configuration unit.

[0059] like Figure 4As shown, the parameter configuration unit includes a synchronous state latch composed of four sets of cross-coupled NAND gates. The four sets of NAND gates include a first NAND gate 401, a second NAND gate 402, a third NAND gate 403, and a fourth NAND gate 404. The clock signal input (CLK) of this state latch is connected to a common clock signal, the state signal input (IN) is connected to the current stage's state input signal, and the two count signal outputs output complementary state signals (code and codeb). The parameter configuration unit also includes an addition control path, including a first AND gate 405. The two inputs of the first AND gate 405 are connected to the previous stage's carry signal (UP) and the count signal (code), respectively, and the output outputs the current stage's carry output signal (UP_OUT). The parameter configuration unit also includes a subtraction control path, including a second AND gate 406. The two inputs of the second AND gate 406 are connected to the previous stage's borrow control signal (DOWN) and the count signal (codeb), respectively, and the output outputs the current stage's borrow output signal (DOWN_OUT). When the UP signal is valid and the current stage's state allows incrementing, a carry output is generated; when the DOWN signal is valid and the current stage's state allows decrementing, a borrow output is generated. The parameter configuration unit also includes an enable merging path, comprising an OR gate 407. The two inputs of the OR gate 407 are connected to the outputs of the addition control path and the subtraction control path, respectively. The output generates the current stage's state output signal (OUT), which is passed to the next-level parameter configuration unit. The OR gate 407 merges the carry / borrow signals (increment / decrement enable signals) of the current stage, outputting the valid counting enable for the current stage, which is then passed to the next level.

[0060] For example, Figure 4 In the circuit structure shown, all units share a common clock signal (CLK), and state transitions are controlled synchronously by the clock, with no asynchronous transmission delay. Through dual control paths (UP / DOWN), it supports bidirectional counting for addition and subtraction, enabling bidirectional adjustment. The carry signal output (UP_OUT) and borrow signal output (DOWN_OUT) can be directly connected to the carry signal input (UP) and borrow signal input (DOWN) of the next stage, expanding it into a multi-bit synchronous counter. `code` and `codeb` are complementary signals, driving the addition / subtraction control paths respectively, ensuring that the addition and subtraction logic is mutually exclusive and conflict-free.

[0061] For example, see again Figure 3The timing diagram shows that the toggle condition of the higher-order cells is determined by the state of the lower-order cells, and all cells update their states synchronously on the clock edge. For binary addition counting, the toggle rule for each stage of the cell is: the least significant bit (code)... <0> It toggles once on each valid clock edge (e.g., rising edge) (0 toggles to 1, 1 to 0, and so on), with a period twice the clock cycle; for code <1> Only when code <0> When = 1, the clock will flip only on the next valid clock edge, and its period is 4 times the clock period. Its flip frequency is code. <0> Half of the code; <2> Only when code <0> = 1 and code <1> When = 1, the clock will flip only on the next valid clock edge; the flip frequency is code. <1> Half of it, its period is 8 times the clock period; for code <3> Only when code <0> = 1、code <1> = 1、code <2> When = 1, the flip will only occur on the next valid clock edge. Its flip frequency is the slowest among the four-level units, and its period is 16 times the clock period.

[0062] For example, such as Figure 1 As shown, the state machine circuit can change the direction of code flipping by using the flip signal (CODE_REVERT).

[0063] Figure 5 A schematic diagram of a circuit for generating an initial state signal is shown, according to at least one embodiment of the present disclosure.

[0064] like Figure 5 As shown, the circuit consists of two MOS transistors (PMOS 501 and NMOS 502) connected in series. The source of the PMOS is connected to the operating voltage (VDD), and the gate and drain are also connected to node X. This connection structure creates a small leakage current (subthreshold leakage current) between the source and drain of the PMOS, slowly pulling its drain node (the gate of the NMOS below) to a high level. When the gate of the NMOS is pulled close to the power supply voltage, the NMOS turns on, forming a low-impedance path between its drain (i.e., the TIEL output terminal) and ground, thus forcing the drain output to a stable low level. The drain is the initial state signal output terminal (TIEL output terminal), and the output signal is the initial state signal TIEL.

[0065] For example, the control circuit according to at least one embodiment of this disclosure can be directly constructed using standard cells (stdcell, i.e., standard cells, standardized logic units in semiconductor design, such as NAND gates) to complete the circuit design, without going through the conventional RTL (Register Transfer Level) design process of digital engineers. Therefore, the embodiments of this disclosure adopt the method of directly constructing standard cells, which simplifies the circuit design process, reduces logic redundancy caused by the synthesis process, and effectively compresses the circuit layout area compared to the traditional design scheme of combining RTL encoding with logic synthesis.

[0066] For example, the control circuit according to at least one embodiment of the present disclosure achieves the purpose of linearly increasing the control word according to the criterion state through logic gates, and the phase criterion state machine and the analog voltage state machine can be implemented respectively by switching different input terminals.

[0067] At least one embodiment of this disclosure also provides a parameter configuration method.

[0068] Figure 6 A flowchart of a parameter configuration method provided by at least one embodiment of the present disclosure is shown.

[0069] like Figure 6 As shown, the method may include steps S610 to S630.

[0070] Step S610: Use N comparison units to compare the timing or numerical relationships between the actual values ​​and reference values ​​of N operating parameters. Here, N is an integer greater than or equal to 2.

[0071] Step S620: Use the multiplexing module to output the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units.

[0072] Step S630: The control module increases or decreases the value of the control parameter according to the comparison result of the first comparison unit. The control parameter is used to adjust the first operating parameter corresponding to the first comparison unit among N operating parameters.

[0073] For example, the parameter configuration method includes: in response to a selection signal update, the multiplexing module switches to outputting the comparison result of the second comparison module.

[0074] This parameter configuration method utilizes a multiplexer module to switch between comparison results of different operating parameters, thereby adjusting different operating parameters in a time-sharing manner. In this way, multiple operating parameters can be adjusted using the same state machine circuit, simplifying the circuit architecture, reducing the circuit footprint, and reusing the same control module for the adjustment process of multiple operating parameters, improving the reusability of the module, which is beneficial for chip mass production calibration and subsequent performance maintenance.

[0075] For details regarding the parameter configuration method, please refer to the description of any of the above embodiments, which will not be repeated here.

[0076] At least one embodiment of this disclosure also provides a chip.

[0077] Figure 7 A schematic diagram of a chip provided in at least one embodiment of the present disclosure is shown.

[0078] like Figure 7 As shown, the chip 700 includes a control circuit 710 and an operating parameter adjustment circuit 720. The control circuit 710 includes a comparison module, a multiplexing module, and a control module. The comparison module includes N comparison units, which are used to compare the timing or numerical relationships between the actual values ​​and reference values ​​of N operating parameters. The input terminal of the multiplexing module is connected to the N comparison units and outputs the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units. The control module is used to increase or decrease the value of the control parameter according to the comparison result of the first comparison unit. The operating parameter adjustment circuit is configured to adjust the first operating parameter corresponding to the first comparison unit among the N operating parameters according to the value of the control parameter, where N is an integer greater than or equal to 2.

[0079] For example, in a chip provided in at least one example of the above embodiments of this disclosure, the operating parameter adjustment circuit is further configured to: adjust the first operating parameter in a first direction when the control parameter increases; and adjust the first operating parameter in a second direction when the control parameter decreases.

[0080] For example, in a chip provided in at least one example of the above embodiments of this disclosure, the control module is configured to output control parameters to the operating parameter adjustment circuit, so that the operating parameter adjustment circuit adjusts the first operating parameter corresponding to the first comparison unit among N operating parameters according to the value of the control parameters.

[0081] For example, in the chip provided in at least one example of the above embodiments of this disclosure, any one of the N comparison units is a comparator or a phase detector. The comparator is used to compare the numerical relationship between the actual value and the reference value of the operating parameter, and the phase detector is used to compare the timing relationship between the actual value and the reference value of the operating parameter.

[0082] For example, in the chip provided in at least one example of the above embodiments of this disclosure, the N operating parameters include numerical parameters and phase parameters, wherein the numerical parameters include at least one of voltage, current and temperature; a comparator is used to compare the numerical parameters, and a phase detector is used to compare the phase parameters.

[0083] For example, in a chip provided by at least one example of the above embodiments of this disclosure, each of the N comparison units includes a first output terminal and a second output terminal, the first output terminal and the second output terminal output a differential signal, the differential signal representing the comparison result; the multiplexing module includes a first multiplexer and a second multiplexer, the first multiplexer is connected to the first output terminal of each comparison unit, and the second multiplexer is connected to the second output terminal of each comparison unit; the first multiplexer and the second multiplexer receive a selection signal and output a differential signal of the first comparison unit corresponding to the selection signal based on the selection signal.

[0084] For example, in the chip provided in at least one example of the above embodiments of this disclosure, the control module includes a plurality of cascaded parameter configuration units, and the counting signal output by each of the plurality of cascaded parameter configuration units represents a single bit of the control parameter, and the counting signals output by the plurality of cascaded parameter configuration units constitute the control parameter; the bit width of the control parameter is equal to the number of cascaded parameter configuration units.

[0085] For example, in the chip provided in at least one example of the above embodiments of this disclosure, each of the multiple cascaded parameter configuration units includes a clock signal input terminal, a status signal input terminal, a carry signal input terminal, a borrow signal input terminal, a count signal output terminal, a carry signal output terminal, a borrow signal output terminal, and a status signal output terminal of the current stage; the clock signal input terminals of the multiple cascaded parameter configuration units receive the same clock signal, the carry signal output terminal and borrow signal output terminal of the adjacent preceding parameter configuration unit are respectively connected to the carry signal input terminal and borrow signal input terminal of the following parameter configuration unit, the status signal output terminal of the preceding parameter configuration unit is connected to the status signal input terminal of the following parameter configuration unit, and the count signal output terminal is used to output a count signal.

[0086] For example, in a chip provided in at least one example of the above embodiments of this disclosure, when the comparison result of the first comparison unit indicates that one of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the multiple parameter configuration units causes the control parameter to increase in binary; when the comparison result of the first comparison unit indicates that the other of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the multiple parameter configuration units causes the control parameter to decrease in binary.

[0087] This chip uses a multiplexer module to switch between comparison results of different operating parameters, and adjusts different operating parameters in a time-sharing manner. In this way, multiple operating parameters can be adjusted using the same state machine circuit, which simplifies the circuit architecture, reduces the circuit area, and reuses the same control module for the adjustment process of multiple operating parameters, improving the reusability of the module and facilitating chip mass production calibration and subsequent performance maintenance.

[0088] For details regarding the chip, please refer to the description of any of the above embodiments, which will not be repeated here.

[0089] This disclosure provides at least one embodiment of an electronic device that includes the chip of any of the above embodiments. For details regarding this electronic device, please refer to the description of any of the above embodiments, which will not be repeated here.

[0090] For example, in some embodiments, the electronic device can be a mobile phone, tablet computer, television, monitor, laptop computer, wearable electronic device, smart home device, etc.

[0091] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0092] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0093] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0094] The following points should be noted regarding this disclosure:

[0095] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0096] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0097] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A control circuit, characterized in that, include: The comparison module includes N comparison units, which are used to compare the timing or numerical relationship between the actual values ​​and reference values ​​of N kinds of operating parameters. The multiplexing module has its input connected to the N comparison units and outputs the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units; as well as The control module is used to increase or decrease the value of a control parameter based on the comparison result of the first comparison unit, wherein the control parameter is used to adjust the first operating parameter corresponding to the first comparison unit among the N operating parameters. The N operating parameters are N different operating parameters selected from voltage, current, temperature, and clock phase. The control module is configured to output the control parameters to the operating parameter adjustment circuit, so that the operating parameter adjustment circuit adjusts the first operating parameter corresponding to the first comparison unit among the N operating parameters according to the value of the control parameters. Where N is an integer greater than or equal to 2.

2. The control circuit according to claim 1, characterized in that, Any of the N comparison units is a comparator or a phase detector. The comparator is used to compare the numerical relationship between the actual value and the reference value of the operating parameter, and the phase detector is used to compare the timing relationship between the actual value and the reference value of the operating parameter.

3. The control circuit according to claim 2, characterized in that, The N operating parameters include numerical parameters and phase parameters, wherein the numerical parameters include at least one of voltage, current and temperature; The comparator is used to compare the numerical parameters, and the phase detector is used to compare the phase parameters.

4. The control circuit according to claim 1, characterized in that, Each of the N comparison units includes a first output terminal and a second output terminal, and the first output terminal and the second output terminal output a differential signal, the differential signal representing the comparison result; The multiplexing module includes a first multiplexer and a second multiplexer, wherein the first multiplexer is connected to the first output terminal of each comparison unit, and the second multiplexer is connected to the second output terminal of each comparison unit; The first multiplexer and the second multiplexer receive the selection signal and output a differential signal of the first comparison unit corresponding to the selection signal based on the selection signal.

5. The control circuit according to any one of claims 1-4, characterized in that, The control module includes multiple cascaded parameter configuration units. The counting signal output by each of the multiple cascaded parameter configuration units represents a single digit of the control parameter. The counting signals output by the multiple cascaded parameter configuration units constitute the control parameter. The bit width of the control parameters is equal to the number of cascaded parameter configuration units.

6. The control circuit according to claim 5, characterized in that, Each of the multiple cascaded parameter configuration units includes a clock signal input terminal, a status signal input terminal, a carry signal input terminal, a borrow signal input terminal, a count signal output terminal, a carry signal output terminal, a borrow signal output terminal, and a status signal output terminal of the current stage. The clock signal input terminals of the multiple cascaded parameter configuration units receive the same clock signal. The carry signal output terminal, borrow signal output terminal, and current status signal output terminal of the adjacent preceding parameter configuration unit are respectively connected to the carry signal input terminal, borrow signal input terminal, and current status signal input terminal of the following parameter configuration unit. For each parameter configuration unit, when either the carry signal output terminal or the borrow signal output terminal outputs a valid level, the current level status signal output terminal outputs a valid level. The counting signal output terminal is used to output the counting signal.

7. The control circuit according to claim 6, characterized in that, When the comparison result of the first comparison unit indicates that one of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the plurality of cascaded parameter configuration units causes the control parameter to increase in binary order. When the comparison result of the first comparison unit indicates that the other of the actual value and the reference value is larger or the timing is ahead, the counting signal output by the plurality of cascaded parameter configuration units causes the control parameter to decrease in binary form.

8. A parameter configuration method, characterized in that, include: N comparison units are used to compare the timing or numerical relationships between the actual values ​​and reference values ​​of N types of operating parameters; The comparison result of the first comparison unit corresponding to the selection signal among the N comparison units is output using the multiplexing module; as well as The control module increases or decreases the value of the control parameter based on the comparison result of the first comparison unit. The control parameter is used to adjust the first operating parameter among the N operating parameters that corresponds to the first comparison unit. The N operating parameters are N different operating parameters selected from voltage, current, temperature, and clock phase. The parameter configuration method further includes: outputting the control parameters to an operating parameter adjustment circuit, so that the operating parameter adjustment circuit adjusts the first operating parameter corresponding to the first comparison unit among the N operating parameters according to the value of the control parameters. Where N is an integer greater than or equal to 2.

9. A chip, characterized in that, include: Control circuit; as well as Run the parameter adjustment circuit. The control circuit includes: The comparison module includes N comparison units, which are used to compare the timing or numerical relationship between the actual values ​​and reference values ​​of N kinds of operating parameters. A multiplexing module, with its input connected to the N comparison units, and outputting the comparison result of the first comparison unit corresponding to the selection signal among the N comparison units; and The control module is used to increase or decrease the value of the control parameter according to the comparison result of the first comparison unit; The operating parameter adjustment circuit is configured to adjust the first operating parameter corresponding to the first comparison unit among the N operating parameters according to the value of the control parameter. The control module is configured to output the control parameters to the operating parameter adjustment circuit, so that the operating parameter adjustment circuit adjusts the first operating parameter corresponding to the first comparison unit among the N operating parameters according to the value of the control parameters. The N operating parameters are N different operating parameters selected from voltage, current, temperature, and clock phase. Where N is an integer greater than or equal to 2.

10. The chip according to claim 9, characterized in that, The operating parameter adjustment circuit is further configured as follows: When the control parameter increases, the first operating parameter is adjusted in the first direction; When the control parameter decreases, the first operating parameter is adjusted in the second direction.

11. The chip according to claim 9, characterized in that, Any of the N comparison units is a comparator or a phase detector. The comparator is used to compare the numerical relationship between the actual value and the reference value of the operating parameter, and the phase detector is used to compare the timing relationship between the actual value and the reference value of the operating parameter.

12. The chip according to claim 9, characterized in that, Each of the N comparison units includes a first output terminal and a second output terminal, and the first output terminal and the second output terminal output a differential signal, the differential signal representing the comparison result; The multiplexing module includes a first multiplexer and a second multiplexer, wherein the first multiplexer is connected to the first output terminal of each comparison unit, and the second multiplexer is connected to the second output terminal of each comparison unit; The first multiplexer and the second multiplexer receive the selection signal and output a differential signal of the first comparison unit corresponding to the selection signal based on the selection signal.

13. The chip according to any one of claims 9-12, characterized in that, The control module includes multiple cascaded parameter configuration units. The counting signal output by each of the multiple cascaded parameter configuration units represents a single digit of the control parameter. The counting signals output by the multiple cascaded parameter configuration units constitute the control parameter. The bit width of the control parameters is equal to the number of cascaded parameter configuration units.

14. An electronic device, characterized in that, Includes the chip as described in any one of claims 9-13.

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