Cache processing method and apparatus, electronic device, and storage medium

Abstract

The present disclosure provides a cache processing method and device, electronic equipment and storage medium, which are related to the field of chips, and the main technical features include: storing target data in a corresponding cache queue based on a virtualization process identifier to which the target data belongs; wherein the virtualization process identifier includes a virtual function identifier and a process identifier; in response to a received processing instruction, determining a target cache queue corresponding to a target virtualization process identifier in the processing instruction from each cache queue; performing a targeted flushing process on the target cache queue to transfer the target data in the target cache queue out.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more particularly to a cache processing method and apparatus, electronic device and storage medium. Background Technology

[0002] In virtualized architecture, various business systems commonly use cache queues to temporarily store data generated during operation. Cache flushing is a common processing method to remove data from the cache queue.

[0003] Currently, most caching solutions employ a global flushing model, which flushes all cache queues in the system upon receiving a processing instruction. However, in scenarios with multiple virtual function instances or multiple processes coexisting, data from different sources may be temporarily stored in the same or different cache queues. The global flushing model will also remove irrelevant data during the flushing process. Summary of the Invention

[0004] Based on this, the present disclosure provides a caching processing method, apparatus, electronic device, and storage medium. Its main purpose is to solve the above-mentioned technical problems.

[0005] According to a first aspect of this disclosure, a caching method is provided, comprising: Based on the virtualization process identifier to which the target data belongs, the target data is stored in the corresponding cache queue; wherein, the virtualization process identifier includes a virtual function identifier and a process identifier; In response to the received processing instruction, the target cache queue corresponding to the target virtualization process identifier in the processing instruction is determined from each cache queue; A targeted flushing process is performed on the target cache queue to transfer the target data out of the target cache queue.

[0006] In some embodiments, storing the target data in a corresponding cache queue based on the virtualization process identifier to which the target data belongs includes: Extract the target virtual function identifier and target process identifier associated with the target data; The target virtual function identifier and the target process identifier are matched in parallel with the virtual function identifier and process identifier stored in multiple pre-configured matching registers to determine the target matching register; wherein the target matching register is enabled, and the target virtual function identifier is consistent with the virtual function identifier stored in the target matching register, and the target process identifier is consistent with the process identifier stored in the target matching register. The target data is written into the cache queue corresponding to the target matching register.

[0007] In some embodiments, the method further includes: If the virtual function identifier and process identifier stored in all enabled matching registers are inconsistent with the target virtual function identifier and the target process identifier, then the target data is written to the default cache queue; wherein the default cache queue does not respond to the processing instruction.

[0008] In some embodiments, before determining the target cache queue corresponding to the target virtualization process identifier in the processing instruction from each cache queue, the method further includes: Verify the validity of the target virtualization process identifier in the processing instruction; If the target virtualization process identifier is invalid, the processing instruction will not be executed, and a flush error status will be output.

[0009] In some embodiments, performing a targeted flushing process on the target cache queue to transfer the target data out of the target cache queue includes: Determine whether the length of the target data meets the bus transmission specifications; If the conditions are met, the target data in the target cache queue will be transferred out. If the conditions are not met, placeholder data is added to the target data to obtain supplemented target data, and the supplemented target data is then transferred out; wherein, the supplemented target data meets the bus transmission specifications.

[0010] In some embodiments, during the process of transferring target data out of the target cache queue, the method further includes: Monitor the bus transmission status of the target data and the queue status of the target cache queue; When an abnormality is detected in the bus transmission status and / or the queue status of the target buffer queue, the transfer of the target data is terminated and a flush error status is output.

[0011] In some embodiments, the method further includes: The status register is updated according to the processing status of the processing instruction; wherein the status register is used to indicate the idle state, the flushing in progress state, the flushing completed state, or the flushing error state.

[0012] According to a second aspect of this disclosure, a cache processing apparatus is provided, comprising: A storage unit is used to store the target data in a corresponding cache queue based on the virtualization process identifier to which the target data belongs; wherein the virtualization process identifier includes a virtual function identifier and a process identifier; The determining unit is configured to, in response to a received processing instruction, determine from each cache queue the target cache queue corresponding to the target virtualization process identifier in the processing instruction; The processing unit is used to perform a targeted flushing process on the target cache queue, and to transfer the target data out of the target cache queue.

[0013] In some embodiments, the storage unit includes: The extraction module is used to extract the target virtual function identifier and target process identifier associated with the target data; The matching module is used to perform parallel matching of the target virtual function identifier and the target process identifier with virtual function identifiers and process identifiers stored in multiple pre-configured matching registers respectively, to determine the target matching register; wherein, the target matching register is enabled, and the target virtual function identifier is consistent with the virtual function identifier stored in the target matching register, and the target process identifier is consistent with the process identifier stored in the target matching register. The first writing module is used to write the target data into the cache queue corresponding to the target matching register.

[0014] In some embodiments, the apparatus further includes: The second write module is used to write the target data into a default cache queue when all virtual function identifiers and process identifiers stored in the matching registers that are enabled are inconsistent with the target virtual function identifier and the target process identifier; wherein the default cache queue does not respond to the processing instruction.

[0015] In some embodiments, the apparatus further includes: A verification unit is configured to verify the validity of the target virtualization process identifier in the processing instruction before the determining unit determines the target cache queue corresponding to the target virtualization process identifier in the processing instruction from each cache queue; The first output unit is configured to not execute the processing instructions and output a flush error status when the target virtualization process identifier is invalid.

[0016] In some embodiments, the processing unit includes: The judgment module is used to determine whether the length of the target data meets the bus transmission specifications. The first transfer module is used to transfer the target data out of the target cache queue when the conditions are met. The second transfer module is used to supplement placeholder data into the target data when the target data is not satisfied, to obtain the supplemented target data, and to transfer the supplemented target data out; wherein the supplemented target data satisfies the bus transmission specification.

[0017] In some embodiments, the apparatus further includes: The monitoring unit is used to monitor the bus transmission status of the target data and the queue status of the target cache queue during the process of the processing unit transferring the target data out of the target cache queue. The second output unit is used to terminate the transfer of the target data and output a flush error status when an abnormality is detected in the bus transmission status and / or the queue status of the target buffer queue.

[0018] In some embodiments, the apparatus further includes: An update unit is used to update a status register according to the processing status of the processing instruction; wherein the status register is used to indicate an idle state, a flushing in progress state, a flushing completed state, or a flushing error state.

[0019] According to a third aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.

[0020] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.

[0021] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0022] In summary, the caching processing method, apparatus, electronic device, and storage medium provided in this disclosure include: storing the target data in a corresponding cache queue based on the virtualization process identifier to which the target data belongs; determining, in response to a received processing instruction, a target cache queue corresponding to the target virtualization process identifier in the processing instruction from among the various cache queues; and performing a targeted flushing process on the target cache queue to remove the target data from the target cache queue. Compared with related technologies, the solution of this disclosure can achieve data queue-based storage based on the virtualization process identifier and select a target cache queue for targeted flushing processing according to the processing instruction, without needing to flush all cache queues, thus achieving targeted processing of cached data.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0024] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is a schematic flowchart of a caching method provided in an embodiment of the present disclosure; Figure 2 This is a schematic flowchart of another caching method provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of a target data flushing process provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the structure of a cache processing device provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of another cache processing device provided in an embodiment of the present disclosure; Figure 6 This is a schematic block diagram of an example electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0025] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0026] The following description, with reference to the accompanying drawings, describes a caching method, apparatus, electronic device, and storage medium according to embodiments of the present disclosure.

[0027] Figure 1 This is a schematic flowchart of a caching method provided in an embodiment of the present disclosure.

[0028] like Figure 1 As shown, the method includes steps 101-103.

[0029] Step 101: Based on the virtualization process identifier to which the target data belongs, store the target data in the corresponding cache queue; wherein, the virtualization process identifier includes a virtual function identifier and a process identifier.

[0030] In some embodiments, the virtualization process identifier is identification information used to distinguish different virtual function instances and data from different process sources. In chips or systems supporting virtualization technology, multiple virtual function instances can run simultaneously on a single physical hardware device, and each virtual function instance can run multiple processes. Different virtual function instances and different processes generate their own data during operation; to distinguish the source of this data, each piece of data is associated with a corresponding virtualization process identifier.

[0031] A cache queue is a hardware storage unit within the chip used to temporarily store data to be transferred out. The system pre-configures multiple cache queues, with different virtualization process identifiers corresponding to different cache queues. When target data is generated, it is stored in the cache queue corresponding to the virtualization process identifier, based on the identifier associated with that data. Thus, data with different virtualization process identifiers is stored in their respective cache queues, and the data stored in each cache queue belongs to the same virtualization process identifier.

[0032] A Virtual Function Identifier (VFID) is used to distinguish different virtual function instances, while a Process Identifier (PID) is used to distinguish different processes within the same virtual function instance. A virtualization process identifier is composed of both a VFID and a PID; a combination of a VFID and a PID uniquely corresponds to a single virtualization process identifier.

[0033] The above method enables the storage of data corresponding to different virtualization process identifiers in separate queues, so that the data in each cache queue is associated with a single virtualization process identifier.

[0034] Step 102: In response to the received processing instruction, determine the target cache queue corresponding to the target virtualization process identifier in the processing instruction from each cache queue.

[0035] In some embodiments, the processing instruction is a control signal or command used to trigger a data transfer operation from the cache queue. The processing instruction carries a target virtualization process identifier, which indicates the virtualization process identifier for which the transfer operation needs to be performed.

[0036] Upon receiving a processing instruction, the system identifies the cache queue corresponding to the target virtualization process identifier carried in the instruction from among the configured cache queues, and designates that cache queue as the target cache queue. The target cache queue is the cache queue targeted by this directed flushing operation.

[0037] Using the above method, the target cache queue that needs to be transferred out is located from multiple cache queues based on the target virtualization process identifier carried in the processing instruction.

[0038] Step 103: Perform a targeted flushing process on the target cache queue to transfer the target data out of the target cache queue.

[0039] In some embodiments, targeted flushing refers to a cache data transfer operation performed only on a target cache queue. After determining the target cache queue, targeted flushing is performed on it, transferring the target data temporarily stored in the target cache queue to external memory via a bus transmission path for reading and use by software or other processing units. During targeted flushing, data in other cache queues outside the target cache queue does not participate in this transfer operation, and the data in other cache queues remains unchanged.

[0040] By using the above method, the data transfer operation is limited to the target cache queue corresponding to the target virtualization process identifier, thus realizing targeted data transfer for a specific virtualization process identifier. Data in other cache queues outside the target cache queue is not affected by this processing instruction.

[0041] In summary, the caching method provided in this embodiment can achieve data segmented storage based on virtualization process identifiers, and select a target cache queue according to processing instructions to perform targeted flushing processing, without having to flush all cache queues, thus achieving targeted processing of cached data.

[0042] Figure 2 A flowchart illustrating a caching method provided in an embodiment of this disclosure is further shown. Based on Figure 1 The illustrated embodiment further explains step 101. Figure 2 This may include the following steps: Step 201: Extract the target virtual function identifier and target process identifier associated with the target data.

[0043] In some embodiments, the virtual function instance and process from which the target data originates are determined when the target data is generated; therefore, the target data is associated with corresponding virtual function identifiers and process identifiers. The virtual function identifiers and process identifiers associated with the target data are extracted to obtain the target virtual function identifier and the target process identifier for subsequent matching. The extraction operation can be automatically performed by hardware logic circuitry during data generation or transmission. Extraction methods include, but are not limited to, reading from user-defined fields of the bus interface, such as obtaining them from the write address channel user field of the Advanced eXtensible Interface (AXI) bus.

[0044] Step 202: Perform parallel matching of the target virtual function identifier and the target process identifier with the virtual function identifier and process identifier stored in multiple pre-configured matching registers respectively to determine the target matching register; wherein, the target matching register is enabled, and the target virtual function identifier is consistent with the virtual function identifier stored in the target matching register, and the target process identifier is consistent with the process identifier stored in the target matching register.

[0045] In some embodiments, a match register is a hardware register unit used to store the correspondence between a set of virtual function identifiers and process identifiers. Multiple sets of match registers are pre-configured in the system. Each set of match registers includes an enable bit, a virtual function identifier field, and a process identifier field. The enable bit indicates whether the set of match registers is currently active; when the enable bit is active, the set of match registers participates in the match process; when the enable bit is inactive, the set of match registers does not participate in the match process. The virtual function identifier field stores a virtual function identifier, and the process identifier field stores a process identifier.

[0046] Parallel matching refers to comparing the target virtual function identifier and the target process identifier with the virtual function identifiers and process identifiers stored in all enabled matching registers simultaneously. Parallel matching can be implemented using combinational logic circuits, eliminating the need for software polling group by group. The matching conditions are: the matching register must be enabled, the target virtual function identifier must match the virtual function identifier stored in the matching register, and the target process identifier must match the process identifier stored in the matching register. A successful match is determined only when all three conditions are met.

[0047] When a set of matching registers meets the above matching conditions, that set of matching registers is determined as the target matching register. Each set of matching registers corresponds to a buffer queue, therefore, the target matching register uniquely corresponds to one buffer queue.

[0048] Step 203: Write the target data into the cache queue corresponding to the target matching register.

[0049] In some embodiments, after determining the target matching register, the cache queue corresponding to the target matching register is found according to the pre-established correspondence between the matching register and the cache queue, and the target data is written into the cache queue. Thus, the target data is stored in the cache queue corresponding to the target virtual function identifier and the target process identifier, completing the data queue-based storage based on the virtualization process identifier.

[0050] Using the above method, the hardware performs parallel matching of virtual function identifiers and process identifiers, determines the target matching register based on the matching results, and then writes the target data into the corresponding cache queue. This realizes hardware-based data queue storage based on virtual function identifiers and process identifiers, and the data corresponding to different combinations of virtual function identifiers and process identifiers are stored in their respective cache queues.

[0051] Optionally, based on any of the above embodiments or optional methods, the method further includes: If the virtual function identifier and process identifier stored in all enabled matching registers are inconsistent with the target virtual function identifier and the target process identifier, then the target data is written to the default cache queue; wherein the default cache queue does not respond to the processing instruction.

[0052] In some embodiments, the default cache queue is a dedicated cache queue pre-configured in the system, used to store data that has not been matched with any valid match register. The default cache queue differs functionally from the cache queues corresponding to each match register: the cache queues corresponding to match registers respond to processing instructions and participate in the directed flushing process; the default cache queue does not respond to any processing instructions, that is, when a processing instruction triggers the directed flushing process, the data in the default cache queue is not transferred out, and the default cache queue does not participate in the flushing process.

[0053] During the parallel matching process in step 202, the following situation may occur: After comparing the target virtual function identifier and the target process identifier with the virtual function identifiers and process identifiers stored in all enabled matching registers one by one, no set of matching registers simultaneously satisfies the three conditions of being enabled, having the same virtual function identifier, and having the same process identifier. In this case, the matching fails, there is no target matching register corresponding to the target virtual function identifier and the target process identifier, and therefore the target data cannot be written to the cache queue corresponding to the matching register. At this time, the target data is written to the default cache queue.

[0054] The default cache queue may accumulate data written after multiple failed matches. Since the default cache queue does not respond to processing commands, this data will not be flushed out. The handling of data in the default cache queue can be configured according to system requirements, including but not limited to: clearing the default cache queue upon system reset or meeting target conditions, reading data from the default cache queue using other dedicated commands, or triggering an interrupt notification to the software when the default cache queue reaches a preset threshold.

[0055] In this way, target data that does not match a valid matching register is written to the default cache queue, preventing this data from entering the cache queue corresponding to the matching register. This prevents unmatched data from being mistakenly dumped during subsequent processing instructions, ensuring that the targeted flushing process only targets data with virtualization process identifiers corresponding to the configured valid matching registers.

[0056] Optionally, based on any of the above embodiments or optional methods, before determining the target cache queue corresponding to the target virtualization process identifier in the processing instruction from each cache queue, the method further includes: Verify the validity of the target virtualization process identifier in the processing instruction; If the target virtualization process identifier is invalid, the processing instruction will not be executed, and a flush error status will be output.

[0057] In some embodiments, verifying the validity of the target virtualization process identifier in the processing instruction refers to performing a legality check on the target virtualization process identifier carried in the processing instruction after receiving the processing instruction and before determining the target cache queue. Validity verification can be based on a set of virtualization process identifiers configured in the system. This set can be the set of virtualization process identifiers corresponding to the valid matching registers among the aforementioned multiple sets of matching registers. Specific verification methods include, but are not limited to: comparing the target virtualization process identifier with each configured valid virtualization process identifier; or checking whether there exists a set of valid matching registers whose virtual function identifier and process identifier stored in the matching register are consistent with the target virtualization process identifier.

[0058] When the target virtualization process identifier matches any configured valid virtualization process identifier, the target virtualization process identifier is deemed valid, and subsequent operations such as determining the target cache queue and targeted flushing are executed. When the target virtualization process identifier does not match any of the configured valid virtualization process identifiers, or when the target virtualization process identifier itself is an illegal value (e.g., a virtual function identifier or process identifier exceeding the allowed range), the target virtualization process identifier is deemed invalid. In this case, the subsequent operations requested by the processing instruction are not executed, the target cache queue is not determined, and targeted flushing is not performed; a flushing error status is directly output. Methods for outputting a flushing error status include, but are not limited to: updating the status register to a flushing error status, returning an error code to the software, or triggering an interrupt notification.

[0059] By using the above method, the validity of the target virtualization process identifier is verified before the processing instruction is executed. Invalid virtualization process identifiers are directly rejected for processing, preventing incorrect data transfer or system abnormalities caused by illegal or non-existent virtualization process identifiers, and ensuring the security and controllability of the cache processing process.

[0060] Optionally, based on any of the above embodiments or optional methods, the step of performing a targeted flushing process on the target cache queue to transfer the target data out of the target cache queue includes: Determine whether the length of the target data meets the bus transmission specifications; If the conditions are met, the target data in the target cache queue will be transferred out. If the conditions are not met, placeholder data is added to the target data to obtain supplemented target data, and the supplemented target data is then transferred out; wherein, the supplemented target data meets the bus transmission specifications.

[0061] In some embodiments, the bus transmission specification refers to the format requirements that data must meet when it is transmitted through the bus transmission path. The bus transmission path has data bit width and alignment requirements, and the length of the transmitted data must conform to the bus transmission specification in order to be transmitted correctly. The specific content of the bus transmission specification is related to the bus protocol adopted by the system, including but not limited to the burst transmission length and data bit width alignment requirements specified by the Advanced eXtensible Interface (AXI) bus or other types of on-chip bus protocols.

[0062] When transferring target data out of the target buffer queue, the first step is to determine whether the length of the target data in the target buffer queue meets the bus transmission specification. This determination can be made in ways including, but not limited to: checking whether the total length of the target data is an integer multiple of the data bit width required by the bus transmission specification, or checking whether the target data can be transmitted according to the burst length specified in the bus transmission specification.

[0063] When the length of the target data meets the bus transmission specifications, the target data in the target buffer queue is read sequentially and transferred to external memory via the bus transmission path. When the length of the target data does not meet the bus transmission specifications, for example, if the total length of the target data is insufficient for the data bit width required by the bus transmission specifications, or if the last group of data is insufficient to fill the length requirement of a burst transmission, placeholder data is added to the target data. Placeholder data is pre-defined, meaningless padding data used to ensure that the total length of the supplemented target data meets the bus transmission specifications. The specific content of the placeholder data can be pre-configured, including but not limited to all-zero data or all-one data. After adding placeholder data, the supplemented target data is obtained. If the supplemented target data meets the bus transmission specifications, the supplemented target data is transferred to external memory via the bus transmission path.

[0064] In some implementations, the destination for writing the target data after it is transferred out can be a ring buffer in external memory. A ring buffer is a circular storage area that is used in a loop. The hardware writes the transferred data into the ring buffer sequentially, and when the writing reaches the end of the buffer, it automatically wraps back to the starting address and continues writing.

[0065] By using the above method, the length of the target data is judged before the data is transferred out, and the target data that does not meet the bus transmission specifications is padded to ensure that the format of the transferred data meets the requirements of the bus transmission path, so that the data transfer operation of the directional flushing process can be completed correctly.

[0066] Optionally, based on any of the above embodiments or optional methods, during the process of transferring the target data out of the target cache queue, the method further includes: Monitor the bus transmission status of the target data and the queue status of the target cache queue; When an abnormality is detected in the bus transmission status and / or the queue status of the target buffer queue, the transfer of the target data is terminated and a flush error status is output.

[0067] In some embodiments, monitoring the bus transmission status of the target data and the queue status of the target buffer queue refers to real-time detection of the working status of the bus transmission path used for data transfer and the status of the target buffer queue itself during the directional flushing process.

[0068] Bus transfer status refers to the operational state of the bus transfer path during data transmission. The bus transfer path is the data transmission channel connecting the chip's internal cache queue and external memory. During the transfer of target data through the bus transfer path, possible abnormal situations may occur, including but not limited to: bus transfer timeout, bus transfer verification error, bus transfer arbitration failure, or bus transfer path not being ready. Monitoring the bus transfer status can be achieved through hardware monitoring circuitry. This circuitry continuously monitors the control and response signals of the bus transfer path. When an error response signal is detected from the bus transfer path, or when the bus transfer path fails to complete data transmission within a specified time, the bus transfer status is determined to be abnormal.

[0069] The queue state of the target cache queue refers to its own operational state during the data transfer process. Queue state anomalies include, but are not limited to: underflow (attempting to read data when the queue is empty); overflow (attempting to write data to the queue when it is full); errors in the read / write pointers of the target cache queue; or unexpected state transitions in the control logic of the target cache queue. Monitoring the queue state can be achieved through a hardware state machine or a queue controller. The queue controller tracks the read / write operations and internal pointers of the target cache queue in real time, and determines the queue state to be abnormal when the above anomalies are detected.

[0070] When an abnormality is detected in the bus transmission status, or an abnormality is detected in the target buffer queue, or both abnormalities are detected simultaneously, the target data transfer operation is immediately terminated. Data reading from the target buffer queue is stopped, and data transmission to the bus transmission path is also stopped. Simultaneously, a flush error status is output to indicate that the directed flushing process was terminated due to an abnormality. The methods for outputting a flush error status include, but are not limited to: updating the status register to a flush error status, returning an error indication to the software, or triggering an interrupt to notify the software to handle the issue.

[0071] Using the above method, the bus transmission status and queue status are monitored in real time during the directional flushing process. Once an abnormality is detected, the transfer operation is immediately terminated and a flushing error status is output, preventing data loss, data errors, or system hangs caused by abnormal bus transmission paths or buffer queues, thus ensuring the safety and reliability of the directional flushing process.

[0072] Optionally, based on any of the above embodiments or optional methods, the method further includes: The status register is updated according to the processing status of the processing instruction; wherein the status register is used to indicate the idle state, the flushing in progress state, the flushing completed state, or the flushing error state.

[0073] In some embodiments, the status register is a hardware-maintained storage unit used to record the processing status of processing instructions. The status register can indicate four states: idle state, flushing in progress state, flushing complete state, and flushing error state.

[0074] The idle state indicates that no instruction is currently being executed, and the cache processing system is waiting to receive new instructions. The initial value of the status register is the idle state after system initialization.

[0075] The flushing in progress status indicates that a processing instruction has been received and has passed validity verification. The instruction is performing a targeted flush on the target cache queue, and the target data is being transferred out.

[0076] The flushing completion status indicates that the processing instructions have been executed and the target data in the target buffer queue has been successfully transferred to the external memory through the bus transmission path. This directional flushing process has ended normally.

[0077] A flush error status indicates that an exception occurred during the execution of the processing instruction, causing the instruction to fail to complete normally. Situations that may result in a flush error status include, but are not limited to: the target virtualization process identifier carried in the processing instruction being verified as invalid; an abnormal bus transmission status being detected during targeted flushing; or an abnormal queue status of the target cache queue being detected during targeted flushing.

[0078] The status register is updated automatically by the hardware based on the processing status of the instruction. Specific update timings include: when the system is idle and receives a processing instruction, if the target virtualization process identifier is valid, the hardware updates the status register from idle to flushing in progress; when the directed flushing process completes normally, the hardware updates the status register from flushing in progress to flushing complete; when the target virtualization process identifier verification is invalid, or an anomaly is detected during directed flushing, the hardware updates the status register to flushing error; after flushing complete or flushing error, the system returns to idle, and the hardware updates the status register to idle to prepare for receiving the next processing instruction.

[0079] Software or other processing units can obtain the execution result of processing instructions by reading the value of the status register. Reading methods include, but are not limited to: reading the current value of the status register through the bus interface; or through an interrupt mechanism, where the hardware actively notifies the software when the status register is updated to a flush complete state or a flush error state.

[0080] Using the above method, the hardware updates the status register in real time according to the processing status of the processing instruction. The status register provides indications of four states: idle state, flushing in progress state, flushing completed state, and flushing error state. This makes the entire processing flow of the processing instruction visible to the software, and the software can obtain the execution progress and results of the processing instruction in real time.

[0081] To clearly illustrate the embodiments of this disclosure, Figure 3 This is a schematic diagram of a target data flushing process provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the target data flushing process after the processing command is triggered includes the following steps.

[0082] The software or upper-level control unit issues a processing instruction, which carries the target virtualization process identifier. The processing instruction is used to request a targeted flushing process to the cache queue corresponding to the target virtualization process identifier.

[0083] After receiving the processing instruction, the hardware verifies the validity of the target virtualization process identifier carried in the instruction. Specifically, the verification method involves comparing the target virtualization process identifier with all valid virtualization process identifiers configured in the system. If the target virtualization process identifier is invalid (i.e., it does not match any of the configured valid virtualization process identifiers), the processing instruction is rejected, the status register is updated to a flush error state, and the processing flow ends. If the target virtualization process identifier is valid, subsequent steps are executed.

[0084] After the target virtualization process identifier is verified, the target cache queue is determined from the various cache queues configured in the system based on the target virtualization process identifier. The target cache queue is a cache queue that corresponds to the target virtualization process identifier.

[0085] After identifying the target buffer queue, check if the target data exists in the target buffer queue. If the target buffer queue is empty, the current targeted flushing process ends directly, and the status register is updated to flushing complete; no actual data transfer operation is required. If the target buffer queue contains the target data, the targeted flushing process is initiated, and the data transfer operation begins.

[0086] During the data transfer operation, the target data in the target buffer queue is read sequentially and transferred to external memory via the bus transmission path. During the data transfer process, it is determined whether the length of the target data meets the bus transmission specifications. If it does not meet the specifications, placeholder data is added to the target data to obtain supplemented target data that meets the bus transmission specifications. Then, the supplemented target data is transferred out.

[0087] During data transfer, the bus transmission status and the target buffer queue status are monitored in real time. If an abnormality is detected in the bus transmission status or the target buffer queue status, the data transfer operation is immediately terminated, the status register is updated to flush error status, and the processing flow ends.

[0088] If no anomalies are detected during the data transfer process and all target data in the target buffer queue is successfully transferred, the status register is updated to the flushing complete state, and the processing flow ends. The software or upper-level control unit can determine the execution result of this processing instruction by reading the current value of the status register.

[0089] Through the above process, the entire process of processing instructions, from issuance to completion, sequentially undergoes validity verification, target cache queue location, queue status check, data completion and transfer, and anomaly monitoring. Data transfer operations are limited to the target cache queue corresponding to the target virtualization process identifier; only data in the target cache queue is transferred out, and data in other cache queues does not participate in the transfer operation of this processing instruction. The data transmitted on the bus transmission path is all target data associated with the target virtualization process identifier and does not include irrelevant data corresponding to other virtualization process identifiers. Simultaneously, each processing stage has a status feedback mechanism, enabling the software to know the execution progress and final result of the processing instructions.

[0090] Corresponding to the above-described caching method, this invention also proposes a caching apparatus. Since the apparatus embodiments of this invention correspond to the above-described method embodiments, details not disclosed in the apparatus embodiments can be referred to the above-described method embodiments, and will not be repeated here.

[0091] Figure 4 This is a schematic diagram of the structure of a cache processing device provided in an embodiment of the present disclosure, as shown below. Figure 4 As shown, the device includes: Storage unit 31 is used to store the target data in a corresponding cache queue based on the virtualization process identifier to which the target data belongs; wherein, the virtualization process identifier includes a virtual function identifier and a process identifier; The determining unit 32 is configured to, in response to a received processing instruction, determine from each cache queue the target cache queue corresponding to the target virtualization process identifier in the processing instruction; Processing unit 33 is used to perform targeted flushing processing on the target cache queue to transfer the target data out of the target cache queue.

[0092] The cache processing apparatus provided in this embodiment can store data in separate queues based on virtualization process identifiers, and select a target cache queue according to the processing instructions to perform targeted flushing processing, without having to flush all cache queues, thus achieving targeted processing of cached data.

[0093] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the storage unit 31 includes: Extraction module 311 is used to extract the target virtual function identifier and target process identifier associated with the target data; The matching module 312 is used to perform parallel matching of the target virtual function identifier and the target process identifier with virtual function identifiers and process identifiers stored in a plurality of pre-configured matching registers respectively, to determine the target matching register; wherein the target matching register is enabled, and the target virtual function identifier is consistent with the virtual function identifier stored in the target matching register, and the target process identifier is consistent with the process identifier stored in the target matching register. The first writing module 313 is used to write the target data into the cache queue corresponding to the target matching register.

[0094] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the device further includes: The second write module 314 is used to write the target data into a default cache queue when all virtual function identifiers and process identifiers stored in the matching registers that are in a valid enable state are inconsistent with the target virtual function identifier and the target process identifier; wherein the default cache queue does not respond to the processing instruction.

[0095] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the device further includes: Verification unit 34 is used to verify the validity of the target virtualization process identifier in the processing instruction before the determining unit 32 determines the target cache queue corresponding to the target virtualization process identifier in the processing instruction from each cache queue; The first output unit 35 is used to not execute the processing instruction and output a flushing error status when the target virtualization process identifier is invalid.

[0096] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the processing unit 33 includes: The judgment module 331 is used to determine whether the length of the target data meets the bus transmission specification; The first transfer module 332 is used to transfer the target data out of the target cache queue when the conditions are met. The second transfer module 333 is used to supplement placeholder data in the target data when the target data is not satisfied, to obtain the supplemented target data, and to transfer the supplemented target data out; wherein the supplemented target data satisfies the bus transmission specification.

[0097] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the device further includes: The monitoring unit 36 ​​is used to monitor the bus transmission status of the target data and the queue status of the target cache queue during the process of the processing unit 33 transferring the target data out of the target cache queue. The second output unit 37 is used to terminate the transfer of the target data and output a flush error status when an abnormality is detected in the bus transmission status and / or the queue status of the target buffer queue.

[0098] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 5 As shown, the device further includes: The update unit 38 is used to update the status register according to the processing status of the processing instruction; wherein the status register is used to indicate the idle status, the flushing in progress status, the flushing completed status, or the flushing error status.

[0099] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0100] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0101] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0102] like Figure 6As shown, the electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory 602 or a computer program loaded from a storage unit 608 into a random access memory 603. The random access memory 603 may also store various programs and data required for the operation of the electronic device 600. The computing unit 601, the read-only memory 602, and the random access memory 603 are interconnected via a bus 604. An input / output interface 605 is also connected to the bus 604.

[0103] Multiple components in electronic device 600 are connected to input / output interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of monitors, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows electronic device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0104] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as cache processing methods. For example, in some embodiments, the cache processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 600 via read-only memory 602 and / or communication unit 609. When the computer program is loaded into random access memory 603 and executed by the computing unit 601, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the aforementioned cache processing method by any other suitable means (e.g., by means of firmware).

[0105] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0106] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0107] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0108] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0109] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0110] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0111] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0112] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0113] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A caching method, characterized in that, include: Based on the virtualization process identifier to which the target data belongs, the target data is stored in the corresponding cache queue; wherein, the virtualization process identifier includes a virtual function identifier and a process identifier; In response to the received processing instruction, the target cache queue corresponding to the target virtualization process identifier in the processing instruction is determined from each cache queue; Perform a targeted flushing process on the target cache queue to remove the target data from the target cache queue; The method of storing the target data in the corresponding cache queue based on the virtualization process identifier to which the target data belongs includes: Extract the target virtual function identifier and target process identifier associated with the target data; The target virtual function identifier and the target process identifier are matched in parallel with the virtual function identifier and process identifier stored in multiple pre-configured matching registers to determine the target matching register; wherein the target matching register is enabled, and the target virtual function identifier is consistent with the virtual function identifier stored in the target matching register, and the target process identifier is consistent with the process identifier stored in the target matching register. The target data is written into the cache queue corresponding to the target matching register.

2. The method according to claim 1, characterized in that, The method further includes: If the virtual function identifier and process identifier stored in all enabled matching registers are inconsistent with the target virtual function identifier and the target process identifier, then the target data is written to the default cache queue; wherein the default cache queue does not respond to the processing instruction.

3. The method according to claim 1, characterized in that, Before determining the target cache queue corresponding to the target virtualization process identifier in the processing instruction from each cache queue, the method further includes: Verify the validity of the target virtualization process identifier in the processing instruction; If the target virtualization process identifier is invalid, the processing instruction will not be executed, and a flush error status will be output.

4. The method according to claim 1, characterized in that, The step of performing a targeted flushing process on the target cache queue to transfer the target data out of the target cache queue includes: Determine whether the length of the target data meets the bus transmission specifications; If the conditions are met, the target data in the target cache queue will be transferred out. If the conditions are not met, placeholder data is added to the target data to obtain supplemented target data, and the supplemented target data is then transferred out; wherein, the supplemented target data meets the bus transmission specifications.

5. The method according to claim 1, characterized in that, The method further includes the following steps during the process of transferring the target data out of the target cache queue: Monitor the bus transmission status of the target data and the queue status of the target cache queue; When an abnormality is detected in the bus transmission status and / or the queue status of the target buffer queue, the transfer of the target data is terminated and a flush error status is output.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: The status register is updated according to the processing status of the processing instruction; wherein the status register is used to indicate the idle state, the flushing in progress state, the flushing completed state, or the flushing error state.

7. A cache processing device, characterized in that, include: A storage unit is used to store the target data in a corresponding cache queue based on the virtualization process identifier to which the target data belongs; wherein the virtualization process identifier includes a virtual function identifier and a process identifier; The determining unit is configured to, in response to a received processing instruction, determine from each cache queue the target cache queue corresponding to the target virtualization process identifier in the processing instruction; The processing unit is used to perform a targeted flushing process on the target cache queue, and to transfer the target data out of the target cache queue; The method of storing the target data in the corresponding cache queue based on the virtualization process identifier to which the target data belongs includes: Extract the target virtual function identifier and target process identifier associated with the target data; The target virtual function identifier and the target process identifier are matched in parallel with the virtual function identifier and process identifier stored in multiple pre-configured matching registers to determine the target matching register; wherein the target matching register is enabled, and the target virtual function identifier is consistent with the virtual function identifier stored in the target matching register, and the target process identifier is consistent with the process identifier stored in the target matching register. The target data is written into the cache queue corresponding to the target matching register.

8. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

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