Data processing method, device and storage medium

Abstract

The application discloses a data processing method and device and a storage medium, relates to the technical field of data processing, and comprises the following steps: an MDB receives to-be-processed data, wherein an MRCD of an MRDIMM performs an alternating addressing operation on a first Rank and a second Rank of the MRDIMM, so that the first Rank and the second Rank staggeredly transmit the to-be-processed data to the MDB; the MDB transmits the to-be-processed data to a MAC unit; the MAC unit performs a multiply-accumulate calculation on the to-be-processed data, and obtains a calculation result; if the alternating addressing operation is completed, the MDB outputs a target calculation result to a corresponding CPU based on the calculation result. The application performs a multiply-accumulate calculation on AI weights through a MAC unit in the gap of staggered reading, and feeds back the corresponding target calculation result to the CPU, so that the amount of data to be transmitted can be greatly reduced, invalid data carrying on a memory bus is reduced, and bandwidth pressure and transmission power consumption are effectively reduced.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing method, apparatus and storage medium. Background Technology

[0002] MRDIMM (Multiplexed Rank DIMM) is a next-generation high-bandwidth server memory standard defined by JEDEC. MRDIMM interleaves and merges data from two sets of DRAM (Dynamic Random-Access Memory) chips within the MDB (Memory Data Buffer) on the memory module, outputting it to the CPU (Central Processing Unit) at double the speed. With the rapid development of artificial intelligence, such as large language models and neural networks, AI inference and training processes require massive amounts of multiply-accumulate (MAC) operations, which depend on the underlying hardware's speed in reading weight data.

[0003] Currently, the logic processing power of CPU / AI chips is extremely powerful, but the physical read / write speed of the underlying DRAM is improving slowly. CPU computing power is forced to remain largely idle, spending most of its time waiting for DRAM data preparation and transfer, resulting in extremely low overall system energy efficiency and a severe "memory wall" problem. To improve bandwidth, Multiplexed Dual In-line Memory Modules (MRDIMMs) have been introduced. These modules interleave data from two native DRAM chips (e.g., 6.4Gbps) through a data buffer (MDB), providing the CPU with double the bandwidth (12.8Gbps = 6.4Gbps * 2). However, this only solves the problem of "widening the channel." The massive amounts of raw weight data still need to travel long distances through the data bus to the CPU, leaving the fundamental pain points of bandwidth pressure and power consumption unresolved.

[0004] Therefore, how to reduce bandwidth pressure and transmission power consumption, and improve the computing power of AI systems, is an urgent problem to be solved.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a data processing method, device and storage medium, which aims to solve the technical problem of how to reduce bandwidth pressure and transmission power consumption, and improve the computing power of AI systems.

[0007] To achieve the above objectives, this application proposes a data processing method applied to a multiplexed memory module (MRDIMM). The MRDIMM includes a data buffer chip (MDB) and a multiply-accumulate (MAC) unit. The data processing method includes: The MDB receives data to be processed, wherein the MRCD of the MRDIMM performs an alternating addressing operation on the first Rank and the second Rank of the MRDIMM, so that the data to be processed is transmitted to the MDB in an interleaved manner between the first Rank and the second Rank. The MDB transmits the data to be processed to the MAC unit; The MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result; If the alternating addressing operation is completed, the MDB outputs the target calculation result to the corresponding CPU based on the calculation result.

[0008] In one embodiment, the step of the MAC unit performing multiplication and accumulation calculations on the data to be processed to obtain the calculation result includes: The MAC unit receives preset AI weight data; The MAC unit performs multiplication and accumulation calculations on the data to be processed based on the preset AI weight data to obtain the calculation result.

[0009] In one embodiment, the step of the MDB outputting the target calculation result to the corresponding CPU based on the calculation result after the alternating addressing operation is completed includes: If the alternating addressing operation is completed, the MAC unit performs an accumulation operation on all the calculation results corresponding to the alternating addressing operation to obtain the target calculation result; The MDB outputs the target calculation result to the corresponding CPU.

[0010] In one embodiment, after the step of outputting the target calculation result by the MDB, the data processing method further includes: The MDB deletes all calculation results corresponding to the alternating addressing operation and the target calculation result.

[0011] In one embodiment, the step of the MDB outputting the target calculation result to the corresponding CPU based on the calculation result after the alternating addressing operation is completed includes: The MAC unit updates the accumulated result corresponding to the alternating addressing operation based on the calculation result; If the alternating addressing operation is completed, the MDB will use the accumulated result as the target calculation result and output the target calculation result to the corresponding CPU.

[0012] In one embodiment, the step of the MDB transmitting the data to be processed to the MAC unit includes: The MDB sends the data to be processed to the MAC unit based on a preset time interval.

[0013] In one embodiment, the step of the MAC unit performing multiplication and accumulation calculations on the data to be processed to obtain the calculation result includes: The MAC unit performs multiplication and accumulation calculations on the data to be processed based on a preset time interval to obtain the calculation result.

[0014] In one embodiment, the MAC unit is disposed within the MDB, and the MAC unit has multiple MAC sub-units; the MDB also has an internal register for storing preset AI weight data; The steps by which the MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result include: If there is currently unprocessed data, determine the number of operand elements between the unprocessed data and the data to be processed, and whether the number of sub-units corresponding to the MAC sub-unit has been reached; If the sum of the given quantity reaches the number of sub-units, then each MAC sub-unit of the MAC unit performs multiplication and accumulation calculations on the data to be processed based on the preset AI weight data in the internal register to obtain the calculation result.

[0015] In one embodiment, after determining the number of operand elements between the unprocessed data and the data to be processed and whether the number of sub-units corresponding to the MAC sub-unit has been reached, the data processing method further includes: If the stated quantity does not reach the stated number of sub-units or there is currently no unprocessed data, then the unprocessed data is updated based on the current pending data.

[0016] In one embodiment, the step of each MAC subunit of the MAC unit performing multiplication and accumulation calculations on the data to be processed based on preset AI weight data in the internal register to obtain the calculation result includes: The unprocessed data and the data to be processed are input to the input terminal of the MAC unit in parallel. Each MAC subunit performs multiplication and accumulation calculations on the data corresponding to each operand element in the unprocessed data and the data to be processed based on the preset AI weight data to obtain the calculation result.

[0017] In addition, to achieve the above objectives, this application also proposes a data processing apparatus, the apparatus comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the data processing method described above.

[0018] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the data processing method described above.

[0019] One or more technical solutions proposed in this application have at least the following technical effects: The MDB receives data to be processed, wherein the MRCD of the MRDIMM performs an alternating addressing operation on the first Rank and the second Rank of the MRDIMM, so that the data to be processed is transmitted to the MDB in an interleaved manner between the first Rank and the second Rank. Then, the MDB transmits the data to be processed to the MAC unit. The MAC unit then performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result. Then, if the alternating addressing operation is completed, the MDB outputs the target calculation result to the corresponding CPU based on the calculation result. By setting the MAC unit in the MRDIMM, during the process of the MDB receiving the data transmitted in an interleaved manner between the Ranks of the MRDIMM, the AI ​​weight data and activation vector are multiplied and accumulated through the MAC unit in the interval of the interleaved transmission, and the corresponding target calculation result is fed back to the CPU. This can greatly reduce the amount of data transmitted, reduce the transmission of massive amounts of raw data on the memory bus, effectively reduce bandwidth pressure and transmission power consumption, and achieve the effect of breaking the memory wall and releasing bus bandwidth.

[0020] Meanwhile, the CPU can perform subsequent AI calculations based on the calculation results, reducing the amount of computation the CPU needs to perform AI calculations and improving the computing power of the AI ​​system. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a flowchart illustrating an embodiment of the data processing method of this application. Figure 2 This is a schematic diagram of the module structure of the multiplexed memory module according to an embodiment of this application; Figure 3 This is a schematic diagram of the device structure of the hardware operating environment involved in the data processing method in the embodiments of this application.

[0024] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not intended to limit this application.

[0026] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0027] The main solution of this application embodiment is as follows: The MRDIMM is equipped with a data buffer chip MDB and a multiply-accumulate-address (MAC) unit. The MDB receives data to be processed. The MRCD of the MRDIMM performs an alternating addressing operation on the first Rank and the second Rank of the MRDIMM, so that the first Rank and the second Rank interleave the data to be processed to the MDB. The MDB transmits the data to be processed to the MAC unit. The MAC unit performs multiply-accumulate-address (MAC) calculation on the data to be processed to obtain the calculation result. If the alternating addressing operation is completed, the MDB outputs the target calculation result to the corresponding CPU based on the calculation result.

[0028] In this embodiment, for ease of description, the following description uses a data processing device as the execution subject.

[0029] MRDIMM (Multiplexed Rank DIMM) is a next-generation high-bandwidth server memory standard defined by JEDEC. MRDIMM interleaves and merges data from two sets of DRAM (Dynamic Random-Access Memory) chips within the MDB (Memory Data Buffer) on the memory module, outputting it to the CPU (Central Processing Unit) at double the speed. With the rapid development of artificial intelligence, such as large language models and neural networks, AI inference and training processes require massive amounts of multiply-accumulate (MAC) operations, which depend on the underlying hardware's speed in reading weight data.

[0030] Currently, the logic processing power of CPU / AI chips is extremely powerful, but the physical read / write speed of the underlying DRAM is improving slowly. CPU computing power is forced to remain largely idle, spending most of its time waiting for DRAM data preparation and transfer, resulting in extremely low overall system energy efficiency and a severe "memory wall" problem. To improve bandwidth, Multiplexed Dual In-line Memory Modules (MRDIMMs) have been introduced. These modules interleave data from two native DRAM chips (e.g., 6.4Gbps) through a data buffer (MDB), providing the CPU with double the bandwidth (12.8Gbps = 6.4Gbps * 2). However, this only solves the problem of "widening the channel." The massive amounts of raw weight data still need to travel long distances through the data bus to the CPU, leaving the fundamental pain points of bandwidth pressure and power consumption unresolved.

[0031] Existing near-memory computing solutions (such as external FPGAs or custom DRAM chips) are expensive and disrupt the physical structure of standardized memory modules. More importantly, inserting computing tasks directly into memory disrupts the original strict read and write timing requirements of the CPU memory controller, resulting in significant system latency and making seamless compatibility impossible.

[0032] Therefore, how to reduce bandwidth pressure and transmission power consumption, and improve the computing power of AI systems, is an urgent problem to be solved.

[0033] This application provides a solution that, by setting up a MAC unit in the MRDIMM, during the process of receiving the Rank interleaved transmission data from the MRDIMM in the MDB, performs multiplication and accumulation operations on AI weight data and activation vectors through the MAC unit during the interleaved transmission intervals, and feeds back the corresponding target calculation results to the CPU. This can greatly reduce the amount of data transmitted, effectively reducing bandwidth pressure and transmission power consumption.

[0034] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or data processing device capable of performing the above functions. The following description uses a data processing device as an example to illustrate this embodiment and the subsequent embodiments.

[0035] Based on this, embodiments of this application provide a data processing method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the data processing method of this application.

[0036] This data processing method is applied to the multiplexed memory module MRDIMM, which is equipped with a data buffer chip MDB and a multiply-accumulate MAC unit.

[0037] When the CPU reads data from MRDIMM for AI calculations, the CPU sends a data acquisition instruction to MRCD (Multiplexed Register Clock Driver). The RCD controls the two sets of DRAMs (e.g., the first Rank and the second Rank) corresponding to the data acquisition instruction in MRDIMM to transmit the data to MDB in an interleaved multiplexing manner. This enables the MDB to perform interleaved transmission operations on the first Rank and the second Rank to obtain the current data.

[0038] It should be noted that during interleaved read and write operations, the data from the two DRAMs arrive at the MDB in turn, and there is a time difference between the arrival times of the data at the MDB. This time difference can be used to perform multiplication and accumulation operations on the weight data and the activation vector.

[0039] In this embodiment, the data processing method includes steps S110~S140: Step S110, the MDB receives data to be processed, wherein the MRCD of the MRDIMM performs an alternating addressing operation on the first Rank and the second Rank of the MRDIMM, so that the first Rank and the second Rank are interleaved to transmit the data to be processed to the MDB; Step S120: The MDB transmits the data to be processed to the MAC unit; Step S130: The MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result; Step S140: If the alternating addressing operation is completed, the MDB outputs the target calculation result to the corresponding CPU based on the calculation result.

[0040] In this embodiment of the application, when the CPU performs AI calculations, the CPU sends a data acquisition command required for AI calculations to the MRCD of the MRDIMM. The MRCD performs alternating addressing operations on the first Rank and the second Rank of the MRDIMM according to the acquisition command. The first Rank and the second Rank interleave the data corresponding to the acquisition command, i.e. the current data to be processed, to the MDB.

[0041] It should be noted that, for AI computation, the number of alternating addressing operations can be determined based on the acquired command. For example, if the alternating addressing operation is 16 times, the first Rank and the second Rank will alternately transmit data to the MDB 8 times each based on the alternating addressing method. There is a basically fixed time gap (time difference) between the MDB receiving the current data to be processed and the next data to be processed. For example, there is a time gap between receiving data from the first Rank and receiving data from the second Rank. The AI ​​weights can then be calculated based on this time gap.

[0042] Among them, the first Rank and the second Rank are the Ranks in the MRDIMM corresponding to the acquisition command, that is, the first Rank and the second Rank store the data corresponding to the acquisition command, which is the data required for AI calculation.

[0043] When the MDB receives the current data to be processed, it transmits the data to the MAC unit. It should be noted that since the MAC unit takes a very short time to perform multiplication and accumulation calculations, usually on the order of nanoseconds, which is much shorter than the time difference between the arrival of data from the first Rank and the second Rank in turn to the MDB, the data to be processed can be transmitted to the MAC unit within a certain period of time after the data is acquired, and multiplication and accumulation calculations can be performed by the MAC unit.

[0044] In one possible implementation, step S120 may include step S121: Step S121: The MDB sends the data to be processed to the MAC unit based on a preset time interval.

[0045] In this embodiment, when the MDB obtains the current data to be processed, the MDB sends the data to be processed to the MAC unit based on a preset time interval. Specifically, the MDB sends the data to be processed to the MAC unit when the duration after obtaining the data reaches the preset time interval. The preset time interval can be reasonably set based on the time consumption of multiply-accumulate calculation and the time difference between the arrival of data from the first Rank and the second Rank to the MDB, so that the time consumption of multiply-accumulate calculation and the preset time interval are less than the time difference between the arrival of data from the first Rank and the second Rank to the MDB, so that the MAC unit can complete the multiply-accumulate calculation within each time difference.

[0046] In this embodiment, when the MAC unit receives the data to be processed transmitted by the MDB, the MAC unit performs multiplication and summation calculations on the data to be processed to obtain the calculation result. Specifically, the MAC unit performs multiplication and summation calculations on the weight data calculated by AI and the data to be processed to obtain the calculation result.

[0047] In one feasible implementation, step S130 may include steps S131-S132: Step S131: The MAC unit receives preset AI weight data; In step S132, the MAC unit performs multiplication and accumulation calculations on the data to be processed based on the preset AI weight data to obtain the calculation result.

[0048] In this embodiment, during AI calculation, the MAC unit receives preset AI weight data. For example, the weight data for AI calculation can be preset, i.e., preset AI weight data. For example, the preset AI weight data can be stored in the MDB in advance. During each AI calculation, the MDB can send the data to be processed obtained from the first alternating addressing operation and the preset AI weight data to the MAC unit at the same time. Alternatively, the preset AI weight data can be stored in the DRAM of the MRDIMM in advance. When the MDB receives the data to be processed obtained from the alternating addressing operation for the first time, it reads the preset AI weight data from the DRAM of the MRDIMM and sends the data to be processed and the preset AI weight data to the MAC unit at the same time.

[0049] When the preset AI weight data is obtained, the MAC unit performs multiplication and summation calculations on the data to be processed based on the preset AI weight data. That is, the MAC unit performs multiplication and summation calculations on the preset AI weight data and the data to be processed to obtain the calculation result.

[0050] In one possible implementation, step S130 may include step S133: In step S133, the MAC unit performs multiplication and accumulation calculations on the data to be processed based on a preset time interval to obtain the calculation result.

[0051] In this embodiment, if the MDB directly inputs the data to be processed to the MAC unit when it receives the data to be processed, the MAC unit performs multiplication and accumulation calculations on the data to be processed based on a preset time interval to obtain the calculation result. That is, when the duration after receiving the data to be processed reaches the preset time interval, the MAC unit performs multiplication and accumulation calculations on the data to be processed. The preset time interval can be reasonably set based on the time consumption of the multiplication and accumulation calculation and the time difference between the data of the first Rank and the second Rank arriving at the MDB in turn, so that the time consumption of the multiplication and accumulation calculation and the preset time interval are less than the time difference between the data of the first Rank and the second Rank arriving at the MDB in turn, so that the MAC unit can complete the multiplication and accumulation calculation within each time difference.

[0052] In this embodiment, when the MAC unit obtains the calculation result, it sends the calculation result to the MDB. The MDB determines whether the alternating addressing operation has been completed. For example, when the number of alternating addressing operations is 16, it determines whether the first Rank and the second Rank have completed 8 data transmissions, or whether the MAC unit has completed 16 multiplication and accumulation calculations. If the first Rank and the second Rank have completed 8 data transmissions, or the MAC unit has completed 16 multiplication and accumulation calculations, the MDB can determine that the alternating addressing operation has been completed. Alternatively, if the number of times the MDB receives data to be processed reaches the number of alternating addressing operations, the MDB can determine that the alternating addressing operation has been completed.

[0053] If the alternating addressing operation is completed, the MDB will output the target calculation result based on the calculation result. Specifically, the MDB can take all the calculation results (i.e. the calculation results of the number of alternating addressing operations) as the target calculation result and output the target calculation result to the corresponding CPU so that the CPU can perform subsequent AI calculations based on the received target calculation result.

[0054] Alternatively, if the alternating addressing operation is completed, the MAC unit can obtain all the calculation results. For example, the MDB can transmit other calculation results corresponding to the alternating addressing operation before the current time to the MAC unit, accumulate all the calculation results to obtain the target calculation result, and output the target calculation result to the corresponding CPU so that the CPU can perform subsequent AI calculations based on the received target calculation result. This can reduce the amount of computation when the CPU performs AI calculations and improve the computing power of the AI ​​system.

[0055] In one feasible implementation, step S140 may include steps S141-S142: Step S141: If the alternating addressing operation is completed, the MAC unit performs an accumulation operation on all the calculation results corresponding to the alternating addressing operation to obtain the target calculation result; In step S142, the MDB outputs the target calculation result to the corresponding CPU.

[0056] In this embodiment, when the MAC unit obtains the calculation result, the MDB determines whether the alternating addressing operation has been completed. If the alternating addressing operation has been completed, the MAC unit receives the other calculation results corresponding to the alternating addressing operation before the current time transmitted by the MDB. The MAC unit performs an accumulation operation on all the calculation results corresponding to the alternating addressing operation to obtain the target calculation result. For example, when the number of alternating addressing operations is 16, the MAC unit accumulates the current 16 calculation results to obtain the target calculation result.

[0057] Next, the MAC unit transmits the target calculation result to the MDB, and the MDB outputs the received target calculation result, that is, sends the received target calculation result to the corresponding CPU, so that the CPU can perform subsequent AI calculations based on the received target calculation result.

[0058] In one feasible implementation, after step S142, the data processing method may further include step S143: Step S143: Delete all calculation results corresponding to the alternating addressing operation and the target calculation result.

[0059] In this embodiment, after the MDB outputs the target calculation result, the MDB deletes all calculation results corresponding to the alternating addressing operation and the target calculation result to release the resources occupied by the calculation results and the target calculation result.

[0060] In one feasible implementation, step S140 may include steps S144-S145: Step S144: The MAC unit updates the accumulated result corresponding to the alternating addressing operation based on the calculation result; Step S145: If the alternating addressing operation is completed, the MDB will use the accumulated result as the target calculation result and output the target calculation result to the corresponding CPU.

[0061] In this embodiment, when the MAC unit obtains the calculation result, the MAC unit updates the accumulated result corresponding to the alternating addressing operation according to the current calculation result. That is, each time the MAC unit performs a multiplication and accumulation calculation to obtain the calculation result, it adds the current calculation result to the accumulated result to obtain a new accumulated result, thereby realizing the accumulation of the calculation result.

[0062] When the MAC unit obtains the accumulated result, the MDB determines whether the alternating addressing operation has been completed. If the alternating addressing operation has been completed, the MDB uses the accumulated result as the target calculation result and outputs the target calculation result. That is, the MDB uses the latest obtained accumulated result as the target calculation result and sends the target calculation result to the corresponding CPU to realize AI weight calculation, so that the CPU can perform subsequent AI calculations based on the received target calculation result.

[0063] It should be noted that since the MAC unit takes a very short time to perform multiply-accumulate calculations, usually on the order of nanoseconds, which is much shorter than the time difference between the arrival of data from the first Rank and the second Rank in turn to the MDB, the MAC unit can perform multiple multiply-accumulate calculations within a time difference. Therefore, the MDB can also send data to be processed to the MAC unit at intervals.

[0064] For example, when the MDB receives data to be processed at intervals, it sends the current data to be processed and the previously received data to be processed to the MAC unit simultaneously. When the two data to be processed are received, the MAC unit can perform multiplication and summation on the two data to be processed separately to obtain two calculation results. Alternatively, when the MDB receives data to be processed again after receiving the two data to be processed, the MAC unit can perform multiplication and summation on the two data to be processed separately to obtain two calculation results.

[0065] In one feasible implementation, such as Figure 2 As shown, the MAC unit can be set within the MDB.

[0066] In this embodiment, by setting the MAC unit within the MDB, compared to near-memory computing solutions using external FPGAs or customized DRAM chips, this embodiment does not require modification of the expensive underlying DRAM wafer manufacturing process. It can be achieved simply by adding a tiny silicon area to the MDB logic chip of the standardized MRDIMM memory module, which can reduce the cost of MRDIMMs and help maintain the standardized physical structure of MRDIMMs. While taking into account cost and compatibility with standard protocols, it improves the cost-effectiveness of MRDIMMs.

[0067] In one feasible implementation, the MAC unit is disposed within the MDB, and the MAC unit has multiple MAC sub-units; the MDB also has an internal register for storing preset AI weight data; step S130 may include steps A110~A120: Step A110: If there is currently unprocessed data, determine whether the number of operand elements between the unprocessed data and the data to be processed has reached the number of sub-units corresponding to the MAC sub-unit; Step A120: If the sum of the quantities reaches the number of sub-units, then each MAC sub-unit of the MAC unit performs multiplication and summation calculations on the data to be processed based on the preset AI weight data of the internal register to obtain the calculation result.

[0068] In one possible implementation, after step A110, step S130 further includes step A130: Step A130: If the quantity has not reached the number of sub-units or there is currently no unprocessed data, then update the unprocessed data based on the current unprocessed data.

[0069] In one feasible implementation, step A120 may include step A121: Step A121: Control the unprocessed data and the data to be processed to be input into the input terminal of the MAC unit in parallel. Each MAC subunit performs multiplication and accumulation calculations on the data corresponding to each operand element in the unprocessed data and the data to be processed based on the preset AI weight data to obtain the calculation result.

[0070] In this embodiment, the MAC unit is located within the MDB. The MAC unit has multiple MAC sub-units, for example, 8 MAC sub-units. Since the DDR5 specification defines the burst length as 16 (Burst Length=16, abbreviated as BL16), that is, for each read / write command, the DRAM continuously transmits 16 data units. Therefore, each MAC sub-unit can integrate a 16-bit multiply-accumulate unit, so that the MAC unit as a whole integrates 8 16-bit multiply-accumulate units, which are used to perform parallel dot product between the operands flowing in from the data bus in real time and the operands (preset AI weight data) residing in the internal register. The dot product result can be temporarily stored inside the MDB. The multiply-accumulate unit can also be extended in bit width (such as extended to 32-bit) to prevent data overflow.

[0071] MDB also has internal registers such as the Weight Register, which are used to store preset AI weight data. It receives and statically resides a portion of the fixed operands required for calculation in advance, and writes the fixed operands (preset AI weight data) required for calculation into the internal register in advance and keeps them at a static level for reuse in subsequent burst calculations. When facing a continuous data stream, one end of the MAC array input maintains a static level, avoiding the power consumption caused by repeated reading or carrying the same data on the bus.

[0072] DRAM can be divided into two groups: the first rank and the second rank. Each of the first and second ranks communicates with the MDB. According to the MRDIMM architecture, when a single MDB is facing the underlying DRAM, it is responsible for handling the 4-bit wide data bus of each of the first and second ranks.

[0073] When a BL16 burst transmission is triggered, the first Rank continuously sends 16 data cycles on the 4-bit bus, for a total data volume of 4 × 16 = 64 bits. This data stream is demultiplexed into four 16-bit operand elements by the demultiplexer at the MDB receiver. Similarly, the interleaved BL16 burst operation of the second Rank also produces four 16-bit operand elements.

[0074] A single MDB can collect eight 16-bit operands through a single complete double-rank interleaved burst, accurately corresponding to the parallel input bit width of its eight internal MAC subunits. This mechanism eliminates the need for data concatenation across bursts or additional buffer reassembly circuits, enabling streaming computation of data.

[0075] During the AI ​​computation phase, if the MAC unit comprises 8 MAC sub-units, the MDB receives streaming operands from DRAM. Based on the aforementioned 8-MAC physical alignment mechanism: 4 operand elements from the first Rank and 4 operand elements from the second Rank enter the MAC array input in parallel. When these 8 data points reach the Data Ready state on the bus, the hardware logic circuit automatically triggers the strobe signal. The MAC immediately performs a parallel dot product operation on this burst of data and the preset AI weight data. Furthermore, the computation triggering process utilizes the inherent protocol gap between the first Rank and the second Rank, which is masked by MRDIMM, eliminating the need for a globally independent clock control.

[0076] In this embodiment, after the MDB transmits the data to be processed to the MAC unit, it determines whether there is any unprocessed data. The unprocessed data is the data previously received that has not been multiplied and accumulated. For example, when the MAC unit includes 8 MAC sub-units, the data to be processed is the data transmitted to the MDB by the first Rank, and the unprocessed data is the data transmitted to the MDB by the second Rank.

[0077] In this embodiment, when the MAC unit obtains the data to be processed, it calculates the sum of the number of operand elements between the unprocessed data and the data to be processed, and determines whether the sum of the number reaches the number of sub-units corresponding to the MAC sub-unit. For example, the unprocessed data includes 4 operand elements, the data to be processed includes 4 operand elements, the sum of the number of operands is 8, and the MAC unit includes 8 MAC sub-units, that is, the number of sub-units is 8. At this time, it is determined that the sum of the number reaches the number of sub-units.

[0078] When the MAC unit includes 8 MAC sub-units, if the number of sub-units reaches the specified number, each MAC sub-unit of the MAC unit performs multiplication and accumulation calculations on the data to be processed based on the preset AI weight data in its internal registers to obtain the calculation result. Specifically, the unprocessed data and the data to be processed are input to the input terminal of the MAC unit in parallel, that is, the four operand elements of the unprocessed data and the four operand elements of the data to be processed are input to each MAC sub-unit of the MAC unit in parallel, so that each operand element is input to a MAC sub-unit. When the 8 data reach the Data Ready state on the bus, the hardware logic circuit automatically triggers the strobe signal, and each MAC sub-unit performs multiplication and accumulation calculations on the received operand elements and the preset AI weight data to obtain the calculation result.

[0079] It should be noted that if the quantity and number of sub-units have not been reached, or if there is currently no unprocessed data, the unprocessed data is updated based on the current pending data. For example, if the MAC unit includes 8 MAC sub-units, the pending data is directly used as the unprocessed data. In other implementations, the number of MAC sub-units can be set appropriately according to requirements. For example, if the number of MAC sub-units is 16, the MDB needs to collect 16 16-bit operand elements through two complete double-rank interleaved bursts before performing multiplication and accumulation calculations. This may result in situations where the quantity and number of sub-units have not been reached. In such cases, the pending data is added to the unprocessed data to update the unprocessed data. This process continues until the number of operand elements in the unprocessed data reaches 12, at which point it is combined with the next pending data for multiplication and accumulation calculations.

[0080] Understandably, upon completion of the multiply-accumulate calculation, the MDB aggregates all the multiply-accumulate calculations. The aggregated result is then output through a standard DRAM interface and sent back to the host (CPU) in BL16 burst format conforming to the standard protocol. This transforms the high-frequency "reading a large number of parameters to the host" into in-place closed-loop calculation within the MDB, ultimately sending only a small amount of aggregated dot product results back to the host, significantly reducing the transmission load of the external high-speed SerDes interface.

[0081] In this embodiment, the computation is completely masked within the protocol gaps of Rank switching, requiring no hardware or timing parameter modifications to the host-side memory controller. The MDB's pinout, package, and electrical specifications are identical to standard MRDIMMs, allowing for seamless integration with existing test equipment.

[0082] Meanwhile, this embodiment utilizes BL16 specification mapping to package data into groups of 8 elements for burst calculation. The internal data path only undergoes a parallel level switch once when all the data is collected. Compared with the non-burst discrete transmission mode, it does not cause high-frequency level state switching of the MDB internal bus and control signals, reducing the signal toggle rate at the hardware level, thereby reducing dynamic switching power consumption.

[0083] This embodiment provides a data processing method. The method involves receiving data to be processed via an MDB. The MRCD of the MRDIMM performs alternating addressing operations on the first and second ranks of the MRDIMM, causing the data to be processed to be transmitted to the MDB in an interleaved manner. The MDB then transmits the data to be processed to a MAC unit. The MAC unit then performs multiplication and summation calculations on the data to be processed to obtain a calculation result. If the alternating addressing operation is completed, the MDB outputs a target calculation result to the corresponding CPU based on the calculation result. By setting a MAC unit in the MRDIMM, during the process of the MDB receiving data transmitted in an interleaved manner from the MRDIMM's ranks, the MAC unit performs multiplication and summation operations on AI weight data and activation vectors during the intervals between interleaving transmissions, and feeds back the corresponding target calculation result to the CPU. This significantly reduces the amount of data transmitted, reduces invalid data movement on the memory bus, effectively reduces bandwidth pressure and transmission power consumption, and achieves the effect of breaking down memory barriers and releasing bus bandwidth.

[0084] Meanwhile, by utilizing the inherent preparation period and interleaving gaps of memory read and write operations, the AI ​​computing process is cleverly hidden within the original data movement and waiting window. The CPU does not need to modify the core scheduling logic or wait additionally, achieving excellent system-level compatibility.

[0085] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the data processing method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0086] This application also provides a multiplexed memory module; please refer to [reference needed]. Figure 2 The multiplexed memory module is equipped with a data buffer chip MDB and a multiply-accumulate (MAC) unit. The MDB receives data to be processed, wherein the MRCD of the MRDIMM performs an alternating addressing operation on the first Rank and the second Rank of the MRDIMM, so that the data to be processed is transmitted to the MDB in an interleaved manner between the first Rank and the second Rank; The MDB transmits the data to be processed to the MAC unit; The MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result; If the alternating addressing operation is completed, the MDB outputs the target calculation result to the corresponding CPU based on the calculation result.

[0087] The multiplexed memory module provided in this application, employing the data processing method described in the above embodiments, can solve the technical problem of how to reduce bandwidth pressure and transmission power consumption, thereby improving the computing power of AI systems. Compared with the prior art, the beneficial effects of the multiplexed memory module provided in this application are the same as those of the data processing method provided in the above embodiments, and other technical features in the multiplexed memory module are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0088] This application provides a data processing apparatus, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the data processing method in Embodiment 1 above.

[0089] The following is for reference. Figure 3 This document illustrates a structural diagram of a data processing device suitable for implementing embodiments of this application. The data processing device in these embodiments may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 3 The data processing device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0090] like Figure 3As shown, the data processing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the data processing device. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the data processing device to communicate wirelessly or wiredly with other devices to exchange data. Although the figures show data processing devices with various systems, it should be understood that it is not required to implement or possess all of the systems shown. More or fewer systems may be implemented alternatively.

[0091] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0092] The data processing device provided in this application, employing the data processing method described in the above embodiments, can solve the technical problem of how to reduce bandwidth pressure and transmission power consumption, and improve the computing power of AI systems. Compared with the prior art, the beneficial effects of the data processing device provided in this application are the same as those of the data processing method described in the above embodiments, and other technical features of this data processing device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0093] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0094] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0095] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the data processing method described in the above embodiments.

[0096] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0097] The aforementioned computer-readable storage medium may be included in a data processing device or may exist independently without being assembled into a data processing device.

[0098] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by a data processing device, the data processing device causes the following: the MDB receives data to be processed, wherein the MRCD of the MRDIMM performs an alternating addressing operation on the first Rank and the second Rank of the MRDIMM, so that the first Rank and the second Rank are interleaved in transmitting the data to be processed to the MDB; the MDB transmits the data to be processed to the MAC unit; the MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain a calculation result; if the alternating addressing operation is completed, the MDB outputs the target calculation result to the corresponding CPU based on the calculation result.

[0099] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0101] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0102] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described data processing method. This solves the technical problem of how to reduce bandwidth pressure and transmission power consumption, and improve the computing power of AI systems. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the data processing method provided in the above embodiments, and will not be repeated here.

[0103] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data processing method described above.

[0104] The computer program product provided in this application can solve the technical problem of how to reduce bandwidth pressure and transmission power consumption, and improve the computing power of AI systems. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the data processing method provided in the above embodiments, and will not be repeated here.

[0105] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A data processing method, characterized in that, The method is applied to a multiplexed memory module (MRDIMM), which includes a data buffer chip (MDB) and a multiply-accumulate (MAC) unit. The data processing method includes: The MDB receives data to be processed, wherein the MRCD of the MRDIMM performs an alternating addressing operation on the first Rank and the second Rank of the MRDIMM, so that the data to be processed is transmitted to the MDB in an interleaved manner between the first Rank and the second Rank; The MDB transmits the data to be processed to the MAC unit. The MDB transmits the data to be processed to the MAC unit when the duration after acquiring the data reaches a preset time interval. The preset time interval is reasonably set based on the time consumption of multiplication and accumulation calculation and the time difference between the arrival of data from the first Rank and the second Rank in turn to the MDB, so that the time consumption of multiplication and accumulation calculation and the preset time interval are less than the time difference between the arrival of data from the first Rank and the second Rank in turn to the MDB. The MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result; If the alternating addressing operation is completed, the MDB outputs the target calculation result to the corresponding CPU based on the calculation result; The MAC unit is located within the MDB, and the MAC unit has multiple MAC sub-units; the MDB also has an internal register, which is used to store preset AI weight data. The steps by which the MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result include: If there is currently unprocessed data, determine the number of operand elements between the unprocessed data and the data to be processed, and whether the number of sub-units corresponding to the MAC sub-unit has been reached; If the sum of the given quantity reaches the number of sub-units, then each MAC sub-unit of the MAC unit performs multiplication and accumulation calculations on the data to be processed based on the preset AI weight data in the internal register to obtain the calculation result.

2. The data processing method as described in claim 1, characterized in that, The steps by which the MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result include: The MAC unit receives preset AI weight data; The MAC unit performs multiplication and accumulation calculations on the data to be processed based on the preset AI weight data to obtain the calculation result.

3. The data processing method as described in claim 1, characterized in that, If the alternating addressing operation is completed, the step of the MDB outputting the target calculation result to the corresponding CPU based on the calculation result includes: If the alternating addressing operation is completed, the MAC unit performs an accumulation operation on all the calculation results corresponding to the alternating addressing operation to obtain the target calculation result; The MDB outputs the target calculation result to the corresponding CPU.

4. The data processing method as described in claim 3, characterized in that, After the step of outputting the target calculation result in the MDB, the data processing method further includes: The MDB deletes all calculation results corresponding to the alternating addressing operation and the target calculation result.

5. The data processing method as described in claim 1, characterized in that, If the alternating addressing operation is completed, the step of the MDB outputting the target calculation result to the corresponding CPU based on the calculation result includes: The MAC unit updates the accumulated result corresponding to the alternating addressing operation based on the calculation result; If the alternating addressing operation is completed, the MDB will use the accumulated result as the target calculation result and output the target calculation result to the corresponding CPU.

6. The data processing method as described in claim 1, characterized in that, The steps by which the MAC unit performs multiplication and accumulation calculations on the data to be processed to obtain the calculation result include: The MAC unit performs multiplication and accumulation calculations on the data to be processed based on a preset time interval to obtain the calculation result.

7. The data processing method according to any one of claims 1 to 6, characterized in that, After the steps of determining the number of operand elements between the unprocessed data and the data to be processed and whether the number of sub-units corresponding to the MAC sub-unit has been reached, the data processing method further includes: If the quantity is less than the number of sub-units or there is no unprocessed data, then the unprocessed data is updated based on the current unprocessed data.

8. The data processing method according to any one of claims 1 to 6, characterized in that, The steps for obtaining the calculation result by having each MAC subunit of the MAC unit perform multiplication and accumulation calculations on the data to be processed based on the preset AI weight data in the internal register include: The unprocessed data and the data to be processed are input to the input terminal of the MAC unit in parallel. Each MAC subunit performs multiplication and accumulation calculations on the data corresponding to each operand element in the unprocessed data and the data to be processed based on the preset AI weight data to obtain the calculation result.

9. A data processing device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the data processing method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the data processing method as described in any one of claims 1 to 8.

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