A low-latency multi-bit data error correction method

Abstract

The application relates to the field of data error correction, in particular to a low-delay multi-bit data error correction method. The method comprises the following steps: segmenting original data at a sending end to obtain a plurality of segmented data; performing an exclusive OR operation on the segmented data to obtain parity field data; using a preset encoding process in an error correction algorithm to respectively obtain code words of each segmented data and code words of the parity field data; constructing to-be-transmitted data and sending the data to a receiving end; judging, according to a preset decoding process in the error correction algorithm, whether the code words of the segmented data correspond to received data with more than n-bit errors and whether the code words of the other segmented data and the parity field data correspond to received data with no more than n-bit errors; if yes, obtaining the segmented data according to the other segmented data and the parity field data; and constructing error-corrected data according to the segmented data and the other segmented data. The application can correct multi-bit errors and has low time delay.

Description

Technical Field

[0001] This invention relates to the field of data error correction, and in particular to a low-latency method for correcting multi-bit data errors. Background Technology

[0002] Currently, in large-scale FPGA emulators or other latency-sensitive transmission processes, the connections between chips or FPGAs have very high latency requirements and lack retransmission mechanisms (retransmission would double the latency). Furthermore, in large systems, long-distance or fiber optic transmissions may occasionally experience minor data errors. Therefore, error correction processing is needed to reduce these minor errors to an extremely low error rate without introducing significant latency.

[0003] In large-scale simulators, FPGA chips are connected using Time Division Multiplexing (TDM) and transmitted via fiber optic cables. Since fiber optic transmission inevitably introduces bit errors, ensuring stable transmission of TDM intellectual property (IP) cores between chips requires guaranteeing that the large system operates without data errors during stable cycles. Therefore, error correction mechanisms must be introduced, while simultaneously minimizing the impact on latency between TDM IP cores and avoiding excessive area increases to prevent overburdening subsequent placement and routing.

[0004] Among current error correction algorithms, Extended Hamming Error Correction (SEC-DED) codes have very low latency, but can only correct 1-bit errors and detect 2-bit errors, resulting in limited error correction capability. RS-FEC error correction codes have strong error correction capability, but require data buffering, introducing significant latency and consuming large amounts of RAM resources. BCH codes can detect multi-bit random errors, requiring only one clock cycle for encoding, but decoding is complex, requiring Chien search to traverse all bits; even with increased resources for parallel processing, it still requires about ten cycles, and with other overhead, the total latency reaches more than ten cycles; while TDM IP has a total latency of only a dozen cycles. The aforementioned error correction algorithms suffer from limitations such as only being able to correct a small number of bit errors or having high latency. How to correct multi-bit errors with low latency is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a low-latency multi-bit data error correction method to solve the above-mentioned problems.

[0006] According to the present invention, a low-latency multi-bit data error correction method is provided, the method comprising the following steps:

[0007] S100, the sending end segments the original data to obtain several segmented data.

[0008] S200, perform an XOR operation on the several segmented data to obtain the odd / even field data.

[0009] S300, using the encoding process in the preset error correction algorithm, the codewords of each segment of data and the codewords of the parity field data are obtained respectively; wherein, the codeword of any segment of data includes the segment of data and the corresponding check bit, and the codeword of the parity field data includes the parity field data and the corresponding check bit; the delay of the preset error correction algorithm is less than the preset delay threshold.

[0010] S400: Construct the data to be transmitted based on the codeword of each segment of data and the codeword of the parity field data, and send the data to be transmitted to the receiving end.

[0011] S500, the receiving end determines whether there are more than n bits of errors in the received data corresponding to the codeword of each segment of data according to the decoding process in the preset error correction algorithm; n is the maximum number of error-correctable bits corresponding to the preset error correction algorithm.

[0012] S600: If the received data corresponding to the codeword of a certain segment of data has more than n bits of error, and the received data corresponding to the codeword of other segment data and the codeword of the parity field data does not have more than n bits of error, then the segment of data is obtained based on the other segment data and the parity field data, and the error-corrected data is constructed based on the segment of data and the other segment data.

[0013] Compared with the prior art, the present invention has at least the following beneficial effects:

[0014] Based on the solution of this invention, an error correction algorithm with a latency less than a preset latency threshold is used (i.e., the encoding and decoding processes take fewer clock cycles), and the XOR operation does not require clock cycles. The recovery process based on the error status of each segment also only requires fewer clock cycles. Overall, this invention takes fewer clock cycles, which can ensure low latency. Furthermore, based on the segmentation strategy and the strategy for obtaining the parity field, this invention can improve the error correction capability and achieve the purpose of correcting multi-bit errors (for example, the preset error correction algorithm itself can only correct 1 bit error and detect 2 bit error, while this invention, based on the preset error correction algorithm, can correct at least 3 bit random errors or burst errors, and at most the number of segments + 2 bits of random errors or burst errors). Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart of a low-latency multi-bit data error correction method provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the processing procedure performed by the sending end according to Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the processing procedure performed by the receiving end according to Embodiment 1 of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1:

[0019] According to this embodiment, a low-latency multi-bit data error correction method is provided, the method including the following steps, such as... Figure 1 As shown:

[0020] S100, the sending end segments the original data to obtain several segmented data.

[0021] In this embodiment, the original data is the data that needs to be protected. The number of bits in the original data is divisible by the number of segments, and the number of bits in different segments obtained by segmenting the original data is equal. For example, if 40 bits of original data are segmented into 5 segments, then each segment is 8 bits; or, if it is segmented into 10 segments, each segment is 4 bits.

[0022] In a preferred embodiment, S100 further includes a process for determining the number of segments, which includes:

[0023] S110, obtain the number of candidate segments corresponding to the original data.

[0024] In this embodiment, the number of bits in the original data can be divided evenly by the number of candidate segments. For example, when the original data is 64 bits, the number of candidate segments can be 2, 4, 8, 16, etc. For example, when the original data is 40 bits, the number of candidate segments can be 2, 4, 5, 8, etc.

[0025] S120, for each candidate segment number, obtain the total number of bits T of the data to be transmitted corresponding to that candidate segment number; T=t1+t1 / m×s+(m+s)×t2, where t1 is the number of bits of the original data, m is the number of candidate segments, s is the number of check segments, and t2 is the number of check bits corresponding to each segment data when the number of segments is the same as the number of candidate segments.

[0026] In this embodiment, the verification segment refers to the segment set up for verifying the original data. The segmented data obtained by segmenting the original data does not belong to the verification segment. When S200 only obtains the parity field data, the verification segment only contains the parity field data, so s=1. If S200 obtains both the parity field data and the weight verification data, the verification segment includes both the parity field data and the weight verification data, so s=2.

[0027] Those skilled in the art will understand that once the error correction algorithm is determined, the number of parity bits corresponding to a specific number of bit segments can be determined. For example, when the error correction algorithm used is SEC-DED, the parity bits corresponding to 32-bit segments are 7 bits, the parity bits corresponding to 16-bit segments are 6 bits, the parity bits corresponding to 8-bit segments are 5 bits, and the parity bits corresponding to 4-bit segments are 4 bits.

[0028] S130, the number of candidate segments corresponding to the minimum total number of bits among the several candidate segment numbers is determined as the selected segment number.

[0029] As a specific implementation, when the original data is 64 bits, the number of candidate segments is: 2, 4, 8, 16; when the number of candidate segments is 2, T=t1+t1 / m+(m+1)×t2=64+64 / 2+3×7=117 bits; when the number of candidate segments is 4, T=t1+t1 / m+(m+1)×t2=64+64 / 4+5×6=110 bits; when the number of candidate segments is 8, T=t1+t1 / m+(m+1)×t2=64+64 / 8+9×5=117 bits; when the number of candidate segments is 16, T=t1+t1 / m+(m+1)×t2=64+64 / 16+17×4=136 bits. In this specific implementation, since the minimum total number of bits corresponds to 4 candidate segments, 4 is determined as the number of segments to be selected, that is, the original data is divided into 4 segments.

[0030] S200, perform an XOR operation on the several segmented data to obtain the odd / even field data.

[0031] In this embodiment, the number of bits in the segment data corresponding to different segments is equal, and the parity field data obtained by XORing the several segment data is equal to the number of bits in the segment data corresponding to each segment. For example, if the segment data corresponding to each segment is 8 bits, then the parity field data is also 8 bits.

[0032] Those skilled in the art are familiar with the process of the XOR operation, and will not elaborate further here.

[0033] S300, using the encoding process in the preset error correction algorithm, the codewords of each segment of data and the codewords of the parity field data are obtained respectively; wherein, the codeword of any segment of data includes the segment of data and the corresponding check bit, and the codeword of the parity field data includes the parity field data and the corresponding check bit; the delay of the preset error correction algorithm is less than the preset delay threshold.

[0034] In this embodiment, the preset latency of the error correction algorithm being less than the preset latency threshold means that the latency of the preset error correction algorithm is small enough to meet the user's latency requirements. The preset latency threshold is determined based on the user's latency requirements for the entire error correction process. If the user's latency requirement for the entire error correction process is no more than y clock cycles, then the preset latency threshold is less than or equal to yz clock cycles, where z is the number of clock cycles spent on processes other than the encoding and decoding processes within the error correction algorithm.

[0035] Those skilled in the art will understand that various error correction algorithms exist in the prior art, and the latency of different error correction algorithms is also known. For example, the latency of standard Hamming ECC and SEC-DED is relatively small, with a total latency of 2 clock cycles for the encoding and decoding processes; RS-FEC error correction code has a huge latency; and BCH code has a large latency of more than ten cycles. In this embodiment, an error correction algorithm with a latency less than a preset latency threshold is selected from the existing error correction algorithms as the preset error correction algorithm.

[0036] S400: Construct the data to be transmitted based on the codeword of each segment of data and the codeword of the parity field data, and send the data to be transmitted to the receiving end.

[0037] As a specific implementation, the codewords of each segment of data and the codewords of the parity field data are sequentially sorted to construct the data to be transmitted; that is, if the original data is divided into f segments, the constructed data to be transmitted sequentially includes: seg1, chk1, seg2, chk2, ..., segi, chki, ..., segf, chkf, parity, chkp, where segi is the segment data of the i-th segment obtained by dividing the original data, chki is the parity bit of segi, i ranges from 1 to f, f is the number of segments, parity is the parity field data, and chkp is the parity bit of the parity field data. Figure 2 As shown.

[0038] In a preferred implementation, S400 includes: interleaving the codewords of each segment of data and the codewords of the parity field data, and determining the interleaved data as the data to be transmitted. Interleaving refers to disrupting the order of the data, dividing originally continuous bits into different segments. This disperses consecutive errors that may occur during subsequent transmission across the received data corresponding to the codewords of different segment data and the parity field data, facilitating the correction of more bit errors.

[0039] S500, the receiving end determines whether there are more than n bits of errors in the received data corresponding to the codeword of each segment of data according to the decoding process in the preset error correction algorithm; n is the maximum number of error-correctable bits corresponding to the preset error correction algorithm.

[0040] It should be understood that during the process of transmitting data from the sending end to the receiving end, errors may occur, resulting in discrepancies between the data received by the receiving end and the data sent by the sending end. That is, the received data corresponding to the codeword of any segment of data may differ from the codeword of that segment; similarly, the received data corresponding to the codeword of the parity field data may differ from the codeword of the parity field data. If the number of differing bits is 1, it indicates a 1-bit error; if the number of differing bits is 2, it indicates a 2-bit error, and so on.

[0041] Those skilled in the art will know that different error correction algorithms correspond to different maximum number of bits that can be corrected. When the number of erroneous bits is less than or equal to the maximum number of bits that can be corrected for the error correction algorithm, the decoding process corresponding to the error correction algorithm can be used to correct the error and obtain the correct data.

[0042] Those skilled in the art will recognize that the process of using an error correction algorithm to determine whether data contains errors is existing technology. As a specific implementation, the preset error correction algorithm is SEC-DED, where n=1, meaning SEC-DED can correct 1 bit error and can detect 2 bit errors.

[0043] In this embodiment, if the data to be transmitted is obtained by sequentially sorting the codewords of each segment of data and the codewords of the parity field data, then the data received by the receiving end is the received data corresponding to the codewords of the first segment of data (the data before t1 / f is the received data corresponding to the first segment of data, and the data after t2 is the received data corresponding to the parity bit of the first segment of data), the data after t1 / f+t2 is the received data corresponding to the codewords of the second segment of data, and so on, with the last t1 / f+t2 being the received data corresponding to the codewords of the parity field data.

[0044] In this embodiment, if the data to be transmitted is obtained by interleaving the codewords of each segment of data and the codewords of the parity field data, then the received data corresponding to the codewords of each segment of data and the received data corresponding to the codewords of the parity field data are obtained according to the data position relationship corresponding to the interleaving sort.

[0045] like Figure 3 As shown, seg'1 represents the received data corresponding to seg1, chk'1 represents the received data corresponding to chk1, seg'2 represents the received data corresponding to seg2, chk'2 represents the received data corresponding to chk2, seg'f represents the received data corresponding to segf, chk'f represents the received data corresponding to chkf, parity' represents the received data corresponding to parity, and chk'p represents the received data corresponding to chkp.

[0046] S600: If the received data corresponding to the codeword of a certain segment of data has more than n bits of error, and the received data corresponding to the codeword of other segment data and the codeword of the parity field data does not have more than n bits of error, then the segment of data is obtained based on the other segment data and the parity field data, and the error-corrected data is constructed based on the segment of data and the other segment data.

[0047] Those skilled in the art will know that once the error correction algorithm is determined, the process of determining whether an error has occurred and the number of errors based on the decoding process of the error correction algorithm is prior art and will not be described in detail here.

[0048] As a specific implementation, obtaining the segmented data based on other segmented data and parity field data includes: performing an XOR operation on the other segmented data and parity field data, and determining the result as the segmented data. It should be understood that if the received data corresponding to the codewords of other segmented data or the codewords of the parity field data contains errors greater than 0 and not exceeding n bits, it is necessary to first obtain the other segmented data or parity field data according to the decoding process of a preset error correction algorithm, and then perform the aforementioned XOR operation.

[0049] As a specific implementation, S600 further includes: if the received data corresponding to the codeword of a certain segment of data has an error greater than 0 and not exceeding n bits, then the received data corresponding to the codeword of the segment of data is corrected according to the decoding process in the preset error correction algorithm.

[0050] As a specific implementation, S600 further includes: if the received data corresponding to the codeword of the parity field data has an error greater than 0 and not exceeding n bits, then the received data corresponding to the codeword of the parity field data is corrected according to the decoding process in the preset error correction algorithm.

[0051] As a specific implementation, the preset error correction algorithm is SEC-DED, which can correct 1-bit errors and detect 2-bit errors. Therefore, if a 1-bit error occurs during data transmission, it can be corrected using the SEC-DED decoding process, regardless of its location.

[0052] If a 2-bit error occurs during data transmission, and if the 2-bit error is distributed across the received data corresponding to codewords in different data segments or parity field data segments, it can be corrected using the SEC-DED decoding process. If the 2-bit error is distributed across the received data corresponding to codewords in parity field data segments, no processing is required. If the 2-bit error is distributed across the received data corresponding to codewords in a specific data segment, the erroneous data segment can be recovered by performing an XOR operation on the other data segments and the parity field data segments.

[0053] If a 3-bit error occurs during data transmission, and if the 3-bit error is distributed across the received data corresponding to codewords in different data segments or parity field data segments, it can be corrected using the SEC-DED decoding process. If the 3-bit error is distributed across the received data corresponding to codewords in the parity field data, no processing is needed. If the 3-bit error is distributed across the received data corresponding to codewords in the same data segment, the erroneous segment data can be recovered by XORing the parity field data with the other segment pairs. If the 3-bit error is distributed across two segments, one can be corrected using the SEC-DED decoding process, while the other can be corrected by XORing the other segment data with the parity field data.

[0054] If more bit errors occur during data transmission, and these errors are scattered across the received data corresponding to codewords in different data segments or parity field data, the SEC-DED decoding process can correct them. If the errors are distributed across the received data corresponding to codewords in the parity field data, no processing is required. If the errors are distributed across the received data corresponding to codewords in a specific data segment and SEC-DED detects them, the erroneous data segment is obtained by performing an XOR operation on other data segments and the parity field data.

[0055] When the preset error correction algorithm is SEC-DED, for sudden errors, the segmentation and interleaved sorting method can be used to distribute sequential errors into different segments. One segment can handle 2-bit errors, so it can correct up to the number of segments + 1 + 1 bits of error.

[0056] Figure 3 In the process, the preset control logic is the sorting logic corresponding to the segmentation of the original data by the sending end. The purpose is to arrange and combine the data according to the original order of each segment in the original data so that the position of each segment in the corrected data is the same as the order of each segment in the original data.

[0057] Based on the scheme of this embodiment, an error correction algorithm with a latency less than a preset latency threshold is used (i.e., the encoding and decoding processes take fewer clock cycles), and the XOR operation does not require clock cycles. The recovery process based on the error status of each segment also only requires fewer clock cycles. Overall, this embodiment takes fewer clock cycles, which can ensure low latency. Furthermore, based on the segmentation strategy and the strategy for obtaining the parity field, this embodiment can improve the error correction capability and achieve the purpose of correcting multi-bit errors (for example, the preset error correction algorithm itself can only correct 1 bit error and detect 2 bit error, while the present invention, based on the preset error correction algorithm, can correct at least 3 bit random errors or burst errors, and at most the number of segments + 2 bits of random errors or burst errors).

[0058] It should be understood that the stronger the error correction capability of the error correction algorithm, the lower the bit error rate, as shown in Table 1. To improve the error correction capability, a second embodiment is also provided, which can solve the error correction problem mentioned above where more bit errors occur and are distributed in the received data corresponding to codewords in two data segments.

[0059] Table 1

[0060]

[0061] Example 2:

[0062] Based on Embodiment 1, S200 further includes: obtaining weight verification data Q, Q=(g1*seg1)Xor(g2*seg2)…Xor(gi*segi)…Xor(gf*segf), where * represents Galois multiplication, Xor represents XOR operation, segi is the segment data of the i-th segment obtained by segmenting the original data, and the value of i ranges from 1 to f. gi is the weight of segi, gi≠0, and different segi correspond to different gi. Optionally, gi=2. i .

[0063] S300 also includes: obtaining the codeword of Q using the encoding process in the preset error correction algorithm; the codeword of Q includes Q and the corresponding parity bit.

[0064] S400 is replaced by: constructing the data to be transmitted based on the codeword of each segment of data, the codeword of the parity field data, and the codeword of Q, and sending the data to be transmitted to the receiving end.

[0065] S600 is replaced by: If the received data corresponding to the codewords of two segments of data has more than n bits of error, and the received data corresponding to the codewords of other segments of data, the codewords of the parity field data, and the codeword of Q does not have more than n bits of error, then the segment data is obtained based on the other segment data, the parity field data, and Q, and the error-corrected data is constructed based on the two segments of data and the other segments of data.

[0066] As a specific implementation, if the received data corresponding to the codewords of two segments of data has more than n bits of error, and the received data corresponding to the codewords of other segments of data, the codewords of the parity field data, and the codeword of Q does not have more than n bits of error, then: (1) use the addition and subtraction (i.e., XOR operation) and multiplication inverse of the Galois field to eliminate one of the erroneous segments of data; (2) calculate the other erroneous data segment segx; (3) XOR segx, the parity field data, and other segments of data together to recover the erroneous segment eliminated in (1). This (1)-(3) requires 3 more cycles of calculation, but it can solve the error correction problem in this complex case.

[0067] As a specific implementation, if the received data corresponding to the codeword of a certain segment of data has more than n bits of error, the received data corresponding to the codeword of the parity field data has more than n bits of error, and the received data corresponding to the codewords of other segment data and the codeword of Q does not have more than n bits of error, then the segment of data is obtained based on the other segment data and Q.

[0068] As a specific implementation, if the received data corresponding to the codeword of a certain segment of data has more than n bits of error, the received data corresponding to the codeword of Q has more than n bits of error, and the received data corresponding to the codewords of other segment data and the codewords of the parity field data does not have more than n bits of error, then the segment data is obtained based on the other segment data and the parity field data.

[0069] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention.

Claims

1. A low-latency multi-bit data error correction method, characterized by, The method includes the following steps: S100, the transmitting end segments the original data to obtain several segmented data; the number of bits in different segmented data is equal; S200, perform an XOR operation on the several segmented data to obtain parity field data; and obtain weight verification data Q, Q=(g1*seg1)Xor(g2*seg2)…Xor(gi*segi)…Xor(gf*segf), where * is Galois multiplication, Xor is the XOR operation, segi is the segmented data of the i-th segment obtained by segmenting the original data, i ranges from 1 to f, f is the number of segments; gi is the weight of segi, gi≠0, and different segi correspond to different gi; S300, using the encoding process in a preset error correction algorithm, the codewords of each segment of data and the codewords of the parity field data are obtained respectively; wherein, the codeword of any segment of data includes the segment data and the corresponding parity bit, and the codeword of the parity field data includes the parity field data and the corresponding parity bit; the delay of the preset error correction algorithm is less than a preset delay threshold; and the codeword of Q is obtained using the encoding process in the preset error correction algorithm; the codeword of Q includes Q and the corresponding parity bit; S400, construct the data to be transmitted based on the codeword of each segment of data, the codeword of the parity field data and the codeword of Q, and send the data to be transmitted to the receiving end; S500, the receiving end determines whether there are more than n bits of error in the received data corresponding to the codeword of each segment of data according to the decoding process in the preset error correction algorithm; n is the maximum number of error-correctable bits corresponding to the preset error correction algorithm. S600: If the received data corresponding to the codeword of two segments of data has more than n bits of error, and the received data corresponding to the codeword of other segments of data, the codeword of the parity field data, and the codeword of Q does not have more than n bits of error, then the two segments of data are obtained based on the other segments of data, the parity field data, and Q, and the error-corrected data is constructed based on the two segments of data and the other segments of data.

2. The low-latency multi-bit data error correction method of claim 1, wherein, S400 includes: interleaving the codewords of each segment of data and the codewords of the parity field data, and determining the data obtained after interleaving the data as the data to be transmitted.

3. The low-latency multi-bit data error correction method of claim 2, wherein, The received data corresponding to the codeword of each data segment and the received data corresponding to the codeword of the odd / even field data are obtained according to the data position relationship corresponding to the interleaved sorting.

4. The low-latency multi-bit data error correction method according to claim 1, characterized in that, The preset error correction algorithm is SEC-DED, n=1.

5. The low-latency multi-bit data error correction method according to claim 1, characterized in that, S100 also includes a process for determining the number of segments, which includes: S110, obtain the number of candidate segments corresponding to the original data; S120, for each candidate segment number, obtain the total number of bits T of the data to be transmitted corresponding to that candidate segment number; T=t1+t1 / m×s+(m+s)×t2, where t1 is the number of bits of the original data, m is the number of candidate segments, s is the number of check segments, and t2 is the number of check bits corresponding to each segment data when the number of segments is the same as the number of candidate segments. S130, the number of candidate segments corresponding to the minimum total number of bits among the several candidate segment numbers is determined as the selected segment number.

6. The low-latency multi-bit data error correction method according to claim 1, characterized in that, S600 further includes: if the received data corresponding to the codeword of a certain segment of data has an error greater than 0 and not exceeding n bits, then the received data corresponding to the codeword of the segment of data is corrected according to the decoding process in the preset error correction algorithm.

7. The low-latency multi-bit data error correction method according to claim 1, characterized in that, S600 further includes: if the received data corresponding to the codeword of the parity field data has an error greater than 0 and not exceeding n bits, then the received data corresponding to the codeword of the parity field data is corrected according to the decoding process in the preset error correction algorithm.

Images