PCIe device connection establishment status monitoring method

Abstract

This application proposes a method for monitoring the connection establishment status of PCIe devices, relating to the field of computer technology. When applied to a monitoring core independent of the CPU main core, the method includes: continuously sampling the state values ​​of the PCIe device's link training state machine in response to receiving a sampling signal sent by the CPU main core in response to a connection establishment start command; storing the sampled state values ​​in chronological order to a target storage space to form a state sequence; during the sampling process, using a preset sliding window, dynamically averaging the latest multiple state values ​​in the state sequence; when the calculated average value equals the target value, sending a connection establishment success command to the CPU main core; if, until the end of a preset time period, the calculated average value does not equal the target value, sending a connection establishment failure command to the CPU main core. This scheme can shorten the time required for PCIe connection establishment status judgment while achieving fault analysis for connection establishment failures at a low cost.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a method for monitoring the connection establishment status of a PCIe device. Background Technology

[0002] During server startup, it is necessary to establish links with the mounted Peripheral Component Interconnect Express (PCIe) devices and stabilize them in the L0 link state before subsequent device enumeration and driver loading can proceed. The PCIe device link establishment process is controlled by the Link Training and Status State Machine (LTSSM), whose values ​​represent the current state of the PCIe link.

[0003] In existing solutions, after the server CPU initiates a PCIe connection establishment, a fixed delay is typically used. After a preset time has elapsed, a specific PCIe register is read to check if the link is in the L0 state, thus determining whether the connection establishment was successful. In this solution, determining the success of the PCIe connection establishment relies on a waiting period, which significantly extends the server's startup time. A server may have multiple PCIe devices connected; if a waiting period is used for each device to determine the connection status, this will further cause the startup time to increase linearly with device data, impacting user experience.

[0004] Furthermore, if the connection fails to establish, technicians can only obtain the state value of the LTSSM at the last moment, without knowing what state transitions the LTSSM underwent before the failure, thus making it impossible to reconstruct the problem situation. Although some solutions attempt to store the changes of the LTSSM in registers for later retrieval, this solution is limited by the number of registers, resulting in limited information that can be recorded. Increasing the number of registers also increases chip area, tape-out costs, and chip design complexity.

[0005] Therefore, how to shorten the time required to determine the PCIe connection status while achieving fault analysis of connection failure at low cost has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The purpose of this application is to provide a method for monitoring the connection establishment status of PCIe devices, which can shorten the time required to determine the PCIe connection establishment status and achieve fault analysis and source tracing of connection establishment failures at low cost.

[0007] This application is implemented as follows: In a first aspect, this application provides a method for monitoring the connection establishment status of a PCIe device, applied to a monitoring core independent of the CPU main core. The method includes the following steps: in response to receiving a sampling signal, continuously sampling the state values ​​of the link training state machine of the PCIe device, wherein the sampling signal is a signal sent by the CPU main core to the monitoring core in response to a connection establishment start command; storing the sampled state values ​​in chronological order to a target storage space to form a state sequence; during the sampling process, using a preset sliding window to dynamically calculate the average value of the latest multiple state values ​​in the state sequence; when the calculated average value is equal to the target value, sending a connection establishment success command to the CPU main core; if, until the end of a preset time period, the calculated average value is not equal to the target value, sending a connection establishment failure command to the CPU main core.

[0008] Secondly, this application provides a method for monitoring the connection establishment status of a PCIe device, applied to a CPU main core. The method includes the following steps: in response to a connection establishment start command, a first interrupt signal is sent to a monitoring core independent of the CPU main core. The first interrupt signal is used to trigger the monitoring core to continuously sample the state values ​​of the link training state machine of the PCIe device, and store the sampled state values ​​in chronological order to a target storage space to form a state sequence. During the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence. When the calculated average value is equal to the target value, the success result is written to the target storage space, and a second interrupt signal is sent to the CPU main core. If the calculated average value is not equal to the target value until the end of a preset time period, the failure result is written to the target storage space, and a third interrupt signal is sent to the CPU main core. In response to receiving the second interrupt signal or the third interrupt signal, the target storage space is read to obtain the connection establishment result.

[0009] Thirdly, this application provides a method for monitoring the connection establishment status of a PCIe device, applied to a server. The server includes a CPU main core and a monitoring core independent of the CPU main core. The method includes the following steps: the CPU main core sends a first interrupt signal to the monitoring core in response to a connection establishment start command. Upon receiving the first interrupt signal, the monitoring core continuously samples the state values ​​of the PCIe device's link training state machine; the sampled state values ​​are stored in a target storage space in chronological order to form a state sequence; during the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence; when the calculated average value equals the target value, a success result is written to the target storage space, and a second interrupt signal is sent to the CPU main core; if, until the end of a preset time period, the calculated average value does not equal the target value, a failure result is written to the target storage space, and a third interrupt signal is sent to the CPU main core; wherein, both the second and third interrupt signals are used to trigger the CPU main core to read the target storage space to obtain the connection establishment result.

[0010] Compared with the prior art, this application has at least the following advantages or beneficial effects: This application proposes a method for monitoring the connection establishment status of PCIe devices. The method involves continuously sampling the state values ​​of the PCIe device's link training state machine and storing them chronologically in a target storage space to form a state sequence. This process comprehensively records all state transitions of the link training state machine during connection establishment, rather than just the final state value. When connection establishment fails, technicians can accurately reconstruct the state transitions the link training state machine underwent before the failure based on this state sequence, thereby precisely locating the fault and effectively solving the problem of difficult fault analysis due to the lack of process records.

[0011] Meanwhile, this application utilizes a preset sliding window during the sampling process to dynamically calculate the average of the latest multiple state values ​​in the state sequence, and determines the success of link establishment by comparing the average with the target value. This mechanism does not require a preset fixed waiting time. Once the link training state machine stabilizes in the L0 state at multiple consecutive sampling times, a link establishment success command is immediately sent to the CPU main core; if it fails to stabilize within the preset time period, a link establishment failure command is sent. This dynamic judgment method replaces the passive waiting time that relies on experience in existing solutions, significantly shortening the time required for link establishment status judgment. Especially for servers with multiple PCIe devices, it avoids the problem of startup time increasing linearly with the number of PCIe devices.

[0012] In other words, this application retains complete chain-building process information for fault analysis while enabling rapid and dynamic judgment of chain-building status. It also balances maintainability and startup efficiency at low cost, which helps improve the user experience, startup speed and operation and maintenance efficiency of servers and other devices. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart for determining the chain establishment status in the existing scheme; Figure 2 This is a flowchart of an embodiment of a PCIe device connection establishment status monitoring method according to this application; Figure 3 This is a schematic diagram illustrating the principle of the sliding window mechanism in one embodiment of this application; Figure 4 This is a flowchart of yet another embodiment of a PCIe device connection establishment status monitoring method according to this application; Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0015] Icons: 201, Processor; 202, Memory; 203, Communication Interface. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0017] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0018] In existing solutions, after the server CPU main core initiates a PCIe connection establishment, a fixed delay is generally used to determine whether the connection establishment is successful. However, in implementing this application, the inventors found that the existing solution still has significant room for improvement in terms of latency and fault tracing. Firstly, as... Figure 1As shown, the existing solution involves the server CPU initiating a PCIe connection establishment and then waiting for a period of time before reading specific PCIe registers to check if the link is in the L0 state, thus determining whether the connection establishment was successful. In other words, the determination of successful PCIe connection establishment relies entirely on a preset waiting time. If this preset waiting time is set too short, a judgment may be made before the connection establishment is complete, leading to false failures and wasting more time by needing to re-initiate the connection establishment or wait again. If it is set too long, although it can cover the connection establishment time under normal circumstances, it will significantly increase the server startup time. Therefore, to avoid the above problems, existing solutions typically employ various methods to optimize this preset waiting time.

[0019] Furthermore, if link establishment fails, technicians can only obtain the state value of the link training state machine at the last moment, and cannot reconstruct the complete state transition process of the link training state machine before the failure, making it difficult to locate the fault. Although some solutions attempt to store the link training state machine change process in registers, the number of registers is limited, and increasing the number of registers will increase the chip area, increase the tape-out cost, and increase the chip design complexity.

[0020] Based on the above analysis, this application proposes a PCIe device link establishment status monitoring method. By introducing a monitoring core independent of the CPU main core, the method continuously samples and stores the link training state machine state values ​​to fully record the link establishment process. At the same time, the method uses a sliding window averaging algorithm to dynamically determine whether the link establishment is stable in the L0 state, so as to achieve a low-cost balance between the traceability of the link establishment process and the efficiency of link establishment judgment.

[0021] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0022] It should be noted that this application can be applied to various scenarios involving PCIe device initialization. Typical application scenarios include the server boot process. By deploying an independent monitoring core (exemplarily an ARM M core, i.e., the ARM Cortex-M series processor core, belonging to the microcontroller (MCU) processor core under the ARM architecture) at the BIOS or firmware level, the connection status of various PCIe devices (such as network cards, storage controllers, GPUs, etc.) connected to the motherboard can be monitored and recorded, accelerating the boot process while providing a complete status trajectory for hardware fault diagnosis. Furthermore, it can be applied to hot-swapping scenarios in data center servers. When PCIe devices are dynamically connected, this application can quickly complete the connection determination and record process data, facilitating maintenance personnel to locate abnormal devices. It can provide data support for hardware reliability and maintainability while ensuring system boot efficiency.

[0023] Please see Figure 2 The method for monitoring the connection status of this PCIe device is applied to a monitoring core independent of the CPU main core. The method specifically includes the following steps: Step S101: In response to receiving the acquisition signal, continuously sample the state value of the link training state machine of the PCIe device. The acquisition signal is the signal sent by the CPU main core to the monitoring core in response to the link establishment start command.

[0024] When the CPU main core receives the link establishment start instruction, it enables the Ltssm state machine recording function by writing to registers. This triggers a sampling signal to the monitoring core (exemplarily an ARM M core), notifying it to begin operation. Once recording is enabled, the monitoring core can begin continuous sampling of the Ltssm state machine. That is, upon receiving the sampling signal, the monitoring core starts continuously sampling the state values ​​of the PCIe device's link training state machine. Continuous sampling means that the monitoring core repeatedly reads the current state value of the link training state machine at a certain frequency, rather than reading it only once. This continuous sampling ensures the temporal continuity of the Ltssm state machine's state values, providing a complete data source for subsequent fault analysis and facilitating sliding window averaging to promptly determine if the link establishment was successful.

[0025] It should be noted that the Ltssm state machine is actually a set of non-zero values ​​representing the current state of PCIe.

[0026] Step S102: Store the sampled state values ​​in the target storage space in chronological order to form a state sequence.

[0027] In step S102, by storing the sampled state values ​​in the target storage space (a pre-allocated storage area for storing link establishment process state data, which can store more information and is less expensive than registers) in chronological order, discrete sampling points can be transformed into ordered time-series data. This allows us to know not only which states occurred during the link establishment process, but also the order and duration of each state. Therefore, when link establishment fails, technicians can completely reconstruct the entire state transition process of the link training state machine during link establishment based on the state sequence stored in the target storage space, accurately pinpointing which state or state transition stage the failure occurred in, facilitating the analysis and tracing of link establishment faults.

[0028] For example, in some implementations of this application, the target storage space is static random access memory (SRAM), and both the CPU main core and the monitoring core can access SRAM. This allows SRAM to be used in scenarios involving frequent read / write operations on state sequences, leveraging its fast access speed and lack of refresh requirements. Furthermore, the fact that both the CPU main core and the monitoring core can access this SRAM means that the CPU main core can directly read the state sequences and link establishment results written by the monitoring core, without requiring additional data transfer or copying operations, thus simplifying system complexity.

[0029] Step S103: During the sampling process, a preset sliding window is used to calculate the dynamic average of the latest multiple state values ​​in the state sequence. When the calculated average is equal to the target value, a link establishment success instruction is sent to the CPU main core. If the calculated average is not equal to the target value until the end of the preset time period, a link establishment failure instruction is sent to the CPU main core.

[0030] First, it should be noted that step S103 is executed synchronously with steps S101 and S102, meaning that the judgment is performed simultaneously with sampling. In step S103, the monitoring core uses a preset sliding window to calculate the dynamic average of the latest multiple state values ​​in the state sequence. The preset sliding window refers to setting a fixed-size window that covers the most recent continuous segment of state values ​​in the state sequence; the dynamic average calculation means that as sampling continues, the window slides forward continuously, covering the latest set of state values ​​each time and calculating its average. The calculated average is compared with the target value: if the average equals the target value, it indicates that the link training state machine has been stable in the L0 state for the most recent consecutive sampling times, and the monitoring core sends a link establishment success command to the CPU main core; if, until the end of the preset time period, all calculated averages are not equal to the target value, it indicates that the link establishment process has failed to stably enter the L0 state within the specified time, and the monitoring core sends a link establishment failure command to the CPU main core.

[0031] By using the sliding window average value instead of single-point state judgment, instantaneous state jitter can be filtered out. Success is only achieved when multiple consecutive state values ​​are in the L0 state, ensuring the stability of the judgment result. At the same time, the judgment process and the sampling process are carried out in parallel, without waiting for a fixed delay, and feedback can be given immediately once the stability condition is reached.

[0032] In other words, in step S103 above, on the one hand, the sliding window average judgment mechanism avoids misjudgments caused by fluctuations in a single state sampling point, improving the accuracy of link establishment success judgment; on the other hand, this dynamic judgment mechanism allows the CPU main core to be notified immediately once the link establishment is stable, without the need for a fixed delay, which can shorten the time required for link establishment status judgment. This is especially true for servers with multiple peripheral components connected to rapidly interconnected devices, which can greatly shorten the time required for link establishment status judgment, facilitating rapid startup. In addition, the instruction mechanism for successful or failed link establishment allows the CPU main core to know the link establishment result in a timely manner, facilitating rapid advancement of subsequent startup processes or execution of fault handling.

[0033] For example, in some implementations of this application, the size of the preset sliding window is dynamically configured based on the type of PCIe device and / or the link rate. Different types of PCIe devices may have different state transition frequencies during link establishment, and the time window required for state stabilization also varies under different link rates. By dynamically configuring the sliding window size according to the type of PCIe device or the link rate, the judgment mechanism can better match the link establishment characteristics of specific devices. When the window size is configured appropriately, it can effectively filter out state jitter without excessively delaying the determination of successful link establishment. This dynamic configuration method makes this application applicable to various PCIe device scenarios, balancing judgment accuracy and response timeliness.

[0034] In summary, this application involves the monitoring core responding to the acquisition signal by continuously sampling the state values ​​of the link training state machine of the PCIe device and storing the sampled state values ​​in chronological order to the target storage space to form a state sequence. Simultaneously, during the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence. By comparing the average value with the target value, the success of link establishment is dynamically determined, and corresponding instructions are sent to the CPU main core.

[0035] In this process, the proposed solution not only preserves the complete state change process of the link training state machine through continuous sampling and storage, providing a data foundation for fault analysis, but also replaces fixed delay waiting with dynamic calculation through sliding window, providing immediate feedback when the state is stable. This shortens the link establishment judgment time while cost-effectively taking into account the fault analysis capability when the link establishment fails.

[0036] Based on the aforementioned scheme, in some implementations of this application, the step of continuously sampling the state value of the link training state machine of the PCIe device includes: polling and reading the state register of the link training state machine of the PCIe controller to obtain the state value. The step of storing the sampled state value into the target storage space in chronological order includes: when a non-zero state value is read for the first time, starting to store the state value into the target storage space in chronological order.

[0037] Polling reads refer to the monitoring core continuously and actively reading the status registers of the PCIe controller's link training state machine at a fixed frequency, ensuring timely capture of status value changes. Regarding storage, the monitoring core does not store all read status values. Instead, it only starts storing subsequently sampled status values ​​in chronological order when a non-zero status value is first read. This is because the link training state machine is typically in an initial state with a value of zero before link establishment begins; the status value only changes to a non-zero value after the link establishment process starts. By setting "first non-zero value read" as the storage initiation condition, invalid states before link establishment can be effectively filtered out. This avoids storing large amounts of redundant zero-value data, saving storage space, while ensuring that the stored state sequence is recorded promptly from the actual start of link establishment, enabling accurate identification of the complete state transition trajectory after link establishment during fault analysis.

[0038] Based on the aforementioned scheme, in some implementations of this application, the step of storing the sampled state values ​​into the target storage space in chronological order includes: starting from a fixed starting address of the target storage space, writing the sampled state values ​​into consecutive address units in bytes.

[0039] In this implementation, the monitoring core starts from a fixed starting address in the target storage space and writes the status values ​​obtained from each sampling sequentially into consecutive address units, byte by byte. This means that each status value occupies one byte of storage space, and the status value obtained from the next sampling is stored immediately adjacent to the position of the previous write, forming a tightly packed, uninterrupted data sequence.

[0040] This fixed starting address approach ensures that data recorded during each link establishment process is stored in a predictable location, facilitating subsequent reading and parsing. Writing data byte-by-byte sequentially to consecutive address units simplifies the storage structure, eliminating the need for complex address mappings and reducing the implementation complexity of the monitoring core. Furthermore, when link establishment fails and analysis is required, technicians can obtain the complete state sequence simply by reading sequentially from this fixed starting address, enabling rapid reconstruction of the link training state machine's state transition trajectory during link establishment.

[0041] Based on the aforementioned scheme, in some implementations of this application, the step of using a preset sliding window to dynamically calculate the average value of the latest multiple state values ​​in the state sequence includes: when the number of state values ​​in the state sequence reaches the size of the preset sliding window, calculating the average value of all state values ​​in the current sliding window; thereafter, whenever a new state value is obtained, the sliding window is slid forward one position, the earliest state value in the window is discarded, and the average value of all state values ​​in the current sliding window is recalculated.

[0042] Understandably, the monitoring kernel continuously accumulates state sequences during the sampling process. In this implementation, when the number of state values ​​in the state sequence first reaches the size of a preset sliding window, the average value of all state values ​​within the current sliding window is immediately calculated. Thereafter, each time a new state value is obtained, the sliding window is moved forward one position, discarding the oldest state value within the window to ensure the window always covers the latest set of state values, and the average value of all state values ​​within the current sliding window is recalculated. This process repeats until the average value meets the chain establishment success condition or the preset time period ends.

[0043] Thus, through the sliding window mechanism, each calculation is based on the most recent set of continuous state values, which can reflect the latest state trend of the link training state machine in a timely manner. The sliding method of discarding the oldest state value and incorporating the latest state value gives the average value calculation a dynamic update characteristic. It can filter out occasional state fluctuations and quickly respond to stable changes in the state, thereby ensuring the accuracy of judgment and realizing the instant capture of the moment of successful link establishment.

[0044] To enable those skilled in the art to more intuitively understand the sliding window mechanism of this application, it will be combined here with Figure 3 Let's illustrate this with a specific example.

[0045] In this example, the monitoring core is an ARM M core. For ease of explanation, it is assumed that the state values ​​of the link training state machine range from 0x1 to 0x20, corresponding to 32 states, where the L0 state, i.e., the successful link establishment state, corresponds to a state value of 0x10. The sliding window size is set to k; here, k=10 is used as an example for illustration. The sliding window mechanism of this application is implemented as follows: The first step is for the ARM M core to poll and read the registers of the link training state machine to obtain state values. When the 10th state value is obtained, the average of the 1st to 10th state values ​​is calculated. The ARM M core retrieves these 10 data points from the target memory space, calculates the average, and determines whether the average is equal to 0x10.

[0046] The second step involves reading the registers of the link training state machine if the average value is not equal to 0x10, and storing the newly acquired state value in the target storage space. At this point, the 11th state value is acquired. The ARM M core retrieves the 2nd to 11th state values ​​from the static random access memory, calculates the average value, and checks if it equals 0x10. If it still does not equal 0x10, the 3rd to 12th state values ​​are read and the average value is calculated, and so on. When the calculated average value equals 0x10, it indicates that the link training state machine has stabilized in the L0 state, and the link establishment is successful. If, within a preset time period, such as 500 milliseconds, all calculated average values ​​are not equal to 0x10, the link establishment is considered a failure.

[0047] Based on the aforementioned scheme, in some implementations of this application, the step of sending a successful link establishment instruction to the CPU main core includes: writing the successful link establishment result data to a specified memory address in the target storage space, and sending a successful link establishment instruction to the CPU main core, so that the CPU main core reads the specified memory address in response to the successful link establishment instruction to obtain the link establishment result. The step of sending a failed link establishment instruction to the CPU main core includes: writing the failed link establishment result data to a specified memory address in the target storage space, and sending a failed link establishment instruction to the CPU main core, so that the CPU main core reads the specified memory address in response to the failed link establishment instruction to obtain the link establishment result.

[0048] Understandably, this implementation, through a mechanism that combines result data with instructions (successful and failed link establishment instructions), enables the monitoring core to reliably transmit the success or failure information of link establishment to the CPU main core. Specifically, after determining that link establishment is successful, the monitoring core writes the successful link establishment result data to a designated memory address in the target storage space and sends a successful link establishment instruction to the CPU main core. Similarly, after determining that link establishment fails, the failed link establishment result data is written to the same designated memory address, and a failed link establishment instruction is sent to the CPU main core. Thus, the CPU main core, in response to the received instruction (successful or failed link establishment instruction), reads the designated memory address to obtain the link establishment result.

[0049] In this implementation, the result data is separated from the instruction. The instruction is used to immediately notify the CPU core that the link establishment has been completed, while the result data is stored in a shared target memory space for the CPU core to read as needed. This implementation ensures timely notification while avoiding the length limitations or parsing complexity associated with carrying data in the instruction. Furthermore, successful and failed link establishments share the same memory address, simplifying the CPU core's reading logic and eliminating the need to determine the read location based on the instruction type, further improving processing efficiency.

[0050] To provide a more intuitive understanding of this implementation for those skilled in the art, a specific example will be used here. Again, using the ARM M core as the monitoring core, the ARM M core, while recording the link training state machine state data, uses a sliding window averaging algorithm to determine whether the PCIe device has successfully established a link. Here, a maximum link establishment time is limited to 500 milliseconds; that is, the preset time period is 500 milliseconds.

[0051] If, within 500 milliseconds, the ARM M-core calculates that the PCIe device connection has been successfully established using the sliding window averaging algorithm, the ARM M-core writes 0x1 to a memory space accessible to both the CPU main core and the ARM M-core, and then initiates a hardware interrupt to the CPU main core by writing to a register. Upon receiving this hardware interrupt, the CPU main core reads the fixed memory space address agreed upon with the ARM M-core and checks if the value at that address is 0x1. If it is 0x1, the connection is considered successfully established.

[0052] If the ARM M-core fails to achieve a successful connection establishment within 500 milliseconds using the sliding window averaging algorithm, then upon completion of the 500-millisecond delay, the ARM M-core writes 0xFF to a memory space accessible to both the CPU main core and the ARM M-core, and initiates a hardware interrupt to the CPU main core via a register write. Upon receiving this hardware interrupt, the CPU main core reads the fixed memory address agreed upon with the ARM M-core and checks if the value at that address is 0xFF. If it is 0xFF, the connection establishment is deemed to have failed.

[0053] Based on the aforementioned scheme, in some implementations of this application, the acquisition signal, the successful connection establishment instruction, and the failed connection establishment instruction are hardware interrupt signals, which are used to trigger the monitoring core or the CPU main core to pause the current task and immediately process the corresponding event.

[0054] Understandably, when the acquisition signal, successful link establishment instruction, and failed link establishment instruction are all hardware interrupt signals, an instantaneous response mechanism between the monitoring core and the CPU main core can be implemented. Specifically, the acquisition signal, as a hardware interrupt signal, triggers the monitoring core to pause its current task and immediately begin continuous sampling of the link training state machine state values ​​of the PCIe device. Similarly, the successful link establishment instruction and the failed link establishment instruction, also as hardware interrupt signals, trigger the CPU main core to pause its current task and immediately read the specified memory address of the target storage space to obtain the link establishment result.

[0055] In this way, by using hardware interrupt signals for communication, critical events can be handled immediately without relying on polling or periodic checks at the software level. Thus, when a connection is established, the CPU core can immediately receive the result and proceed with subsequent processes; when a connection fails, fault information can also be obtained and processed promptly, avoiding wasted system waiting time due to response delays and further shortening the overall startup time.

[0056] Based on the aforementioned scheme, this application also proposes a method for monitoring the connection establishment status of a PCIe device, applied to a CPU main core. The method includes the following steps: In response to a connection establishment start command, a first interrupt signal is sent to a monitoring core independent of the CPU main core. The first interrupt signal is used to trigger the monitoring core to continuously sample the state values ​​of the link training state machine of the PCIe device, and store the sampled state values ​​in chronological order to a target storage space to form a state sequence. During the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence. When the calculated average value is equal to the target value, the success result is written to the target storage space, and a second interrupt signal is sent to the CPU main core. If the calculated average value is not equal to the target value until the end of a preset time period, the failure result is written to the target storage space, and a third interrupt signal is sent to the CPU main core. In response to receiving the second interrupt signal or the third interrupt signal, the target storage space is read to obtain the connection establishment result.

[0057] It is understood that this embodiment is based on the same concept as the PCIe device connection status monitoring method applied to the monitoring core, and describes the interaction process between the CPU main core and the monitoring core from the perspective of the CPU main core, realizing the collaborative processing of the connection connection task through interrupts and shared memory. Specifically, in response to the connection connection start command, the CPU main core sends a first interrupt signal to the monitoring core, which is independent of the CPU main core, triggering the monitoring core to perform continuous sampling, storage, and sliding window average calculation. After the monitoring core completes the judgment, it writes the success or failure result to the target storage space and sends the corresponding second or third interrupt signal to the CPU main core. After receiving the second or third interrupt signal, the CPU main core reads the target storage space to obtain the connection connection result. Thus, it is possible to shorten the time required for PCIe connection connection status judgment while realizing fault analysis and tracing of connection connection failures.

[0058] For the specific implementation process, please refer to the PCIe device connection status monitoring method applied to the monitoring core provided in the aforementioned embodiments, which will not be repeated here.

[0059] Based on the aforementioned solution, please refer to Figure 4This application also proposes a method for monitoring the connection establishment status of a PCIe device, applied to a server. The server includes a CPU main core and a monitoring core independent of the CPU main core. The method includes the following steps: the CPU main core sends a first interrupt signal to the monitoring core in response to a connection establishment start command. Upon receiving the first interrupt signal, the monitoring core continuously samples the state values ​​of the PCIe device's link training state machine; the sampled state values ​​are stored in a target storage space in chronological order to form a state sequence; during the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence. When the calculated average value equals the target value, a success result is written to the target storage space, and a second interrupt signal is sent to the CPU main core; if, until the end of a preset time period, the calculated average value does not equal the target value, a failure result is written to the target storage space, and a third interrupt signal is sent to the CPU main core; wherein, both the second and third interrupt signals are used to trigger the CPU main core to read the target storage space to obtain the connection establishment result.

[0060] It is understood that this embodiment is based on the same concept as the PCIe device connection status monitoring method applied to the monitoring core. By deploying a collaborative mechanism between the CPU main core and an independent monitoring core in the server, the connection monitoring task is entirely handled by the monitoring core. For the specific implementation process, please refer to the PCIe device connection status monitoring method applied to the monitoring core provided in the aforementioned embodiment; it will not be repeated here.

[0061] Please see Figure 5 This application provides an electronic device including at least one processor 201 and at least one memory 202. The processor 201 and the memory 202 are directly connected to each other, or communicate with each other through a communication interface 203, or are electrically connected through one or more communication buses or signal lines to achieve data transmission or interaction. The memory 202 stores program instructions that can be executed by the processor 201. The processor 201 can call the program instructions to execute the program instructions to implement any of the PCIe device connection status monitoring methods provided by the above-described implementation methods.

[0062] The memory 202 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0063] The processor 201 can be an integrated circuit chip with signal processing capabilities. The processor 201 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0064] Understandable. Figure 5 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown. Figure 5 The components shown can be implemented using hardware, software, or a combination thereof.

[0065] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor 201, implements a method for monitoring the connection status of any of the PCIe devices provided by the various implementations described above.

[0066] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0067] Furthermore, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, implement the steps of any of the PCIe device connection status monitoring methods provided by the various implementations described above.

[0068] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0069] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for monitoring the connection establishment status of a PCIe device, characterized in that, The method, applied to a monitoring core independent of the CPU main core, includes: In response to receiving the acquisition signal, the state value of the link training state machine of the PCIe device is continuously sampled. The acquisition signal is a signal sent by the CPU main core to the monitoring core in response to the link establishment start command. The sampled state values ​​are stored in the target storage space in chronological order to form a state sequence; During the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence. When the calculated average value is equal to the target value, a connection establishment success instruction is sent to the CPU main core. If the calculated average value is not equal to the target value until the end of the preset time period, a connection establishment failure instruction is sent to the CPU main core.

2. The method according to claim 1, characterized in that, The step of continuously sampling the state value of the link training state machine of the PCIe device includes: polling and reading the state register of the link training state machine of the PCIe controller to obtain the state value; The step of storing the sampled state values ​​into the target storage space in chronological order includes: when a non-zero state value is read for the first time, starting to store the state value into the target storage space in chronological order.

3. The method according to claim 1, characterized in that, The step of storing the sampled state values ​​into the target storage space in chronological order includes: starting from a fixed starting address of the target storage space, writing the sampled state values ​​into consecutive address units in bytes.

4. The method according to claim 1, characterized in that, The step of calculating the dynamic average of the latest multiple state values ​​in the state sequence using a preset sliding window includes: When the number of state values ​​in the state sequence reaches the size of the preset sliding window, calculate the average value of all state values ​​in the current sliding window; Subsequently, each time a new state value is obtained, the sliding window is moved forward one position, the earliest state value in the window is discarded, and the average value of all state values ​​in the current sliding window is recalculated.

5. The method according to claim 1, characterized in that, The step of sending a successful link establishment instruction to the CPU main core includes: writing the successful link establishment result data into a specified memory space address of the target storage space, and sending a successful link establishment instruction to the CPU main core, so that the CPU main core reads the specified memory space address in response to the successful link establishment instruction to obtain the link establishment result; The step of sending a link establishment failure instruction to the CPU main core includes: writing the result data of the link establishment failure into a specified memory space address of the target storage space, and sending a link establishment failure instruction to the CPU main core, so that the CPU main core reads the specified memory space address in response to the link establishment failure instruction to obtain the link establishment result.

6. The method according to claim 1 or 5, characterized in that, The acquisition signal, successful connection establishment instruction, and failed connection establishment instruction are hardware interrupt signals used to trigger the monitoring core or CPU main core to pause the current task and immediately process the corresponding event.

7. The method according to claim 1, characterized in that, The target storage space is a static random access memory (SRAM), and both the CPU main core and the monitoring core can access the SRAM.

8. The method according to claim 1, characterized in that, The size of the preset sliding window is dynamically configured based on the type of PCIe device and / or the link rate.

9. A method for monitoring the connection establishment status of a PCIe device, characterized in that, Applied to the CPU main core, the method includes: In response to the link establishment start command, a first interrupt signal is sent to the monitoring core, which is independent of the CPU main core. The first interrupt signal is used to trigger the monitoring core to continuously sample the state values ​​of the link training state machine of the PCIe device and store the sampled state values ​​in the target storage space in chronological order to form a state sequence. At the same time, during the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence. When the calculated average value is equal to the target value, the success result is written to the target storage space and a second interrupt signal is sent to the CPU main core. If the calculated average value is not equal to the target value until the end of the preset time period, the failure result is written to the target storage space and a third interrupt signal is sent to the CPU main core. In response to receiving a second or third interrupt signal, the target storage space is read to obtain the link establishment result.

10. A method for monitoring the connection establishment status of a PCIe device, characterized in that, Applied to a server, the server including a CPU main core and a monitoring core independent of the CPU main core, the method includes: The CPU main core sends a first interrupt signal to the monitoring core in response to the chain establishment start instruction; Upon receiving the first interrupt signal, the monitoring core continuously samples the state value of the link training state machine of the PCIe device. The sampled state values ​​are stored in the target storage space in chronological order to form a state sequence; During the sampling process, a preset sliding window is used to dynamically calculate the average value of the latest multiple state values ​​in the state sequence. When the calculated average value is equal to the target value, the success result is written to the target storage space and a second interrupt signal is sent to the CPU main core. If the calculated average value is not equal to the target value until the end of the preset time period, the failure result is written to the target storage space and a third interrupt signal is sent to the CPU main core. The second and third interrupt signals are used to trigger the CPU main core to read the target storage space to obtain the chain establishment result.

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