A computer system

Abstract

The application discloses a computer system in the computer technical field. The application can dynamically update bus segment identification in a device bus distribution process, and provides sufficient and accurate space for storing bus segment identification according to target information, so that the BIOS supports the dynamically changed PCIE Segment quantity, and does not need to interrupt system services, thereby improving the BIOS operation and maintenance efficiency, the management efficiency and flexibility of devices in the system; and the management controller and the BIOS synchronize the number of different bus segment identifications that have been distributed, so that correct data basis is provided for functions such as device fault diagnosis and communication between devices, and the normal effectiveness of related functions of the management controller and the BIOS related to device management on both ends can be ensured.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a computer system. Background Technology

[0002] PCIE Segment is a logical partitioning concept in the PCI Express bus that can be used to manage complex multi-level devices.

[0003] Typically, a BIOS supports a fixed number of PCIe segments, occupying a small amount of system memory for storage. Furthermore, modifying the number of PCIe segments supported by the BIOS requires updating the BIOS code, compiling the updated code, flashing the resulting binary file, and manually adjusting other related configurations. This significantly increases BIOS maintenance costs and time, and the flashing process requires system shutdown, interrupting system operations and reducing the efficiency of PCIe device management.

[0004] Therefore, how to flexibly change the number of PCIe segments supported by the system to improve the management efficiency of PCIe devices is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a computer system that can flexibly change the number of PCIE segments supported by the system to improve the management efficiency of PCIE devices.

[0006] In a first aspect, this application provides a computer system, including: a basic input / output system and a management controller; When enumerating peripherals, the basic input / output system dynamically updates and allocates bus segment identifiers. After allocation, it generates target information carrying the number of bus segment identifiers. Based on the target information, it selects the bus memory space corresponding to each bus segment identifier and synchronizes the target information to the management controller. The management controller stores the bus segment identifier corresponding to the corresponding peripheral in the idle bits of the peripheral endpoint identifier according to the target information, and manages and interacts with the corresponding peripheral based on the bus segment identifier.

[0007] Secondly, this application provides a device management method applied to a basic input / output system, comprising: dynamically updating and allocating bus segment identifiers when enumerating peripherals; generating target information carrying the number of bus segment identifiers after allocation; selecting the bus memory space corresponding to each bus segment identifier according to the target information; synchronizing the target information to the management controller; so that the management controller stores the bus segment identifier corresponding to the corresponding peripheral in the free bits of the peripheral endpoint identifier according to the target information; and managing and interacting with the corresponding peripheral based on the bus segment identifier.

[0008] Thirdly, this application provides another device management method applied to a management controller, including: Receive target information indicating the number of different bus segment identifiers synchronized by the basic input / output system; Based on the target information, the idle bits in the peripheral endpoint identifier are used to store the bus segment identifier corresponding to the corresponding peripheral, and the corresponding peripheral is managed and interacted with based on the bus segment identifier. Before synchronizing target information, the basic input / output system dynamically updates and allocates bus segment identifiers when enumerating peripherals. After allocation, target information carrying the number of bus segment identifiers is generated, and the bus memory space corresponding to each bus segment identifier is selected according to the target information.

[0009] Fourthly, this application provides an electronic device, including: a memory and a processor; Memory is used to store computer programs; The processor is used to execute the computer program to implement the aforementioned disclosed device management method.

[0010] Fifthly, this application provides a non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned disclosed device management method.

[0011] Sixthly, this application provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed device management method.

[0012] The beneficial effects of this application are as follows: The basic input / output system (BIOS) and the management controller cooperate to complete the enumeration of bus peripherals and the dynamic update and allocation of bus segment identifiers (such as the identifier of a PCIe segment). The number of bus segments supported by the BIOS is no longer fixed, and the bus memory space corresponding to each bus segment identifier is selected according to the target information, ensuring sufficient space to store each bus segment identifier. After completing the peripheral enumeration, the BIOS generates target information containing the number of bus segments and synchronizes it to the management controller. The management controller reuses the idle bits in the communication endpoint identifier to store the bus segment identifier of the corresponding peripheral and manages and interacts with the peripherals accordingly. It is evident that this scheme can dynamically update bus segment identifiers during device bus allocation and select the bus memory space corresponding to each bus segment identifier based on the target information. This provides sufficient and accurate storage space for each bus segment identifier, saving storage space and enabling the BIOS to support dynamically changing the number of PCIe segments without interrupting system services. This improves BIOS operation and maintenance efficiency, device management efficiency, and flexibility. Furthermore, since the management controller and BIOS synchronize the number of different allocated bus segment identifiers, this provides a correct data foundation for functions such as device fault diagnosis and inter-device communication, ensuring the normal operation of device management-related functions on both the management controller and BIOS.

[0013] Correspondingly, the equipment management method, apparatus, equipment, medium, and program product provided in this application also have the above-mentioned technical effects. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a computer system disclosed in this application; Figure 2 This is a flowchart of an equipment management method disclosed in this application; Figure 3 This is a flowchart of the second equipment management method disclosed in this application; Figure 4 This is a schematic diagram of a system architecture disclosed in this application; Figure 5 This is a schematic diagram of a bus memory space relocation method disclosed in this application; Figure 6 A server architecture diagram provided for this application; Figure 7 A terminal structure diagram provided for this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0017] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0018] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Currently, BIOS supports a fixed number of PCIe segments, occupying a small amount of system memory for recording. Modifying the number of PCIe segments supported by the BIOS requires updating the BIOS code, compiling the updated code, flashing the resulting binary file, and manually adjusting other related configurations. This significantly increases BIOS maintenance costs and time, and the flashing process requires system shutdown, interrupting system operations. Therefore, this application provides a device management solution that allows for flexible adjustment of the number of PCIe segments supported by the BIOS and BMC, thereby improving the management efficiency of PCIe devices.

[0020] The following is a brief explanation of the relevant technical terms used in this case: BIOS: Base Input / Output System. In this application, the base input / output system can specifically refer to a BIOS hardware entity with BIOS firmware programmed into it.

[0021] BMC: Baseboard Management Controller.

[0022] MTCP: Management Component Transport Protocol, is a protocol used to manage communication between system components. MCTP over PCIe specifically refers to this protocol transmitting management data over the PCI Express bus. This technology is primarily used in servers, data centers, and embedded systems for monitoring and controlling hardware devices (such as CPUs, GPUs, and SSDs).

[0023] A PCIe segment (also referred to as a bus segment in this article) is a logical partitioning concept in the PCI Express bus topology used to manage complex, multi-level device connections. Specifically, a PCIe segment is a physically isolated PCIe hierarchical domain, with each segment corresponding to an independent PCIe subsystem, such as different CPU domains in a multi-CPU server. Each PCIe segment has a unique segment number (also referred to as a bus segment identifier in this article), which is typically 0 in a single-host system.

[0024] Each segment contains a complete PCIe topology tree, including the root union, switches, and endpoints. Devices within a segment are uniquely addressed by bus number, device number, and function number (BDF), in the format: Segment:Bus:Device:Function, such as 0000:03:00.0 representing segment 0, bus 3, device 0, and function 0.

[0025] PCIe MMCFG: Memory Mapped Configuration Space, is a mechanism defined in the PCIe specification for accessing device configuration space via memory addresses. It is used to replace the traditional PCI I / O mapping configuration mechanism, significantly improving the access efficiency of the configuration space.

[0026] Specifically, each PCIe device (including root federations, switches, endpoint devices, etc.) contains a configuration space (standard 256 bytes + extended 4KB) to store critical information such as device ID, status, and base address register (BAR), which is the foundation for system identification and management of devices. Mapping the device's configuration space to the system's physical memory address space allows the CPU to access the configuration space through ordinary memory read / write instructions (rather than dedicated I / O instructions), simplifying the access process and improving efficiency.

[0027] MMCFG maps the configuration space through a fixed range of memory addresses. Its address format consists of three parts (32-bit or 64-bit address space): [Segment number] + [Bus number] + [Device number] + [Function number] + [Configuration space offset].

[0028] Specifically: Segment Number: 16 bits (0~65535), corresponding to a PCIe segment, valid only in multi-segment systems (default is 0 in single-segment systems).

[0029] Bus Number: 8 bits (0~255), identifies the bus within the segment.

[0030] Device Number: 5 bits (0~31), identifies the device on the bus.

[0031] Function Number: 3 digits (0~7), which identifies the function within the device (e.g., a network card may have multiple functions).

[0032] Configuration space offset: 12 bits (0~4095), corresponding to the byte offset of the 4KB extended configuration space (the traditional 256-byte offset is the lower 8 bits).

[0033] Address calculation formula (taking 64-bit as an example): MMCFG_BASE + (Segment<<28) + (Bus<<20) + (Device<<15) + (Function<<12) + Offset. MMCFG_BASE: The starting physical memory address allocated by the system for the MMCFG (set by firmware / BIOS, such as 0xE0000000). The offset design of each field ensures address uniqueness: for example, the bus number occupies 8 bits (2^8 = 256 buses), and each bus corresponds to 2^8 (device + function = 5 + 3 = 8 bits). Therefore, a single MMCFG segment has 256 buses × = 256 functions, and each function has 4KB of space: 256 functions × 4KB = 256MB.

[0034] See Figure 1 As shown in the figure, this application discloses a computer system, including: a basic input / output system and a management controller.

[0035] When enumerating peripherals (such as PCIe devices), the Basic Input / Output System (BIOS) dynamically updates and allocates bus segment identifiers. After allocation, it generates target information carrying the number of bus segment identifiers. Based on the target information, it selects the bus memory space corresponding to each bus segment identifier, stores each bus segment identifier in the bus memory space, and synchronizes the target information to the management controller. In one example, the BIOS uses the largest bus segment identifier as the target information; or it uses the data obtained by incrementing the largest bus segment identifier by one as the target information.

[0036] The management controller stores the bus segment identifier corresponding to the corresponding peripheral in the idle bits of the peripheral endpoint identifier according to the target information, and manages and interacts with the corresponding peripheral based on the bus segment identifier. Specifically, this embodiment can reuse the idle bits in the peripheral endpoint identifier to record the bus segment identifier of the corresponding peripheral. The management controller obtains the attribute information of each peripheral in the system; based on the target information and attribute information, it adds a flag bit representing the bus segment identifier corresponding to the peripheral for the communication and fault diagnosis functions of each peripheral; and records the flag bit in the idle bits of the peripheral endpoint identifier.

[0037] In one implementation, the BIOS also receives a first notification message from the management controller (such as the baseboard management controller) indicating that the system supports multiple bus segment identifiers; logs the information based on the first notification message; and, during the device initialization phase, performs steps to detect whether a device needs to be allocated a bus and other subsequent steps. In another implementation, the BIOS also receives a second notification message from the management controller indicating that the system supports a single bus segment identifier; generates corresponding configuration suggestion information based on the second notification message. The configuration suggestion information may include: the current system only supports a single segment; please configure the maximum supported limit of the system processor to 0; and the bus segment identifier generally starts from 0. Therefore, the management controller can send a first notification message indicating that the system supports multiple bus segment identifiers to the basic input / output system, causing the basic input / output system to log the information based on the first notification message; and allocate and update bus segment identifiers during the peripheral initialization phase. The management controller can also send a second notification message indicating that the system supports a single bus segment identifier to the basic input / output system, causing the basic input / output system to generate corresponding configuration suggestion information based on the second notification message.

[0038] In this embodiment, the process of dynamically updating bus segment identifiers by the Basic Input / Output System (PIOS) includes: when the PIOS detects a peripheral that needs bus allocation, it determines whether there are remaining quotas for the target bus segment identifier currently in use; if there are remaining quotas, the target bus segment identifier is allocated to the current peripheral, and the system continues to detect whether there are other peripherals that need bus allocation; if there are no remaining quotas and the target bus segment identifier meets the preset update conditions, the target bus segment identifier is updated, the updated target bus segment identifier is allocated to the current peripheral, and the system continues to detect whether there are other peripherals that need bus allocation; if no other peripherals that need bus allocation are detected, the allocation is confirmed to be complete. It can be seen that the PIOS can continuously detect bus peripherals, and when a peripheral to be allocated is identified, it first checks the remaining available quota of the current bus segment identifier. When there are still remaining identifiers, the peripheral allocation is completed directly; when the existing identifiers are exhausted and the preset update conditions are met, the bus segment identifier is automatically updated and then allocated to the current peripheral. The entire process continuously traverses and detects other peripherals to be processed until there are no more peripherals to be allocated, at which point the allocation process ends. This allows the bus segment identifier to be adjusted in real time according to the peripheral access status, adapting to different numbers of peripherals without modifying firmware code or flashing firmware, and adapting to operating scenarios with dynamically changing numbers of peripherals, ensuring that all types of access peripherals can obtain a matching bus segment identifier.

[0039] Specifically, the Basic Input / Output System (PIS) determines whether the used flag value of the target bus segment identifier is less than a first threshold. If the used flag value is less than the first threshold, it confirms that the target bus segment identifier has remaining usage; otherwise, it confirms that the target bus segment identifier has no remaining usage. Further, the PIS checks whether the target bus segment identifier is less than the maximum limit supported by the system processor. If so, it confirms that the target bus segment identifier meets preset update conditions; otherwise, it confirms that the target bus segment identifier does not meet the preset update conditions. Further, the PIS increments the target bus segment identifier by one; the incremented value is assigned to a preset global variable, and the value of the global variable is used as the updated target bus segment identifier and allocated to the current peripheral.

[0040] In one implementation, if the basic input / output system confirms that the target bus segment identifier does not meet the preset update conditions, it generates a prompt message indicating that the bus segment identifier has reached the maximum limit supported by the system processor.

[0041] In one implementation, the Basic Input / Output System (BIOS) determines the bus memory space in a first memory region and / or a second memory region based on the number of bus segment identifiers carried by the target information and the amount of space to be occupied; wherein the storage space of the first memory region is smaller than the storage space of the second memory region. Specifically, the BIOS can determine the bus memory space in the first memory region and / or the second memory region based on the target information, including: determining the bus memory space in the first memory region when the number of bus segment identifiers carried by the target information is not greater than a preset upper limit; determining the bus memory space in the second memory region when the number of bus segment identifiers carried by the target information is greater than the preset upper limit; first determining the bus memory space in the first memory region, and then, when the remaining space in the first memory region is lower than a threshold, supplementing the bus memory space in the second memory region. Therefore, when the number of bus segment identifiers carried by the target information is not greater than the preset upper limit, the bus memory space is determined in the first memory region; when the number of bus segment identifiers carried by the target information is greater than the preset upper limit, the bus memory space is determined in the second memory region. In other words: if the space to be occupied by the number of currently allocated bus segment identifiers is less than the remaining storage space in the first memory region, the storage space in the first memory region will be used; if the space to be occupied by the number of currently allocated bus segment identifiers exceeds the remaining storage space in the first memory region, the second memory region with the larger storage space will be used. Alternatively, bus memory space can be selected first from the smaller first memory region, and then selected from the second memory region when the remaining space in the first memory region is insufficient, thus supplementing the bus memory space.

[0042] Furthermore, the basic input / output system can also flexibly migrate and change the space occupied by the allocated bus segment identifier between the first and second memory regions based on the overall memory space usage and the actual peripheral device availability.

[0043] In one implementation, the basic input / output system writes target information into a first register; based on the register value in the first register, it determines a bus memory space in a first memory region and / or a second memory region (e.g., selecting a portion of the addresses in the first memory region and / or a portion of the addresses in the second memory region, the selected addresses constituting the bus memory space); it allocates corresponding memory segments in the bus memory space for different bus segment identifiers according to their size order; and it writes the address information of the bus memory space and the address information of the memory segments corresponding to different bus segment identifiers into a second register. The storage space of the first memory region is smaller than the storage space of the second memory region.

[0044] Please see Figure 5In one example, if two or fewer segments are configured or the number of peripherals is not large, 0-4GB of memory (corresponding to the first memory region) is used; if three or more segments are configured or the number of peripherals exceeds the limit, more than 4GB of memory is used (corresponding to the second memory region). In other words, the BIOS flexibly selects the required bus memory space based on the actual memory usage and the current peripheral initialization status. This could lead to a situation where the processor supports a maximum of eight segments, but a single segment is initially configured, using 0-4GB of memory; later, if support for four segments is increased, the newly added three segments will use more than 4GB of memory, while the previously used 0-4GB portion remains unchanged.

[0045] In this system memory region, the first memory region is the system memory region, and the second memory region is the user memory region. Since the user memory region is generally much larger than the system memory region (i.e., the address range of the user memory region is larger than that of the system memory region), transferring the space originally used to record bus segment identifiers from system memory to user memory can provide sufficient storage space for each bus segment identifier. Alternatively, both system memory and user memory regions can be used simultaneously to provide even more ample storage space for each bus segment identifier.

[0046] In this embodiment, the Basic Input / Output System (BIOS) and the Management Controller (MDC) work together to dynamically update and allocate bus peripherals and bus segment identifiers (such as PCIe Segment identifiers). The number of bus segments supported by the BIOS is no longer fixed, and sufficient memory space is provided by selecting the bus memory space corresponding to each bus segment identifier based on the target information. After completing peripheral enumeration, the BIOS generates target information containing the number of bus segments and synchronizes it to the MDC. The MDC reuses idle bits in the communication endpoint identifier to store the bus segment identifier of the corresponding peripheral and manages and interacts with the peripheral accordingly. This scheme dynamically updates bus segment identifiers during device bus allocation and provides ample space to store each bus segment identifier, enabling the BIOS to support dynamically changing PCIe Segment numbers without interrupting system services. This improves BIOS operation and maintenance efficiency, device management efficiency, and flexibility. Furthermore, the synchronization of the allocated number of different bus segment identifiers between the MDC and BIOS provides a correct data foundation for device fault diagnosis and inter-device communication, ensuring the normal operation of device management functions on both the MDC and BIOS ends.

[0047] The following describes a device management method provided by an embodiment of this application. The device management method described below can be referred to in conjunction with other embodiments described herein.

[0048] This application provides a device management method applied to a basic input / output system, comprising: dynamically updating and allocating bus segment identifiers when enumerating peripherals; generating target information carrying the number of bus segment identifiers after allocation; selecting the bus memory space corresponding to each bus segment identifier according to the target information; synchronizing the target information to the management controller; so that the management controller stores the bus segment identifier corresponding to the corresponding peripheral in the free bits of the peripheral endpoint identifier according to the target information; and managing and interacting with the corresponding peripheral based on the bus segment identifier.

[0049] Accordingly, the process of dynamically updating the bus segment identifier in the Basic Input / Output System (PIOS) includes: when the PIOS detects a peripheral that needs to be allocated a bus, it determines whether there is any remaining quota for the target bus segment identifier currently in use; if there is remaining quota, the target bus segment identifier is allocated to the current peripheral, and the system continues to detect whether there are any other peripherals that need to be allocated a bus; if there is no remaining quota and the target bus segment identifier meets the preset update conditions, the target bus segment identifier is updated, the updated target bus segment identifier is allocated to the current peripheral, and the system continues to detect whether there are any other peripherals that need to be allocated a bus; if no other peripherals that need to be allocated a bus are detected, the allocation is confirmed to be complete.

[0050] Please refer to the above. Figure 2 As shown in the illustration, this application discloses a more specific device management method applied to a basic input / output system, including: S201. Detect whether there is a device that needs to be allocated a bus; if there is a device that needs to be allocated a bus, then execute S202; if there is no device that needs to be allocated a bus, then execute S205.

[0051] This embodiment can be executed during the device enumeration phase of the server's system initialization process. Specifically, when the system initializes and enumerates each device (peripheral), it allocates a bus to each device. The specific allocation information includes: Segment (bus segment identifier): Bus (bus number): Device (device number): Function (function number). Each device can be a physical PCIe device or a logical PCIe device virtualized from a physical PCIe device. These physical PCIe devices are all connected to the server and can be peripheral devices such as network cards, accelerator cards, and memory. The specific implementation process of system initialization and device enumeration can refer to traditional related technologies and will not be elaborated here.

[0052] It's important to note that the number of segments supported by a server system varies depending on the processor model. For example, a certain type of processor supports a maximum of 4 segments (4 bus segment identifiers). Each bus segment identifier can be 0, 1, 2, or 3; and each bus segment identifier can be assigned to 0 to 255 devices. For instance, if the bus segment identifiers for devices 0 to 255 are all 0, the devices belonging to the same bus segment identifier 0 are distinguished by the different values ​​of their subsequent Bus:Device:Function values, ensuring each device has a unique Segment:Bus:Device:Function. That is, under the same bus segment identifier, there will be 256 devices, whose attribute information can be represented as 0:0:Device:Function to 0:255:Device:Function, distinguished by the 0 to 255 Bus numbers. Correspondingly, the bus segment identifiers for devices 256 to 510 can all be 1, and so on.

[0053] S202. Determine if there is any remaining usage of the bus segment identifier currently in use; if there is remaining usage of the bus segment identifier currently in use, then execute S203; if there is no remaining usage of the bus segment identifier currently in use, then execute S204.

[0054] In this embodiment, determining whether there is remaining usage of the bus segment identifier currently in use essentially means determining whether the 0-255 tag values ​​that can be allocated to each bus segment identifier have been exhausted. In one implementation, determining whether there is remaining usage of the bus segment identifier currently in use includes: determining whether the used tag values ​​of the bus segment identifier are less than a first threshold (e.g., 255); if the used tag values ​​are less than the first threshold, it is confirmed that there is remaining usage of the bus segment identifier; otherwise, it is confirmed that there is no remaining usage of the bus segment identifier.

[0055] S203. Assign a bus segment identifier to the device and continue to detect whether there are other devices that need to be assigned a bus.

[0056] S204. If the bus segment identifier meets the preset update conditions, update the bus segment identifier, assign the updated bus segment identifier to the device, and continue to detect whether there are other devices that need to be assigned a bus.

[0057] Referring to the example above, a certain type of processor supports a maximum of 4 segments. Each bus segment identifier can be 0, 1, 2, or 3. Therefore, updating the bus segment identifier means incrementing it by one. In one implementation, updating the bus segment identifier includes: incrementing the bus segment identifier by one; and assigning the incremented value to a preset global variable. Correspondingly, allocating the updated bus segment identifier to the device includes: using the value of the global variable as the updated bus segment identifier and allocating it to the device.

[0058] In one implementation, it is detected whether the bus segment identifier is less than the maximum limit supported by the system processor (e.g., a maximum limit of 4 segments supported by a certain type of processor); if so, it is confirmed that the bus segment identifier meets the preset update conditions; otherwise, it is confirmed that the bus segment identifier does not meet the preset update conditions. If the bus segment identifier does not meet the preset update conditions, a prompt message indicating that the bus segment identifier has reached the maximum limit supported by the system processor is generated.

[0059] S205. If no device requiring bus allocation is detected, determine the target information representing the number of different bus segment identifiers, configure the bus memory space corresponding to the target information, and synchronize the target information to the management controller so that the management controller manages device information based on the target information.

[0060] In one implementation, determining target information representing the number of different bus segment identifiers includes: using the largest bus segment identifier as target information; or using data obtained by incrementing the largest bus segment identifier by one as target information.

[0061] In one example, configuring the bus memory space (MMCFG space) corresponding to the target information includes: writing the target information into a first register (which may be a register in the processor that supports system operation); determining the bus memory space in a first memory region and / or a second memory region based on the register value in the first register; allocating corresponding memory segments in the bus memory space for different bus segment identifiers in order of their size; and writing the address information of the bus memory space and the address information of the memory segments corresponding to different bus segment identifiers into a second register (which may be a register in the processor that supports bus configuration).

[0062] Furthermore, the process of synchronizing the number of segments supported by the BIOS and the management controller can include: transmitting target information to the management controller via a preset protocol (such as IPMI, Redfish, etc.), so that the management controller obtains the number of different bus segment identifiers based on the target information, and manages device information based on the number of different bus segment identifiers. The number of different bus segment identifiers is: the currently supported number of segments. Transmitting the target information to the management controller via the preset protocol includes: writing the target information into a shared space shared by the basic input / output system and the management controller via the preset protocol, so that the management controller reads the target information from the shared space. Transmitting the target information to the management controller via the preset protocol also includes: transmitting the target information to a complex programmable logic device (CPL) via the preset protocol, so that the CPL forwards the target information to the management controller.

[0063] In this embodiment, during the device bus allocation process, the Basic Input / Output System dynamically updates the bus segment identifiers and completes the allocation as needed by real-time judgment of the remaining usage of the current bus segment identifiers. This enables the BIOS to support dynamically changing PCIe Segments without interrupting system services, effectively improving BIOS operation and maintenance efficiency, while enhancing the flexibility and adaptability of the system's device bus allocation mechanism. This achieves dynamic allocation and updating of bus segment identifiers, improving system adaptability and flexibility.

[0064] Furthermore, this embodiment constructs a closed-loop allocation logic encompassing remaining usage detection, identifier updates, and continuous allocation. This ensures that all devices in the system efficiently complete bus allocation, avoiding allocation stagnation or resource idleness caused by rigid identifier allocation rules, thus significantly improving the overall management efficiency of devices in the system. This optimizes the device bus allocation process and enhances the system's device management efficiency.

[0065] It should also be noted that the BIOS synchronizes the number of allocated bus segment identifiers, as mutually identifiable target information, to the management controller, ensuring data consistency. This provides an accurate data foundation for core functions such as device fault diagnosis and inter-device communication, effectively guaranteeing the normal operation of device management functions on both the BIOS and the management controller, and preventing functional failures or errors due to data inconsistency. This ensures data consistency between the BIOS and the management controller, supporting the stable operation of device management functions. Furthermore, based on the number of allocated bus segment identifiers, the required bus memory space is configured, accurately matching actual business needs. This avoids resource waste caused by excessive memory space configuration or business limitations caused by insufficient configuration, optimizing system resource allocation strategies, improving the rational utilization of memory resources, and achieving precise bus memory space configuration, thereby improving system resource utilization.

[0066] The following describes another device management method provided by an embodiment of this application. The device management method described below can be referred to in conjunction with other embodiments described herein.

[0067] The device management method provided in this application embodiment is applied to a management controller, including: receiving target information indicating the number of different bus segment identifiers synchronized by the basic input / output system; storing the bus segment identifier corresponding to the corresponding peripheral in the idle bits of the peripheral endpoint identifier based on the target information, and managing and interacting with the corresponding peripheral based on the bus segment identifier; wherein, before the basic input / output system synchronizes the target information, the basic input / output system dynamically updates and allocates bus segment identifiers when enumerating peripherals, and after the allocation is completed, generates target information carrying the number of bus segment identifiers, and selects the bus memory space corresponding to each bus segment identifier according to the target information.

[0068] Accordingly, the bus segment identifier corresponding to the corresponding peripheral is stored in the idle bits of the peripheral endpoint identifier based on the target information. This includes: obtaining the attribute information of each device in the system; and adding flag bits representing the bus segment identifier corresponding to the corresponding device to the communication function and fault diagnosis function of each device based on the target information and attribute information. The attribute information of each device may include: Segment (bus segment identifier): Bus (bus number): Device (device number): Function (function number). Among them, a preset number of bits (such as Bit6 and Bit7) in the endpoint identifier (such as Endpoint ID) of the corresponding device are used to record the flag bits. The flag bits that can be recorded by Bit6 and Bit7 include: 00, 01, 10, and 11. These four flag bits can each correspond to a bus segment identifier.

[0069] For more detailed information on the working process of each step in this embodiment, please refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0070] As can be seen, this embodiment provides a device management apparatus that can dynamically update bus segment identifiers during device bus allocation, enabling the BIOS to support dynamically changing the number of PCIe segments without interrupting system services. This improves BIOS operation and maintenance efficiency, device management efficiency, and flexibility. Furthermore, since the management controller and BIOS synchronize the number of different allocated bus segment identifiers, a correct data foundation is provided for functions such as device fault diagnosis and inter-device communication, ensuring the normal operation of device management-related functions on both the management controller and BIOS.

[0071] In one example, to enable BIOS support for adjusting the number of segments, a global variable X can be defined in the BIOS to identify the number of supported segments. The default value is 0, meaning only a single segment is supported. This variable can be, but is not limited to, the PCD value in the assignable UEFI architecture, or a Variable variable in the UEFI specification. Note that this global variable differs from global variables in ordinary software because the BIOS experiences different software environments during server startup and device initialization. For example, the memory space environment differs between the early and later stages of BIOS startup before initialization. Defining a variable in the early stages renders it inaccessible later due to changes in memory space.

[0072] Please see Figure 3 The BIOS defines a global variable X to record the number of supported segments. Then, the BIOS initializes all PCIe devices on the machine and allocates resources including Segment:Bus:Device.Function to each device. It checks the Bus Number to determine whether to update the segment; then it determines the required number of segments; if it's a single segment, the allocation ends; if it's multiple segments, the allocation continues. After allocation, the segment count is synchronized with the BMC so that the BMC can adapt to multi-segment functionality.

[0073] When allocating resources including Segment:Bus:Device.Function to devices, the allocation starts from SegmentNumber of 0 by default. The BIOS adds monitoring of the allocated Bus Number values. When BusNumber is allocated from 0 to 255 (meaning 256 Bus Numbers have been allocated, i.e., one Segment has been allocated its maximum supported Bus), the global variable X is incremented by 1, and the current value of X is assigned to the device's SegmentNumber. Then, for devices that haven't yet been allocated Segment Numbers, the current value of X is used, and the Bus Number is reset to start from 0, up to 255. This cycle repeats until all devices are initialized or the system's maximum supported Segment limit is reached. Therefore, the attribute information for each PCIe device is Segment:Bus:Device:Function. After all PCIe devices are initialized, the value of X+1 (because X is assigned starting from 0) represents the total number of Segments used in the current machine environment.

[0074] Accordingly, in the interaction between the BIOS and BMC, synchronization of the PCIe device Segment:Bus:Device.Function between the two is achieved. The BIOS can also transmit the total number of segments currently used on the system to the BMC, which is X+1 mentioned above. This transmission can be achieved through software methods such as IPMI, Redfish, and shared memory spaces; hardware methods such as shared memory chips; hardware signals accessible to both the BIOS and BMC; and firmware relay methods such as CPLD (BIOS->CPLD->BMC). If the BMC receives a Segment value (i.e., the value of X), then adding 1 to X yields the total number of segments currently used on the system. Accordingly, the system architecture applicable to this embodiment can be referred to... Figure 4 The system architecture diagram specifically includes: a device set consisting of BIOS, BMC, CPLD, and numerous PCIe devices.

[0075] Furthermore, the total number of segments supported by the BIOS needs to be filled into the corresponding CPU register that informs the system of the number of segments, so that the chip system function layer knows how many segments are currently supported, and can make corresponding adjustments to related functions such as MCTP and MMCFG.

[0076] To support PCIe architectures with multiple segments, the BIOS also needs to modify the MMCFG space accordingly. When the system supports multiple segments, the MMCFG space size will expand to a multiple of the total number of segments. This will be necessary in smaller system memory areas (such as...). Figure 5 Expanding the MMCFG space in the 0~4G area shown would affect other system functions supported by the system function memory area. Therefore, in this embodiment, the original space occupied by the MMCFG is moved to... Figure 5 The area shown is 4G~Max (user memory area), which has a larger space. Max is the maximum address of system memory. Expanding the MMCFG space means allocating corresponding address segments for each segment within the 4G~Max area. The address segments of each segment are sequentially accumulated to form the bus memory space.

[0077] In addition to optimizing and implementing corresponding solutions and functions in the BIOS, the BMC also needs to make corresponding design and implementation adjustments for multi-segment support. The BMC receives the actual number of segments supported from the BIOS and can determine whether that number is supported, specifically based on the processor model. For example, a certain processor's 7th generation and earlier CPUs can only support single-segment information acquisition and device monitoring. Therefore, if the BMC confirms that the current processor is in this situation, it can provide user prompts and logs through the BMC web interface, such as: the current CPU does not support MCTP multi-segment functionality and only supports single-segment; it can also provide user processing suggestions, such as switching back to the single-segment solution. Of course, this judgment function can be executed before the BIOS runs.

[0078] When the BMC confirms that the current system supports MCTP functionality with multiple segments, the BMC can make corresponding functional adjustments to MCTP, PCIe device asset information management, and PCIe device fault diagnosis. For example, this includes, but is not limited to, using the EID function design in the BMCMCTP to determine and support the segment attributes of devices. For instance, when the system supports two segments (0 and 1), the BMC can use whether bit 6 of the device's EID data is 0 or 1 to determine whether the device belongs to segment 0 or 1. When the system supports four segments, the BMC can use the combination of bit 6 and bit 7 of the device's EID data to determine which segment the device belongs to.

[0079] Therefore, this embodiment achieves adaptive adjustment of multiple PCIe segments across BIOS and BMC without requiring manual function adjustments or special settings. Furthermore, the BIOS and BMC can cooperate to support the function without any inconsistency in the number of segments supported. Moreover, the BIOS does not need to be recompiled and flashed with a new version due to the number of segments supported, which will not affect the operation of the user's upper-layer business and save BIOS version development costs.

[0080] The following describes a device management apparatus provided in an embodiment of this application. The device management apparatus described below can be referred to in conjunction with other embodiments described herein.

[0081] This application discloses a device management apparatus applied to a basic input / output system, comprising: The initialization module is used to dynamically update and allocate bus segment identifiers when enumerating peripherals. After allocation, it generates target information carrying the number of bus segment identifiers and selects the bus memory space corresponding to each bus segment identifier according to the target information. The synchronization module is used to synchronize target information to the management controller, so that the management controller stores the bus segment identifier corresponding to the corresponding peripheral in the idle bits of the peripheral endpoint identifier according to the target information, and manages and interacts with the corresponding peripheral based on the bus segment identifier.

[0082] In one implementation, the initialization module includes: The judgment unit is used to determine whether there is any remaining quota for the bus segment identifier currently in use when a device that needs to be allocated a bus is detected. The first allocation unit is used to allocate bus segment identifiers to devices if there is remaining capacity, and to continue to detect whether there are other devices that need to be allocated bus segments. The second allocation unit is used to update the bus segment identifier if there is no remaining usage and the bus segment identifier meets the preset update conditions, allocate the updated bus segment identifier to the device, and continue to detect whether there are other devices that need to be allocated a bus.

[0083] In one implementation, the synchronization module includes: The synchronization unit is used to determine the target information representing the number of different bus segment identifiers if no other devices that need to be allocated the bus are detected, configure the bus memory space corresponding to the target information, and synchronize the target information to the management controller so that the management controller can manage device information based on the target information.

[0084] In one implementation, the determining unit is specifically used for: Determine whether the used flag value of the bus segment identifier is less than the first threshold; If the used flag value is less than the first threshold, it is confirmed that there is remaining usage for the bus segment identifier; otherwise, it is confirmed that there is no remaining usage for the bus segment identifier.

[0085] In one implementation, it is detected whether the bus segment identifier is less than the maximum limit supported by the system processor; if so, it is confirmed that the bus segment identifier meets the preset update conditions; otherwise, it is confirmed that the bus segment identifier does not meet the preset update conditions.

[0086] In one implementation, the second allocation unit is specifically used for: Increment the bus segment identifier by one; The incremented value is assigned to a preset global variable.

[0087] In one implementation, the second allocation unit is specifically used for: The value of the global variable is used as the updated bus segment identifier and assigned to the device.

[0088] In one implementation, the synchronization unit is specifically used for: Use the largest bus segment identifier as the target information.

[0089] In one implementation, the synchronization unit is specifically used for: The data obtained by incrementing the maximum bus segment identifier by one is used as the target information.

[0090] In one implementation, the synchronization unit is specifically used for: Write the target information into the first register; Based on the register value in the first register, determine the bus memory space in the first memory region and / or the second memory region; In the bus memory space, allocate corresponding memory segments for different bus segment identifiers according to their size order. Write the address information of the bus memory space and the address information of the memory segment corresponding to different bus segment identifiers into the second register.

[0091] In one implementation, the synchronization unit is specifically used for: The target information is transmitted to the management controller through a preset protocol, so that the management controller can obtain the number of different bus segment identifiers based on the target information and manage the device information based on the number of different bus segment identifiers.

[0092] In one implementation, the synchronization unit is specifically used for: The target information is written into the shared space between the basic input / output system and the management controller through a preset protocol, so that the management controller can read the target information from the shared space.

[0093] In one implementation, the synchronization unit is specifically used for: The target information is transmitted to the complex programmable logic device (CPLD) through a preset protocol, so that the CPLD forwards the target information to the management controller.

[0094] In one implementation, it further includes: The first receiver is used to receive a first notification message from the management controller indicating that the system supports multiple bus segment identifiers; to log the information based on the first notification message; and during the device initialization phase, to perform the steps of detecting whether there are devices that need to be allocated a bus and other subsequent steps.

[0095] In one implementation, it further includes: The second receiver is used to receive a second notification message from the management controller indicating that the system supports a single bus segment identifier; and to generate corresponding configuration suggestion information based on the second notification message.

[0096] In one implementation, it further includes: The generation module is used to generate a prompt message indicating that the bus segment identifier has reached the maximum limit supported by the system processor if the bus segment identifier does not meet the preset update conditions.

[0097] For more detailed information on the working process of each module and unit in this embodiment, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0098] As can be seen, this embodiment provides a device management apparatus that enables the BIOS to support dynamically changing the number of PCIESegments, and the management controller and BIOS synchronize the number of different bus segment identifiers that have been allocated. This provides a correct data foundation for functions such as device fault diagnosis and inter-device communication, and ensures that the relevant functions of device management at both ends of the management controller and BIOS are functioning normally.

[0099] The following describes another device management device provided in the embodiments of this application. The device management device described below can be referred to in conjunction with the other embodiments described herein.

[0100] This application discloses another device management apparatus, applied to a management controller, including: The receiving module is used to receive target information indicating the number of different bus segment identifiers synchronized by the basic input / output system; The management module is used to store the bus segment identifier corresponding to the corresponding peripheral based on the idle bits in the peripheral endpoint identifier of the target information, and to manage and interact with the corresponding peripheral based on the bus segment identifier.

[0101] Before synchronizing target information, the basic input / output system dynamically updates and allocates bus segment identifiers when enumerating peripherals. After allocation, target information carrying the number of bus segment identifiers is generated, and the bus memory space corresponding to each bus segment identifier is selected according to the target information.

[0102] In one implementation, the Basic Input / Output System (BIOS) dynamically updates and allocates bus segment identifiers when enumerating peripherals. After allocation, target information carrying the number of bus segment identifiers is generated. The system then selects the bus memory space corresponding to each bus segment identifier based on the target information. This includes: the BIOS detecting whether there are devices that need bus allocation; when detecting devices, determining whether there are remaining bus segment identifiers; if there are remaining identifiers, allocating bus segment identifiers to the devices and continuing to detect whether there are other devices that need bus allocation; if there are no remaining identifiers and the bus segment identifiers meet preset update conditions, updating the bus segment identifiers, allocating the updated bus segment identifiers to the devices, and continuing to detect whether there are other devices that need bus allocation; if no other devices need bus allocation are detected, determining the target information and configuring the bus memory space corresponding to the target information.

[0103] In one implementation, the management module is specifically used for: Obtain the attribute information of each device in the system; Based on target information and attribute information, flag bits representing the corresponding bus segment identifier are added to the communication and fault diagnosis functions of each device.

[0104] In one implementation, a preset number of bits in the endpoint identifier of the corresponding device are used to record the flag bit.

[0105] For more detailed information on the working process of each module and unit in this embodiment, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0106] As can be seen, this embodiment provides a device management apparatus that enables the BIOS to support dynamically changing the number of PCIESegments, and the management controller and BIOS synchronize the number of different bus segment identifiers that have been allocated. This provides a correct data foundation for functions such as device fault diagnosis and inter-device communication, and ensures that the relevant functions of device management at both ends of the management controller and BIOS are functioning normally.

[0107] The following describes an electronic device provided by an embodiment of this application. The electronic device described below can be referred to in conjunction with other embodiments described herein. The electronic device in this embodiment can be a BMC or any processor running a BIOS.

[0108] This application discloses an electronic device, including: Memory, used to store computer programs; A processor is configured to execute the computer program to implement the methods disclosed in any of the above embodiments.

[0109] Furthermore, embodiments of this application also provide an electronic device. The aforementioned electronic device can be, for example,... Figure 6 The server shown can also be as follows: Figure 7 The terminal shown. Figure 6 and Figure 7 These are all diagrams illustrating the structure of an electronic device according to an exemplary embodiment. The content in the diagrams should not be considered as any limitation on the scope of this application.

[0110] Figure 6This is a schematic diagram of a server provided in an embodiment of this application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory stores a computer program, which is loaded and executed by the processor to implement the relevant steps in device management disclosed in any of the foregoing embodiments.

[0111] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0112] In addition, as a carrier for resource storage, the memory can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system, computer programs and data, etc., and the storage method can be temporary storage or permanent storage.

[0113] The operating system is used to manage and control the various hardware devices and computer programs on the server, enabling the processor to perform operations and processes on the data in the memory. It can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs capable of performing the device management methods disclosed in any of the foregoing embodiments, the computer programs may further include computer programs capable of performing other specific tasks. The data may include application update information and application developer information.

[0114] Figure 7 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. The terminal may include, but is not limited to, a smartphone, tablet computer, laptop computer, or desktop computer.

[0115] Typically, the terminal in this embodiment includes a processor and a memory.

[0116] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor can be implemented using at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and coprocessors. The main processor, also known as the CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which handles computational operations related to machine learning.

[0117] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory is used to store at least the following computer programs, which, after being loaded and executed by the processor, are capable of implementing the relevant steps in the device management method executed by the terminal side as disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory may also include operating systems and data, and the storage method may be temporary or permanent storage. The operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, application update information.

[0118] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0119] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on the terminal and may include more or fewer components than illustrated.

[0120] The following describes a non-volatile storage medium provided in an embodiment of this application. The non-volatile storage medium described below can be referred to in conjunction with other embodiments described herein.

[0121] A non-volatile storage medium is provided for storing a computer program, wherein the computer program, when executed by a processor, implements the device management method disclosed in the foregoing embodiments. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored thereon include an operating system, computer programs, and data, and the storage method can be temporary storage or permanent storage.

[0122] The following describes a computer program product provided by an embodiment of this application. The computer program product described below can be referred to in conjunction with other embodiments described herein.

[0123] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed device management method.

[0124] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium for storing a computer program that, when executed by a processor, implements the steps in any of the above embodiments.

[0125] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0126] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of non-volatile storage medium known in the art.

[0127] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A computer system, characterized in that, include: Basic input / output system and management controller; The number of bus segments supported by the basic input / output system is not fixed. When enumerating peripherals, the bus segment identifiers are dynamically updated and allocated. After allocation, target information carrying the number of bus segment identifiers is generated. The bus memory space corresponding to each bus segment identifier is selected according to the target information, and the target information is synchronized to the management controller. The bus segment identifier is SegmentNumber; when there are remaining bus segment identifiers, peripheral allocation is completed directly; when the bus segment identifiers are exhausted and the preset update conditions are met, the bus segment identifiers are automatically updated before peripheral allocation is performed. The management controller stores the bus segment identifier corresponding to the corresponding peripheral in the idle bits of the peripheral endpoint identifier according to the target information, and manages and interacts with the corresponding peripheral based on the bus segment identifier.

2. The computer system according to claim 1, characterized in that, When the basic input / output system detects a peripheral that needs to be allocated a bus, it determines whether there is any remaining quota for the target bus segment identifier currently in use. If there is remaining quota, the target bus segment identifier is allocated to the current peripheral, and the system continues to detect whether there are any other peripherals that need to be allocated a bus. If there is no remaining usage and the target bus segment identifier meets the preset update conditions, then the target bus segment identifier is updated, the updated target bus segment identifier is assigned to the current peripheral, and the system continues to detect whether there are other peripherals that need to be assigned a bus; if no other peripherals that need to be assigned a bus are detected, then the assignment is confirmed to be complete.

3. The computer system according to claim 2, characterized in that, The basic input / output system determines whether the used flag value of the target bus segment identifier is less than a first threshold; if the used flag value is less than the first threshold, it confirms that the target bus segment identifier has remaining usage; otherwise, it confirms that the target bus segment identifier has no remaining usage.

4. The computer system according to claim 2, characterized in that, The basic input / output system detects whether the target bus segment identifier is less than the maximum limit supported by the system processor. If so, then confirm that the target bus segment identifier meets the preset update conditions; Otherwise, it is confirmed that the target bus segment identifier does not meet the preset update conditions.

5. The computer system according to claim 2, characterized in that, The basic input / output system increments the target bus segment identifier by one; the incremented data is assigned to a preset global variable, and the value of the global variable is used as the updated target bus segment identifier and allocated to the current peripheral.

6. The computer system according to claim 2, characterized in that, The basic input / output system uses the maximum bus segment identifier as the target information; or uses the data obtained by incrementing the maximum bus segment identifier by one as the target information.

7. The computer system according to claim 2, characterized in that, If the basic input / output system confirms that the target bus segment identifier does not meet the preset update conditions, it generates a prompt message indicating that the bus segment identifier has reached the maximum limit supported by the system processor.

8. The computer system according to claim 1, characterized in that, The basic input / output system determines the bus memory space in a first memory region and / or a second memory region based on the number of bus segment identifiers carried by the target information and the amount of space to be occupied; wherein, the storage space of the first memory region is smaller than the storage space of the second memory region; Accordingly, when the number of bus segment identifiers carried in the target information is not greater than a preset upper limit, the basic input / output system determines the bus memory space in the first memory region; when the number of bus segment identifiers carried in the target information is greater than the preset upper limit, the system determines the bus memory space in the second memory region; the system first determines the bus memory space in the first memory region, and when the remaining space in the first memory region is lower than a threshold, the system then supplements the bus memory space in the second memory region.

9. The computer system according to any one of claims 1-8, characterized in that, The management controller sends a first notification message to the basic input / output system, indicating that the system supports multiple bus segment identifiers. Accordingly, the basic input / output system logs information based on the first notification message; Assign bus segment identifiers during the peripheral initialization phase; The management controller sends a second notification message to the basic input / output system, indicating that the system supports a single bus segment identifier. Accordingly, the basic input / output system generates corresponding configuration suggestion information based on the second notification message.

10. The computer system according to any one of claims 1-8, characterized in that, The management controller acquires the attribute information of each peripheral in the system; based on the target information and the attribute information, it adds a flag bit representing the bus segment identifier corresponding to the peripheral to the communication function and fault diagnosis function of each peripheral; wherein, the flag bit is recorded in the idle bit of the peripheral endpoint identifier.

Images