LDO power supply safe starting control device and method

Abstract

The application provides a kind of LDO power safe start control device and method, the device includes LDO unit and user load unit;The LDO unit includes standard LDO kernel module, random number generator, single-line authentication protocol module and perturbation injection module.System power-on, through single-line authentication protocol module and user load unit execute two-way identity authentication;Through, LDO enters normal voltage regulating mode;When failing, start hidden error injection mode, generate analog perturbation voltage and inject LDO control loop, so that output voltage produces controllable random disturbance, downstream chip can be powered on but cannot work stably.The application moves the security trust root to the power domain, uses hidden error injection to replace the traditional direct shutdown method, it is difficult for external to distinguish between safety lock and power failure, the anti-cracking ability is strong, the circuit is simple, and only single-line communication interface can complete authentication handshake.

Description

Technical Field

[0001] This invention belongs to the field of power management circuits and chip safety technology, specifically a power safety startup control device and method. Background Technology

[0002] With the rapid development and widespread application of information technology, information security has become a core concern in electronic system design. Information security encompasses multiple layers, including the application layer, operating system layer, circuit board layer, and chip layer. Among these, chip-level security mechanisms, due to their enclosed nature within the chip, provide the highest level of security authentication and protection.

[0003] In existing chip security solutions, low-dropout linear regulators (LDOs) are commonly used power management chips, primarily responsible for providing stable voltage to downstream load chips. Traditional chip systems typically employ a layered security strategy, implementing security verification through software protocols, encryption authentication, and key verification after the digital kernel boots up. While these security solutions can meet the basic requirements of most application scenarios, their inherent technical architecture inherently contains security flaws that are difficult to overcome.

[0004] Specifically, existing security authentication mechanisms suffer from significant time lags. The security verification process occurs after the chip has been powered on and started operating. At this point, attackers can potentially eavesdrop and speculate on the specific details of the encryption authentication process using side-channel attack methods such as power consumption analysis and electromagnetic radiation sampling. Attackers can roughly deduce the authentication process and the effective range of the key based on changes in the chip's power consumption patterns and the characteristics of the encryption algorithm used, and then crack the authentication through side-channel attacks.

[0005] Furthermore, during the window period after the system powers on, unauthorized users have ample time and a wealth of tools to comprehensively monitor and analyze the system authentication process. Once the location of the authentication circuit is discovered, targeted hardware cracking or firmware tampering attacks can be launched. Since the typical response to authentication failure is to directly shut off the power, this failure behavior is too obvious. It not only exposes the existence of the security mechanism but also allows attackers to bypass the authentication circuit through simple forced output methods, rendering the system's security protection capabilities virtually non-existent.

[0006] In response to the technical problems in existing technologies, such as delayed security verification, late protection nodes, and overly obvious failure behaviors, there is an urgent need for a new technical solution to improve the overall security of the chip system from the power supply head and achieve a more covert and effective hardware-level security protection mechanism. Summary of the Invention

[0007] The purpose of this invention is to solve the technical problems of delayed safety verification, delayed protection points, and obvious failure behavior in the prior art, and to provide an LDO power supply safety start-up control device and method.

[0008] The technical solution of this invention is: In a first aspect, the present invention provides an LDO power safe start control device, including an LDO unit and a user load unit; The LDO unit includes a standard LDO kernel module, a random number generator, a single-wire authentication protocol module, and a perturbation injection module; wherein... A standard LDO core module includes a bandgap reference source, an error amplifier, a power transistor, and a voltage divider feedback loop. The output of the bandgap reference source is connected to one input of the error amplifier. The other input of the error amplifier receives the feedback voltage output by the voltage divider feedback loop. The output of the error amplifier outputs a gate drive voltage to the gate of the power transistor. The source of the power transistor is connected to the system input power supply, and the drain serves as the LDO output to power the downstream load chip. A random number generator is used to generate random numbers; the random number generator is connected to the single-line authentication protocol module and the digital-to-analog conversion module; A single-wire authentication protocol module is used to perform bidirectional communication handshake with the user load unit during the power-on phase. It includes a first single-wire interface, a checksum receiving module, a decision module, and a first key memory. The communication signal terminal of the first single-wire interface is connected to the output terminal of an LDO via a pull-up resistor, and also connected to the second single-wire interface of the user load unit. The input terminal of the first single-wire interface is connected to the output terminal of a random number generator. The output terminal of the first single-wire interface is connected in series with the checksum receiving module and then connected to the checksum input terminal of the decision module. The key input terminal of the decision module is connected to the output terminal of the first key memory. The output terminal of the decision module is connected to the corresponding input terminals of the random number generator and the digital-to-analog converter module. The disturbance injection module includes a digital-to-analog converter for performing analog feature modulation on the random numbers generated by the random number generator, converting them into random analog disturbance voltages, and superimposing them onto the circuitry of the standard LDO core module through three injection nodes; The user load unit includes an existing logical user chip, a second single-line interface, and a verification module. The verification module has a second key memory. The LDO output of the LDO unit is connected to the existing logical user chip, the second single-line interface, and the verification module. The second single-line interface is connected to the first single-line interface and the verification module. The second single-line interface is used to receive the dynamic challenge code sent by the first single-line interface and forward it to the verification module. The verification module encrypts the dynamic challenge code based on the key generated by the second key memory and generates a verification code that is sent back to the first single-line interface through the second single-line interface.

[0009] Furthermore, the three injection nodes include injection node one, injection node two, and injection node three; The injection node is located between the output terminal of the bandgap reference source and the reference voltage input terminal of the error amplifier; The second injection node is located between the output of the voltage divider feedback loop and the feedback input of the error amplifier; The injection node three is located between the output of the error amplifier and the gate of the power transistor.

[0010] Furthermore, the voltage divider feedback loop is composed of resistor 1 and resistor 2 connected in series. One end of resistor 1 is connected to the output terminal of the LDO and the drain of the power transistor, and the other end is connected to resistor 2 and the feedback input terminal of the error amplifier. The other end of resistor 2 is grounded.

[0011] Furthermore, both the first key memory and the second key memory are non-volatile memories used to store symmetric keys in ciphertext form.

[0012] Furthermore, the random simulated disturbance voltage generated by the disturbance injection module is controlled within the range of 5%-10% of the LDO output voltage.

[0013] Furthermore, the three injection nodes are controlled by an auxiliary control switch; When the decision module outputs a high-level control signal, the auxiliary control switch is turned off, cutting off the connection between the output of the disturbance injection module and the control loop of the standard LDO kernel module; When the decision module outputs a low-level control signal, the auxiliary control switch closes, connecting the output of the disturbance injection module to the control loop of the standard LDO kernel module, and initiating covert error injection.

[0014] Secondly, the present invention provides an LDO power safe startup control method, applied to the aforementioned LDO power safe startup control device, comprising the following steps: S1, the system input power is powered on, the standard LDO kernel module enters the initial startup state, and the LDO output voltage is maintained at the preset initial supply voltage to the user load unit, and the disturbance injection module is in the off state by default when powered on; S2, the LDO unit performs handshake authentication with the user load unit through the single-wire authentication protocol module; If the authentication is successful, the LDO unit enters the normal voltage regulation mode, where the voltage is greater than the initial supply voltage. If authentication fails, the normal regulated operating voltage will be output, and the concealed error injection mode will be activated.

[0015] Furthermore, the handshake authentication described in S2 includes: A random number generator generates a dynamic challenge code, which is sent to the second single-line interface of the downstream user load unit through the first single-line interface. The second single-line interface receives the dynamic challenge code and forwards it to the verification module. The verification module encrypts the dynamic challenge code based on the key generated by the second key storage, generates a verification code, and sends it back to the first single-line interface through the second single-line interface. The first single-line interface forwards the verification code to the decision module through the verification code receiving module; The decision module decrypts and verifies the verification code based on the key generated by the first key storage. If the verification matches, the authentication is successful; otherwise, the authentication fails.

[0016] Furthermore, the activation of the covert error injection mode described in S2 includes: Start the random number generator to continuously output random numbers, and output them to the digital-to-analog conversion module; The digital-to-analog converter module converts the random number into a random analog disturbance voltage and injects it into the three injection nodes of the standard LDO kernel module control loop; The LDO output may generate random offsets, random noise, or slow fluctuations, causing the original logic user chip of the user load unit to output a normal regulated working mode voltage upon power-up, but it cannot work normally and stably.

[0017] Furthermore, the injection position of the random simulated disturbance voltage injection control device includes at least one of the following: injected into the reference voltage input terminal of the error amplifier, causing the voltage regulation target of the LDO to be randomly tampered with; injected into the feedback input terminal of the error amplifier, causing the error amplifier to misjudge the output voltage; injected into the output terminal of the error amplifier, directly interfering with the gate voltage of the power adjustment transistor.

[0018] Furthermore, if authentication fails, or the operation is to directly disable the LDO output.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. Security Authentication Moved to the Power Supply Level: This invention integrates a single-wire authentication protocol module within the LDO unit, performing bidirectional encrypted handshake authentication with the user load unit during power-up. Only after successful authentication does the LDO enter normal voltage regulation mode (output voltage rises to normal operating voltage); if authentication fails, a covert error injection mode is activated. Compared to traditional solutions that perform software authentication after chip startup, this invention moves the security boundary from the chip level to the power supply level, fundamentally preventing unauthorized chips from obtaining normal operating voltage and significantly improving overall system security.

[0020] 2. Covert Failure Mechanism, Strong Anti-Cracking Capability: When authentication fails, this invention can employ a simple explicit failure method of power-off, or use a perturbation injection module to generate random simulated perturbation voltages by converting random numbers generated by a random number generator into digital-to-analog conversion. This voltage is then injected into the three nodes of the standard LDO core module, causing random offsets, random noise, or slow fluctuations at the LDO output. Although the user load unit chip receives an output voltage upon power-up, it cannot operate stably. External attackers find it difficult to distinguish between a security lockout and a power failure, significantly improving anti-cracking capabilities.

[0021] 3. Simple circuit structure and low integration cost: This invention only adds a few circuits such as a random number generator, a single-wire authentication protocol module and a disturbance injection module to the traditional standard LDO core module. It does not significantly increase the chip area and power consumption, resulting in low cost and easy application.

[0022] 4. Single-wire communication interface, simplifying system integration: This invention adopts a single-wire authentication protocol module. The LDO unit and the user load unit communicate bidirectionally via a single communication signal line. The communication signal end is connected to the LDO output end through a pull-up resistor. Compared with multi-wire parallel communication schemes, single-wire communication significantly simplifies the system interface and improves integration and reliability.

[0023] 5. Encrypted Authentication, Anti-eavesdropping and Cracking: This invention adopts a symmetric key encryption authentication mechanism. A random number generator generates a dynamic challenge code, which is sent to the user load unit via the first single-line interface. The verification module encrypts the challenge code based on the key in the second key memory to generate a verification code and sends it back. The decision module decrypts and verifies based on the key in the first key memory. The entire authentication process adopts a dynamic challenge-response mode, which effectively avoids the risk of attackers cracking the authentication protocol by eavesdropping on the data line.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0025] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0026] Figure 1 A schematic block diagram of the LDO power safe start control device of the present invention is shown. Detailed Implementation

[0027] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0028] like Figure 1 As shown, an embodiment of the present invention provides an LDO power safety start control device, including an LDO unit and a user load unit. The LDO unit and the user load unit are connected for power supply through the LDO output terminal VOUT and communicate bidirectionally through a single-wire interface; The LDO unit includes a standard LDO kernel module, a random number generator, a single-wire authentication protocol module, and a perturbation injection module; wherein... A standard LDO core module includes a bandgap reference source, an error amplifier, a power transistor, and a voltage divider feedback loop. The output of the bandgap reference source is connected to one input of the error amplifier. The other input of the error amplifier receives the feedback voltage output by the voltage divider feedback loop. The output of the error amplifier outputs a gate drive voltage to the gate of the power transistor. The source of the power transistor is connected to the system input power supply, and the drain serves as the LDO output to power the downstream load chip. Specifically, the voltage divider feedback loop is composed of resistor 1 and resistor 2 connected in series. One end of resistor 1 is connected to the output terminal of the LDO and the drain of the power transistor, and the other end is connected to resistor 2 and the feedback input terminal of the error amplifier. The other end of resistor 2 is grounded.

[0029] A random number generator is used to generate random numbers; the random number generator is connected to the single-line authentication protocol module and the digital-to-analog conversion module; A single-wire authentication protocol module is used to perform bidirectional communication handshake with the user load unit during the power-on phase. It includes a first single-wire interface, a checksum receiving module, a decision module, and a first key memory. The communication signal terminal of the first single-wire interface is connected to the output terminal of an LDO via a pull-up resistor, and also connected to the second single-wire interface of the user load unit. The input terminal of the first single-wire interface is connected to the output terminal of a random number generator. The output terminal of the first single-wire interface is connected in series with the checksum receiving module and then connected to the checksum input terminal of the decision module. The key input terminal of the decision module is connected to the output terminal of the first key memory. The output terminal of the decision module is connected to the corresponding input terminals of the random number generator and the digital-to-analog converter module. The disturbance injection module includes a digital-to-analog converter for performing analog feature modulation on the random numbers generated by the random number generator, converting them into random analog disturbance voltages, and superimposing them onto the circuitry of the standard LDO core module through three injection nodes; The user load unit includes an existing logical user chip, a second single-line interface, and a verification module. The verification module has a second key memory. The LDO output of the LDO unit is connected to the existing logical user chip, the second single-line interface, and the verification module. The second single-line interface is connected to the first single-line interface and the verification module. The second single-line interface is used to receive the dynamic challenge code sent by the first single-line interface and forward it to the verification module. The verification module encrypts the dynamic challenge code based on the key generated by the second key memory and generates a verification code that is sent back to the first single-line interface through the second single-line interface.

[0030] Specifically, both the first key memory and the second key memory are non-volatile memories used to store symmetric keys in ciphertext form.

[0031] In one example, the random simulated disturbance voltage generated by the disturbance injection module is controlled within 5%-10% of the LDO output voltage; the three injection nodes are controlled by an auxiliary control switch. When the decision module outputs a high-level control signal, the auxiliary control switch is turned off, cutting off the connection between the output of the disturbance injection module and the control loop of the standard LDO kernel module; When the decision module outputs a low-level control signal, the auxiliary control switch closes, connecting the output of the disturbance injection module to the control loop of the standard LDO kernel module, and initiating covert error injection. The concealed error injection has three injection nodes. When initiating concealed error injection, one or more nodes can be selected to complete the injection. The three injection nodes include injection node one, injection node two, and injection node three. Injection node one is located between the output terminal of the bandgap reference source and the reference voltage input terminal of the error amplifier, and is used to randomly tamper with the voltage regulation target of the LDO. Injection node two is located between the output terminal of the voltage divider feedback loop and the feedback input terminal of the error amplifier, and is used to cause the error amplifier to misjudge the output voltage. Injection node three is located between the output terminal of the error amplifier and the gate of the power transistor, and is used to directly interfere with the gate voltage of the power adjustment transistor.

[0032] This invention provides an LDO power supply safe startup control method, comprising the following steps: S1. When the system input power is turned on (using an external battery or upstream power supply output), the standard LDO core module enters the initial startup state, maintaining the LDO output voltage at the preset initial supply voltage to the user load unit. The disturbance injection module is in the off state by default when it is powered on. S2 and LDO units perform handshake authentication with user load units through a single-line authentication protocol module; If the authentication is successful, the LDO unit enters the normal voltage regulation mode, where the voltage is greater than the initial supply voltage. If authentication fails, the normal regulated operating voltage will be output, and the concealed error injection mode will be activated; or the LDO output will be turned off directly.

[0033] In S2, performing handshake authentication includes: A random number generator generates a dynamic challenge code, which is sent to the second single-line interface of the downstream user load unit through the first single-line interface. The second single-line interface receives the dynamic challenge code and forwards it to the verification module. The verification module encrypts the dynamic challenge code based on the key generated by the second key storage, generates a verification code, and sends it back to the first single-line interface through the second single-line interface. The first single-line interface forwards the verification code to the decision module through the verification code receiving module; The decision module decrypts and verifies the verification code based on the key generated by the first key storage. If the verification matches, the authentication is successful; otherwise, the authentication fails.

[0034] In this embodiment, single-wire authentication is crucial to the system. Upon power-up, the user chip and power chip can interact and handshake via the single-wire authentication protocol to verify identity. To prevent attackers from eavesdropping, replaying, or simulating responses to the single-wire power communication, this invention employs an encrypted response mechanism based on a random challenge code. Each power-up generates a dynamic challenge value using an internal random number generator within the LDO, which is then combined with a key for encryption. External devices cannot obtain valid protocol characteristics through eavesdropping, significantly enhancing anti-cracking capabilities. The single-wire communication protocol physical layer uses an open-drain output with pull-up resistors, and communication is achieved through a time-division multiplexed bus driven by the power chip and user chip.

[0035] Furthermore, the activation of the covert error injection mode includes: Start the random number generator to continuously output random numbers, and output them to the digital-to-analog conversion module; The digital-to-analog converter module converts the random number into a random analog disturbance voltage and injects it into the three injection nodes of the standard LDO kernel module control loop; The LDO output may generate random offsets, random noise, or slow fluctuations, causing the original logic user chip of the user load unit to output a normal regulated working mode voltage upon power-up, but it cannot work normally and stably.

[0036] The injection position of the random simulated disturbance voltage injection control device includes at least one of the following: injected into the reference voltage input terminal of the error amplifier, causing the voltage regulation target of the LDO to be randomly tampered with; injected into the feedback input terminal of the error amplifier, causing the error amplifier to misjudge the output voltage; injected into the output terminal of the error amplifier, directly interfering with the gate voltage of the power adjustment transistor.

[0037] In this embodiment, after authentication failure, the output voltage "appears normal," but random, irregular disturbances / offsets are superimposed, causing the backend chip to "power on and run, but never work stably." External attackers cannot distinguish between a "power failure" and a "security lockout," making targeted attacks even more difficult.

[0038] For general-purpose LDO architectures, errors can be injected at different nodes of the control loop. This invention specifically proposes three implementation methods: 1. Inject random offset / noise into the reference voltage terminal (VREF) of EA; Implementation: A random analog signal generated by a random number generator and a digital-to-analog converter is superimposed on the VREF output of the bandgap reference source, and then fed into the negative input terminal of the error amplifier.

[0039] Effect: The LDO's voltage regulation target is randomly altered, and the output voltage VOUT will continuously and irregularly deviate from the nominal value (for example, nominally 3.3V, but actually fluctuating randomly between 3.1V and 3.5V).

[0040] Advantages: Minimal modifications, requiring only the addition of an adder between VREF and the error amplifier, with almost no increase in area.

[0041] 2. Inject random disturbances into the feedback input (VFB) of EA; Implementation: A random noise signal is superimposed on the output of the feedback voltage divider network and then fed into the positive input of the error amplifier.

[0042] Effect: The error amplifier misjudges the output voltage and continuously adjusts the conduction level of the power transistor, resulting in "pseudo-load fluctuations" in the output voltage and a significant increase in ripple.

[0043] Advantages: It can reuse the feedback path with the normal voltage regulation mode, and the access of disturbance signals can be controlled by a switch, making the logic simple and clear.

[0044] 3. Inject a random control signal into the output terminal (power transistor gate) of EA; Implementation method: Directly modify the drive signal from the error amplifier output to the power transistor gate, and superimpose random pulses or level offsets.

[0045] Effect: The on-resistance of the power transistor changes randomly, causing drastic random fluctuations in the output current and voltage, similar to a power supply with "severe noise".

[0046] Advantages: The disturbance effect is the most direct, and it can quickly destabilize the clock, phase-locked loop (PLL), and analog circuits (ADC / DAC) of the back-end digital circuits.

[0047] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A safe start control device for an LDO power supply, characterized in that, Includes LDO units and user load units; The LDO unit includes a standard LDO kernel module, a random number generator, a single-wire authentication protocol module, and a perturbation injection module; wherein... A standard LDO core module includes a bandgap reference source, an error amplifier, a power transistor, and a voltage divider feedback loop. The output of the bandgap reference source is connected to one input of the error amplifier. The other input of the error amplifier receives the feedback voltage output by the voltage divider feedback loop. The output of the error amplifier outputs a gate drive voltage to the gate of the power transistor. The source of the power transistor is connected to the system input power supply, and the drain serves as the LDO output to power the downstream load chip. A random number generator is used to generate random numbers; the random number generator is connected to the single-line authentication protocol module and the digital-to-analog conversion module; A single-wire authentication protocol module is used to perform bidirectional communication handshake with the user load unit during the power-on phase. It includes a first single-wire interface, a checksum receiving module, a decision module, and a first key memory. The communication signal terminal of the first single-wire interface is connected to the output terminal of an LDO via a pull-up resistor, and also connected to the second single-wire interface of the user load unit. The input terminal of the first single-wire interface is connected to the output terminal of a random number generator. The output terminal of the first single-wire interface is connected in series with the checksum receiving module and then connected to the checksum input terminal of the decision module. The key input terminal of the decision module is connected to the output terminal of the first key memory. The output terminal of the decision module is connected to the corresponding input terminals of the random number generator and the digital-to-analog converter module. The disturbance injection module includes a digital-to-analog converter for performing analog feature modulation on the random numbers generated by the random number generator, converting them into random analog disturbance voltages, and superimposing them onto the circuitry of the standard LDO core module through three injection nodes; The user load unit includes an existing logical user chip, a second single-line interface, and a verification module. The verification module has a second key memory. The LDO output of the LDO unit is connected to the existing logical user chip, the second single-line interface, and the verification module. The second single-line interface is connected to the first single-line interface and the verification module. The second single-line interface is used to receive the dynamic challenge code sent by the first single-line interface and forward it to the verification module. The verification module encrypts the dynamic challenge code based on the key generated by the second key memory and generates a verification code that is sent back to the first single-line interface through the second single-line interface.

2. The LDO power supply safety start control device as described in claim 1, characterized in that, The three injection nodes include injection node one, injection node two, and injection node three; The injection node is located between the output terminal of the bandgap reference source and the reference voltage input terminal of the error amplifier; The second injection node is located between the output of the voltage divider feedback loop and the feedback input of the error amplifier; The injection node three is located between the output of the error amplifier and the gate of the power transistor.

3. The LDO power supply safety start control device as described in claim 1, characterized in that, The voltage divider feedback loop is composed of resistor 1 and resistor 2 connected in series. One end of resistor 1 is connected to the output terminal of the LDO and the drain of the power transistor, and the other end is connected to resistor 2 and the feedback input terminal of the error amplifier. The other end of resistor 2 is grounded.

4. The LDO power supply safety start control device as described in claim 1, characterized in that, Both the first key memory and the second key memory are non-volatile memories used to store symmetric keys in ciphertext form.

5. The LDO power supply safety start control device as described in claim 2, characterized in that, The random simulated disturbance voltage generated by the disturbance injection module is controlled within 5%-10% of the LDO output voltage; the three injection nodes are controlled by an auxiliary control switch. When the decision module outputs a high-level control signal, the auxiliary control switch is turned off, cutting off the connection between the output of the disturbance injection module and the control loop of the standard LDO kernel module; When the decision module outputs a low-level control signal, the auxiliary control switch closes, connecting the output of the disturbance injection module to the control loop of the standard LDO kernel module, and initiating covert error injection.

6. A method for safe startup control of an LDO power supply, applied to the safe startup control device of an LDO power supply as described in any one of claims 1-5, characterized in that, Includes the following steps: S1. When the system input power is turned on, the standard LDO core module enters the initial startup state, maintaining the LDO output voltage at the preset initial supply voltage to the user load unit. The disturbance injection module is in the off state by default when it is powered on. S2 and LDO units perform handshake authentication with user load units through a single-line authentication protocol module; If the authentication is successful, the LDO unit enters the normal voltage regulation mode, where the voltage is greater than the initial supply voltage. If authentication fails, the normal regulated operating voltage will be output, and the concealed error injection mode will be activated.

7. The LDO power supply safe start control method as described in claim 6, characterized in that... In S2, the handshake authentication process includes: A random number generator generates a dynamic challenge code, which is sent to the second single-line interface of the downstream user load unit through the first single-line interface. The second single-line interface receives the dynamic challenge code and forwards it to the verification module. The verification module encrypts the dynamic challenge code based on the key generated by the second key storage, generates a verification code, and sends it back to the first single-line interface through the second single-line interface. The first single-line interface forwards the verification code to the decision module through the verification code receiving module; The decision module decrypts and verifies the verification code based on the key generated by the first key storage. If the verification matches, the authentication is successful; otherwise, the authentication fails.

8. The LDO power supply safe start control method as described in claim 6, characterized in that... In S2, the activation of the covert error injection mode includes: Start the random number generator to continuously output random numbers, and output them to the digital-to-analog conversion module; The digital-to-analog converter module converts the random number into a random analog disturbance voltage and injects it into the three injection nodes of the standard LDO kernel module control loop; The LDO output may generate random offsets, random noise, or slow fluctuations, causing the original logic user chip of the user load unit to output a normal regulated working mode voltage upon power-up, but it cannot work normally and stably.

9. The LDO power supply safe start control method as described in claim 8, characterized in that, The injection position of the random simulated disturbance voltage injection control device includes at least one of the following: injected into the reference voltage input terminal of the error amplifier, causing the voltage regulation target of the LDO to be randomly tampered with; injected into the feedback input terminal of the error amplifier, causing the error amplifier to misjudge the output voltage; injected into the output terminal of the error amplifier, directly interfering with the gate voltage of the power adjustment transistor.

10. The LDO power supply safe start control method as described in claim 6, characterized in that, If authentication fails, or the operation is to directly disable LDO output.

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