An automatic design method for NPU chip

Abstract

The present application relates to the technical field of NPU chip design, in particular to an NPU chip automatic design method. The NPU chip automatic design method of the present application realizes full-link automatic iteration optimization from parameterized RTL generation to logic synthesis by introducing multi-objective Bayesian optimization assisted by transfer learning. Therefore, the method can efficiently utilize historical design experience, reduce the demand for expensive simulation and synthesis samples, and effectively overcome the defects of artificial dependence, slow iteration, high sample cost and difficulty in balancing multiple objectives in traditional design. Finally, in the design of NPU chips, the synergistic optimization effect of power consumption, performance and area (PPA) can be stably improved, the design cycle can be significantly shortened, the trial and error cost can be reduced, and the globally optimal design scheme can be obtained.

Description

Technical Field

[0001] This invention relates to the technical field of NPU chip design, and in particular to an automated design method for NPU chips. Background Technology

[0002] With the surge in demand for edge AI deployments, the design complexity of dedicated NPU chips is constantly increasing, making multi-objective collaborative optimization of chip power consumption, performance, and area (PPA) a core challenge. Traditional NPU design flows heavily rely on engineer experience, manually adjusting RTL parameters and logic synthesis tool parameters. This not only results in long iteration cycles and high trial-and-error costs but also makes it difficult to achieve global optimization among the three conflicting objectives of power consumption, performance, and area. Conventional automated optimization methods, such as single-objective optimization or static hyperparameter tuning, cannot achieve synergistic improvement in multi-objective PPA.

[0003] Some existing solutions attempt to introduce Bayesian optimization for chip design, but their alternative models are usually trained from scratch, requiring a large number of expensive simulation samples and taking a very long time. Summary of the Invention

[0004] The purpose of this invention is to provide an automated design method for NPU chips, so as to reduce the cost of simulation samples and shorten the iteration time.

[0005] To address the aforementioned technical problems, this invention provides an automated design method for NPU chips.

[0006] The NPU chip automated design method of the present invention includes: Determine the basic architecture and design constraints of the NPU chip; A multi-objective Bayesian optimization assisted by transfer learning is used to automatically iteratively optimize the parameterized RTL generation process, output the optimal parameterized RTL code, and save the RTL stage surrogate model generated during the optimization process. The parameters of the logic synthesis tool are automatically iteratively optimized again using transfer learning-assisted multi-objective Bayesian optimization, outputting the optimal synthesis configuration and gate-level netlist, and saving the surrogate model of the logic synthesis stage generated during the optimization process; The standard physical design process is executed to place, route, and physically verify the gate-level netlist to obtain the chip layout.

[0007] Furthermore, the multi-objective Bayesian optimization assisted by transfer learning, which performs automated iterative optimization of the parameterized RTL generation process, includes: Retrieve pre-trained neural network surrogate models from historical NPUs of the same specifications in the RTL phase from the model library and use them as the initial surrogate models for the RTL phase. During the iterative optimization process, the initial proxy model of the RTL stage is fine-tuned online using newly generated RTL simulation samples.

[0008] Furthermore, the automated iterative optimization of the logic synthesis tool parameters using transfer learning-assisted multi-objective Bayesian optimization includes: Retrieve pre-trained neural network proxy models from the logic synthesis stage of historical NPUs of the same specifications from the model library and use them as the initial proxy models for the logic synthesis stage; During the iterative optimization process, the initial proxy model of the logic synthesis stage is fine-tuned online using the newly generated logic synthesis result samples.

[0009] Furthermore, the parameterized RTL generation is implemented based on a parameterized hardware description language, which encapsulates the adjustable hyperparameters within the NPU architecture into a set of hyperparameters, including at least one or more of the following: cache size, pipeline stages, parallelism, and bit width configuration.

[0010] Furthermore, the multi-objective Bayesian optimization employs weighted expectation boosting as the acquisition function.

[0011] Furthermore, the automated iterative optimization of the parameterized RTL generation process includes: The selection of parameter combinations is guided by the weighted expectation improvement as the acquisition function, and the corresponding RTL code for hyperparameters is generated and simulated to obtain power consumption, performance and area indicators. After every few iterations, the proxy model is fine-tuned online once. Once the convergence condition or iteration limit is reached, output the parameterized RTL code with optimal power consumption, performance, and area.

[0012] Furthermore, the logic synthesis tool parameters include at least one or more of the following: timing optimization level, power optimization strategy, area optimization intensity, compilation thread configuration, mapping strategy, and clock uncertainty.

[0013] Furthermore, the step of employing transfer learning-assisted multi-objective Bayesian optimization again to automatically iteratively optimize the parameters of the logic synthesis tool, outputting the optimal synthesis configuration and gate-level netlist, includes: Bayesian optimization automatically selects parameter combinations, calls logic synthesis tools to complete synthesis, and automatically captures timing, power consumption, and area reports to evaluate the objective function. Output the optimal tool parameters and the comprehensive result netlist.

[0014] Furthermore, the standard physical design process adopts a preset industry standard process, sequentially executing layout planning, clock tree synthesis, routing, and physical verification, and using the optimized netlist and constraints.

[0015] Furthermore, it also includes: The proxy model, optimal parameter combination, and full-process power consumption, performance, and area data generated during the optimization process are archived into the model library for subsequent design tasks to transfer and learn from.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: The NPU chip automated design method of this invention achieves fully automated iterative optimization from parameterized RTL generation to logic synthesis by introducing transfer learning-assisted multi-objective Bayesian optimization. This method efficiently utilizes historical design experience, reduces the need for expensive simulation and synthesis samples, and effectively overcomes the shortcomings of traditional design methods, such as reliance on manual intervention, slow iteration, high sample costs, and difficulty in simultaneously achieving multiple objectives. Ultimately, in NPU chip design, it can stably improve the synergistic optimization effect of power consumption, performance, and area (PPA), significantly shorten the design cycle, reduce trial-and-error costs, and obtain the globally optimal design solution. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an embodiment of the NPU chip automated design method of the present invention. Detailed Implementation

[0018] The NPU chip automated design method of the present invention will be described below with reference to the schematic diagrams, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0019] The serial numbers assigned to components in this document, such as "first," "second," etc., are merely used to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention.

[0020] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0021] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. In addition, the term "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0022] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0023] The following is in conjunction with the instruction manual appendix. Figure 1 The present invention introduces the automated design method for NPU chips.

[0024] In some of these embodiments, such as Figure 1 As shown, the NPU chip automated design method includes the following steps: Step S100: Determine the basic architecture and design constraints of the NPU chip; Step S200: Employ transfer learning-assisted multi-objective Bayesian optimization to automatically iteratively optimize the parameterized RTL generation process, output the optimal parameterized RTL code, and save the RTL stage surrogate model generated during the optimization process. Step S300: Again, use transfer learning-assisted multi-objective Bayesian optimization to automatically iteratively optimize the parameters of the logic synthesis tool, output the optimal synthesis configuration and gate-level netlist, and save the surrogate model of the logic synthesis stage generated during the optimization process; Step S400: Execute the standard physical design flow, perform placement, routing, and physical verification on the gate-level netlist to obtain the chip layout.

[0025] For ease of understanding, the following explains some key terms in this embodiment: NPU (Neural Processing Unit) chips are neural network processor chips specifically designed to accelerate artificial intelligence computing tasks.

[0026] Transfer learning is a machine learning method that improves learning efficiency and performance by transferring knowledge learned from one task to another related task.

[0027] Multi-objective Bayesian optimization is an optimization algorithm based on Bayesian theory, used to find the optimal solution among multiple conflicting objective functions. It efficiently explores the parameter space by constructing a surrogate model.

[0028] Parameterized RTL (Register Transfer Level) generation refers to the process of automatically generating RTL code with different configurations based on a parameterized hardware description language template by adjusting preset parameters.

[0029] RTL code, or Register Transfer Level code, is an abstract description in hardware design used to describe the functionality and timing behavior of digital circuits.

[0030] In Bayesian optimization, a surrogate model is a mathematical model used to approximate the behavior of the true objective function. It is usually a neural network model, and the structure and weights of the neural network model, including parameters such as layers and activation functions, can be set according to requirements.

[0031] Logic synthesis refers to the process of converting RTL code into a gate-level netlist, where the functionality described by the RTL is mapped to specific logic gates and flip-flops.

[0032] A gate-level netlist is a circuit description composed of basic units such as logic gates and flip-flops and their connections. It is the foundation of physical design.

[0033] The standard physical design flow refers to the back-end flow of chip design, which includes steps such as placement planning, clock tree synthesis, routing, and physical verification, converting the gate-level netlist into a manufacturable chip layout.

[0034] The NPU chip automated design method in this embodiment achieves fully automated iterative optimization from parameterized RTL generation to logic synthesis by introducing transfer learning-assisted multi-objective Bayesian optimization. This method efficiently utilizes historical design experience, reduces the need for expensive simulation and synthesis samples, and effectively overcomes the shortcomings of traditional design methods, such as manual dependence, slow iteration, high sample costs, and difficulty in simultaneously achieving multiple objectives. Ultimately, in NPU chip design, it can stably improve the synergistic optimization effect of power consumption, performance, and area (PPA), significantly shorten the design cycle, reduce trial-and-error costs, and obtain the globally optimal design solution.

[0035] In some embodiments, step S100 is a pre-design stage, completing the top-level architecture definition of the NPU chip.

[0036] Specifically, firstly, based on the target application scenario (e.g., offline voice recognition for smart home appliances, edge image analysis for smart cameras, real-time inference for wearable devices), the core specifications of the chip should be clearly defined, including but not limited to: computing power requirements (e.g., 0.5 TOPS, 1 TOPS, 2 TOPS), power consumption constraints (e.g., ≤10mW, ≤30mW, ≤100mW), and area limits (e.g., 0.5mm²). 2 0.8mm 2 1.2mm 2 ).

[0037] Secondly, determine the basic architecture of the NPU computing unit. Optional architecture types include: single-core SIMD architecture, multi-core homogeneous architecture, and systolic array architecture. Simultaneously, configure basic design schemes such as cache hierarchy structure (e.g., L1 cache, L2 cache), data path width (e.g., 8-bit, 16-bit, 32-bit), and external interface protocols (e.g., AHB, AXI, APB).

[0038] Then, the architecture design document and constraint file are output to provide a fixed architectural foundation for subsequent parameterized RTL generation. The architecture design document includes at least the upper and lower limits of adjustable parameters such as instruction set specifications, pipeline stage range, parallelism range, and cache size range. The constraint file includes timing constraints (clock cycles, setup / hold time), power constraints (maximum dynamic power consumption, leakage power consumption), and area constraints (upper limit of logic gates, upper limit of macrocells), etc.

[0039] It's important to note that this step does not involve large-scale modifications to the NPU core architecture; only adjustable parameters within the architecture are optimized automatically. Specifically, the top-level design, such as compute unit type, number of cache levels, and bus protocol, remains fixed, while parameters like cache capacity, pipeline depth, parallelism, and bit width configuration are treated as hyperparameters to be optimized, which are then automatically searched and tuned in the subsequent S200 step. This ensures the stability of design convergence and provides a clear search space for generating parameterized RTL.

[0040] After this step is completed, the standardized architecture specification, timing constraint file (SDC format), functional simulation script, and interface definition of parameterized RTL template are output as input for step S200.

[0041] In some embodiments, step S200 specifically includes the following sub-steps: Sub-step S210: Implemented using a parameterized hardware description language, the adjustable hyperparameters within the NPU architecture are encapsulated into a hyperparameter set for parameterized modeling.

[0042] Specifically, preferably, parameterized RTL can be automatically generated based on the Chisel language. The compilation parameters involved in the Chisel compilation process (such as compilation optimization options and generator configurations) and the adjustable microarchitectural parameters within the NPU architecture are encapsulated into a set of hyperparameters. These hyperparameters include, but are not limited to: pipeline stages (e.g., 6–10 stages, with a step size of 1), cache size (e.g., 16KB, 32KB, 64KB), computational parallelism (e.g., 2-way, 4-way, 8-way), and register bit width configuration (e.g., 12-bit, 14-bit, 16-bit, 18-bit, 20-bit). All hyperparameters are discretized into integer inputs (e.g., pipeline stages, parallelism) or floating-point inputs (e.g., the ratio of cache size to clock frequency) based on their numerical characteristics. After modeling, a parameterized RTL template is generated, where each hyperparameter is embedded in the Chisel code as a configurable variable.

[0043] Sub-step S220: Iterate the target Bayesian optimization, retrieve the pre-trained neural network surrogate model of the RTL stage of the historical NPU with the same specifications from the model library, and use it as the initial surrogate model for the RTL stage.

[0044] Specifically, during the automated iterative optimization of the parameterized RTL generation stage, pre-trained neural network surrogate models from the RTL stage of historical NPUs of the same specifications are first retrieved from the model library and used as existing surrogate models for initialization. The model library is a database storing a large amount of experiential knowledge learned from past NPU chip design tasks, including pre-trained neural network surrogate models for different NPU architectures, technology nodes, or design goals. These pre-trained models have learned and encoded the complex mapping relationships between design parameters (such as cache size, pipeline stages, parallelism, bit width configuration, etc.) and NPU chip power consumption, performance, and area (PPA) metrics. By using these pre-trained models as the initial surrogate models for the current optimization task, learning from random states or general models can be avoided, thus providing a high-quality starting point for Bayesian optimization and enabling it to identify potential regions in the design space more quickly.

[0045] In the process of multi-objective Bayesian optimization, the weighted expectation boosting is used as the acquisition function to guide the selection of parameter combinations, generate corresponding hyperparameter RTL code and perform simulation evaluation to obtain power consumption, performance and area indicators; the weighted expectation boosting is used as the acquisition function, which is used to balance exploration and development, and supports users to make custom adjustments according to the multi-objective weights of power consumption, performance and area to meet the diverse needs of NPU chip design.

[0046] The specific formula for weighted expected value enhancement is as follows: ; in, Represents the mathematical expectation. This represents the optimal value for the current i-th objective.

[0047] Sub-step S230: During the iterative optimization process, the surrogate model is fine-tuned online using the newly generated RTL simulation samples.

[0048] Specifically, as the Bayesian optimization algorithm selects new parameter combinations based on the surrogate model's predictions and generates RTL code for simulation, new RTL simulation samples are produced—new design parameter configurations and their corresponding power consumption, performance, and area metrics. These new samples are used in real-time to update and refine the current surrogate model. Online fine-tuning means that the surrogate model can continuously learn from the latest simulation data, thereby constantly improving its prediction accuracy for the current design task. For example, after each iteration, the model parameters of the neural network surrogate model are lightly fine-tuned online using the newly generated simulation samples. This dynamic adjustment mechanism ensures that the surrogate model can adapt to the specific details of the current design task and changes in the design space, maintaining its effectiveness even if the current task differs from historical tasks. Online fine-tuning can gradually improve the surrogate model's prediction accuracy for PPA metrics, reduce ineffective parameter combination attempts, and accelerate convergence.

[0049] Sub-step S240: When the convergence condition or iteration limit is reached, output the parameterized RTL code with optimal power consumption, performance, and area, and save the RTL stage proxy model generated during the optimization process.

[0050] Specifically, the convergence condition can be set to a return of 2%, and the iteration limit can be set to 1000 iterations. When either condition is met, the parameter combination that satisfies the design constraints and has the best overall PPA return is selected from the Pareto front, and the corresponding parameterized RTL code is output. Compared to manually configured RTL, this step can stably achieve performance improvement of ≥2%, power consumption reduction of ≥2%, and area reduction of ≥2% without changing the core architecture (at least one indicator reaches 2%, and the other indicators do not degrade). The output optimal RTL code and its corresponding RTL stage proxy model (including model structure and weights) will be saved for model reuse in subsequent NPU chip designs of the same specifications.

[0051] In some embodiments, step S300 is performed using mainstream EDA synthesis tools (such as Synopsys DesignCompiler, electronic design automation software from Synopsys, Inc.), continuing to employ a transfer learning-assisted multi-objective Bayesian optimization framework. The aim is to achieve an additional 2% PPA overall gain on top of the optimized RTL obtained in step S200. Specifically, this includes the following sub-steps: Sub-step S310: Extract key parameters from the logic synthesis tool that affect the PPA results.

[0052] Specifically, the key parameters in the logic synthesis tool include at least the timing optimization level (e.g., level 1 to 5, with higher values ​​indicating more aggressive optimization), power optimization strategy (e.g., high throughput mode or low power mode), area optimization intensity (e.g., level 0 to 3, where 0 indicates no optimization and 3 indicates aggressive area compression), compilation thread configuration (e.g., 2 threads, 4 threads, 8 threads), mapping strategy (e.g., area-first, timing-first, balanced strategy), and clock uncertainty (e.g., one or more of 5% to 15% of the clock cycle). All parameters are converted to a uniform numerical format according to their type. For example, discrete enumerated parameters are represented by integer codes (e.g., 1, 2, 3), and continuous parameters are normalized to the [0,1] interval to facilitate Bayesian optimization.

[0053] By clearly defining the above key parameters, the blindness of the optimization process is avoided, ensuring that the optimization algorithm can efficiently explore the design space constituted by these parameters.

[0054] Sub-step S320: Retrieve a pre-trained neural network proxy model for the logic synthesis stage of a historical NPU of the same specification from the model library and use it as the initial proxy model for the logic synthesis stage. During the iterative optimization process, use the newly generated logic synthesis result samples to perform lightweight online fine-tuning of the proxy model.

[0055] Specifically, pre-trained neural network surrogate models from the logic synthesis stage of historical NPUs of the same specifications can be reused from the model library. This eliminates the need to build or train a new surrogate model from scratch; instead, pre-trained neural network surrogate models from historical NPUs of the same specifications are directly loaded as the initial model for the logic synthesis stage. This significantly shortens model training time and reduces computational costs. During reuse, the model structure can be appropriately adjusted based on the input-output characteristics of the logic synthesis stage, or it can be used as a feature extractor.

[0056] In each Bayesian optimization iteration, after selecting a set of logic synthesis tool parameters based on the predictions of the surrogate model in the logic synthesis stage and performing the actual logic synthesis, a new set of real sample data is obtained. After obtaining a small number of new samples (e.g., 5 to 15 sets of synthesis results), a lightweight online fine-tuning is performed on the surrogate model in the logic synthesis stage. During fine-tuning, a small learning rate and fewer iterations are used, or only the parameters in the model that are more relevant to the logic synthesis task are updated. For example, if the surrogate model in the logic synthesis stage is a neural network, only its output layer or the last few layers can be fine-tuned to quickly adapt to the specific mapping relationship of the logic synthesis stage, while avoiding overfitting.

[0057] Sub-step S330: Automatically select parameter combinations through Bayesian optimization, call the logic synthesis tool to complete synthesis, and automatically capture timing, power consumption, and area reports to evaluate the objective function.

[0058] Specifically, using the Weighted Expectation Improvement (WEI) as the acquisition function, Bayesian optimization automatically selects the next set of parameter combinations to be evaluated. A logic synthesis tool is invoked to perform a complete logic synthesis process on the current parameter combination. After synthesis, timing reports (checking setup and hold time violations), power consumption reports (dynamic and static power consumption), and area reports (standard cell area and macrocell area) are automatically captured to evaluate the objective function. Key metrics are extracted to form the objective function value, which is calculated based on user-preset weights for power consumption, performance, and area (e.g., for low-power edge chips, power consumption weight is 0.4, performance weight is 0.35, and area weight is 0.25). The parameter combination and its corresponding objective function value are added as new samples to the training set to update the surrogate model. This process is repeated until the convergence condition is met (e.g., the improvement in the objective function value is less than a threshold for multiple consecutive iterations) or the preset maximum number of iterations (e.g., 30 iterations) is reached.

[0059] Sub-step S340: Output the optimal tool parameters and the synthesis result netlist, and save the logical synthesis stage proxy model generated during the optimization process.

[0060] Specifically, after optimization convergence, the parameter combination that satisfies the timing constraints and achieves the optimal overall PPA benefit is selected from the Pareto front. The corresponding synthesis tool configuration script and the synthesized gate-level netlist are output. Experiments show that, based on the ≥2% PPA benefit already achieved in step S200, this step can further achieve a performance improvement of ≥2%, a power consumption reduction of ≥2%, or an area reduction of ≥2% (at least one indicator reaches 2%, and the other indicators do not degrade). The output netlist and constraint file will be passed to the subsequent step S400 (physical design stage). At the same time, the optimal parameter combination and the final logic synthesis stage proxy model are archived to the model library for future project transfer learning initialization.

[0061] In some embodiments, for step S400, a standard physical design flow is executed to place, route, and physically verify the gate-level netlist to obtain the chip layout. The standard physical design flow adopts a preset industry-standard flow, sequentially executing placement planning, clock tree synthesis, routing, and physical verification, using the optimized netlist and constraints.

[0062] Step S400 adopts the industry-standard physical design flow, preferably the Innovus (an advanced physical implementation tool mainly used for digital back-end physical design of integrated circuits) flow, without performing additional hyperparameter optimizations on placement and routing, clock tree synthesis, etc. Considering the extremely time-consuming physical design flow (typically requiring hours to days) and huge computational resource consumption (requiring multi-core servers and large amounts of memory), this step proactively forgoes time-consuming hyperparameter optimization to balance overall design efficiency and PPA benefits. Specifically, it includes the following sub-steps: Sub-step S410: Design import and data preparation.

[0063] Specifically, the gate-level netlist, timing constraint file, power constraint file, and technology library file obtained from step S300 optimization are imported into the Innovus tool. The design exchange format file and physical technology file are also imported. The netlist integrity and constraint consistency are checked to ensure there are no floating ports or unconnected pins.

[0064] Sub-step S420: Layout planning.

[0065] Specifically, based on area constraints and the number of macrocells, a placement plan is executed. This includes: defining the chip core region and I / O ring region; determining the placement of macrocells, following design rules (such as avoiding obstruction of standard cell placement channels); and generating a preliminary plan for the power grid, including power ring width, stripe spacing, and via density. This sub-step uses Innovus' standard placement planning process and does not perform hyperparameter optimization.

[0066] Sub-step S430: Standard cell layout.

[0067] Specifically, this involves the logical and physical placement of standard cells. A coarse placement is performed first to assess wiring congestion, followed by a detailed placement to optimize timing. This step uses Innovus' default placement algorithm, with basic optimization options enabled, and the underlying algorithm parameters are not adjusted.

[0068] Sub-step S440: Clock tree synthesis.

[0069] Specifically, clock tree synthesis is performed based on the clock definition in the timing constraints (e.g., 400MHz). The standard Innovus workflow is used, including: clock tree buffer insertion, clock routing layer selection, offset adjustment, and jitter optimization.

[0070] Sub-step S450: Wiring.

[0071] Specifically, global routing and detailed routing are performed. Global routing allocates trace resources based on congestion estimation, while detailed routing completes the actual metal interconnections. Innovus' default routing algorithm is used, and timing-driven and signal integrity-driven options are enabled.

[0072] Sub-step S460: Physical verification and approval.

[0073] Specifically, parasitic parameters are extracted for static timing analysis and power consumption analysis. A design rule check (DRC) is performed to verify that metal spacing, width, and via rules meet process requirements; layout and schematic analysis are also performed. Figure 1 Consistency checks (LVS, Layout vs. Schematic) ensure that the layout-based netlist is logically consistent with the original gate-level netlist.

[0074] Sub-step S470: Output the final layout.

[0075] Specifically, after physical verification by DRC / LVS, the final chip layout file is output, along with supporting data for tape-out (such as the coordinate file required for the chip packaging substrate).

[0076] No hyperparameter optimization is performed in this step, ensuring the predictability and timeliness of the physical design process.

[0077] In some embodiments, the NPU chip automated design method further includes: The proxy model, optimal parameter combination, and full-process power consumption, performance, and area data generated during the optimization process are archived into the model library for subsequent design tasks to transfer and learn from.

[0078] Specifically, in automated iterative optimization, Bayesian optimization typically constructs a surrogate model to approximate the complex relationship between the objective function (such as power consumption, performance, and area) and design parameters. This surrogate model continuously learns and updates during optimization iterations, capturing nonlinear characteristics in the design space. Archived in a model library, it means preserving the knowledge accumulated during the optimization process, including the model's structure, training parameters, and the design space characteristics it has learned, providing valuable prior knowledge for subsequent tasks. The optimal parameter combination refers to the best design parameter configuration determined after automated iterative optimization, based on preset design objectives (e.g., a weighted combination of power consumption, performance, and area). These parameters may cover hyperparameters in the parameterized RTL generation stage, such as cache size, pipeline stages, parallelism, and bit width configuration, as well as logic synthesis tool parameters, such as timing optimization level, power optimization strategy, and area optimization intensity. Archived these optimal parameter combinations aim to record successful design experiences, providing a direct and efficient reference starting point for subsequent similar design tasks. End-to-end power consumption, performance, and area data refer to the final power consumption, performance, and area metrics obtained through RTL simulation, logic synthesis, placement and routing, and other processes for specific combinations of design parameters throughout the entire NPU chip automated design flow. These data are crucial for objectively measuring design quality and optimization effectiveness. Archiving this data allows for the construction of a comprehensive design database for in-depth analysis of the quantitative impact of different parameter combinations on the final chip's metrics. The model library is a central storage system specifically designed for storing, managing, and retrieving this archived data. This model library can be implemented based on a database, file system, or dedicated data management platform. Its design should support efficient data retrieval, version control, and access control to ensure that subsequent design tasks can easily and accurately access the required data.

[0079] Through the above technical solution, this method can effectively accumulate and manage historical design experience. When faced with a new NPU chip design task, these historical data and models can be retrieved from the model library, and transfer learning techniques can be used to provide high-quality initial points or pre-trained models for the new task. This significantly reduces the time and computational resources required to explore the design space from scratch, accelerates the convergence of the optimization process, thereby greatly improving the efficiency and quality of NPU chip design, avoiding repetitive work, and realizing the effective reuse and inheritance of knowledge.

[0080] The following example will provide a more detailed explanation of the above technical solution: First, determine the basic architecture and design constraints of the NPU chip: Specifically, it adopts a single-core SIMD (Single Instruction, Multiple Data) computing architecture, a 2-level cache configuration, an 8-stage pipeline, a 16-bit data width, and uses an AHB bus interface; with explicit constraints: clock speed ≥ 400MHz, area ≤ 0.8mm². 2 Power consumption ≤30mW. Output architecture specification, timing constraint file, and functional simulation script; no changes are made to the core architecture, only automated tuning of internal parameters.

[0081] Secondly, a transfer learning-assisted multi-objective Bayesian optimization is used to automatically iteratively optimize the parameterized RTL generation process, outputting the optimal parameterized RTL code and saving the surrogate model generated during the optimization process. Specifically, select adjustable hyperparameters: number of pipeline stages (6-10 stages), L1 cache size (16KB-64KB), computational parallelism (2-8 channels), and register bit width (12-20 bits), all of which are discretized into integer parameters.

[0082] We retrieved a pre-trained neural network model from a historical NPU of the same specifications and initialized the surrogate model through transfer learning, requiring only 15 initial samples (compared to more than 40 samples in traditional methods).

[0083] Initiate multi-objective Bayesian optimization, select weighted expectation boosting as the acquisition function, automatically generate Chisel code in each round and run functional simulation and power consumption simulation, and output PPA index.

[0084] Online fine-tuning is completed every 3 iterations, and convergence is achieved in a total of 42 iterations, reducing the time to 40% of that of traditional methods.

[0085] The optimal parameters were finally selected as follows: 8-stage pipeline, 32KB L1 cache, 4-way parallelism, and 16-bit width.

[0086] Optimization results: Compared with manual configuration, performance is improved by 2.4%, power consumption is reduced by 2.2%, area is reduced by 1.9%, and the overall PPA benefit meets the requirement of ≥2%.

[0087] Next, based on the aforementioned optimized surrogate model, transfer learning-assisted multi-objective Bayesian optimization is used again to automatically iteratively optimize the parameters of the logic synthesis tool, outputting the optimal synthesis configuration and gate-level netlist: Specifically, extract the following parameters from the logic synthesis tool: timing optimization level (1-5), power optimization strategy (high throughput / low power), area optimization intensity (0-3), and clock uncertainty, and convert them to floating-point input.

[0088] Based on the aforementioned optimized proxy model, only 12 sets of synthesis samples are used for lightweight fine-tuning to quickly adapt to synthesis scenarios. Bayesian optimization automatically calls the Design Compiler to automatically complete synthesis, timing analysis, and power consumption report capture without manual intervention.

[0089] After 28 iterations, the system converges and outputs the optimal parameters.

[0090] Optimization results: Based on the S2 optimization, additional performance is improved by 2.3%, power consumption is reduced by 2.1%, area is reduced by 2.0%, single-stage benefit is ≥2%, gate-level netlist timing convergence is achieved, and there are no violations.

[0091] Next, proceed to step S400: The optimized gate-level netlist and timing constraints are imported into Innovus to perform standard 28nm process physical design: placement planning, power grid design, standard cell placement, clock tree synthesis, global routing and detailed routing, and DRC / LVS physical verification.

[0092] This step does not involve any hyperparameter optimization; the entire process follows the standard procedure.

[0093] Finally, the optimized NN agent model, optimal parameter combination, full-process PPA data, and architecture labels are archived to the model library. Subsequent similar edge-side NPU designs can directly call this model for initialization, further reducing the initial sample size by 30% and shortening the iteration cycle.

[0094] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An automated design method for an NPU chip, characterized in that, include: Determine the basic architecture and design constraints of the NPU chip; A transfer learning-assisted multi-objective Bayesian optimization is used to automate the iterative optimization of the parameterized RTL generation process. This includes: retrieving pre-trained neural network surrogate models for the RTL stage from the model library using historical NPUs of the same specifications, and using them as the initial surrogate models for the RTL stage; fine-tuning the initial surrogate models for the RTL stage online using newly generated RTL simulation samples during the iterative optimization process; outputting the optimal parameterized RTL code and saving the RTL stage surrogate models generated during the optimization process. The parameters of the logic synthesis tool are automatically iteratively optimized again using transfer learning-assisted multi-objective Bayesian optimization. This includes: retrieving a pre-trained neural network surrogate model for the logic synthesis stage from the model library using historical NPUs of the same specifications, and initializing it as the initial surrogate model for the logic synthesis stage; during the iterative optimization process, using newly generated logic synthesis result samples to perform lightweight online fine-tuning of the initial surrogate model for the logic synthesis stage; outputting the optimal synthesis configuration and gate-level netlist, and saving the surrogate model for the logic synthesis stage generated during the optimization process. The standard physical design process is executed to place, route, and physically verify the gate-level netlist to obtain the chip layout.

2. The NPU chip automated design method according to claim 1, characterized in that, The parameterized RTL generation is implemented based on a parameterized hardware description language, which encapsulates the adjustable hyperparameters within the NPU architecture into a set of hyperparameters. The hyperparameters include at least one or more of the following: cache size, pipeline stages, parallelism, and bit width configuration.

3. The NPU chip automated design method according to claim 1, characterized in that, The multi-objective Bayesian optimization uses weighted expectation boosting as the acquisition function.

4. The NPU chip automated design method according to claim 3, characterized in that, The automated iterative optimization of the parameterized RTL generation process includes: The selection of parameter combinations is guided by the weighted expectation improvement as the acquisition function, and the corresponding RTL code for hyperparameters is generated and simulated to obtain power consumption, performance and area indicators. After every few iterations, the proxy model is fine-tuned online once. Once the convergence condition or iteration limit is reached, output the parameterized RTL code with optimal power consumption, performance, and area.

5. The NPU chip automated design method according to claim 1, characterized in that, The logic synthesis tool parameters include at least one or more of the following: timing optimization level, power optimization strategy, area optimization intensity, compilation thread configuration, mapping strategy, and clock uncertainty.

6. The NPU chip automated design method according to claim 1, characterized in that, The process involves again employing transfer learning-assisted multi-objective Bayesian optimization to automatically iteratively optimize the parameters of the logic synthesis tool, outputting the optimal synthesis configuration and gate-level netlist, including: Bayesian optimization automatically selects parameter combinations, calls logic synthesis tools to complete synthesis, and automatically captures timing, power consumption, and area reports to evaluate the objective function. Output the optimal tool parameters and the comprehensive result netlist.

7. The NPU chip automated design method according to claim 1, characterized in that, The standard physical design process adopts a preset industry standard process, which sequentially executes layout planning, clock tree synthesis, routing and physical verification, and uses the optimized netlist and constraints.

8. The NPU chip automated design method according to claim 1, characterized in that, Also includes: The proxy model, optimal parameter combination, and full-process power consumption, performance, and area data generated during the optimization process are archived into the model library for subsequent design tasks to transfer and learn from.

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