Hierarchical physical design method and system with soft boundary control

Abstract

The application provides a soft boundary control hierarchical physical design method and system, and relates to the technical field of integrated circuit physical design. The method comprises the following steps: converting a module hard core boundary into a region control soft boundary, and constructing a physical overlapping region by reshaping a module topological shape to allow signal wiring to pass through a module region to shorten a critical path; meanwhile, a logic hierarchical port is reserved, and a key path directional constraint is combined to achieve accurate response to a module level local engineering change in an almost flattened physical implementation. The application can fundamentally eliminate wire congestion, realize perfect convergence of cross-module timing, solve timing problems in advance, have convergence efficiency of flattened design and ECO flexibility of hierarchical design, effectively shorten a project cycle and save manpower cost, and can be applied to super large scale design through a hybrid strategy.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a hierarchical physical design method and system with soft boundary control. Background Technology

[0002] In large-scale VLSI chip design, the chip, apart from the top-level (top-only) layer, is typically composed of multiple main sub-modules (blocks / IPs). For example, some specific digital chip designs include eight parallel high-frequency modules similar to Serdes Lane (TX & RX), and a single central microcontroller unit (MCU) module. Due to the extremely compressed design cycles in modern microelectronics, tight front-end design timelines and often insufficient system-level verification, the back-end physical design phase frequently faces unscheduled Engineering of Logic (ECO) changes or significant register-transfer level (RTL) design modifications.

[0003] To address these challenges, existing integrated circuit physical design techniques typically employ standard hierarchical design methods. In the place-and-route (PR) phase, the SerDes module and the MCU module are physically isolated as independent entities. The SerDes module is invoked eight times at the top level, and timing closure is achieved in the later stages of the physical design through full-chip timing flattening. Under this traditional hierarchical architecture, if any logic changes or ECOs occur between the two modules, designers only need to perform a back-end local ECO at the block level. The top-level place-and-route and clock tree synthesis results are usually unaffected, thus achieving isolation control of the design.

[0004] However, when faced with constrained, irregular physical layouts, this traditional approach reveals serious physical deadlock and timing collapse defects: 1. Irregular physical layout leads to extreme congestion in routing channels: Due to the irregular shape of the overall chip layout (similar to an L-shape), it is extremely unfriendly to back-end physical catalysis. The aspect ratio of its effective area (the height part of the L-shape) is as high as 1:5. Within this narrow physical space, two rows of a total of 8 SerDes hard core modules must be placed symmetrically, which makes the channel left for top-level signal routing in the middle extremely narrow. Since the boundary of the hard core is an "insurmountable physical wall" for top-level routing, all top-level signals are forced to squeeze into the narrow channel, resulting in extremely high local routing density and causing severe congestion problems.

[0005] 2. Cross-module multi-party interaction causes timing disasters: There are high-frequency interaction requirements between the top-level logic, the first lane (S1) of the eight SerDes, and the internal logic of the MCU module. Under traditional physical hard-core isolation, the interaction signals cannot cross the module boundary with the shortest straight-line distance and are forced to detour to the pin positions preset by the hard core. The severe elongation of physical traces not only significantly increases the interconnect delay but also forces EDA tools to insert a large number of buffers on the long lines to maintain the signal transition time. This directly makes it extremely difficult for the cross-module timing path to converge.

[0006] 3. Routing deadlock and low iteration efficiency: Timing requirements and narrow routing channels create severe resource constraints. The aforementioned three-party interaction areas exhibit significant local routing congestion risks during the placement and clock tree synthesis (CTS) phases, ultimately leading to numerous short circuits and open circuits that cannot be closed. Furthermore, in traditional methods, timing violations across long routes are often not fully exposed until the final top-level flattening stage. Once a problem is discovered, it is necessary to backtrack to the front end to modify the RTL (such as inserting pipeline timing), which will result in at least two weeks of verification and synthesis delays, severely hindering the project's sign-off schedule. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a hierarchical physical design method and system for soft boundary control.

[0008] According to the present invention, a hierarchical physical design method and system for soft boundary control is provided, the scheme of which is as follows: Firstly, a hierarchical physical design method for soft boundary control is provided, the method comprising: The hard core isolation area of ​​a submodule in the layout is converted into a soft boundary control area. The soft boundary control area is controlled by physical area, so that the logic and traces in the adjacent wiring channels of the submodule can borrow and enter the soft boundary control area. The hard core rectangular area of ​​an interactive module is reshaped into an irregular area, causing the local boundary of the irregular area to be extended. The irregular region overlaps in physical space with the soft boundary control area of ​​at least one of the sub-modules and the wiring channel to form a shared interaction area, which is a shared interaction area where multiple physical resources overlap. The sub-modules and the interaction module are configured to retain hierarchical port attributes to blur physical boundaries, while maintaining the independence of logical pins of each module. The logic related to special key timing paths within the interaction module is placed into a preset corresponding physical grid area by means of directional placement constraints, thereby completing the layout and routing.

[0009] Preferably, the layout is changed from a rectangle to an L-shaped structure.

[0010] Preferably, the submodule includes multiple symmetrically placed high-frequency serial deserializer (Serdes) modules, and the wiring channel is a narrow channel formed by the compression of two symmetrically placed Serdes modules.

[0011] Preferably, converting the hard core isolation region of a submodule in the layout into a soft boundary control region includes maintaining the same physical area size for all the submodules in the entire chip.

[0012] Preferably, the interaction module is a microcontroller unit (MCU) module, and the step of reshaping the hard core rectangular region of an interaction module into an irregular region includes the reshaping of the irregular region into an L-shaped soft boundary physical region.

[0013] Preferably, the shared interaction area where multiple physical resources overlap is specifically a physical area formed by the upward extension of the L-shaped physical area of ​​the MCU module, the interior of the soft boundary control area of ​​the first Serdes module, and the narrow channel.

[0014] Preferably, the irregular region overlaps in physical space with the soft boundary control area of ​​at least one of the sub-modules and the wiring channel to form a shared interaction area. This includes setting the reserved hierarchical port attribute to lock the boundary pins of each module in the near-flat physical layout wiring process. When an engineering change (ECO) occurs in the front-end logic design, the back-end design directly responds to the module-level local engineering change (ECO) through the original port.

[0015] Preferably, the method further includes a step of providing a physical replacement guarantee for the repeatedly reused sub-modules through engineering change (ECO), including: When an Engineering Change ECO occurs, only the first submodule within the shared interaction area is selected for a local physical engineering change ECO implementation. After its physical layout and timing are fully converged, the logic netlist and physical layout results of that submodule are extracted and seamlessly replaced with other submodules of the same type in the chip layout.

[0016] Preferably, for designs where the total number of instances is less than a preset threshold, all modules to be processed adopt soft boundary and physical region control methods; For designs where the total number of instances exceeds the preset threshold, modules with high-frequency interactions are flattened and combined with physical area control and the preservation of hierarchical port attributes, while the remaining modules remain hardcore and are instantiated multiple times.

[0017] Secondly, a hierarchical physics design system with soft boundary control is provided, the system comprising: The boundary conversion module is used to convert the hard core isolation area of ​​the sub-module in the layout into a soft boundary control area based on physical area control, so that the logic and traces in the adjacent wiring channels of the sub-module can borrow and enter the soft boundary control area. The region reshaping module is used to reshape the hard core rectangular region of the interaction module into an irregular region, so that the local boundary of the irregular region is extended and overlaps with the soft boundary control area of ​​at least one of the sub-modules and the wiring channel in physical space, forming a shared interaction area with multiple physical resources overlapping. The hierarchical port retention module is used in electronic design automation (EDA) tools to set the hierarchical port retention attribute for the sub-modules and the interaction modules, so as to maintain the independence of the logic pins of each module while blurring the physical boundaries. The directional placement constraint module is used to place the relevant logic with special key timing paths inside the interaction module into a preset corresponding physical grid area through directional placement constraints, thereby completing the layout and routing.

[0018] Compared with the prior art, the advantages of the present invention are as follows: 1. After converting the hard physical boundary of the module into a soft constraint of the region, the top-level logic and routing can use the module region, which indirectly widens the extremely narrow routing channel and eliminates the routing congestion problem caused by irregular layout from the root, ensuring that the routing stage can converge smoothly. 2. This invention reshapes the module topology and establishes a physical overlap area, which constrains the key logic of multi-party interaction within the overlap area, significantly shortening the physical routing distance of high-frequency signals across modules and fundamentally solving the problem of timing paths failing to converge due to hard core boundary isolation. 3. This invention places the relevant logic of special key timing paths within the interaction module into a preset corresponding physical grid area through directional placement constraints. This allows cross-module timing conflicts to be exposed and resolved in the early layout planning stage of the design, avoiding the problem in traditional methods where key timing violations can only be discovered in the later full-chip flattening stage, and significantly improving design iteration efficiency. 4. This invention blurs the physical boundaries by setting the hierarchical port attribute to sub-modules and interaction modules. While achieving top-level collaborative convergence by blurring the physical boundaries, it also allows the backend to accurately locate and quickly respond to local engineering changes for specific modules, just like in traditional hierarchical design, by retaining the independent hierarchical ports of the modules, resulting in high operational flexibility. 5. This invention directly solves cross-module timing issues at the backend physical level in a closed loop, eliminating the need for frontend design modifications, pipeline insertion, and re-verification, thus saving weeks of critical development time. Simultaneously, this method ensures extremely high collaboration between the top-level layer and modules, optimizing tasks that originally required multiple engineers to collaborate on into tasks that a single person can complete independently, effectively saving labor costs. 6. This invention not only offers significant advantages for small- to medium-scale chips (e.g., overall scale below ten million instances), but its core concepts can also be adopted by subsystems of large-scale system-on-a-chip (SoC) to overcome multiple bottlenecks in timing and physical routing. For ultra-large-scale designs, a hybrid strategy of partially flattening modules and partially hardening modules can also be used to achieve an effective balance between timing performance and machine runtime.

[0019] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0020] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the overall process of the present invention; Figure 2 This diagram illustrates the effects and conflicts of a hard-core hierarchical physics design method in the prior art. Figure 3 This is a schematic diagram illustrating the architecture and implementation of the design method described in a specific embodiment of the present invention. Detailed Implementation

[0021] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0022] This invention provides a hierarchical physical design method with soft boundary control, which aims to break the rigid physical boundaries of traditional hard cores, completely solve the problems of winding congestion and cross-boundary timing collapse caused by irregular layouts and narrow channels, while still retaining the ability to provide efficient local response to frequent logic ECOs at the front end.

[0023] Reference Figure 1 and Figure 2 As shown, due to the final packaging requirements of this chip product, its effective die area presents an extremely irregular "L" shape, with the aspect ratio of the long side reaching an extreme 1:5. The diagram includes eight similar high-speed serializers / deserializers (Serdes S1-S8) and one control center (MCU). S1-S8 are eight independent Serdes hard-core modules, and the MCU is also an independent hard-core module. The area between the two columns of S1-S8 represents a severely compressed and congested narrow channel; the solid ellipse marks the area where severe timing and wiring conflicts erupt at the intersection of the top layer, S1, and MCU. If a traditional block hardening strategy is implemented, EDA tools will generate an impenetrable blockage (physical blockage) around each module. As a result, the channel between the two columns of Serdes must not only carry tens of thousands of signal lines in the top layer but also deploy a global clock tree. The severe shortage of physical channels directly leads to... Figure 2 The I / O region reported unrecoverable congestion violations during the layout phase. Even more critically, there was data exchange between the Top layer logic, the internal logic of S1, and the MCU below at a high-frequency synchronous clock domain. Due to the large physical distance between the hard cores, this region reported hundreds of Setup Time violations that could not be repaired by inserting buffers.

[0024] This specific implementation addresses these multiple technical bottlenecks by adopting a novel, near-flattened architecture strategy, referring to... Figure 3 As shown in the figure, the boundary between S1 and S8 is turned into a dashed line, indicating that it has become a soft boundary (Region), and the channel traces can partially penetrate into it; the MCU module has changed from a rectangle to an upwardly extending L-shaped Region; the dashed ellipse shows the shared physical interaction area of ​​the cross-border integration of MCU, Channel, and S1; the solid block in the lower left corner shows the directional constraint placement area set for specific critical paths inside the MCU.

[0025] The core implementation steps are as follows: Step 1: Convert the hard-core isolation region of a submodule in the layout to a soft-boundary control region. The soft-boundary control region uses physical region control, allowing logic and traces in adjacent wiring channels of the submodule to access and enter the soft-boundary control region. This step is a conversion from hard-core isolation (Harden) to soft-boundary control (Region).

[0026] To address the layout and routing congestion issue in narrow channels within irregular floor plans, the physical hard boundaries of specific sub-modules (such as S1-S8) are completely eliminated, transforming them into soft boundaries controlled by region constraints. While ensuring the planned area size of these eight modules remains consistent within the tool, some top-level logic units and routing resources within the narrow channels are allowed to borrow, and even cross, the region edges of these sub-modules. This step physically removes the "isolation walls," effectively widening the channel routing resources.

[0027] Step 2: Reshape the hard core rectangular region of an interactive module into an irregular region, causing the local boundaries of the irregular region to extend. This step reshapes the topological form of the interactive module to construct the physical overlapping area.

[0028] Breaking away from the limitations of conventional rectangular hard cores, the physical boundaries of interactive modules (such as MCUs) are reshaped and adjusted into L-shaped region control areas. The aim is to physically overlap the region of this module with that of the S1 module and the narrow central channel by stretching the local area upwards. This successfully creates an interactive area on the layout where physical resources are shared among "S1, MCU, and Channel" (such as...). Figure 3 (The physically overlapping area is marked by the dashed ellipse in the middle). Within this area, cross-module signals can achieve "zero-distance" interconnection, thereby eliminating timing issues caused by long-distance detours.

[0029] Step 3: The irregular region overlaps with the soft boundary control area of ​​at least one of the sub-modules and the wiring channel in physical space to form a shared interaction area, which is a shared interaction area where multiple physical resources overlap.

[0030] Step 4: Set the Keep HierarchyPort attribute for the sub-modules and the interaction module to blur physical boundaries while maintaining the independence of logical pins for each module. This step explicitly retains the logical hierarchy port (Keep HierarchyPort) to support ECO.

[0031] Since the first two steps establish physical boundaries, locking at the logic netlist level is necessary to handle potential future logic changes. When reading the netlist and configuring constraints, the hierarchical port attributes are explicitly set for SerDes and MCU module instances (e.g., constraining `keep_hierarchy` to `true` in the tool). This ensures that while the physical engine performs a near-flattened layout for hybrid routing, the logic synthesis engine can still accurately identify and maintain the module's pin structure. If the front-end requires a local ECO on the MCU or SerDes, back-end engineers can still quickly isolate and import the netlist using the existing logic hierarchy for a precise response.

[0032] Step 5: Place the relevant logic with special critical timing paths within the interaction module into the corresponding preset physical grid area using directional placement constraints, thereby completing the layout and routing. This step is the directional placement of specific critical paths.

[0033] To address the residual long timing paths that may arise within the MCU module due to its L-shaped configuration, a high-precision region placement / bounds constraint strategy is employed to force the high-frequency logic to be placed within the corresponding planned grid region (e.g., Figure 3 (The solid square shown in the lower left corner) ensures the absolute safety and timing convergence of the sensitive clock domain inside the module.

[0034] The following is a more detailed description of this specific implementation method.

[0035] Reference Figure 2 As shown, if a traditional block-hardening strategy is implemented, EDA tools will generate an impenetrable blockage (physical blockage) around each module. Consequently, the channel between the two rows of SerDes must not only carry tens of thousands of signal lines from the Top layer but also deploy a global clock tree. This severe shortage of physical channels directly leads to… Figure 2 The I / O area in the middle reported unrecoverable congestion violations during the layout phase. Even more critically, there was data exchange between the Top layer logic, the internal logic of S1, and the MCU below at a high-frequency synchronous clock domain. Due to the large physical distance between the hard cores, this area reported hundreds of Setup Time violations that could not be repaired by inserting buffers.

[0036] Reference Figure 3 As shown, this specific implementation addresses these multiple technical bottlenecks by adopting a near-flattened architecture strategy: First, during the floorplanning phase, soft region constraints are used instead of hard physical isolation. The tool defines the coordinate system for S1-S8, but does not set hard isolation zones. This keeps the area of ​​S1-S8 under control, but from the perspective of the global router, narrow channels are opened to both sides for penetration. Top-layer routing can utilize the metal layer resources of S1-S8 for traversal, effectively diluting congested hotspots.

[0037] Secondly, the geometry of the MCU module was reconstructed. Instead of being limited to a square rectangle, it was designed as an L-shaped polygon region. The upward-protruding part of the L-shape was forcibly stretched to cover the lower half of S1 and the end of the narrow channel. At this point, the three previously hard-isolated logic components were given a common physical space in the physics engine. Figure 3 (At the dashed ellipse). When performing placement, the tool automatically snaps together and mixes registers and combinational logic that have data interaction (Talk) between the three parties in this overlapping area. The physical distance is reduced from thousands of micrometers to tens of micrometers, the interconnect latency approaches zero, and cross-boundary timing achieves "painless convergence".

[0038] This method breaks physical boundaries, meaning the entire chip needs to perform macroscopic calculations on millions of instances (approximately two to three million in this project) in Flatten mode. Thanks to the powerful computing capabilities of current EDA servers, the increased runtime can be completely masked for designs with a manageable overall scale (<10M scale).

[0039] For highly reused SerDes modules (reused 8 times), slight differences in the surrounding environment under soft boundaries may lead to subtle differences in the final internal routing of S1 to S8. If the project has stringent requirements for the absolute symmetry of the 8 SerDes, this specific implementation provides a "guaranteed ECO replacement method" with a dimensionality reduction approach: the front end only needs to provide an ECO solution for S1 within the overlapping region. The back end designer only performs precise physical ECO repairs within S1 containing the overlapping environment. After S1 passes all timing and DRC approvals, its converged local layout and netlist are directly cut out, and the "Clone / Replace" function of the tool is used to seamlessly cover and replace modules S2 to S8, which are also under the Region constraint, thereby completing the global ECO at extremely low cost.

[0040] The method described in this specific implementation is particularly suitable for digital chip physical designs with an overall scale of less than 10 million instances (10M). For very large system-on-a-chip (SoC) designs, the design ideas of this specific implementation can also be perfectly applied to the various sub-systems within it—that is, overcoming multiple bottlenecks in timing and physical routing through means such as region control, soft boundary transformation, preservation of hierarchical ports, and physical region overlap. Real-world examples show that for scales exceeding 30 million instances (30M), a hybrid strategy of flattening the two high-frequency interaction modules S1 and S2 and hard-core and instantiating the remaining modules (the remaining 6 modules) multiple times can also achieve an effective balance between timing performance requirements and runtime.

[0041] This specific embodiment provides a hierarchical physical design method and system for soft boundary control, which aims to break the rigid physical boundaries of traditional hard cores, completely solve the problems of winding congestion and cross-boundary timing collapse caused by irregular layouts and narrow channels, while still retaining the efficient local response capability for frequent logic ECOs at the front end.

[0042] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided in this specific embodiment in the form of pure computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units provided in this specific embodiment function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0043] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A hierarchical physical design method for soft boundary control, characterized in that, include: The hard core isolation area of ​​at least one submodule in the layout is converted into a soft boundary control area. The soft boundary control area is controlled by physical area, so that the logic and traces in the adjacent wiring channels of the submodule can borrow and enter the soft boundary control area. The submodule includes multiple symmetrically placed high-speed serializer / deserializer Serdes S1-S8 modules, and the wiring channel is a narrow channel formed by two rows of symmetrically placed Serdes S1-S8 modules. The hard rectangular area of ​​the interaction module is reshaped into an irregularly shaped area, causing the local boundary of the irregularly shaped area to extend; wherein, the interaction module is a microcontroller unit (MCU) module, and the reshaping of the hard rectangular area of ​​the interaction module into an irregularly shaped area includes: the reshaped irregularly shaped area is an L-shaped soft boundary physical area; the extension of the local boundary of the irregularly shaped area means stretching the local area of ​​the interaction module upward so that it physically overlaps with the soft boundary control area of ​​the S1 module and the wiring channel; The irregular region overlaps with the soft boundary control area of ​​at least one sub-module and the wiring channel in physical space to form a shared interaction area, which is a shared interaction area where multiple physical resources overlap. The sub-modules and the interaction module are configured to retain hierarchical port attributes to blur physical boundaries, while maintaining the independence of logical pins of each module. The logic related to special key timing paths within the interaction module is placed into a preset corresponding physical grid area by means of directional placement constraints, thereby completing the layout and routing; Specifically, for the residual specific long timing path generated inside the MCU module due to the change in shape to L-shape, a directional placement constraint strategy is adopted to force the relevant logic of this special critical timing path to be placed in the corresponding planning grid area, so as to ensure the safety and timing convergence of the sensitive clock domain inside the module.

2. The hierarchical physical design method for soft boundary control according to claim 1, characterized in that, The process of converting the hard core isolation region of the sub-module in the layout into a soft boundary control region includes maintaining the same physical area size for all the sub-modules in the entire chip.

3. The hierarchical physical design method for soft boundary control according to claim 2, characterized in that, The shared interaction area where multiple physical resources overlap is specifically a physical area formed by the upward extension of the L-shaped physical area of ​​the MCU module, the interior of the soft boundary control area of ​​the first Serdes module, and the narrow channel.

4. The hierarchical physical design method for soft boundary control according to claim 3, characterized in that, The irregular region overlaps with the soft boundary control area of ​​at least one of the sub-modules and the wiring channel in physical space to form a shared interaction area. This includes setting the reserved hierarchical port attribute to lock the boundary pins of each module in the near-flat physical layout wiring process. When an engineering change (ECO) occurs in the front-end logic design, the back-end design directly responds to the module-level local engineering change (ECO) through the original port.

5. The hierarchical physical design method for soft boundary control according to claim 1, characterized in that, It also includes a step of providing a physical replacement guarantee for the repeatedly reused submodules through engineering change ECO, including: When an Engineering Change ECO occurs, only the first submodule within the shared interaction area is selected for a local physical engineering change ECO implementation. After its physical layout and timing are fully converged, the logic netlist and physical layout results of that submodule are extracted and seamlessly replaced with other submodules of the same type in the chip layout.

6. The hierarchical physical design method for soft boundary control according to claim 1, characterized in that, For designs where the total number of instances is less than a preset threshold, all modules to be processed adopt soft boundary and physical region control methods. For designs where the total number of instances exceeds the preset threshold, modules with high-frequency interactions are flattened and combined with physical area control and the preservation of hierarchical port attributes, while the remaining modules remain hardcore and are instantiated multiple times.

7. A hierarchical physics design system with soft boundary control, characterized in that, include: A boundary conversion module is used to convert the hard core isolation area of ​​at least one sub-module in the layout into a soft boundary control area based on physical area control, so that the logic and traces in the adjacent routing channels of the sub-module can borrow and enter the soft boundary control area; wherein, the sub-module includes multiple symmetrically placed high-speed serializer / deserializer Serdes S1-S8 modules, and the routing channel is a narrow channel formed by two rows of symmetrically placed Serdes S1-S8 modules. The region reshaping module is used to reshape the hard core rectangular region of the interaction module into an irregularly shaped region, causing the local boundary of the irregularly shaped region to extend and overlap with the soft boundary control area of ​​at least one sub-module and the wiring channel in physical space, forming a shared interaction area with overlapping physical resources. The interaction module is a microcontroller unit (MCU) module. Reshaping the hard core rectangular region of the interaction module into an irregularly shaped region includes: the reshaped irregularly shaped region being an L-shaped soft boundary physical region; the extension of the local boundary of the irregularly shaped region refers to stretching the local area of ​​the interaction module upwards, causing it to overlap physically with the soft boundary control area of ​​the S1 module and the wiring channel. The hierarchical port retention module is used in electronic design automation (EDA) tools to set the hierarchical port retention attribute for the sub-modules and the interaction modules, so as to maintain the independence of the logic pins of each module while blurring the physical boundaries. The directional placement constraint module is used to place the relevant logic with special key timing paths inside the interaction module into a preset corresponding physical grid area through directional placement constraints, thereby completing the layout and routing. Specifically, for the residual specific long timing path generated inside the MCU module due to the change in shape to L-shape, a directional placement constraint strategy is adopted to force the relevant logic of this special critical timing path to be placed in the corresponding planning grid area, so as to ensure the safety and timing convergence of the sensitive clock domain inside the module.

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