Chip pin positioning method and device, electronic equipment and storage medium

Abstract

The application provides a chip pin positioning method and device, electronic equipment and storage medium, and relates to the technical field of pin positioning. First, the standard pin information of the corresponding model of the to-be-tested chip is acquired, and a theoretical topological grid model for spatial comparison is constructed; then, image information containing the to-be-tested chip is acquired, the mirror reflection interference of the flat metal pad is eliminated by using multi-level exposure fusion, and the front view rectangular image of the chip is determined, and further three-dimensional nonlinear warping deformation compensation is performed; spatial hash matching is performed to select a reference point, and a spatial mapping relationship between the pins and the standard pin information is established; finally, a target pin query instruction is acquired, and the target pin information in the standard pin information is highlighted and rendered and superimposed on the corresponding pin, and X-ray bottom perspective rendering of dynamic label avoidance and occlusion blind area is realized. The scheme provided by the application has the advantages of high anti-reflection, elimination of physical deformation error, prevention of tool occlusion, and higher positioning efficiency and accuracy.

Description

Technical Field

[0001] This application relates to the field of pin positioning technology, and more specifically, to a chip pin positioning method, apparatus, electronic device, and storage medium. Background Technology

[0002] Currently, in the process of server motherboard development, chip testing, or failure analysis (FA), when faced with high-density packaged chips (such as BGA, LGA, with 5000~10000+ pins), the common practice for engineers to locate specific pins (such as finding a signal pin or power domain) is "manual visual comparison".

[0003] The procedure typically involves the engineer opening the pin map (BallMap / PinList) in the chip datasheet on a computer screen, then observing the physical chip's package surface with the naked eye, a magnifying glass, or a microscope, and manually counting the pins on the physical chip based on the row and column coordinates (e.g., RowA, Column1) in the BallMap to deduce the location of the target pins.

[0004] However, this manual identification method suffers from extremely low efficiency, fatigue, and low positioning accuracy. Specifically: Extremely inefficient and prone to fatigue: For advanced packaged chips with tens of thousands of pins and a spacing of less than 1mm, counting them manually takes a very long time, and focusing on tiny solder joints for a long time can easily lead to visual fatigue.

[0005] Low positioning accuracy (extremely prone to errors): Due to the dense arrangement of solder joints, manual counting is very prone to "misalignment" or "misalignment", resulting in incorrect measurement points. In severe cases, the chip may even be burned out due to a short circuit caused by the probe accidentally touching the wrong spot.

[0006] The requirements for the observation angle are stringent: existing vision aids typically require the lens to be strictly perpendicular to the chip surface; otherwise, the resulting perspective distortion will prevent engineers from accurately determining the row and column correspondences. In addition, for packages such as FCLGA, their flat metal pads are prone to high-intensity directional specular reflections under coaxial light sources, causing overexposed pixels and obscuring the true edges of the pins.

[0007] Lack of intuitiveness and physical obstruction: Electronic documents and physical objects are separate and cannot be displayed in real time. More importantly, at the moment of probe insertion, the test probe itself and the operator's hand directly obstruct the physical line of sight, causing the operator to lose visual guidance. Summary of the Invention

[0008] The purpose of this application is to provide a chip pin positioning method, device, electronic device and storage medium to solve the problems of low efficiency and fatigue caused by manual positioning of chip pins in the prior art, low positioning accuracy, high reflective interference, large-size package deformation leading to alignment misalignment, and tool obstruction leading to positioning failure.

[0009] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a chip pin positioning method, the chip pin positioning method comprising: Obtain the standard pin information of the corresponding model of the chip under test, and construct a theoretical topology matrix template based on the standard pin information; Acquire image information containing the chip under test, perform multi-level exposure fusion on the image information to eliminate specular reflection interference from the metal pads, and determine the frontal rectangular image of the chip under test from the image information; Nonlinear three-dimensional warping deformation compensation is performed based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the frontal rectangular image. A measured topological fingerprint is generated based on the pin physical gap arrangement features in the frontal rectangular image. The measured topological fingerprint is hash-matched with the theoretical topological matrix template to select the grid alignment origin as the reference point. The mapping relationship between the pins of the frontal rectangular image and the standard pin information is established based on the reference point. Obtain the target pin query command, and based on the mapping relationship, superimpose the target pin information from the standard pin information onto the corresponding pin of the front view rectangular image. Combine the real-time measured test probe motion trajectory to perform dynamic label avoidance control, and perform virtual bottom-level perspective rendering on the blind area occluded by the test probe body to achieve the positioning of the target pin.

[0010] Optionally, the step of determining the frontal rectangular image of the chip under test from the image information includes: Based on the image information, the local highlight overflow state is detected in real time. Multiple frames of original images with different exposure values ​​are automatically acquired within a preset time. Overexposed pixels are removed based on dynamic pixel grayscale threshold. The boundary between the metal pad and the solder mask layer is extracted and fused to generate a high-contrast reference binarized image. Edges are extracted from the reference binarized image using an edge detection operator, and a closed quadrilateral contour consisting of four vertices is fitted using a polygon approximation algorithm. The homography matrix is ​​determined based on the extracted closed quadrilateral contour; Based on the homography matrix, an inverse perspective transformation is performed on the image of the chip under test. Coordinate remapping operation is performed on each pixel in the original image, and the image is stretched and restored to obtain a front-view rectangular image.

[0011] Optionally, the step of determining the homography matrix based on the extracted closed quadrilateral contour includes: Using the pixel coordinates of the four vertices of the closed quadrilateral contour as input and the physical coordinates of the four corner points of a preset ideal frontal rectangle as output targets, the direct linear transformation method is used to calculate 3. 3. Homogeneous homography matrix.

[0012] Optionally, the step of performing nonlinear three-dimensional warpage compensation based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the frontal rectangular image includes: The distortion gradient between the actual pixel spacing and the ideal standard spacing of adjacent pads in the front-view rectangular image is calculated. The physical warping deformation surface of each region of the chip packaging substrate in the Z-axis direction is obtained by reverse calculation. The virtual mesh of the standard pin information is then finely adjusted with the same curvature using a non-uniform rational B-spline algorithm.

[0013] Optionally, the steps for obtaining the standard pin information of the corresponding model of the chip under test include: Obtain the model selection instruction, and retrieve and determine the standard pin information from the database based on the model selection instruction; or Obtain an external file containing standard pin information, wherein the external file includes at least one of an Excel spreadsheet, a CSV file, a TXT text file, a PNG bitmap, a DXF drawing, or a DWG drawing; The external file is parsed to obtain the standard pin information.

[0014] Optionally, the step of generating a measured topological fingerprint based on the physical void arrangement features of the pins in the frontal rectangular image, and selecting a grid alignment origin as a reference point by hash matching the measured topological fingerprint with the theoretical topological matrix template, includes: Scan the front-view rectangular image, generate a measured topology binary matrix based on the actual center point pixel coordinates of its pads, perform spatial hash matching between the measured topology binary matrix and the theoretical topology matrix template, and automatically determine the corresponding alignment origin as the first pin reference point when the matching degree exceeds a preset threshold.

[0015] Optionally, the step of superimposing the target pin information from the standard pin information onto the corresponding pin of the front-view rectangular image includes: In response to the target pin query command, calculate the absolute pixel coordinates of each target pin on the canvas layer, and call the graphics rendering engine to draw a highlighted primitive with a preset color and geometric shape at the absolute pixel coordinates; The canvas layer and the front view rectangular image are pixel-blended and superimposed using the Alpha channel blending algorithm, and the remaining unselected non-target pins are made semi-transparent and blurred or completely hidden. Based on color space segmentation, the outline and tip coordinates of the physical test probe entering the screen are tracked in real time. When the pixel distance between the probe tip and the bright target pin is less than the safety threshold, the text label of the target pin is controlled to move along the direction of probe entry to avoid it. The area obscured by the physical test probe body is defined as the mask area. Within the mask area, the transparency of the real-time video stream background image is reduced, and the virtual network layer at the bottom of the canvas layer is forced to be highlighted and rendered to perform virtual bottom-layer perspective.

[0016] Secondly, embodiments of this application also provide a chip pin positioning device, the chip pin positioning device comprising: The data acquisition module is used to acquire the standard pin information of the corresponding model of the chip under test, and to construct a theoretical topology matrix template based on the standard pin information; The data acquisition module is also used to acquire image information containing the chip under test, perform multi-level exposure fusion on the image information to eliminate specular reflection interference from the metal pads, and determine the frontal rectangular image of the chip under test from the image information. The data processing module is used to perform nonlinear three-dimensional warping deformation compensation based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the frontal rectangular image. The data processing module is also used to generate a measured topological fingerprint based on the pin physical gap arrangement features in the frontal rectangular image, and to select the grid alignment origin as the reference point by performing hash matching between the measured topological fingerprint and the theoretical topological matrix template, and to establish the mapping relationship between the pins of the frontal rectangular image and the standard pin information based on the reference point. The image rendering module is used to obtain the target pin query command, and based on the mapping relationship, superimpose the target pin information in the standard pin information onto the corresponding pin of the front view rectangular image, and perform dynamic label avoidance control in combination with the real-time measured test probe motion trajectory, and perform virtual bottom layer perspective rendering on the blind area occluded by the test probe body to achieve the positioning of the target pin.

[0017] Thirdly, embodiments of this application also provide an electronic device, including: a memory for storing one or more programs; a processor; and when the one or more programs are executed by the processor, the above-described method is implemented.

[0018] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0019] Compared with the prior art, this application has the following advantages: Overcoming "planar perspective bias" with 3D physical warp compensation: Traditional linear perspective transformations are prone to engineering defects such as "center alignment and edge misalignment" when dealing with large-size, high-performance chips. This application introduces the nonlinear physical warpage characteristics of the chip packaging substrate at room temperature. By calculating the distortion rate of the local micro-pitch, the Z-axis physical curvature is inversely derived. Then, a non-uniform rational spline algorithm is used to perform 3D nonlinear mapping on the virtual mesh, improving the alignment accuracy from the planar pixel level to the sub-millimeter level of the 3D physical level.

[0020] This invention eliminates the reliance on local gap fingerprint anchoring based on global contours: Existing technologies rely on complete chip contours or specific PinA1 artificial markings, which cannot achieve alignment under high magnification and extremely limited field of view in testing scenarios. This application extracts naturally occurring "unmarked areas" in the pin array to construct a feature topology matrix fingerprint, thereby forming an absolute positioning benchmark with global recognizability. This mechanism maps local features to the global layout, effectively enhancing the system's anti-interference capability and stability under extreme testing conditions.

[0021] Dynamic perspective and avoidance for pin touch testing scenarios: This application pioneers a real-time probe contour tracking mechanism, which controls the text label to actively shift and avoid the probe tip when it approaches; and for blind spots physically blocked by the probe, it breaks through the visual interference barrier in the superposition of virtual and real by forcibly lowering the alpha value of the background image and rendering a virtual BallMap (X-Ray mode) on top, effectively preventing chip short circuit damage caused by probe deviation.

[0022] Multi-level exposure fusion eliminates specular reflections: Addressing the industry pain point that flat metal pads such as FCLGA are prone to specular reflection spots, causing image overexposure and overflow, multi-level exposure image differential fusion is triggered in a short time to eliminate overexposed pixels and accurately lock the dark boundary between the metal edge of the pad and the solder mask layer, ensuring a high-precision edge recognition benchmark. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is an exemplary flowchart of a chip pin positioning method provided in an embodiment of this application.

[0025] Figure 2 An exemplary flowchart of the sub-step S104 provided in the embodiments of this application.

[0026] Figure 3 An exemplary flowchart of a sub-step of S108 provided in an embodiment of this application.

[0027] Figure 4 This is a schematic diagram of a chip pin positioning device provided in an embodiment of this application.

[0028] Figure 5 A schematic diagram of the modules of an electronic device provided in an embodiment of this application.

[0029] In the picture: 100-Chip pin positioning device; 110-Data acquisition module; 120-Data processing module; 130-Image rendering module; 200-Electronic device; 201-Processor; 202-Memory; 203-Communication interface; 204-High-frequency hardware camera module; 205-System bus; 206-Augmented reality display / AR headset. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0031] As described in the background section, the current method for locating chip pins is generally a manual visual comparison method. This requires engineers to manually locate the pins in conjunction with the chip datasheet. However, this method has serious engineering drawbacks, such as extremely low efficiency and fatigue, low positioning accuracy (very prone to errors), strict requirements on the observation angle, lack of intuitiveness, and physical obstruction interference.

[0032] In view of this, to solve the above problems, this application provides a chip pin positioning method that achieves automatic and precise positioning of chip pins through image recognition, physical deformation adaptive compensation, and dynamic anti-occlusion AR rendering. As one implementation method, please refer to... Figure 1 The method includes: S102: Obtain the standard pin information of the corresponding model of the chip under test, and construct a theoretical topology matrix template based on the standard pin information.

[0033] In engineering practices such as chip testing, failure analysis, and motherboard development, engineers often need to deal with mass-produced standard chips or chip samples still in the R&D and verification stage. In this application, as one implementation method, the system can directly retrieve and load the corresponding ball map structured data from a built-in local or network-accessible standardized database via a model selection command, thereby determining the standard pin information. As another implementation method, the system also provides an external file import interface, supporting users to load and parse external Excel spreadsheets, CSV comma-separated value files, TXT plain text files, netlist files, PCB layout diagrams (DXF / DWG format), or package appearance images (PNG). During the parsing process, the system extracts the pin names, relative physical coordinates, and functional attributes, uniformly converting them into a virtual pin distribution mesh model suitable for AR rendering.

[0034] It should be noted that the data parsing module will further retrieve and extract the spatial geometric arrangement features of the "dummy ball voids" that are naturally reserved in the pin array due to circuit routing, power isolation or process design. In memory, it will map and generate a standard "theoretical topology binary matrix template" (the physical coordinates corresponding to the pads are encoded as 1, and the empty spaces without pads are encoded as 0), which will be used as the unique feature fingerprint of the chip in physical space.

[0035] S104: Acquire image information containing the chip under test, perform multi-level exposure fusion on the image information to eliminate specular reflection interference from metal pads, and determine the frontal rectangular image of the chip under test from the image information; perform nonlinear three-dimensional warping deformation compensation based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the frontal rectangular image.

[0036] In on-site operations such as server motherboard debugging, due to limited work space, when shooting with a handheld mobile terminal or AR headset, it is almost impossible to guarantee that the camera's optical axis is strictly perpendicular to the chip surface. Once there is a handheld tilt angle, perspective distortion occurs in the image, and the originally rectangular chip substrate appears as a trapezoid in the image. In addition, the immersion gold or OSP metal pads on the bottom of the FCLGA package will produce extremely strong specular directional reflections, resulting in local overexposure and blown-out white areas of the image, destroying edge features.

[0037] In order to reconstruct a two-dimensional / three-dimensional reference plane that strictly matches the actual spatial layout of the physical pins while addressing the aforementioned geometric distortions and optical interference, this application breaks down step S104 as follows: Figure 2 The specific hardware and software co-processing algorithm chain is shown below: S1041 detects local highlight overflow in real time based on image information, automatically acquires multiple frames of original images with different exposure values ​​within a preset time, removes overexposed pixels based on dynamic pixel grayscale threshold, extracts the boundary between metal pads and solder mask layer and fuses them to generate a high-contrast reference binarized image.

[0038] S1042 uses an edge detection operator to extract edges from a reference binarized image and fits a closed quadrilateral contour composed of four vertices using a polygon approximation algorithm.

[0039] S1043, determine the homography matrix based on the extracted closed quadrilateral contour; perform inverse perspective transformation on the image of the chip under test based on the homography matrix, perform coordinate remapping operation on each pixel in the original image, and stretch and restore to obtain the frontal rectangular image.

[0040] S1044 calculates the distortion gradient between the actual pixel spacing and the ideal standard spacing of adjacent pads in the front-view rectangular image, and reverses it to obtain the physical warping deformation surface of each region of the chip packaging substrate in the Z-axis direction. Then, it uses the non-uniform rational B-spline algorithm to fine-tune the three-dimensional bending deformation of the virtual mesh of the standard pin information with the same curvature.

[0041] In S1041, multi-level exposure acquisition and specular reflection suppression (optical preprocessing) can be achieved: the system controls the camera module of the mobile terminal, and when it detects local saturation highlight overflow in the image, it continuously triggers the capture of three original images with exposure values ​​of EV=-1.0, EV=0, and EV=+1.0 within 100ms. The algorithm uses grayscale conversion and differential fusion to set a dynamic grayscale threshold to remove interference pixels caused by overexposed strong light clusters inside the pads, accurately extracts the dark low reflectivity boundary ring naturally formed between the edge of the metal pad and the substrate solder mask, and fuses them to generate a high-contrast reference binarized image.

[0042] In S1042, edge and contour recognition is achieved: Gaussian filtering is applied to the reference binarized image to remove high-frequency fiber noise from the substrate, followed by edge extraction using the Canny edge detection operator. The findContours function is used to detect closed loops in the light-dark boundary region, and the contour is simplified using the approxPolyDP polygonal approximation algorithm. Finally, the pixel coordinates of the four vertices of the outer edge of the chip substrate under test are accurately located, denoted as... .

[0043] In S1043, homography matrix calculation and two-dimensional correction of inverse perspective transformation can be achieved: using the pixel coordinates of the four vertices of the extracted quadrilateral contour as input, and the physical coordinates of the four corner points of the preset ideal frontal rectangle as output targets, the direct linear transformation (DLT) method is used to calculate 3D homography matrix. 3. Homogeneous homography matrix H. Using this homography matrix, coordinate remapping and bilinear interpolation resampling operations are performed on each pixel in the original image to stretch and restore the perspective-distorted trapezoidal region into a standard two-dimensional front-view rectangular image with accurate aspect ratio and uniform row and column spacing.

[0044] In S1044, nonlinear deformation surface inversion and three-dimensional deformation compensation can be achieved: Since homography transformation is a linear transformation, it cannot eliminate the physical thermal warpage of large-size substrates caused by residual stress during processing or reflow soldering heat history. After completing two-dimensional rectangular correction, the system calculates the actual pixel spacing on the image between the centers of any two adjacent solid pads from the center to the edge. ), and the theoretical standard spacing loaded in step S102 ( The algorithm compares the two data points based on the nonlinear distortion gradient between them. The physical warping deformation of each region of the chip packaging substrate in the Z-axis vertical direction is obtained by reverse calculation. Subsequently, the system starts the Non-Uniform Rational B-Spline (NURBS) algorithm to perform "3D reverse surface mapping deformation calculation" with the same curvature on the virtual BallMap standard mesh in the plane inside the system, to ensure that the projection of the bent electronic mesh on the two-dimensional screen can achieve sub-millimeter level perfect engagement with the actual metal pad array that has undergone physical warping.

[0045] S106. Based on the pin physical gap arrangement features in the frontal rectangular image, a measured topological fingerprint is generated. The measured topological fingerprint is hash-matched with the theoretical topological matrix template to select the grid alignment origin as the reference point. Based on the reference point, the mapping relationship between the pins in the frontal rectangular image and the standard pin information is established.

[0046] This application establishes a dual decision-making mechanism in frontal rectangular images, with fully automatic topological fingerprinting as the primary method and manual path confirmation as a secondary method. In practical applications, this includes both automatic identification mode and automatic identification mode.

[0047] In automatic recognition mode, the system scans the front-view rectangular image generated in step S104, identifies the actual center point pixel coordinates of each pad, and generates a "measured topology binary matrix". The algorithm uses local spatial hash matching (HashMatching) or normalized cross-correlation (NCC) to perform a graph alignment comparison between this measured matrix and the "theoretical topology binary matrix template" generated in step S102. When the topology matching confidence exceeds a preset threshold (e.g., 95%), the system automatically locks the spatial geometric center of the unfilled area and marks it as the origin of the first pin (PinA1).

[0048] It should be noted that this anchoring method based on local void fingerprints allows the system to accurately determine the absolute spatial coordinate mapping of the current field of view, even when the field of view is extremely limited due to blind spots in the chassis or high magnification under a microscope, and only a quarter of the chip is captured. This eliminates the rigid dependence on the complete outer boundary of the chip. If the chip is a full-array ball-and-ball package (with no empty pins), the system automatically switches to multi-source feature verification, scanning the corner area of ​​the substrate to find the triangular exposed copper pad, which has a clear geometric outline and high contrast, or to identify the rectangular structure feature formed by the silkscreen frame, and determine it as the physical Pin A1 location.

[0049] In manual assistance mode, when the confidence level of automatic identification is insufficient due to severe scratches and contamination on the packaging surface, the APP interface will pop up a prompt to guide the user to click on the visible physical location of PinA1 on the screen with their finger, and the system will directly adopt the click coordinates as the reference point.

[0050] Regardless of the method used to determine the reference point, the system combines the known pin spacing parameters to calculate the complete layout of the virtual pin distribution grid after three-dimensional deformation correction in the image coordinate system, thereby establishing a strict spatial mapping relationship between the pins of the front-view rectangular image and the standard pin information.

[0051] S108: Obtain the target pin query command, and based on the mapping relationship, overlay the target pin information in the standard pin information onto the corresponding pin in the frontal rectangular image, and perform dynamic label avoidance control in combination with the real-time measured test probe motion trajectory, and perform virtual bottom-level perspective rendering on the blind area occluded by the test probe body to achieve the positioning of the target pin.

[0052] As one implementation method, please refer to Figure 3 The steps in S108 include: S1081, in response to the target pin query command, calculates the absolute pixel coordinates of each target pin on the canvas layer, and calls the graphics rendering engine to draw the highlighted primitives of preset colors and geometric shapes at the absolute pixel coordinates.

[0053] S1082 uses an Alpha channel blending algorithm to perform pixel fusion and overlay between the canvas layer and the front rectangular image, and performs semi-transparent blurring or complete hiding of the remaining unselected non-target pins.

[0054] S1083 uses color space segmentation to track the outline and tip coordinates of the physical test probe entering the screen in real time. When the pixel distance between the probe tip and the bright target pin is less than the safety threshold, the text label of the target pin is controlled to move along the direction of the probe to avoid it.

[0055] S1084 defines the area occluded by the physical test probe body as the mask area, reduces the transparency of the real-time video stream background image within the mask area, and forces the virtual network layer at the bottom of the canvas layer to be highlighted to perform virtual bottom-layer perspective.

[0056] In practical engineering scenarios, the system uses a mobile terminal or augmented reality headset as the implementation subject, creating a transparent two-dimensional Canvas layer in memory with the same size as the currently viewed rectangular image (initially with a global alpha value of 0). When the user enters a query command in the software interface (supporting semantic search by pin name "VCC_CORE", power type "0.8VPower", and function category "GND"), the backend data parsing module quickly filters the standard pin information database and extracts the row and column matrix indices of all matching pins.

[0057] Based on the established spatial scale transformation matrix and NURBS warping model fine-tuning, the system batch calculates the absolute pixel coordinates of all target pins on the Canvas. The graphics rendering module calls graphics APIs (such as OpenGL / Vulkan) to highlight and render geometric primitives of preset colors and shapes on the canvas layer centered on each absolute pixel coordinate (e.g., drawing a semi-transparent red circular block for the power network and a blue ring for the high-speed signal line). Then, pixel blending is performed through the Alpha blending engine. The image transparency of the remaining unmatched non-target pins is reduced so that their outlines are visible but do not interfere with the visual focus (or they are hidden directly in advanced mode), achieving intuitive semantic-level mapping.

[0058] In particular, to prevent the hardware test probe body and the operator's hand from directly obstructing the physical line of sight during probe measurement at the micrometer level, this application integrates an anti-obstruction probe recognition and X-Ray dynamic interaction mechanism at the software level: the system performs color segmentation and morphological extraction on the video stream in the HSV color space, and tracks the outline of the metal test probe entering the screen and the real-time two-dimensional coordinates of the tip in real time.

[0059] Dynamic collision avoidance: The software calculates the Euclidean distance between the probe tip coordinates and the highlighted target pin coordinates in real time. When the distance is less than the safety threshold (e.g., 30 pixels), the system activates collision avoidance logic, automatically controlling the text label (e.g., “VCC_CORE”) originally superimposed on the pad to be shifted 45 pixels in the opposite direction of the probe's entry, ensuring that the text information is always clearly visible during the operation and is not obscured by the probe entity.

[0060] X-Ray perspective mechanism: The system defines the area obscured by the probe as a mask. Within this mask, the software dynamically adjusts the transparency of the real-time video background image to 20% (for global blurring) through shaders, while forcibly raising the rendering level (Z-Index) of the virtual BallMap color network and the target highlight primitives in memory to the top layer. This creates a surreal visual effect on the screen that "sees through the probe metal and directly views the underlying physical pads," preventing short circuit risks caused by probe slippage or misalignment, and meeting the objective requirements of quality control in large-scale integrated circuit production for testing efficiency and accuracy.

[0061] Based on the above implementation, this application also provides a chip pin positioning device 100. Please refer to [link to relevant documentation]. Figure 4 The chip pin positioning device 100 includes: The data acquisition module 110 is used to acquire the standard pin information of the corresponding model of the chip under test, and to construct a theoretical topology matrix template based on the standard pin information.

[0062] The data acquisition module 110 is also used to acquire image information containing the chip under test, perform multi-level exposure fusion on the image information to eliminate specular reflection interference from the metal pads, and determine the frontal rectangular image of the chip under test from the image information.

[0063] The data processing module 120 is used to perform nonlinear three-dimensional warping deformation compensation based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the front-view rectangular image.

[0064] The data processing module 120 is also used to generate a measured topological fingerprint based on the pin physical gap arrangement features in the frontal rectangular image. By performing hash matching between the measured topological fingerprint and the theoretical topological matrix template, the grid alignment origin is selected as the reference point, and a mapping relationship between the pins and standard pin information in the frontal rectangular image is established based on the reference point.

[0065] The image rendering module 130 is used to obtain the target pin query command, and based on the mapping relationship, superimpose the target pin information in the standard pin information onto the corresponding pin of the front view rectangular image, and perform dynamic label avoidance control in combination with the real-time measured test probe motion trajectory, and perform virtual low-level perspective rendering on the blind area occluded by the test probe body to achieve the positioning of the target pin.

[0066] Please see Figure 5This application provides an electronic device 200, which includes at least one processor 201, at least one memory 202, a communication interface 203, a high-frequency hardware camera module 204, and an augmented reality display / AR headset 206. The components are directly connected to each other or electrically connected via a system bus 205 to achieve data transmission or interaction. The memory 202 stores program instructions executable by the processor 201, which can call and execute the program instructions to implement any of the chip pin positioning methods provided by the various implementations described above.

[0067] Among them, the high-frequency hardware camera module 204 is used to perform multi-level exposure acquisition to eliminate specular reflection, and the augmented reality display / AR headset 206 is used to output a graphical interface that includes dynamic anti-occlusion and X-ray perspective.

[0068] The memory 202 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0069] Processor 201 can be an integrated circuit chip with signal processing capabilities. This processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0070] Understandable. Figure 5 The structure shown is for illustrative purposes only; the electronic device 200 may also include components that are more advanced than those shown. Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown. Figure 5The components shown can be implemented using hardware, software, or a combination thereof.

[0071] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for positioning chip pins, characterized in that, The chip pin positioning method includes: Obtain the standard pin information of the corresponding model of the chip under test, and construct a theoretical topology matrix template based on the standard pin information; Image information containing the chip under test is acquired, and multi-level exposure fusion is performed on the image information to eliminate specular reflection interference from metal pads. The frontal rectangular image of the chip under test is determined from the image information. Nonlinear three-dimensional warping deformation compensation is performed based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the frontal rectangular image. A measured topological fingerprint is generated based on the pin physical gap arrangement features in the frontal rectangular image. The measured topological fingerprint is hash-matched with the theoretical topological matrix template to select the grid alignment origin as the reference point. The mapping relationship between the pins of the frontal rectangular image and the standard pin information is established based on the reference point. Obtain the target pin query command, and based on the mapping relationship, superimpose the target pin information from the standard pin information onto the corresponding pin of the front view rectangular image. Combine the real-time measured test probe motion trajectory to perform dynamic label avoidance control, and perform virtual bottom-level perspective rendering on the blind area occluded by the test probe body to achieve the positioning of the target pin.

2. The chip pin positioning method as described in claim 1, characterized in that, The steps for determining the frontal rectangular image of the chip under test from the image information include: Based on the image information, the local highlight overflow state is detected in real time. Multiple frames of original images with different exposure values ​​are automatically acquired within a preset time. Overexposed pixels are removed based on dynamic pixel grayscale threshold. The boundary between the metal pad and the solder mask layer is extracted and fused to generate a high-contrast reference binarized image. Edges are extracted from the reference binarized image using an edge detection operator, and a closed quadrilateral contour consisting of four vertices is fitted using a polygon approximation algorithm. The homography matrix is ​​determined based on the extracted closed quadrilateral contour; Based on the homography matrix, an inverse perspective transformation is performed on the image of the chip under test. Coordinate remapping operation is performed on each pixel in the original image, and the image is stretched and restored to obtain a front-view rectangular image.

3. The chip pin positioning method as described in claim 2, characterized in that, The steps for determining the homography matrix based on the extracted closed quadrilateral contour include: Using the pixel coordinates of the four vertices of the closed quadrilateral contour as input and the physical coordinates of the four corner points of a preset ideal frontal rectangle as output targets, the direct linear transformation method is used to calculate 3.

3. Homogeneous homography matrix.

4. The chip pin positioning method as described in claim 1, characterized in that, The steps for nonlinear three-dimensional warpage compensation based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the front-view rectangular image include: The distortion gradient between the actual pixel spacing and the ideal standard spacing of adjacent pads in the front-view rectangular image is calculated. The physical warping deformation surface of each region of the chip packaging substrate in the Z-axis direction is obtained by reverse calculation. The virtual mesh of the standard pin information is then finely adjusted with the same curvature using a non-uniform rational B-spline algorithm.

5. The chip pin positioning method as described in claim 1, characterized in that, The steps to obtain the standard pin information of the chip under test include: Obtain the model selection instruction, and retrieve and determine the standard pin information from the database based on the model selection instruction; or Obtain an external file containing standard pin information, wherein the external file includes at least one of an Excel spreadsheet, a CSV file, a TXT text file, a PNG bitmap, a DXF drawing, or a DWG drawing; The external file is parsed to obtain the standard pin information.

6. The chip pin positioning method as described in claim 1, characterized in that, The step of generating a measured topological fingerprint based on the pin physical gap arrangement features in the frontal rectangular image, and selecting a grid alignment origin as a reference point by hash matching the measured topological fingerprint with the theoretical topological matrix template includes: Scan the front-view rectangular image, generate a measured topology binary matrix based on the actual center point pixel coordinates of its pads, perform spatial hash matching between the measured topology binary matrix and the theoretical topology matrix template, and automatically determine the corresponding alignment origin as the first pin reference point when the matching degree exceeds a preset threshold.

7. The chip pin positioning method as described in claim 1, characterized in that, The steps of superimposing the target pin information from the standard pin information onto the corresponding pin of the front-view rectangular image, performing dynamic label avoidance control in conjunction with the real-time measured test probe motion trajectory, and performing virtual bottom-level perspective rendering on the blind area occluded by the test probe body include: In response to the target pin query command, calculate the absolute pixel coordinates of each target pin on the canvas layer, and call the graphics rendering engine to draw a highlighted primitive with a preset color and geometric shape at the absolute pixel coordinates; The canvas layer and the front view rectangular image are pixel-blended and superimposed using the Alpha channel blending algorithm, and the remaining unselected non-target pins are made semi-transparent and blurred or completely hidden. Based on color space segmentation, the outline and tip coordinates of the physical test probe entering the screen are tracked in real time. When the pixel distance between the probe tip and the bright target pin is less than the safety threshold, the text label of the target pin is controlled to move along the direction of probe entry to avoid it. The area obscured by the physical test probe body is defined as the mask area. Within the mask area, the transparency of the real-time video stream background image is reduced, and the virtual network layer at the bottom of the canvas layer is forced to be highlighted and rendered to perform virtual bottom-layer perspective.

8. A chip pin positioning device, characterized in that, The chip pin positioning device includes: The data acquisition module is used to acquire the standard pin information of the corresponding model of the chip under test, and to construct a theoretical topology matrix template based on the standard pin information; The data acquisition module is also used to acquire image information containing the chip under test, perform multi-level exposure fusion on the image information to eliminate specular reflection interference from the metal pads, and determine the frontal rectangular image of the chip under test from the image information. The data processing module is used to perform nonlinear three-dimensional warping deformation compensation based on the distortion gradient between the actual spacing and the theoretical standard spacing of adjacent pads in the frontal rectangular image. The data processing module is also used to generate a measured topological fingerprint based on the pin physical gap arrangement features in the frontal rectangular image, and to select the grid alignment origin as the reference point by performing hash matching between the measured topological fingerprint and the theoretical topological matrix template, and to establish the mapping relationship between the pins of the frontal rectangular image and the standard pin information based on the reference point. The image rendering module is used to obtain the target pin query command, and based on the mapping relationship, superimpose the target pin information in the standard pin information onto the corresponding pin of the front view rectangular image, and perform dynamic label avoidance control in combination with the real-time measured test probe motion trajectory, and perform virtual bottom layer perspective rendering on the blind area occluded by the test probe body to achieve the positioning of the target pin.

9. An electronic device, characterized in that, include: Memory, used to store one or more programs; processor; When the one or more programs are executed by the processor, the method as described in any one of claims 1-7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1-5.

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