A multi-channel real-time single-pixel image reconstruction system

Abstract

The present application relates to the technical field of photoelectric signal acquisition and computational imaging, and discloses a multi-channel real-time single-pixel image reconstruction system, comprising: a laser light source module for generating a plurality of channel laser beams; a spatial radio frequency marker light path module for introducing different frequency spatial radio frequency markers into the laser beams in different channels according to a radio frequency marker signal to irradiate a measured target; a single-pixel detector module for synchronously collecting modulated light signals of the reflected or transmitted combined beams of the measured target by a plurality of single-pixel detectors and converting the modulated light signals into analog electrical signals; a LabVIEW FPGA control and reconstruction module for generating a synchronous radio frequency marker clock and a sampling clock, sending the radio frequency marker signal to the spatial radio frequency marker light path module according to the radio frequency marker clock, collecting the analog electrical signals according to the sampling clock, and performing real-time parallel image reconstruction. The system has high real-time image reconstruction capability.

Description

Technical Field

[0001] This invention relates to the field of photoelectric signal acquisition and computational imaging technology, specifically to a multi-channel real-time single-pixel image reconstruction system. Background Technology

[0002] With the development of applications such as flow cytometry imaging, ultrafast materials detection, online industrial quality inspection, and intelligent sensing, there are increasing demands on the real-time performance, throughput, and scalability of imaging systems.

[0003] Traditional optical imaging systems mainly rely on CCD (Charge-Coupled Devices) or CMOS (Complementary Metal-Oxide-Semiconductor) array imaging devices to acquire images. The imaging speed is limited by physical bottlenecks such as electronic shutter response, pixel readout speed, frame rate and data throughput, making it difficult to meet the needs of real-time, high-quality imaging of high-speed moving or large number of dynamic targets.

[0004] In related technologies, single-pixel imaging technology is used. This involves temporally modulating the light field using a spatial light modulator (such as DMD or LCoS), acquiring the modulated light intensity signal using a single photodetector, and then reconstructing the image using a reconstruction algorithm. However, single-pixel imaging systems lack high-precision hardware-level synchronization between the modulation sequence and the acquisition channel, leading to temporal errors affecting the reconstruction results. Furthermore, the computational load for image reconstruction is high, making it difficult to meet the demands of high frame rate real-time reconstruction.

[0005] Therefore, there is an urgent need for an image reconstruction scheme with good real-time performance. Summary of the Invention

[0006] This invention provides a multi-channel real-time single-pixel image reconstruction system to solve the problem of poor real-time performance in related imaging systems.

[0007] In a first aspect, the present invention provides a multi-channel real-time single-pixel image reconstruction system, comprising: Laser source module, used to generate laser beams with multiple channels; The spatial radio frequency marker optical path module is used to introduce spatial radio frequency markers of different frequencies into the corresponding laser beams in different channels according to the radio frequency marker signal, forming marker beams containing different frequency characteristics and then combining them to form a combined beam that illuminates the target under test. The single-pixel detector module is used to synchronously acquire the modulated light signal formed by the combined beam reflected or transmitted by the target under test through multiple single-pixel detectors, and convert it into an analog electrical signal output. The LabVIEW FPGA control and reconstruction module is used to generate a synchronized RF marker clock and a sampling clock, send RF marker signals to the spatial RF marker optical path module according to the RF marker clock, and acquire the analog electrical signals according to the sampling clock. The module then performs real-time parallel image reconstruction on the analog electrical signals to obtain the reconstruction result.

[0008] In one optional implementation, the LabVIEW FPGA control and reconstruction module includes: A timing control unit is used to simultaneously generate an RF marker clock and a sampling clock via a phase-locked loop; the frequency multiplication and phase relationship of the RF marker clock and the sampling clock remain unchanged.

[0009] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes: The high-speed sampling unit is used to synchronously sample the analog electrical signals output by the multi-channel single-pixel detectors according to the sampling clock via a multiplex analog-to-digital converter, and convert them into multiple digital signals.

[0010] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes: The parallel spectrum demodulation unit is used to perform fast Fourier transform on the multiple digital signals to obtain multiple spectrum data streams, and for each spectrum data stream, extract the amplitude and phase information of the corresponding spatial radio frequency marker frequency window through a multi-parallel digital frequency mask, so as to separate the spectrum data stream within a single clock cycle and obtain the frequency domain signal of the corresponding channel.

[0011] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes: The image reconstruction unit is used to perform image reconstruction processing on the frequency domain signals of each channel using an image reconstruction algorithm to obtain a reconstructed image; An image preprocessing unit is used to preprocess the reconstructed image to obtain a preprocessed reconstructed image; The image processing algorithm unit is used to extract features from the preprocessed reconstructed image to obtain the region of interest image and feature data. The intelligent analysis unit is used to perform intelligent recognition, classification, and decision analysis on the image and feature data of the region of interest.

[0012] In one alternative implementation, the image reconstruction algorithm includes at least one of the following: A fast reconstruction algorithm based on Fourier inversion; Reconstruction algorithms based on compressed sensing; Iterative solution algorithms based on least squares or total variation.

[0013] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes: The data dimensionality conversion unit is used to query the spatial information corresponding to the frequency domain signal according to the preset frequency domain-space mapping lookup table, and to map the one-dimensional scalar to the two-dimensional image storage space in real time for image reconstruction.

[0014] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes: A high-speed oversampling and pipelined integrator is used to perform multiple oversampling of the analog electrical signal within a single modulation cycle and calculate the average sample value for hardware-level noise reduction to obtain a denoised digital signal.

[0015] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes: The buffer unit includes a first buffer and a second buffer; the first buffer and the second buffer are used to alternately perform data writing and recombination operations or data reading and display operations according to the number of image frames.

[0016] In one alternative implementation, the system further includes: The host computer is used to visualize the reconstruction results and configure parameters based on the LabVIEW interface.

[0017] The technical solution provided by this invention may include the following beneficial effects: This invention provides a multi-channel real-time single-pixel image reconstruction system. By setting up a spatial radio frequency marker optical path module, different frequencies of spatial radio frequency markers are introduced into different channels and beamed together for illumination, realizing the physical differentiation and parallel acquisition of multi-channel signals in the frequency domain, significantly improving the utilization rate of optical signals and system throughput. By setting up a LabVIEW FPGA control and reconstruction module, synchronous radio frequency marker clocks and sampling clocks are generated, achieving nanosecond-level deterministic synchronization of spatial light modulation and signal acquisition, eliminating the phase drift problem. Furthermore, this LabVIEW FPGA control and reconstruction module relies on the hardware parallel computing architecture of FPGA to realize pipelined processing of signal acquisition and reconstruction, breaking the speed bottleneck of software reconstruction schemes in related technologies, solving the problem of multi-channel parallel acquisition and real-time processing in single-pixel imaging systems, and achieving low-latency and real-time image reconstruction. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a multi-channel real-time single-pixel image reconstruction system according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the LabVIEW FPGA control and reconstruction module according to an embodiment of the present invention; Figure 3 This is a schematic diagram of an analog electrical signal according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a frequency domain signal according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the reconstruction result according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] With the development of applications such as flow cytometry imaging, ultrafast materials detection, online industrial quality inspection, and intelligent sensing, there are increasing demands on the real-time performance, throughput, and scalability of imaging systems.

[0025] Traditional optical imaging systems mainly rely on CCD (Charge-Coupled Devices) or CMOS (Complementary Metal-Oxide-Semiconductor) array imaging devices to acquire images. The imaging speed is limited by physical bottlenecks such as electronic shutter response, pixel readout speed, frame rate and data throughput. In high-throughput detection tasks, traditional array imaging often needs to make trade-offs between imaging resolution, signal-to-noise ratio and frame rate, which makes it difficult to meet the requirements for real-time, high-quality imaging of high-speed moving or large number of dynamic targets.

[0026] Among related technologies, single-pixel imaging technology is employed. This involves temporally modulating the light field using spatial light modulators (such as DMD and LCoS), acquiring the modulated light intensity signal using a single photodetector, and then reconstructing the image using a reconstruction algorithm. Compared to traditional array imaging methods, single-pixel imaging offers advantages such as a wide detection band range, high sensitivity, low cost, and flexible structure, making it suitable for rapid and highly sensitive imaging of rapidly changing samples or low-light targets. However, single-pixel imaging systems lack high-precision hardware-level synchronization between the modulation sequence and the acquisition channels, leading to temporal errors affecting the reconstruction results. Furthermore, the computational load for image reconstruction is high, making it difficult to meet the demands of high-frame-rate real-time reconstruction. Additionally, the system architecture of single-pixel imaging systems has limited scalability, making it difficult to achieve multi-channel parallel acquisition and high-throughput reconstruction, thus restricting its further application in high-throughput detection and high-speed imaging scenarios.

[0027] Figure 1This is a schematic diagram of a multi-channel real-time single-pixel image reconstruction system according to an embodiment of the present invention. The multi-channel real-time single-pixel image reconstruction system includes a laser source module, a spatial radio frequency marker optical path module, a single-pixel detector module, and a LabVIEW FPGA control and reconstruction module.

[0028] This laser source module is used to generate laser beams with multiple channels.

[0029] This spatial radio frequency marker optical path module is used to introduce spatial radio frequency markers of different frequencies into the corresponding laser beams in different channels according to the radio frequency marker signal, forming marker beams containing different frequency characteristics, and then combining them to form a combined beam that illuminates the target under test.

[0030] This single-pixel detector module is used to synchronously acquire modulated light signals formed by the combined beam reflected or transmitted by the target under test through multiple single-pixel detectors, and convert them into analog electrical signals for output.

[0031] The LabVIEW FPGA control and reconstruction module is used to generate a synchronized RF marker clock and sampling clock, send RF marker signals to the spatial RF marker optical path module according to the RF marker clock, and acquire the analog electrical signal according to the sampling clock. The analog electrical signal is then used for real-time parallel image reconstruction to obtain the reconstruction result.

[0032] This laser source module outputs a stable laser beam, and the number of channels can be set according to requirements, for example, to 3.

[0033] Optionally, the laser source module includes multiple lasers, each corresponding to a different laser band, laser power, and operating time, to achieve multi-band, multi-power beam output. The target under test can be a high-speed moving dynamic sample, and the multi-band, multi-power beam output illuminates the high-speed moving dynamic sample, supporting radio frequency marking.

[0034] This spatial RFID tagging optical path module is used to achieve high-throughput multi-channel acquisition, RFID tagging, and multi-channel differentiation. Based on the RFID tagging signal, the module introduces spatial RFID tags of different frequencies into the laser beams of different optical channels to form corresponding tagging beams. This gives each channel's tagging beam a unique frequency characteristic, resulting in distinguishable frequency characteristics in the optical field. After acquisition, the optical signal forms a multi-peak spectral structure with discriminative characteristics, achieving physical differentiation and temporal identification of different signal channels. The tagging beams from multiple channels are superimposed at the target, allowing simultaneous illumination of the target and enabling parallel excitation of multiple optical channels. The modulated optical signals corresponding to each channel are separated during the detection phase through frequency demodulation, thus achieving high-throughput parallel acquisition. The RFID tagging signal is generated by the LabVIEW FPGA control and reconstruction module, which drives the spatial RFID tagging optical path module with a preset encoding matrix (such as Hadamard, random matrix, Fourier basis matrix, etc.). In this LabVIEW FPGA control and reconstruction module, LabVIEW and an FPGA are deployed. Control is achieved by LabVIEW sending control signals to the FPGA, and image reconstruction is implemented by the FPGA. LabVIEW is a tool with a graphical programming environment, and FPGA (Field-Programmable Gate Array) is a field-programmable gate array. The spatial RF marking optical path module modulates the laser beams of multiple channels using a spatial light modulator based on the RF marking signals. By applying RF marking signals of different frequencies to the spatial light modulator, each diffraction-level laser beam is assigned a unique frequency code (spatial RF mark), achieving synchronous mapping between the spatial and frequency domains. This process converts the optical signal of the laser beam into a dynamic optical field distribution with spatiotemporal coupling characteristics, forming a series of mutually orthogonal spatial RF marking beams for structured light illumination of the target under test. For example, the spatial light modulator can be an acousto-optic deflector (AOD).

[0035] After the target object is illuminated by the combined beam, the modulated optical signal formed by the reflected or transmitted combined beam is received by the single-pixel detector module. This single-pixel detector module contains multiple single-pixel detectors, which can be of different types, corresponding to different response ranges and sensitivities, and can be selected according to application requirements. Each single-pixel detector converts the corresponding modulated optical signal into an analog electrical signal, such as a pulse voltage / current. The simultaneous acquisition of the optical response of the target object can be achieved through multiple single-pixel detectors.

[0036] Optionally, the single-pixel detector can be an avalanche photodiode (APD), a photomultiplier tube (PMT), a photodiode (PD), or other photodetectors with high sensitivity to adapt to different bands and application scenarios, and to meet various application requirements such as high sensitivity, low light, high linearity, and high dynamic range. Different types of detectors can be configured to work in parallel according to experimental needs, supporting more than ten or even dozens of photoelectric signal channels.

[0037] The multi-channel analog signal, formed by the mixing of analog electrical signals acquired by the multi-channel single-pixel detector, is sampled in real time by the LabVIEW FPGA control and reconstruction module, and then reconstructed in real time in parallel to obtain the reconstruction result. Specifically, the LabVIEW FPGA control and reconstruction module generates a synchronized RF marker clock and a sampling clock, and sends RF marker signals to the spatial RF marker optical path module according to the RF marker clock for spatial light modulation. Simultaneously, the LabVIEW FPGA control and reconstruction module also acquires the analog electrical signal according to the sampling clock, thus ensuring that the optical modulation rate and sampling rate are uniformly controlled by the LabVIEW FPGA control and reconstruction module, maintaining consistency and ensuring accurate data correspondence. The FPGA in the LabVIEW FPGA control and reconstruction module features parallel computing, precise hardware timing control, high-speed I / O, and low-latency data paths, enabling deep integration of modulation control, optical signal acquisition, and reconstruction calculation at the hardware level, systematically improving the real-time performance and stability of the single-pixel imaging system. Therefore, this invention builds a system based on the LabVIEW FPGA platform, which can achieve multi-channel synchronous sampling control, high-bandwidth data transmission, pipelined reconstruction calculation and modular expansion capabilities while ensuring development efficiency, thus breaking through the bottlenecks of single-pixel imaging technology in terms of speed, number of channels and real-time calculation in related technologies.

[0038] Therefore, the above system, by setting up a spatial radio frequency marker optical path module, introduces spatial radio frequency markers of different frequencies into different channels and combines them for illumination, realizing the physical differentiation and parallel acquisition of multi-channel signals in the frequency domain, significantly improving the utilization rate of optical signals and system throughput; by setting up a LabVIEW FPGA control and reconstruction module, synchronous radio frequency marker clocks and sampling clocks are generated, realizing nanosecond-level deterministic synchronization of spatial light modulation and signal acquisition, eliminating the phase drift problem; and the LabVIEW FPGA control and reconstruction module, relying on the hardware parallel computing architecture of FPGA, realizes pipelined processing of signal acquisition and reconstruction, breaking the speed bottleneck of software reconstruction schemes in related technologies, solving the problem of multi-channel parallel acquisition and real-time processing in single-pixel imaging systems, and realizing low-latency and real-time image reconstruction.

[0039] In one optional implementation, the LabVIEW FPGA control and reconstruction module includes a timing control unit for simultaneously generating an RF marker clock and a sampling clock via a phase-locked loop (PLL), ensuring that the frequency multiplication and phase relationships between the RF marker clock and the sampling clock remain constant. Specifically, to meet the stringent phase stability requirements of RF marker imaging, the LabVIEW FPGA control and reconstruction module constructs a source-synchronous coherent sampling architecture based on the FPGA global clock tree. The module integrates a Mixed-Mode Clock Manager (MMCM) as the sole time base source and, in conjunction with the FPGA's underlying Phase-Locked Loop (PLL), performs frequency multiplication and division processing on the onboard reference clock to synchronously generate the RF marker clock and the sampling clock, forcing them to maintain a fixed frequency multiplication and phase-locked relationship, thus achieving strict synchronization of key signals at the physical level.

[0040] The above design effectively eliminates the frequency drift and phase asynchrony problems in traditional discrete systems, ensures phase consistency in the RF tag demodulation process, and avoids spectrum leakage and phase jitter caused by asynchronous sampling from the hardware level, fundamentally reducing the interference of clock jitter on the single-pixel frequency domain reconstruction algorithm.

[0041] Furthermore, by configuring the LabVIEW FPGA control and reconstruction module, RF marker clocks and sampling clocks can be generated within the same module, along with the algorithm processing clock for image reconstruction, achieving unified clock management. The system modules employ LVDS (Low Voltage Differential Signaling) or TTL (Transistor-Transistor Logic) level triggering to achieve nanosecond-level synchronization, thus constructing a unified clock driving and trigger synchronization mechanism. At the hardware level, this clock driving and trigger synchronization mechanism can handle RF marker signal driving, sampling triggering, cross-module synchronization signal transmission, buffer scheduling, and image reconstruction algorithm execution, avoiding phase drift caused by modulation and sampling misalignment, and achieving high-speed, low-latency single-pixel image restoration. In addition, each clock frequency can be adaptively adjusted according to application requirements to support stable imaging at different frame rates.

[0042] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes a high-speed sampling unit for isochronously sampling the analog electrical signals output by the multiple single-pixel detectors via a multiplexer analog-to-digital converter (ADC) according to the sampling clock, and converting them into multiple digital signals. The sampling rate of the ADC is synchronized with the RFID tag signal transmission rate, and is uniformly time-controlled by the LabVIEW FPGA control and reconstruction module. Uniform timing control of the ADC by the FPGA achieves synchronous sampling; simultaneously, the sampling clocks and trigger signals of corresponding channels of each ADC are strictly aligned to ensure time consistency and phase synchronization during multi-channel sampling. The multiple digital signals are transmitted to the high-speed logic processing unit inside the FPGA for subsequent image reconstruction processing.

[0043] Optionally, the analog-to-digital converter is a high-speed analog-to-digital converter (ADC). The high-speed sampling unit is a high-speed data acquisition board.

[0044] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes a parallel spectrum demodulation unit, used to perform Fast Fourier Transform (FFT) on the multiple digital signals to obtain multiple spectral data streams. For each spectral data stream, the amplitude and phase information of the corresponding spatial RF marker frequency window are extracted through multiple parallel digital frequency masks to separate the spectral data stream within a single clock cycle, obtaining the frequency domain signal of each channel. Each digital signal corresponds to an independent probe channel, and each digital signal requires a separate Fast Fourier Transform processing unit to perform a Fast Fourier Transform to obtain one spectral data stream. Each spectral data stream contains N spatial RF marker frequency windows, N digital frequency masks, and N frequency domain signals, where N is set according to the FFT size. To address the high aliasing characteristics of multi-channel RFID signals (i.e., multi-channel aliased analog electrical signals with spatial RFID tags) in the time domain, a fully hardware-based parallel frequency domain feature extraction pipeline based on FPGA is constructed. This pipeline includes a Fast Fourier Transform (FFT) core and specific frequency energy extraction logic, enabling hardware demodulation of multi-channel signals without software intervention. Specifically, a parallel spectrum demodulation unit with a parallel spectrum slicing demodulation architecture is built. Unlike traditional serial spectrum scanning, this parallel spectrum demodulation unit is deployed at the output of the FFT pipeline. Multiple parallel digital frequency masks are set for each tiled data path. Each channel of the digital frequency mask is independently configured with a specific spatial RFID tag frequency window. At the instant the corresponding spectrum data stream passes through, each spatial RFID tag frequency window concurrently and synchronously extracts the amplitude and phase information of each key frequency point corresponding to the spectrum data stream within the same system clock cycle, achieving physical-level separation of multi-channel signals within a single clock cycle. The digital frequency mask is essentially a frequency-selective digital filtering mechanism that filters specific frequency indices, retaining only the target frequency component and suppressing irrelevant spectral components. Optionally, the parallel spectrum demodulation unit is a high-speed logic processing device.

[0045] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes an image reconstruction unit, which uses FPGA parallel logic to perform image reconstruction processing on the frequency domain signals of each channel using an image reconstruction algorithm to obtain a reconstructed image. Specifically, the image reconstruction unit employs a hardware-level parallel computing architecture to implement at least one of the following algorithm functions: executing a compressed sensing reconstruction algorithm (CS Reconstruction) or a Fourier transform reconstruction algorithm; custom algorithm modules can be deployed, such as reconstruction models based on least squares (LS) or total variation (TV) minimization algorithms. For multi-channel signals, the LabVIEW FPGA control and reconstruction module utilizes the spatial radio frequency markers of each channel to perform frequency domain demodulation and signal separation, achieving independent reconstruction of images from different channels. Image fusion or multispectral reconstruction can also be performed as needed to obtain a complete high-resolution target image. Because different channels use different spatial radio frequency marker frequencies, the acquired optical signal can form a multi-peak spectral structure with distinct characteristics. Combined with digital bandpass filtering, fast Fourier transform, digital demodulation, and frequency domain energy extraction algorithms implemented within the FPGA, hardware-based separation of multi-channel data is achieved without relying on software computation, thereby further reducing demodulation latency and enhancing channel isolation. Therefore, this image reconstruction unit can directly utilize FPGA logic resources, executing image reconstruction algorithms without relying on software layer parsing, thus avoiding the bottleneck of traditional CPU / PC software. A pipelined parallel execution strategy enables real-time, high-throughput image inversion operations.

[0046] In one alternative implementation, the image reconstruction algorithm includes at least one of the following: A fast reconstruction algorithm based on Fourier inversion; Reconstruction algorithms based on compressed sensing; Iterative solution algorithms based on least squares or total variation.

[0047] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes a data preprocessing unit, which uses algorithms such as median filtering, spatial filtering, brightness equalization, and non-uniformity correction to process the multiple digital signals acquired by the high-speed sampling unit in order to suppress fixed-pattern noise, stripe noise, and uneven illumination.

[0048] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes a data dimension conversion unit, used to query the spatial information corresponding to the frequency domain signal according to a preset frequency-space mapping lookup table (LUT), mapping the one-dimensional scalar to the two-dimensional image storage space in real time, achieving zero-latency dimension reassembly for image reconstruction. Specifically, the data dimension conversion unit, as a key bridge connecting the frequency domain signal and the spatial image, adopts streaming address mapping based on FPGA hardware logic. By pre-setting the frequency-space mapping lookup table in the FPGA on-chip memory, the one-dimensional frequency domain data after Fast Fourier Transform processing can directly query the frequency-space mapping lookup table using the frequency index as the address, outputting the two-dimensional spatial information corresponding to the signal within a single clock cycle.

[0049] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes a high-speed oversampling and pipelined integrator for performing multiple oversampling of the analog electrical signal within a single modulation cycle and calculating the average sample value for hardware-level noise reduction. This significantly improves the signal-to-noise ratio of weak optical signals, resulting in a denoised digital signal. This multiple oversampling is also known as N-fold oversampling. The LabVIEW FPGA control and reconstruction module calculates this average sample value in real time using the FPGA's internal addition logic.

[0050] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes a buffer unit for temporarily storing and streaming the reconstructed images. This buffer unit employs a double-buffered, pipelined, non-blocking queue approach, comprising a first buffer and a second buffer. The first and second buffers are used to alternately perform data writing and reconstruction operations or data reading and display operations according to the number of image frames, ensuring that data acquisition and processing do not wait for each other, achieving continuous and stable data transmission and real-time processing.

[0051] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes an image preprocessing unit. This unit receives the preliminary reconstructed image (including two-dimensional or three-dimensional matrix form) output from the image reconstruction unit and preprocesses the reconstructed image, performing a series of targeted optimization processes to suppress inherent noise, artifacts, and distortion caused by pixel differences during the reconstruction process. This results in a preprocessed reconstructed image, providing high-quality input for subsequent precise reconstruction and advanced analysis modules. The image preprocessing unit is deployed on the LabVIEW FPGA hardware platform and employs a multi-stage parallel pipeline structure to implement algorithm processing, ensuring the real-time performance and stability of the overall image reconstruction process. Since the response characteristics of single-pixel detectors in multiple channels have slight differences, they can easily lead to fixed-pattern noise and uneven brightness in the image. Therefore, deploying various image preprocessing algorithms, such as non-uniformity correction, median filtering, spatial filtering, and contrast enhancement, in the image preprocessing unit effectively eliminates random noise, stripe noise, and uneven illumination while maintaining image edge structure, thereby effectively improving image quality and providing a high signal-to-noise ratio data foundation for subsequent image algorithm deployment units.

[0052] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes an image processing algorithm unit for extracting features from the preprocessed reconstructed image to generate high-quality, structured image data and obtain the region of interest (ROI) image and feature data. This provides reliable input for subsequent intelligent analysis. Specifically, the image processing algorithm unit is preferably deployed on the FPGA side, utilizing its parallel pipeline architecture to achieve high-speed, low-latency hardware-level image processing. The image processing algorithm unit includes, but is not limited to, the following functions: (1) Low-level image processing functions: filtering and denoising, such as median filtering, Gaussian filtering, wavelet denoising, etc.; background suppression and signal-to-noise ratio optimization; automatic exposure correction and contrast enhancement; edge enhancement and image sharpening. (2) Image segmentation and ROI extraction functions: edge detection algorithms, such as Sobel operator and Canny operator; threshold segmentation and adaptive segmentation; region of interest (ROI) detection and cropping; connected component labeling and region filtering. (3) Feature extraction functions: geometric feature extraction, such as area, perimeter, aspect ratio and circularity; shape descriptor extraction, such as Hu moments. Through the above processing, the image processing algorithm unit outputs structured feature data and region of interest images, providing high-quality input for subsequent intelligent analysis and significantly reducing system data transmission bandwidth.

[0053] In one optional implementation, the LabVIEW FPGA control and reconstruction module further includes an intelligent analysis unit for intelligent identification, classification, and decision analysis of the region of interest image and feature data output by the image processing algorithm unit. Specifically, the intelligent analysis unit constructs a cascaded inference architecture based on FPGA-CPU heterogeneous collaboration to realize a hierarchical intelligent processing task allocation mechanism. Among them, the CPU-side processing functions include, but are not limited to: (1) realizing target category discrimination and state analysis by deploying lightweight convolutional neural networks (CNN) and target detection algorithms (such as YOLO series models); (2) outputting target location and bounding box information; and (3) providing statistical analysis and auxiliary decision results. Through the above design, only the region of interest selected by the FPGA is subjected to in-depth analysis, which effectively reduces the data transmission pressure and solves the contradiction between real-time performance and complex algorithms in high-throughput imaging systems.

[0054] Figure 2 This is a schematic diagram of the structure of the LabVIEW FPGA control and reconstruction module according to an embodiment of the present invention, as shown below. Figure 2As shown, this LabVIEW FPGA control and reconstruction module can be implemented entirely in hardware, with the FPGA as its core, ensuring high-speed and low-latency data processing. It is suitable for fields requiring real-time feedback, such as scientific imaging, industrial inspection, and medical imaging. The high-speed sampling unit is responsible for synchronously acquiring light intensity signals from multiple single-pixel detectors, supporting high-throughput input and parallel acquisition across channels to ensure data integrity and timing consistency. Utilizing the I / O parallelism of the FPGA, it supports simultaneous data acquisition from dozens to hundreds of channels, ensuring high-throughput data input efficiency and timing consistency between channels, and outputting multiple parallel digital signals to provide a reliable data foundation for subsequent processing. The data preprocessing unit performs preliminary processing on the raw digital signals acquired by the high-speed sampling unit, such as filtering, denoising, and gain adjustment, thereby improving signal quality and preparing for subsequent transformation and reconstruction. The parallel spectrum demodulation unit performs a fast Fourier transform on the preprocessed time-domain signal, converting the time-domain signal from the time domain to the frequency domain, based on LabVIEW... In a high-throughput, multi-channel real-time single-pixel image reconstruction system using FPGA, frequency domain information is the core of image reconstruction. This parallel spectrum demodulation unit implements hardware-accelerated Fast Fourier Transform (FFT) operations via FPGA, significantly improving the FFT speed and meeting the system's real-time and high-throughput processing requirements. The data dimensionality conversion unit reassembles and maps the one-dimensional frequency domain data or multi-channel parallel data stream after FFT processing into two-dimensional or three-dimensional spatial structure data. This conversion is a crucial step in image generation. By converting one-dimensional frequency domain or multi-channel signals into two-dimensional or three-dimensional data formats suitable for image reconstruction, it achieves a mapping from signal to image space, providing structured input for the image reconstruction unit. To adapt to high-throughput real-time imaging, the image reconstruction unit demodulates and reconstructs the frequency data obtained after Fourier transform, recovering the spatial information of the object based on the information carried by the frequency domain signal and converting it into image data, ensuring the real-time performance and reliability of image generation. The buffer unit employs a dual-port ping-pong storage architecture, utilizing two independent image buffers for each channel to alternately perform "write-read" operations. While the current frame's frequency domain data is rapidly written to the first buffer for reconstruction, the system simultaneously locks the second buffer without waiting to read and display the complete image of the previous frame, thus completely eliminating read-write conflicts and ensuring data integrity and smooth image display during high-speed imaging. The image preprocessing unit receives the preliminary reconstructed image output from the image reconstruction unit and performs preprocessing. The image processing algorithm unit extracts features from the preprocessed reconstructed image to obtain the region of interest (ROI) image and feature data. The intelligent analysis unit performs intelligent recognition, classification, and decision analysis on the ROI image and feature data output from the image processing algorithm unit.

[0055] Figure 3 This is a schematic diagram of an analog electrical signal according to an embodiment of the present invention. Figure 3As shown, the horizontal axis represents time (in seconds), and the vertical axis represents amplitude. The curve reflects the time-domain waveform of the photoelectric signal (analog electrical signal) acquired by the single-pixel detector module. When the spatial RF marker optical path module operates according to the set encoding sequence, the incident laser beam is diffracted by the spatial light modulator to generate diffracted beams with different frequency shifts, forming an RF marker optical field with a specific spatial distribution. The reflection or transmission signals generated by the target object to the marker beams of each channel are captured by the single-pixel detector module, and each RF marker corresponds to an independent time-domain response. Specifically, the LabVIEW FPGA control and reconstruction module outputs multi-frequency RF marker signals to the spatial RF marker optical path module to achieve precise control of the spatial light modulator, so that the marker beams at different spatial positions carry RF frequency markers that are orthogonal to each other, thereby mapping the spatial position information of the target object to the frequency domain. Each set of modulation sequences is not a simple intensity mask, but a spatiotemporal encoded signal carrying specific frequency characteristics, making the time-domain response signal captured by the single-pixel detector module a composite waveform containing full-field spatial information. Therefore, in Figure 3 Multiple sets of periodic pulse signals can be observed, and their occurrence positions and amplitudes reflect the response intensity of the target scene to the light intensity of the marker beams in each channel, realizing frequency domain multiplexing and parallel demodulation of spatial information. Specifically, the original analog electrical signal output by the single-pixel detector module is represented in the time domain as a high-frequency modulated analog carrier carrying spatial information. The occurrence position and amplitude of the pulse signal reflect the response intensity of the target scene to different light field modes. This time-domain response signal contains: high-frequency components, corresponding to spatially modulated high-frequency light field information; low-frequency components, corresponding to background noise and system drift; and mixed signals of spatial radio frequency markers between multiple channels. This time-domain response signal is captured and converted in real time by the high-speed sampling unit of the LabVIEW FPGA control and reconstruction module, and transmitted to the subsequent image reconstruction unit in the form of a digital data stream. Oversampling is performed through high-speed oversampling and pipeline integrator to satisfy the Nyquist sampling theorem, ensuring that the sampling frequency is at least twice the highest frequency of the input signal to avoid spectral aliasing.

[0056] Figure 4 This is a schematic diagram of a frequency domain signal according to an embodiment of the present invention. Figure 4 As shown, it illustrates Figure 3 The frequency domain signal obtained by Fourier transforming the time-domain analog electrical signal in the image shows its spectral distribution, with the horizontal axis representing frequency and the vertical axis representing amplitude. Figure 4Significant spectral peaks can be clearly seen in the target region (e.g., 30-50MHz), which represent the frequency components corresponding to the spatial radio frequency markers of different channels. The amplitude of each spectral peak reflects the energy intensity of the corresponding channel's optical signal. The parallel spectrum demodulation unit, based on the frequency domain data output by the Fast Fourier Transform, extracts the amplitude and phase information within the corresponding spatial radio frequency marker frequency window using a multi-channel parallel digital frequency mask, achieving separation of different signal channels and obtaining multi-channel signal vectors after frequency domain demodulation. Each frequency spatial radio frequency marker corresponds to a set of optical modes in the spatial optical modulator. By extracting the amplitude and correcting the phase of each channel's signal vector after frequency domain demodulation, the intensity value of the optical signal for each channel is obtained. The frequency-demodulated channel signal vectors are input to the image reconstruction unit, where a Fourier inversion-based restoration algorithm is used on the LabVIEW FPGA platform to achieve real-time hardware solution of the sparse signal (the discrete digital signal sampled by the high-speed sampling unit).

[0057] Figure 5 This is a schematic diagram of the reconstruction result according to an embodiment of the present invention. Figure 5 As shown, it illustrates Figure 4 The restored image after the frequency domain signal is processed by the frequency domain demodulation and reconstruction algorithm shows that the image brightness corresponds to the reflected light intensity of the target, and the dark area represents the background or no signal area. It can be clearly seen that the target area shows obvious brightness distribution, indicating that the system has successfully recovered the spatial light intensity information of the measured target and verified the effectiveness of the system in multi-channel synchronous acquisition and high-speed reconstruction.

[0058] In one optional implementation, the system further includes a host computer for visualizing and configuring the reconstruction results using a LabVIEW interface. The digital image data (reconstruction results) output by the LabVIEW FPGA control and reconstruction module is transmitted to the host computer via DMA (Direct Memory Access) or PCIe (Peripheral Component Interconnect Express) bus. The host computer is equipped with human-computer interaction software for a LabVIEW FPGA-based intelligent performance testing platform for multi-channel photodetectors. This software displays images acquired by the photodetector under test and various operating parameters (such as sampling frequency, optical modulation mode, number of channels, modulation sequence, etc.) that need to be monitored during the photodetector testing process, all through a LabVIEW visual interface. Users can change the operating parameters of various modules, including the photodetector under test (single-pixel detector), through the host computer, enabling the photodetector to operate in multiple states and displaying the final performance evaluation results. This allows for real-time image display and frame-level dynamic updates, system status monitoring and operating parameter adjustment, selection and performance comparison of reconstruction algorithms, partitioned display of experimental data images / intelligent algorithm analysis results, and storage and export of experimental data. Optionally, the reconstruction result supports two-dimensional or three-dimensional image output, which can be displayed as grayscale or pseudo-color images.

[0059] In one alternative implementation, the system further includes a power supply module for providing a stable and reliable multi-channel power supply to the various modules in the system (such as the single-pixel detector module and the LabVIEW FPGA control and reconstruction module), and has electromagnetic shielding and overvoltage protection functions.

[0060] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the invention.

Claims

1. A multi-channel real-time single-pixel image reconstruction system, characterized in that, include: Laser source module, used to generate laser beams with multiple channels; The spatial radio frequency marker optical path module is used to introduce spatial radio frequency markers of different frequencies into the corresponding laser beams in different channels according to the radio frequency marker signal, forming marker beams containing different frequency characteristics and then combining them to form a combined beam that illuminates the target under test. The single-pixel detector module is used to synchronously acquire the modulated light signal formed by the combined beam reflected or transmitted by the target under test through multiple single-pixel detectors, and convert it into an analog electrical signal output. The LabVIEW FPGA control and reconstruction module is used to generate a synchronized RF marker clock and sampling clock, send RF marker signals to the spatial RF marker optical path module according to the RF marker clock, and acquire the analog electrical signals according to the sampling clock. The module then performs real-time parallel image reconstruction on the analog electrical signals to obtain the reconstruction result. The LabVIEW FPGA control and reconstruction module includes: The timing control unit is based on a source-synchronous coherent sampling architecture constructed from an FPGA global clock tree. It integrates a hybrid-mode clock management unit as the sole time base source, which is used to simultaneously generate the RF marker clock and the sampling clock through a phase-locked loop. The frequency multiplication and phase relationship of the RF marker clock and the sampling clock remain unchanged. A high-speed sampling unit is used to synchronously sample the analog electrical signals output by the multi-channel single-pixel detectors according to the sampling clock via a multiplex analog-to-digital converter, and convert them into multiple digital signals. The parallel spectrum demodulation unit is used to perform fast Fourier transform on the multiple digital signals to obtain multiple spectrum data streams, and for each spectrum data stream, extract the amplitude and phase information of the corresponding spatial radio frequency marker frequency window through a multi-parallel digital frequency mask, so as to separate the spectrum data stream within a single clock cycle and obtain the frequency domain signal of the corresponding channel. The data dimensionality conversion unit is used to query the spatial information corresponding to the frequency domain signal according to the preset frequency domain-space mapping lookup table, and to map the one-dimensional scalar to the two-dimensional image storage space in real time for image reconstruction.

2. The system according to claim 1, characterized in that, The LabVIEW FPGA control and reconstruction module also includes: The image reconstruction unit is used to perform image reconstruction processing on the frequency domain signals of each channel using an image reconstruction algorithm to obtain a reconstructed image; An image preprocessing unit is used to preprocess the reconstructed image to obtain a preprocessed reconstructed image; The image processing algorithm unit is used to extract features from the preprocessed reconstructed image to obtain the region of interest image and feature data. The intelligent analysis unit is used to perform intelligent recognition, classification, and decision analysis on the image and feature data of the region of interest.

3. The system according to claim 2, characterized in that, The image reconstruction algorithm includes at least one of the following: A fast reconstruction algorithm based on Fourier inversion; Reconstruction algorithms based on compressed sensing; Iterative solution algorithms based on least squares or total variation.

4. The system according to claim 1, characterized in that, The LabVIEW FPGA control and reconstruction module also includes: A high-speed oversampling and pipelined integrator is used to perform multiple oversampling of the analog electrical signal within a single modulation cycle and calculate the average sample value for hardware-level noise reduction to obtain a denoised digital signal.

5. The system according to claim 1, characterized in that, The LabVIEW FPGA control and reconstruction module also includes: The buffer unit includes a first buffer and a second buffer; the first buffer and the second buffer are used to alternately perform data writing and recombination operations or data reading and display operations according to the number of image frames.

6. The system according to any one of claims 1 to 5, characterized in that, The system also includes: The host computer is used to visualize the reconstruction results and configure parameters based on the LabVIEW interface.

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