Chip-based ray tracing processing method, processor, device and medium

Abstract

The present disclosure provides a chip-based light ray tracing processing method, a processor, a device and a medium, and relates to the technical field of chips. The method comprises the following steps: determining task processing logic matched with a chip and used for implementing a light ray tracing task; and encapsulating the task processing logic as a light ray tracing interface, wherein the light ray tracing interface is used for creating a light ray tracing task executed by the chip. The method simplifies the process of light ray tracing processing.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, specifically to a chip-based ray tracing processing method, processor, device, and medium. Background Technology

[0002] Ray tracing is a rendering computation task that involves emitting rays from a camera into a scene and calculating pixel colors to generate realistic images by tracing the paths of these rays as they intersect, reflect, and refract. Current ray tracing tasks are primarily applicable to the graphics domain, while performing ray tracing on a chip requires configuring various application programming interfaces (APIs) needed for the rendering pipeline, making the configuration process quite complex. Summary of the Invention

[0003] This disclosure presents a chip-based ray tracing processing method, processor, device, and medium.

[0004] In a first aspect, embodiments of this disclosure provide a chip-based ray tracing processing method, the method comprising: determining task processing logic matched with the chip for implementing a ray tracing task; and encapsulating the task processing logic into a ray tracing interface, wherein the ray tracing interface is used to create a ray tracing task executed by the chip.

[0005] In some embodiments, the ray tracing interface includes at least one of a context interface, an acceleration structure interface, and a shader interface.

[0006] In some embodiments, the task processing logic includes shading processing logic. Encapsulating the task processing logic into a ray tracing interface includes: layering the shading processing logic to obtain multiple shader interfaces.

[0007] In some embodiments, the various shader interfaces include a module interface, a program group interface, and a pipeline interface.

[0008] In some embodiments, the module interface includes a module creation interface for creating a module that includes multiple shaders, which are described in the form of an intermediate representation.

[0009] In some embodiments, the task processing logic includes task startup logic, which is encapsulated as a ray tracing interface, including: creating a shader binding table; and encapsulating the task startup logic as a task startup interface, which is used to start a ray tracing task based on the shader binding table.

[0010] In some embodiments, the method further includes: configuring the ray tracing interface as a ray tracing dynamic library for the chip; configuring the header file of the ray tracing dynamic library for the chip; wherein the header file of the ray tracing dynamic library is used to record the definition code that calls the ray tracing interface.

[0011] Secondly, this disclosure also provides a chip-based ray tracing processing method, the method comprising: receiving a ray tracing task, wherein the ray tracing task is created by any embodiment of the first aspect above; and calling a built-in function to execute the ray tracing task, wherein the built-in function includes at least one of a ray emission function, an accelerated structure traversal function, an intersection information acquisition function, and a shader stage control function.

[0012] Thirdly, embodiments of this disclosure also provide a processor for performing the methods of any one of the first or second aspects described above.

[0013] Fourthly, embodiments of this disclosure provide an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the method described in either the first or second aspect.

[0014] Fifthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that enable a computer to perform the method as described in either the first or second aspect.

[0015] The chip-based ray tracing processing method provided in this disclosure ensures complete compatibility between the task data flow and the chip processing path by determining the task processing logic that matches the chip for implementing the ray tracing task. This avoids hardware-software mismatch issues such as cache invalidation, idle computing power, and wasted transmission bandwidth. Furthermore, the task processing logic is encapsulated into a ray tracing interface, which has a simple structure and clear calling logic, significantly reducing the integration and usage costs of the chip. Simultaneously, by integrating the task processing logic for implementing the ray tracing task into the ray tracing interface, this disclosure achieves a unified ray tracing task creation process, reducing the interaction complexity and coordination overhead between multiple modules, and improving task creation efficiency and reliability. Attached Figure Description

[0016] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating a chip-based ray tracing processing method provided in this disclosure embodiment; Figure 2 A schematic diagram illustrating the invocation of a ray tracing interface according to an embodiment of this disclosure; Figure 3 A flowchart illustrating yet another ray tracing processing method provided in this disclosure embodiment; Figure 4 A structural block diagram of a processor provided in an embodiment of this disclosure; Figure 5 A structural block diagram of a system architecture provided in this disclosure embodiment; Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0017] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0018] Currently, ray tracing is mainly applied to the graphics field. For example, ray tracing can be applied to DirectX Raytracing (DXR, a set of API standards and runtime frameworks for graphics or multimedia).

[0019] DXR includes five types of shaders: Raygen shader, Closest hit shader, Any hit shader, Intersection shader, and Callable shader. These shaders together form the Ray Tracing Pipeline. In addition, DXR includes a Bounding Volume Hierarchy (BVH, also known as an acceleration structure), which contains two structures: Bottom-level Acceleration Structure (BLAS) and Top-level Acceleration Structure (TLAS).

[0020] Based on the above DXR, the overall process of performing ray tracing is as follows:

[0021] First, the Ray Tracing Unit (RTU) checks each triangle primitive in the scene along the direction of the ray. After traversing the process, it finds a geometric primitive that has been hit by the ray, such as a triangle primitive (TriangleGeometry / procedural Geometry).

[0022] If the geometry hit by the ray is a triangle and opaque, the RTU will automatically determine whether the geometry and the ray intersect. If they do not intersect, the RTU will continue searching for the next geometry. If they do intersect, the RTU will determine if the geometry is the nearest geometry. If it is not the nearest geometry, the RTU will skip it and continue searching for the next geometry. If it is the nearest geometry, the RTU will update the maximum distance the ray can reach (Tmax) and mark the current state as the nearest geometry.

[0023] If the geometry primitive hit by the ray is a triangle and not an opaque, the RTU will automatically determine whether the geometry primitive and the ray intersect. If they do not intersect, the RTU will continue searching for the next primitive. If they intersect, the RTU will determine if it is the nearest geometry primitive. Furthermore, if the geometry primitive is not the nearest primitive, the RTU will skip it and continue searching for the next primitive. If the geometry primitive is the nearest primitive, but the Any hit shader is NULL, the RTU will update Tmax and mark the current state as the nearest. If the geometry primitive is the nearest primitive and the Any hit shader is not NULL, the RTU will call the Any hit shader to determine if it was actually hit. If the geometry primitive was indeed hit by the ray, the current state will be marked as the nearest primitive, and Tmax will be updated. If the geometry primitive was not hit by the ray, the RTU will skip it and continue searching for the next primitive.

[0024] Based on the above steps, each primitive is searched sequentially until the entire acceleration structure has been traversed. The closest hit shader is called for the nearest primitive. If no primitive is found, the miss shader is called.

[0025] However, DXR is part of DX12, and using DXR requires configuring various DX12 APIs, including the APIs required for the rendering pipeline, and the configuration process is quite cumbersome. For example, it requires setting APIs related to creating command lists (Cmdlist), setting APIs for various queues, configuring APIs related to state objects, configuring APIs related to various shaders, configuring APIs related to the global root signature, and configuring APIs related to the local root signature, etc., before ray tracing can actually be performed.

[0026] Therefore, it is clear that DXR is actually tied to DirectX and is not compatible with other graphics processing units (GPUs), which is detrimental to the development of ray tracing technology.

[0027] Based on this, embodiments of this disclosure provide a simplified ray tracing interface, which simplifies the rendering pipeline while increasing the controllability of autonomous ray tracing. This ray tracing interface is an API designed based on the chip provided in these embodiments, allowing free access to the chip's APIs. This avoids introducing a separate graphics pipeline and only requires adding a few APIs that support ray tracing.

[0028] To accommodate the current ray tracing core (RT core) of this chip, the method disclosed herein does not alter the underlying architecture of ray tracing; that is, the BVH (Browser Vector Height) within the chip remains two layers, consisting of a lower-level acceleration structure and a upper-level acceleration structure. The algorithm for traversing rays within the BVH also remains unchanged. Furthermore, the shaders also remain the same: Raygenshader, Miss shader, Closest hit shader, Any hit shader, Intersection shader, and Callable shader.

[0029] This disclosure presents a chip-based ray tracing processing method.

[0030] Figure 1This flowchart illustrates a chip-based ray tracing processing method provided in this embodiment of the disclosure. This method can be applied to the host side of a system architecture. The system architecture includes a host unit and a chip. The host unit can be a Central Processing Unit (CPU), and the chip can be a Graphics Processing Unit (GPU). The host unit is generally used to create ray tracing tasks, while the chip is used to execute the specific ray tracing tasks. This method can be applied to the host unit.

[0031] like Figure 1 As shown, the method specifically includes the following steps: Step 101: Determine the task processing logic that matches the chip and is used to implement the ray tracing task.

[0032] Specifically, a ray tracing task is a standardized rendering task that integrates acceleration architecture, shaders, rendering parameters, and scheduling instructions, and can be executed by the chip hardware. It is used to perform ray traversal and intersection calculations and global illumination shading calculations. This task is only encapsulated and processed by the host machine; all core ray tracing calculations are handled by the chip hardware units. That is, the ray tracing task is executed by the chip; the host machine does not participate in core ray tracing calculations such as ray intersection, shading, and illumination integration. It is only responsible for matching the task processing logic of the ray tracing task with the hardware units within the chip, ensuring complete compatibility between the task data flow and the hardware processing path, and avoiding hardware-software mismatch issues such as cache invalidation, idle computing power, and wasted transmission bandwidth. The hardware units within the chip that process the ray tracing task may include ray tracing cores, computing units, acceleration units, etc., which are not limited in this disclosure.

[0033] Step 102: Encapsulate the task processing logic into a ray tracing interface.

[0034] The ray tracing interface is used to create ray tracing tasks that are executed by the chip.

[0035] Specifically, the entire task processing logic for ray tracing tasks adapted to this chip is lightweighted and encapsulated into a dedicated API for ray tracing tasks, precisely adapting to the specific needs of these tasks. The ray tracing interface integrates the entire task processing logic for creating ray tracing tasks, covering key aspects such as resource configuration, acceleration structure construction, rendering pipeline creation, and shader configuration. The host machine can create ray tracing tasks by calling this interface, avoiding external logic interference and improving the stability and reusability of the ray tracing task execution process. Furthermore, this disclosure uses the ray tracing interface as a unified relay scheduling layer to directly distribute ray tracing tasks to the chip's hardware computing units, and calls the chip's dedicated hardware computing units, such as the ray tracing core (RT Core) and acceleration structure units, to complete hardware acceleration execution. This achieves efficient integration between software logic and hardware acceleration units, ultimately achieving high-performance, highly stable ray tracing calculations.

[0036] The embodiments provided in this disclosure ensure complete compatibility between the task data flow and the chip processing path by determining task processing logic that matches the chip for implementing ray tracing tasks, thus avoiding hardware-software mismatch issues such as cache invalidation, idle computing power, and wasted transmission bandwidth. Furthermore, this task processing logic is encapsulated into a ray tracing interface, which has a simple structure and clear calling logic, significantly reducing the integration and usage costs of the chip. Simultaneously, this disclosure achieves a unified ray tracing task creation process by integrating the task processing logic for implementing ray tracing tasks into the ray tracing interface, reducing the interaction complexity and coordination overhead between multiple modules, and improving task creation efficiency and reliability.

[0037] In some embodiments, the ray tracing interface includes at least one of a context interface, an acceleration structure interface, and a shader interface.

[0038] Specifically, firstly, the host side encapsulates the context interface. The context interface is formed by encapsulating a context object based on ray tracing-specific resources and configurations, and this context interface is bound to the context object within the chip. Specifically, the context interface is obtained from the context object within the chip, which refers to the chip-related resource configuration information. This resource configuration constitutes a common context environment within the chip, including basic environment setup such as device initialization, memory resource allocation, and resource scheduling. The context interface is used to centrally manage all environmental dependencies, resource constraints, and core configurations related to ray tracing, allowing all ray tracing interfaces to execute based on a unified context, avoiding resource chaos and configuration inconsistencies.

[0039] The context interface includes memory and some ray tracing related properties, such as the maximum number of primitives contained in each geometry, the recursion depth, etc.

[0040] In some embodiments, the context interface may include a context creation interface (e.g., the PhotonDeviceContextCreate interface), which is formed by encapsulating the context creation logic in the task processing logic. By calling the context creation interface, a ray tracing context can be created, which includes ray tracing-specific resources and configurations.

[0041] In some embodiments, the context interface may also include a context destruction interface (e.g., the PhotonDeviceContextDestroy interface). This context destruction interface is an encapsulation of the destruction logic for destroying the ray tracing context in the task processing logic. By calling this context destruction interface, the ray tracing context and its corresponding memory can be destroyed.

[0042] In some embodiments, the context interface may further include a context retrieval interface (e.g., the PhotonDeviceContextGetProperty interface). This context retrieval interface is formed by encapsulating the parameter retrieval logic of the ray tracing context in the task processing logic. By calling this context retrieval interface, ray tracing-related parameters can be obtained.

[0043] After the host side encapsulates the context interface, it further encapsulates the acceleration structure interface based on the context interface.

[0044] An acceleration structure interface refers to the encapsulation of logic related to acceleration structures in task processing logic, which is used to process acceleration structures.

[0045] In some embodiments, the acceleration structure interface includes a memory computation sub-interface (e.g., the PhotonAccelComputeMemoryUsage interface). This memory computation sub-interface encapsulates the computational logic for memory computation. It is used to calculate the memory size required to construct an acceleration structure and can call muMemoryAlloc (a memory allocation function) to allocate the memory needed for the acceleration structure. This required memory is used temporarily during the construction of the acceleration structure.

[0046] In some embodiments, the acceleration structure interface may further include a creation sub-interface (e.g., the PhotonAccelBuild interface). This creation sub-interface encapsulates the creation logic for creating the acceleration structure and is used to call a preset function to construct the acceleration structure after allocating the required memory.

[0047] In some embodiments, the acceleration structure interface further includes at least one of the following: compression sub-interface, copy sub-interface, information retrieval sub-interface, and conversion sub-interface.

[0048] The compression sub-interface (e.g., the PhotonAccelCompact interface) encapsulates the compression logic of the compression acceleration structure. This compression sub-interface is used to compress the acceleration structure, thereby improving the performance when traversing the acceleration structure.

[0049] This copy sub-interface (e.g., the PhotonAccelRelocate interface) encapsulates the copying logic of the accelerated structure. This copying interface is used to copy the accelerated structure. Specifically, copying the accelerated structure means copying a portion of the accelerated structure to a new accelerated structure.

[0050] This information call sub-interface (e.g., the PhotonAccelEmitProperty interface) encapsulates the logic for obtaining information related to the acceleration structure. Specifically, after the acceleration structure is built, it's necessary to determine its size, compressed size, or other relevant information. This information can be obtained by scheduling this information call sub-interface.

[0051] This conversion sub-interface (for example, the PhotonConvertPointerToTraversableHandle interface) is formed by encapsulating address translation logic. This conversion sub-interface is used to convert an address into a pointer to a BLAS or a pointer to a TLAS.

[0052] The calculation of the memory size required to construct an acceleration structure and the steps of creating the acceleration structure are implemented by the host side calling the corresponding acceleration structure interface; while the steps of compression, copying and information acquisition of the acceleration structure are executed by the processing unit in the chip by scheduling the corresponding acceleration structure interface.

[0053] The shader interface encapsulates the shading logic related to shaders. It refers to the interface associated with shaders in a ray tracing task. Ray tracing involves various types of shaders, and each geometry can specify its own shader. Therefore, a ray tracing pipeline often contains multiple shaders, and the ray tracing interface also includes a series of shader interfaces to support ray tracing operations.

[0054] The embodiments provided in this disclosure, by encapsulating at least one of the context interface, acceleration structure interface and shader interface, can encapsulate various processes for creating ray tracing tasks into a simple and easy-to-use interface, meet different needs, achieve lightweight design, and ultimately form a dedicated ray tracing interface with specific functions, strong adaptability and efficient calling.

[0055] In some embodiments, the task processing logic includes shading processing logic. Encapsulating the task processing logic into a ray tracing interface includes: layering the shading processing logic to obtain multiple shader interfaces.

[0056] Specifically, ray tracing tasks involve various types of shaders, and each geometric object can have its own shader specified. Therefore, a ray tracing pipeline often contains multiple types of shaders. A module can contain multiple executable programs, which are the smallest executable units of a single shader. Each executable program corresponds to an independent ray tracing shader logic, and each executable program is the basic unit of shader input.

[0057] Furthermore, in the execution flow of a ray tracing task, execution is carried out in units of program groups, where a program group can contain multiple executable programs. However, in a ray tracing task, the input data is in the form of modules, and each module also contains multiple executable programs. The program group specifies the entry function for each module, and selects the corresponding executable program based on the entry function of that module to form the program group.

[0058] Therefore, it can be seen that the shading processing logic of the ray tracing task has the characteristic of layered execution. Based on this shading processing logic, this disclosure can be encapsulated in layers to obtain a variety of shader interfaces.

[0059] The embodiments provided in this disclosure, by layering and encapsulating the shader processing logic, achieve clear interface division and well-defined functional boundaries, facilitating independent development, debugging, and replacement of various shader logics, and reducing the development and maintenance costs of ray tracing programs. Simultaneously, the layered shader interface matches the chip hardware's layered execution mechanism, allowing various shader tasks to be independently distributed at the hardware scheduling granularity, improving the parallel execution efficiency of the chip's ray tracing hardware units. The layered and encapsulated shader interface possesses good versatility, allowing different shader interfaces to be combined as needed to adapt to various ray tracing rendering scenarios without modifying the underlying hardware adaptation logic, thus expanding the applicability of the solution. The layered interface isolates the upper-layer application logic from the underlying chip hardware details; the upper layer only needs to call the corresponding shader interface to complete the shader logic configuration, without needing to concern itself with the chip hardware execution specifications, lowering the development and adaptation threshold.

[0060] In some embodiments, the various shader interfaces include a module interface, a program group interface, and a pipeline interface.

[0061] Specifically, the module interface is formed by encapsulating the module processing logic related to the shader module. This module interface refers to the interface related to the module corresponding to the shader.

[0062] In some embodiments, the module interface includes at least one of a module creation interface and a module destruction interface.

[0063] Specifically, the module creation interface (e.g., the PhotonModuleCreate interface) encapsulates the module creation logic, allowing the creation of modules containing multiple shaders. The module destruction interface (e.g., the PhotonModuleDestroy interface) encapsulates the module destruction logic, allowing the destruction of modules.

[0064] The program group interface is formed by encapsulating the program group processing logic related to the program group. The program group interface refers to the interface for processing related to the executable program corresponding to the shader.

[0065] In some embodiments, the program group interface includes at least one of a program group creation sub-interface, a program group destruction sub-interface, and a program group information retrieval sub-interface.

[0066] Specifically, the program group creation sub-interface (such as the PhotonProgramGroupCreate interface) encapsulates the logic for creating program groups. This sub-interface is used to create a collection of program groups, which includes multiple program groups, each corresponding to a different program group type. This program group type is consistent with the shader type. For example, program group types include Raygen, hit, Miss, etc.

[0067] The program group destruction sub-interface (such as the PhotonProgramGroupDestroy interface) is formed by encapsulating the program group destruction logic. This program group destruction sub-interface is used to destroy a program group.

[0068] The program group information retrieval sub-interface (such as the PhotonProgramGroupGetStackSize interface) is formed by encapsulating the program group information retrieval logic. This program group information retrieval sub-interface is used to obtain relevant information about the program group, which can be the stack information required by the program group.

[0069] The pipeline interface is a wrapper around the pipeline creation logic for creating ray tracing pipelines. This pipeline interface is used to create ray tracing pipelines.

[0070] Specifically, the pipeline is a crucial parameter in ray tracing, containing all the shaders needed to perform a single ray tracing operation. Since different geometries require different types of shaders, a pipeline contains multiple shader groups. Therefore, when creating a pipeline, it's necessary to determine the number of shader groups required and the pointers corresponding to each group.

[0071] In some embodiments, the pipeline interface may include at least one of a pipeline creation sub-interface and a pipeline destruction sub-interface.

[0072] The pipeline creation sub-interface (such as the PhotonPipelineCreate interface) encapsulates the pipeline creation logic. This pipeline creation sub-interface is used to create pipelines, and it specifies the number of program groups required to create a pipeline and a pointer to each program group.

[0073] The pipeline destruction sub-interface (such as the PhotonPipelineDestroy interface) is formed by encapsulating the pipeline destruction logic. This pipeline destruction sub-interface is used to destroy pipelines.

[0074] The embodiments provided in this disclosure divide the shader interface into a multi-level shader interface, including module interfaces, program group interfaces, and pipeline interfaces, fully corresponding to the layered shading processing logic. Each interface has a clear boundary of responsibility, achieving modular decomposition of the shading process. This facilitates independent development, debugging, and updating of the corresponding stage of shading logic. The layered interfaces progressively complete the construction of shader modules, the combination of shading programs, and the overall configuration of the ray tracing pipeline. Adapting to the layered execution logic of the chip hardware, it can orderly distribute shading tasks according to hardware scheduling rules, improving the execution efficiency of the chip hardware. Multiple types of shader interfaces cooperate with each other, allowing for flexible combination and matching of different shading modules and programs to adapt to various ray tracing rendering needs without modifying the underlying task processing logic, thus improving the reusability and scene adaptability of the solution. The layered interfaces isolate the upper-layer application from the underlying hardware adaptation details. Developers can call the corresponding interface as needed to complete the shading configuration without needing to be aware of the underlying hardware resources or task granularity adaptation logic, reducing the difficulty of ray tracing program development.

[0075] In some embodiments, the module interface includes a module creation interface for creating a module that includes multiple shaders, which are described in the form of an intermediate representation.

[0076] Specifically, a module can contain multiple executable programs. A program is the smallest executable unit of a single shader, and each program corresponds to an independent ray tracing shader logic. Each program takes an intermediate representation (IR) as input, which is the basic unit of shader input. This intermediate representation can be directly recognized by the chip's hardware computing unit, and one intermediate representation can correspond to one shader binary module.

[0077] The embodiments provided in this disclosure encapsulate multiple shader sets through a unified module creation interface, enabling the creation of a group of associated shader resources at once. This simplifies the upper-layer calling process and reduces the overhead of creating shaders individually multiple times. Furthermore, in this disclosure, shaders are described using an intermediate representation, without being bound to a specific hardware instruction set. Hardware adaptation logic is uniformly converged at the lower layer, eliminating the need to modify the upper-layer shader description when replacing chips of different specifications, thus improving the cross-hardware reusability of shaders.

[0078] In some embodiments, the task processing logic includes task startup logic, which is encapsulated as a ray tracing interface, including: creating a shader binding table; and encapsulating the task startup logic as a task startup interface, which is used to start a ray tracing task based on the shader binding table.

[0079] Specifically, each geometric object in the acceleration structure needs to have a designated shader. When a ray hits the corresponding geometric object, the corresponding shader is selected for execution. Therefore, this disclosure also requires binding the shaders in the ray tracing pipeline with the geometric objects in the acceleration structure, forming a shader binding table (SBT). Each element in the SBT is called a record. The record includes information such as the shader identifier and the texture buffer bound to that shader. Thus, the SBT contains the information needed to execute each shader. The SBT can include the type, number, address of the shader, and the size of each record. For an SBT, only one raygen shader and one expectation shader are needed, while there can be multiple miss shaders. The selection of the miss shaders can be specified by the user based on requirements. The intersection shader, any hit shader, and closest hit shader together form a hit group. The number of hit groups is equal to the number of geometric objects. Which hit group is called is determined by which geometric object the ray hits.

[0080] On the host side, the shader binding table, pipeline, and pipeline parameters are encapsulated into a task launch interface (such as LaunchRaytracing). The task launch interface is formed by encapsulating the startup logic for launching a ray tracing task.

[0081] Specifically, after the shader binding table is created, the address where the shader binding table is located is sent to the ray tracing pipeline. The host then encapsulates the shader binding table, pipeline, and pipeline parameters into a task startup interface, which the host then calls to start the ray tracing task.

[0082] In some embodiments, the task launch interface (e.g., the PhotonLaunch interface) includes a ray tracing pipeline (e.g., PhotonPipeline), pipeline parameters (pipelineParams), a shader binding table (e.g., PhotonShaderBindingTable), and the number of rays in three dimensions (width, height, and depth). The ray tracing pipeline is used to perform photon tracing or ray tracing tasks; pipeline parameters refer to the parameter structure passed to the pipeline execution function, used to configure the ray tracing dispatch parameters; the shader binding table is used to establish the relationship between the ray tracing pipeline and the acceleration structure; the number of rays in three dimensions defines the dimensions of ray tracing dispatch, i.e., the mesh size of the emitted rays; where width refers to the number of ray tracing threads dispatched along the X-axis, typically equal to the pixel width of the rendering target; height refers to the number of ray tracing threads dispatched along the Y-axis, typically equal to the pixel height of the rendering target; and depth refers to the number of ray tracing threads dispatched along the Z-axis, typically 1 for screen space rendering, but can also be other values ​​depending on actual needs.

[0083] This disclosure allows a single ray tracing operation to be performed based on the ray tracing rendering pipeline, pipeline parameters, shader binding tables, and the three-dimensional number (length, width, height) of rays.

[0084] In some embodiments, the method further includes: configuring the ray tracing interface as a ray tracing dynamic library for the chip; configuring the header file of the ray tracing dynamic library for the chip; wherein the header file of the ray tracing dynamic library is used to record the definition code that calls the ray tracing interface.

[0085] The ray tracing dynamic library only provides interfaces related to ray tracing. Additionally, the host-side component includes the chip's dynamic library, which is derived from the chip's dynamic library.

[0086] Specifically, Figure 2 This is a schematic diagram illustrating the invocation of a ray tracing interface provided in an embodiment of this disclosure.

[0087] like Figure 2As shown, this example uses the chip as an example of a Meta-computing Unified System Architecture (MUSA). The host side includes a MUSA dynamic library 201, a MUSA runtime library 202, a ray tracing dynamic library 211, and header files 221 for the ray tracing dynamic library. MUSA dynamic library 201 is a native dynamic library of the MUSA system, used to provide the MUSA API, i.e., the native API within the MUSA system. Furthermore, based on the MUSA API, a ray tracing dynamic library 211 related to ray tracing tasks can be obtained. This ray tracing dynamic library 211 provides the ray tracing API. Specifically, this ray tracing dynamic library 211 only exposes the ray tracing API, enabling the host-side ray tracing interface API caller 203 to create ray tracing tasks by calling the corresponding ray tracing API.

[0088] Furthermore, header file 221 of the ray tracing dynamic library contains the relevant definitions of the ray tracing API. Therefore, in the process of calling the ray tracing API based on ray tracing dynamic library 211 to create a ray tracing task, it is also necessary to combine the relevant definitions in header file 221 of the ray tracing dynamic library to complete the call to the ray tracing API. The header file 221 of the ray tracing dynamic library can be a C++ file or other types of files; this disclosure does not limit this. In addition, the ray tracing dynamic library also provides ray tracing-related startup functions. In the process of calling the ray tracing API, the corresponding startup functions are actually called through the ray tracing API to create the ray tracing task.

[0089] Furthermore, since the ray tracing dynamic library only contains ray tracing-related functions (i.e., the default startup functions), and the use of this ray tracing dynamic library requires the relevant APIs of MUSA or MUSA runtime library 202 to complete other functions, such as memory copying, this disclosure also requires the MUSA runtime API provided by MUSA runtime library 202 to call the corresponding functions (such as the memory copy-related functions) to assist the ray tracing API in performing the preprocessing configuration work for ray tracing tasks.

[0090] The embodiments provided in this disclosure configure a ray tracing dynamic library and corresponding header files for the chip based on the ray tracing interface. The dynamic library internally embeds the interface implementation of task processing logic that matches the chip, and the header files uniformly expose standardized calling declarations. This unified software and hardware interface specification effectively avoids rendering anomalies and hardware execution errors caused by inconsistencies in underlying adaptation logic. This disclosure allows for the creation and execution of ray tracing tasks simply by calling the corresponding interface in the ray tracing dynamic library according to the header file declarations, shielding the details of the chip hardware architecture and lowering the hardware adaptation threshold for developers. Furthermore, the dynamic library can be independently iterated and updated. When optimizing the chip hardware execution adaptation logic, there is no need to modify the upper-layer application code; only the corresponding dynamic library file needs to be replaced to complete performance optimization and hardware compatibility upgrades, improving program maintenance and version iteration efficiency.

[0091] Secondly, this disclosure also provides a chip-based ray tracing processing method that can be applied to the chip.

[0092] Figure 3 A flowchart of yet another chip-based ray tracing processing method provided in this disclosure.

[0093] like Figure 3 As shown, the method specifically includes the following steps: Step 301: Receive ray tracing task.

[0094] The ray tracing task is created by any of the embodiments in the first aspect described above.

[0095] Step 302: Call the built-in function to perform the ray tracing task.

[0096] The built-in functions include at least one of the following: ray emission function, accelerated structure traversal function, intersection information acquisition function, and shader stage control function.

[0097] Specifically, after a ray tracing task is created on the host side according to any of the above embodiments, the ray tracing task is sent to the chip.

[0098] Since the shaders of this chip typically do not contain functions related to ray tracing, the execution function for performing ray tracing operations can be pre-defined within the chip. In this way, when the chip performs a ray tracing task, it can directly call this execution function to perform the ray tracing task.

[0099] The ray emission function is used to emit rays, specifying the tracing range, acceleration structure, shader procedures, etc. This ray emission function can be a tracing function (such as the `photonTrace` function), used to emit a ray in a ray tracing task for ray tracing and other tasks.

[0100] The accelerated structure traversal function is used to traverse the accelerated structure and detect the intersection relationship between light rays and geometric objects.

[0101] The intersection information acquisition function is used to obtain the geometric information of rays / intersection detection. This function can include a ray origin acquisition function to obtain the origin information of rays. This ray origin acquisition function can include the `photonGetWorldRayOrigin` function to obtain the origin coordinates of rays below the Top-Level Acceleration Structure (TLAS) space; and the `photonGetObjectRayOrigin` function to obtain the origin coordinates of rays below the Bottom-Level Acceleration Structure (BLAS) space. Rays below TLAS space refer to world space rays, used to traverse all object instances in the scene; rays below BLAS space refer to local model space rays, used only for geometric intersection calculations within a single model.

[0102] The intersection information acquisition function may also include a ray direction acquisition function to obtain ray direction information. This ray direction acquisition function may include the `photonGetWorldRayDirection` function to obtain the ray direction in TLAS space, and the `photonGetObjectRayDirection` function to obtain the ray direction in BLAS space.

[0103] The intersection information acquisition function may also include a function for obtaining ray extremum information, used to obtain the maximum and minimum values ​​of the rays. This function may include a photonGetRayTmin function to obtain the minimum ray value, and a photonGetRayTmax function to obtain the maximum ray value.

[0104] Shader phase control functions are used to control the shader execution logic during the hit / miss phase, including functions for obtaining information about hit geometry, such as obtaining at least one of the following: vertex information, centroid coordinate information, address information, primitive type information, index information, and transformation matrix information of the hit geometry.

[0105] The shader phase control functions may include: `photonGetTriangleVertexData` to obtain vertex information of the hit triangle; `photonGetTriangleBarycentrics` to obtain the centroid coordinates of the hit triangle; `photonGetLaunchDimensions` to obtain the dimension coordinates of the current thread; `photonGetSbtDataPointer` to obtain the SBT address of the currently hit triangle; `photonContinuationCall` to execute the callable shader; `photonGetPrimitiveType` to obtain the primitive type of the hit; `photonTerminateRay` to terminate the current ray; `photonGetPrimitiveIndex` to obtain the primitive index of the hit; `photonGetInstanceIndex` to obtain the instance index of the hit; `photonGetObjectToWorldTransformMatrix` to obtain the transformation matrix from BLAS space to TLAS space; and `photonGetWorldToObjectTransformMatrix` to obtain the transformation matrix from TLAS space to BLAS space.

[0106] This embodiment of the disclosure receives a ray tracing task generated by the host and calls a built-in function to execute the ray tracing task, thereby realizing a complete ray tracing task and improving the execution efficiency of the ray tracing task.

[0107] The following examples illustrate the specific processing procedure for ray tracing tasks.

[0108] First, the host machine encapsulates a context interface (such as the Photon context interface). Then, based on this context interface, the host machine encapsulates an acceleration structure interface (such as the Photon BVH build interface) and various shader interfaces (including modules, program groups, and pipeline interfaces). Further, the host machine binds the shaders in the acceleration structure interface to the shaders in the pipeline interfaces, obtaining a shader binding table (STB). Finally, the host machine encapsulates the shader binding table, pipeline, and pipeline parameters into a launch raytracing interface. The context interface, acceleration structure interface, shader interfaces, and launch raytracing interface together constitute the ray tracing interface.

[0109] Furthermore, the host side configures the ray tracing interface as a ray tracing dynamic library 211, and also configures the header file 221 for this ray tracing dynamic library 211. Additionally, the host side includes a runtime library and a device-side dynamic library. For example, the device-side library can be based on the MUSA architecture; correspondingly, the runtime library can be the MUSA runtime library 202, and the device-side dynamic library can be the MUSA dynamic library 201. The ray tracing interface encapsulated on the host side is based on this MUSA dynamic library 201, and only provides ray tracing-related APIs within the ray tracing interface.

[0110] Combination Figure 2 The ray tracing API caller 203 can be the host machine. During the execution of a ray tracing task, the host machine first initializes the device context and computation flow using the MUSA API provided by the MUSA dynamic library 201, and transfers scene, texture, and other data from the host memory to the device's video memory using the memory copy interface in the MUSA API. Subsequently, the host machine calls the ray tracing API exported by the ray tracing dynamic library 211 to create a ray tracing context and bind existing MUSA device resources, as well as build the BVH acceleration structure, bind shader programs, and configure rendering parameters. Then, it calls the pipeline interface in the ray tracing API to submit batch ray tracing tasks. Internally, the ray tracing dynamic library 211 automatically calls the underlying MUSA runtime library 202 to send the computation instructions and video memory data corresponding to the ray tracing task to the MUSA device runtime. The MUSA device hardware completes the core ray tracing tasks, such as ray traversal, intersection testing, and shading calculations, by calling built-in functions related to the core ray tracing tasks. After the ray tracing task is completed, the rendering results are returned from the device's video memory to the host memory through the memory copy interface in the MUSA API, completing the entire ray tracing task execution process.

[0111] Furthermore, this disclosure also provides a processor.

[0112] Figure 4 This is a structural block diagram of a processor provided in an embodiment of the present disclosure. The processor may be a central processing unit.

[0113] like Figure 4 As shown, the processor includes a determination module 401 and a packaging module 402. The determination module 401 is used to determine the task processing logic that matches the chip and is used to implement the ray tracing task; the packaging module 402 is used to encapsulate the task processing logic into a ray tracing interface, wherein the ray tracing interface is used to create a ray tracing task executed by the chip.

[0114] In some embodiments, the ray tracing interface includes at least one of a context interface, an acceleration structure interface, and a shader interface.

[0115] In some embodiments, the task processing logic includes shading processing logic, and the encapsulation module 402 is specifically used to encapsulate the shading processing logic in layers to obtain multiple shader interfaces.

[0116] In some embodiments, the various shader interfaces include a module interface, a program group interface, and a pipeline interface.

[0117] In some embodiments, the module interface includes a module creation interface for creating a module that includes multiple shaders, which are described in the form of an intermediate representation.

[0118] In some embodiments, the task processing logic includes task startup logic, and the encapsulation module 402 is specifically used to: create a shader binding table; encapsulate the task startup logic into a task startup interface, which is used to start a ray tracing task based on the shader binding table.

[0119] In some embodiments, the processor further includes a configuration module for configuring the ray tracing interface as a ray tracing dynamic library for the chip; configuring the header file of the ray tracing dynamic library for the chip; wherein the header file of the ray tracing dynamic library is used to record the definition code that calls the ray tracing interface.

[0120] In some embodiments, the processor may also be a graphics processor. The processor may include a receiving module and an execution module. The receiving module is used to receive a ray tracing task, wherein the ray tracing task is created by any embodiment of the first aspect described above. The execution module is used to call built-in functions to execute the ray tracing task, wherein the built-in functions include at least one of a ray emission function, an accelerated structure traversal function, an intersection information acquisition function, and a shader stage control function.

[0121] The specific execution flow of the processor provided in this embodiment corresponds to the method flow provided above, and will not be repeated here.

[0122] Furthermore, this disclosure also provides a system architecture.

[0123] Figure 5 This is a structural block diagram of a system architecture provided in an embodiment of the present disclosure.

[0124] like Figure 5 As shown, the system architecture includes a host unit 501 and a chip 502. The host unit 501 can be a central processing unit, and the chip 502 is used to perform ray tracing tasks.

[0125] In some embodiments, the chip 502 may include an image processor.

[0126] According to embodiments of the present disclosure, the present disclosure also provides an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the ray tracing processing method described in any of the above embodiments when executed.

[0127] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. For example... Figure 6 As shown, the electronic device 600 of this embodiment includes a processor 601 and a memory 602; wherein, the memory 602 is used to store computer execution instructions; the processor 601 is used to execute the computer execution instructions stored in the memory to implement the various steps performed by the electronic device in the above embodiment. For details, please refer to the relevant descriptions in the foregoing method embodiments. For example, the electronic device 600 can be a general-purpose processor, a graphics processing device, a neural network computing device, or a graph neural network computing device.

[0128] In some embodiments, the memory 602 can be either standalone or integrated with the processor 601.

[0129] When the memory 602 is set up independently, the electronic device also includes a bus 603 for connecting the memory 602 and the processor 601.

[0130] It should be understood that the processor 601 described above can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0131] The memory 602 may include high-speed RAM memory, and may also include non-volatile memory NVM, such as at least one disk storage device, and may also be a USB flash drive, portable hard drive, read-only memory, disk or optical disc, etc.

[0132] Bus 603 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0133] This disclosure also provides a computer storage medium storing computer execution instructions, which, when executed by a processor, implement the steps of the ray tracing processing method in any of the above method embodiments.

[0134] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the ray tracing processing method according to any of the above embodiments.

[0135] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0136] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.

[0137] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The aforementioned modular unit can be implemented in hardware or in a combination of hardware and software functional units.

[0138] The integrated modules described above, implemented as software functional modules, can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute partial steps of the methods in the various embodiments of this application.

[0139] The aforementioned storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0140] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in application-specific integrated circuits (ASICs). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0141] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0142] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0143] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0144] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip-based ray tracing processing method, characterized in that, The method includes: Determine the task processing logic that matches the hardware unit of the chip for implementing the ray tracing task; The task processing logic is encapsulated as a ray tracing interface, and the ray tracing task is sent to the hardware unit of the chip through the ray tracing interface. The hardware unit of the chip is then scheduled to execute ray tracing calculation tasks including ray intersection, shading, and illumination integration. The ray tracing interface includes a shader interface.

2. The method according to claim 1, characterized in that, The ray tracing interface also includes at least one of a context interface and an acceleration structure interface.

3. The method according to claim 1, characterized in that, The task processing logic includes shading processing logic, and the encapsulation of the task processing logic into a ray tracing interface includes: The shading logic is layered and encapsulated to obtain multiple shader interfaces.

4. The method according to claim 3, characterized in that, The various shader interfaces include module interfaces, program group interfaces, and pipeline interfaces.

5. The method according to claim 4, characterized in that, The module interface includes a module creation interface, which is used to create a module that includes multiple shaders, which are described in the form of an intermediate representation.

6. The method according to claim 1, characterized in that, The task processing logic includes task initiation logic, which is encapsulated as a ray tracing interface, including: Create a shader binding table; The task startup logic is encapsulated into a task startup interface, which is used to start a ray tracing task based on the shader binding table.

7. The method according to claim 1, characterized in that, The method further includes: Configure the ray tracing interface as the ray tracing dynamic library of the chip; Configure the header file for the ray tracing dynamic library for the chip; wherein the header file of the ray tracing dynamic library is used to record the definition code that calls the ray tracing interface.

8. A chip-based ray tracing processing method, characterized in that, The method includes: Receive a ray tracing task, wherein the ray tracing task is created by the method according to any one of claims 1-7; The ray tracing task is executed by calling built-in functions, wherein the built-in functions include at least one of the following: ray emission function, accelerated structure traversal function, intersection information acquisition function, and shader stage control function.

9. A processor, characterized in that, The processor is used to perform the method as described in any one of claims 1-7 or to perform the method as described in claim 8.

10. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7 or the method of claim 8.

11. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method of any one of claims 1-7 or to perform the method of claim 8.

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