Display panel water ripple elimination method, device, equipment and storage medium

Abstract

The application discloses a display panel water ripples elimination method and device, equipment and storage medium, relate to display technical field, the disclosed method is through monitoring the beat frequency generated between the switching frequency of the driving power supply and the load current frequency, using whether the beat frequency is frequency coupling with the refresh rate of the display panel to judge that there is water ripple on the display panel, and when there is water ripple on the display panel, the switching frequency is actively adjusted to remove the frequency coupling, which avoids the defects that the switching frequency of the backlight source cannot eliminate the water ripple caused by the driving power supply ripple in the prior art, and even may introduce new flicker, eliminates the water ripple generated by the driving power supply, and effectively improves the display quality.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to methods, apparatus, devices and storage media for eliminating water ripples on display panels. Background Technology

[0002] In LCD panels, sometimes slow-moving horizontal bright and dark stripes appear on the screen, resembling ripples on the surface of water, and are called water ripples.

[0003] One common method to improve water ripples is to use pulse width modulation dimming in the backlight driving circuit. By changing the switching frequency of the backlight source, the backlight source is made to avoid the panel refresh rate and integer multiples of the panel refresh rate. This raises the low-frequency difference between the switching frequency of the backlight source and the panel refresh rate to a range that is not easily perceived by the human eye, thereby avoiding the formation of visible water ripples due to periodic fluctuations in screen brightness caused by this low-frequency difference.

[0004] However, the aforementioned solution of adjusting the switching frequency of the backlight source assumes that the main source of the ripple effect is the interaction between the switching frequency of the backlight source and the panel refresh rate. In reality, the power supply driving the display panel itself can also cause ripple effects. In this case, adjusting the switching frequency of the backlight source may not only fail to eliminate the ripple effect but may also introduce new flickering. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, device, and storage medium for eliminating water ripples on a display panel, aiming to solve the technical problem that adjusting the switching frequency of the backlight source not only fails to eliminate water ripples but may also introduce new flickering.

[0006] To achieve the above objectives, this application proposes a method for eliminating water ripples on a display panel, the method comprising: Obtain the switching frequency of the drive power supply and the load current frequency at the output terminal of the drive power supply; The beat frequency is determined based on the switching frequency and the load current frequency; When there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, it is determined that there are water ripples on the display panel; The water ripples are eliminated by adjusting the switching frequency to decouple the frequency coupling.

[0007] In one embodiment, the step of determining the beat frequency based on the switching frequency and the load current frequency includes: Among the harmonic components of the load current frequency, the harmonic component with the smallest frequency difference from the switching frequency is identified as the coupling harmonic. The beat frequency is determined based on the frequency difference between the switching frequency and the coupled harmonic.

[0008] In one embodiment, before the step of determining the presence of water ripples on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, the method further includes: Among the harmonic components of the refresh rate of the display panel, the harmonic component with the smallest frequency difference from the beat frequency is determined as the reference harmonic. Determine whether the frequency difference between the beat frequency and the reference harmonic is less than a preset difference value; If the frequency difference between the beat frequency and the reference harmonic is less than a preset difference, it is determined that there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel.

[0009] In one embodiment, the step of eliminating the water ripples by adjusting the switching frequency to decouple the frequency coupling includes: The adjustment amount of the switching frequency is determined based on the frequency difference between the beat frequency and the reference harmonic. When the beat frequency is greater than the reference harmonic, the switching frequency is reduced by the adjustment amount to release the frequency coupling relationship and eliminate the water ripples; When the beat frequency is less than the reference harmonic, the switching frequency is increased by the adjustment amount to release the frequency coupling relationship and eliminate the water ripples.

[0010] In one embodiment, after the step of decoupling the frequency coupling relationship by adjusting the switching frequency when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, the method further includes: Obtain at least one peak phase of the load current; Determine the start time of pixel charging and the duration of charging; The charging window corresponding to the pixel is determined based on the charging start time and the charging duration. Determine whether at least one of the peak phases is within the charging window; If at least one of the peak phases is within the charging window, the peak phase within the charging window will be shifted out of the charging window by adjusting the switching phase of the drive power supply.

[0011] In one embodiment, the step of shifting the peak phase within the charging window out of the charging window by adjusting the switching phase of the drive power supply if at least one of the peak phases is within the charging window includes: If at least one of the peak phases is within the charging window, the phase offset is determined based on the time difference between the peak phase within the charging window and the boundary of the charging window. Convert the phase offset into a phase delay value; The phase delay value is written into the phase control register of the drive power supply. The phase control register outputs a corresponding switching waveform based on the phase delay value, so that the switching phase of the drive power supply generates an offset corresponding to the phase offset. The shift in the switching phase causes the peak phase within the charging window to shift out of the charging window.

[0012] Furthermore, to achieve the above objectives, this application also proposes a display panel water ripple elimination device, the device comprising: The data acquisition module is used to acquire the switching frequency of the drive power supply and the load current frequency at the output terminal of the drive power supply. A beat frequency determination module is used to determine the beat frequency based on the switching frequency and the load current frequency; The judgment module is used to determine that there are water ripples on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel; A water ripple elimination module is used to eliminate the water ripples by adjusting the switching frequency to decouple the frequency coupling relationship.

[0013] In addition, to achieve the above objectives, this application also proposes a display panel water ripple elimination device, the device including at least a controller, the controller including a memory, a processor and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the display panel water ripple elimination method as described above.

[0014] In one embodiment, the display panel ripple elimination device further includes: a timing controller, an adjustable frequency power management chip, a parameter detection module, and an external crystal oscillator; The timing controller is connected to the controller, the adjustable frequency power management chip and the external crystal oscillator respectively. The adjustable frequency power management chip is connected to the controller and the parameter detection module respectively. The parameter detection module is connected to the timing controller and the controller respectively.

[0015] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the display panel water ripple elimination method described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: The display panel ripple elimination method provided in this application obtains the switching frequency of the driving power supply and the load current frequency at the output terminal of the driving power supply; determines the beat frequency based on the switching frequency and the load current frequency; determines the presence of ripples on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel; and eliminates the ripples by adjusting the switching frequency to decouple the frequency coupling relationship. This application monitors the beat frequency generated between the switching frequency of the driving power supply and the load current frequency, and uses whether the beat frequency is frequency-coupled with the refresh rate of the display panel to determine the presence of ripples on the display panel. When ripples are present on the display panel, the switching frequency is actively adjusted to decouple the frequency coupling. This avoids the shortcomings of existing technologies where adjusting the backlight switching frequency cannot eliminate ripples caused by driving power supply ripples, and may even introduce new flickering. It eliminates ripples caused by the driving power supply, effectively improving display quality. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the internal module structure of the display panel water ripple elimination device of this application; Figure 2 This is a flowchart illustrating the first embodiment of the method for eliminating water ripples on a display panel according to this application; Figure 3 This is the circuit schematic of the current detection circuit in this application; Figure 4 This is a flowchart illustrating the second embodiment of the method for eliminating water ripples on a display panel according to this application; Figure 5 This is a flowchart illustrating the third embodiment of the method for eliminating water ripples on a display panel according to this application; Figure 6 This is a schematic diagram of the module structure of the display panel water ripple elimination device of this application; Figure 7 This is a schematic diagram of the structure of the display panel water ripple elimination device of this application.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] The main solution of this application embodiment is: to obtain the switching frequency of the driving power supply and the load current frequency at the output terminal of the driving power supply; to determine the beat frequency based on the switching frequency and the load current frequency; to determine that there is a water ripple on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel; and to eliminate the water ripple by adjusting the switching frequency to remove the frequency coupling relationship.

[0024] Existing technologies for adjusting the backlight switching frequency assume that the main source of ripples is the interaction between the backlight switching frequency and the panel refresh rate. In reality, the display panel's driving power supply itself can also cause ripples. In this case, adjusting the backlight switching frequency may not only fail to eliminate the ripples but may also introduce new flickering.

[0025] This application provides a solution that monitors the beat frequency generated between the switching frequency of the drive power supply and the load current frequency, and uses whether the beat frequency is frequency-coupled with the refresh rate of the display panel to determine whether there are water ripples on the display panel. When water ripples are present on the display panel, the switching frequency is actively adjusted to decouple the frequency. This avoids the defects in the prior art where adjusting the backlight switching frequency cannot eliminate water ripples caused by drive power supply ripples, and may even introduce new flickering. This eliminates water ripples caused by the drive power supply and effectively improves display quality.

[0026] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a display panel ripple removal device, a display driver board, a monitor, etc., or an electronic device or display panel ripple removal device capable of the above functions. The following description uses a display panel ripple removal device as an example to illustrate this embodiment and the subsequent embodiments.

[0027] Understandably, referring to Figure 1 , Figure 1 This is a schematic diagram of the internal module structure of the display panel ripple elimination device of this application. The display panel ripple elimination device includes: a controller 10, a timing controller 20, an adjustable frequency power management chip 30, a parameter detection module 40, and an external crystal oscillator 50.

[0028] The timing controller 20 is connected to the controller 10, the adjustable frequency power management chip 30 and the external crystal oscillator 50 respectively. The adjustable frequency power management chip 30 is connected to the controller 10 and the parameter detection module 40 respectively. The parameter detection module 40 is connected to the timing controller 20 and the controller 10 respectively.

[0029] Based on this, the embodiments of this application provide a method, referring to Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the method for eliminating water ripples on a display panel according to this application.

[0030] In this embodiment, the method for eliminating water ripples on the display panel includes steps S10 to S40: Step S10: Obtain the switching frequency of the drive power supply and the load current frequency at the output terminal of the drive power supply.

[0031] It should be noted that the driving power supply can be the power supply in the display panel that provides analog voltage for charging the pixels. In this embodiment, the driving power supply is described using the adjustable frequency power management chip 30, but this does not limit the solution.

[0032] Understandably, the switching frequency can be the periodic frequency of the switching transistors inside the drive power supply (i.e., the frequency-adjustable power management chip 30) turning on and off.

[0033] It should be noted that the load current frequency can be the periodic variation frequency of the load current at the output of the drive power supply. The load current can be the instantaneous current supplied by the output of the drive power supply (i.e., the frequency-adjustable power management chip 30) to the pixel charging circuit.

[0034] In a specific implementation, the controller 10 reads the set value or actual detection value of the switching frequency from the adjustable frequency power management chip 30 through the internal bus; at the same time, the controller 10 can acquire the current waveform at the output terminal of the adjustable frequency power management chip 30 through the parameter detection module 40, and extract the periodic change frequency of the load current from the current waveform as the load current frequency.

[0035] It should be understood that the parameter detection module 40 can be a circuit module used to detect the power switch node signal and the output current waveform. The parameter detection module 40 includes at least a current detection circuit, see reference... Figure 3 , Figure 3 This is the circuit schematic of the current detection circuit in this application. Figure 3 In the circuit, the current detection circuit includes: sampling resistor Rsen, differential amplifier 41, filter 42, and hysteresis comparator 43.

[0036] The first terminal of the differential amplifier 41 is connected to the first power supply VDD, and the second terminal of the differential amplifier is grounded. The differential amplifier 41 includes at least: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first comparator U1; the filter 42 includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, and a second comparator U2; the hysteresis comparator 43 includes: a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a third comparator U3.

[0037] The first terminal of the sampling resistor Rsen is connected to the second power supply AVDD, and the second terminal of the sampling resistor Rsen can be connected to the source drive circuit. The first terminal of the first resistor R1 is connected to the first terminal of the sampling resistor Rsen. The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the non-inverting input terminal of the first comparator U1. The second terminal of the second resistor R2 is grounded. The inverting input terminal of the first comparator U1 is connected to the first terminals of the third resistor R3 and the fourth resistor R4. The second terminal of the third resistor R3 is connected to the second terminal of the sampling resistor Rsen, and the second terminal of the fourth resistor R4 is connected to the output terminal of the first comparator U1.

[0038] The first end of the fifth resistor R5 is connected to the output of the first comparator U1. The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, the first end of the first capacitor C1, and the first end of the second capacitor C2. The second end of the sixth resistor R6 is grounded. The second end of the first capacitor C1 is connected to the first end of the ninth resistor R9 and the inverting input of the second comparator U2. The second end of the second capacitor C2 and the second end of the ninth resistor R9 are both connected to the output of the second comparator U2. The non-inverting input of the second comparator U2 is connected to the first end of the seventh resistor R7. The second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8. The second end of the eighth resistor R8 is connected to the logic power supply VDD.

[0039] The first end of the tenth resistor R10 is connected to the output of the second comparator U2, the second end of the tenth resistor R10 is connected to the inverting input of the third comparator U3, the non-inverting input of the third comparator U3 is connected to the first end of the eleventh resistor R11 and the first end of the twelfth resistor R12, the second end of the eleventh resistor R11 is grounded, and the second end of the twelfth resistor R12 is connected to the output of the third comparator U3 and the timing controller 20.

[0040] Wherein, the first power supply VDD can be a DC power supply that provides the operating voltage for the digital circuit, and the second power supply AVDD is the aforementioned driving power supply.

[0041] The process of acquiring the load current frequency based on the above current detection circuit is as follows: When the source drive circuit draws current from the drive power supply, the load current flows through the sampling resistor Rsen, generating a small differential voltage across the sampling resistor Rsen. This differential voltage reflects the instantaneous change in the load current. The first comparator U1 and its external resistors (i.e., the first to fourth resistors R1 to R4) form a differential amplifier structure to amplify the differential voltage. The output signal generated at the output terminal of the first comparator U1 can be a voltage signal that is proportional to and amplified in amplitude with respect to the load current wave.

[0042] In filter 42, the high-frequency component of the output signal of differential amplifier 41 is coupled to the inverting input of second comparator U2 through the first capacitor C1. The high-frequency component of the output signal of second comparator U2 is then fed back to the inverting input through the second capacitor C2, forming high-frequency negative feedback and suppressing the gain of the high-frequency component. The low-frequency component of the output signal of differential amplifier 41 has reduced coupling efficiency due to the large capacitive reactance of the first capacitor C1. Simultaneously, the ninth resistor R9 provides a low-frequency negative feedback path for the inverting input, further suppressing the gain of the low-frequency component. The fundamental component of the load current in the output signal of differential amplifier 41 has high coupling efficiency through the first capacitor C1, and the high-frequency feedback of the second capacitor C2 and the low-frequency feedback of the ninth resistor R9 have little impact on the gain of this fundamental component. Therefore, this fundamental component obtains a high gain at the output of second comparator U2. After the above filtering process, the output of second comparator U2 receives a signal dominated by the fundamental component of the load current, with high-frequency noise and low-frequency fluctuations effectively attenuated. This signal is then sent to hysteresis comparator 43.

[0043] Hysteresis comparator 43 receives the analog signal output from filter 42, which is primarily composed of the fundamental component of the load current. In hysteresis comparator 43, the eleventh resistor R11 and the twelfth resistor R12 form a positive feedback voltage divider network, providing a reference voltage to the non-inverting input of the third comparator U3 that varies with the output level of the third comparator U3. When the third comparator U3 outputs a high level, the reference voltage at its non-inverting input is a higher value; when it outputs a low level, the reference voltage is a lower value. When the voltage of the analog signal output from filter 42 is lower than the lower reference voltage, the third comparator U3 outputs a high level; when the voltage of the analog signal output from filter 42 is higher than the higher reference voltage, the third comparator U3 outputs a low level. The difference between the higher and lower reference voltage values ​​is determined by the resistance values ​​of the eleventh resistor R11, the twelfth resistor R12, and the amplitude of the high-level output of the third comparator U3.

[0044] Since the higher reference voltage value is not equal to the lower reference voltage value, when the analog signal output by filter 42 fluctuates slightly near the transition point due to residual noise, if the voltage fluctuation amplitude of the analog signal output by filter 42 does not exceed the difference between the higher and lower reference voltage values, the output state of the third comparator U3 will not change, thereby suppressing the output jitter caused by residual noise in the analog signal output by filter 42.

[0045] The output of the third comparator U3 generates a digital square wave signal. The frequency of this digital square wave signal is equal to the fundamental frequency of the load current. The rising edge of this digital square wave signal relative to the frame synchronization signal corresponds to the phase information of the fundamental component in the load current waveform. The output of the third comparator U3 is connected to the timing controller 20. The timing controller 20 obtains the load current frequency and the peak phase of the load current by performing frequency counting and phase latching on the digital square wave signal. The peak phase of the load current can be the time offset of the moment when the maximum current value occurs in each cycle of the load current waveform relative to the frame synchronization signal or the line synchronization signal.

[0046] Step S20: Determine the beat frequency based on the switching frequency and the load current frequency.

[0047] It should be noted that beat frequency can be a low-frequency difference frequency component generated by the interaction between the switching frequency and the load current frequency.

[0048] In a specific implementation, the controller 10 compares the integer multiples of the load current frequency with the switching frequency, determines the integer multiple of the switching frequency that is closest to it, and then calculates the frequency difference between the switching frequency and the integer multiple of the frequency. The absolute value of the frequency difference is taken as the beat frequency.

[0049] Step S30: When there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, it is determined that there are water ripples on the display panel.

[0050] It should be noted that the refresh rate of the display panel can be the number of times the display panel updates the image per second, for example, 60 Hz or 120 Hz.

[0051] Understandably, frequency coupling can be a synchronization lock between the beat frequency and the refresh rate of the display panel. Under frequency coupling, the brightness fluctuations caused by the beat frequency can maintain a fixed phase synchronization with the frame-by-frame refresh rhythm of the display panel. The phase of the brightness fluctuations within each frame almost repeats, thus producing a stable rolling water ripple in the human eye.

[0052] It should be noted that water ripples can be slow-moving horizontal stripes of light and dark that appear on the display panel.

[0053] In a specific implementation, the controller 10 can multiply the reference frequency generated by a local oscillator according to the refresh rate of the display panel to generate a reference signal synchronized with the refresh rate. Then, the controller 10 inputs the beat frequency signal and the reference signal to a frequency comparison circuit, which outputs the frequency difference between the two signals. If the absolute value of the frequency difference is less than a preset capture threshold, the frequency coupling relationship between the beat frequency and the refresh rate is confirmed, indicating that ripples appear on the display panel. If the frequency difference is greater than or equal to the capture threshold, the frequency coupling relationship is confirmed to be non-existent, and no ripples appear on the display panel.

[0054] Step S40: The frequency coupling relationship is released by adjusting the switching frequency to eliminate the water ripples.

[0055] In its implementation, the controller 10 can gradually change the switching frequency of the adjustable frequency power management chip 30 according to a preset adjustment step size. After each change in the switching frequency, the current beat frequency is recalculated, and it is re-evaluated whether the frequency coupling relationship between the beat frequency and the refresh rate of the display panel still exists. If the changed switching frequency causes the frequency coupling relationship between the beat frequency and the refresh rate to disappear, the adjustment is stopped, the switching frequency is locked as the operating frequency, and the water ripples are eliminated. If the adjustment process touches the lower or upper limit of the operating frequency allowed by the adjustable frequency power management chip 30, and the frequency coupling relationship is still not resolved, the controller 10 changes the sign of the adjustment step size (i.e., from increasing to decreasing, or from decreasing to increasing) and continues the adjustment until the frequency coupling relationship is resolved.

[0056] This embodiment obtains the switching frequency of the driving power supply and the load current frequency at the output terminal of the driving power supply; determines the beat frequency based on the switching frequency and the load current frequency; when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, it determines that there are water ripples on the display panel; and eliminates the water ripples by adjusting the switching frequency to decouple the frequency coupling relationship. This embodiment monitors the beat frequency generated between the switching frequency of the driving power supply and the load current frequency, and uses whether the beat frequency is frequency coupled with the refresh rate of the display panel to determine whether there are water ripples on the display panel. When water ripples are present on the display panel, the switching frequency is actively adjusted to decouple the frequency coupling. This avoids the defects of the prior art where adjusting the backlight switching frequency cannot eliminate water ripples caused by driving power supply ripples, and may even introduce new flickering. It eliminates water ripples caused by the driving power supply and effectively improves display quality.

[0057] Based on the first embodiment of this application, a second embodiment of this application is proposed. In the second embodiment, content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 4, Figure 4 This is a flowchart illustrating the second embodiment of the method for eliminating water ripples on a display panel according to this application.

[0058] In this embodiment, step S20 includes steps S201 to S202: Step S201: Among the harmonic components of the load current frequency, determine the harmonic component with the smallest frequency difference from the switching frequency as the coupling harmonic.

[0059] It should be noted that harmonic components can be other periodic frequency components in the load current waveform besides the fundamental frequency, and can be integer multiples of the load current frequency, such as one times the load current frequency, two times the load current frequency, three times the load current frequency, etc.

[0060] Understandably, the coupled harmonic can be the frequency component of the fundamental frequency or a certain harmonic component of the load current that is closest in the frequency domain to the switching frequency of the adjustable power management chip 30 and is most likely to interact with it.

[0061] In a specific implementation, the controller 10 sequentially calculates the harmonic components of the switching frequency and the load current frequency, that is, the frequency difference between the load current frequency of one times the load current frequency, two times the load current frequency, three times the load current frequency, and up to the load current frequency of the preset highest multiple. The minimum value is found from all the calculated frequency differences, and the harmonic component corresponding to the minimum value is the coupled harmonic.

[0062] Step S202: Determine the beat frequency based on the frequency difference between the switching frequency and the coupled harmonic.

[0063] In a specific implementation, the controller 10 can subtract the frequency of the coupled harmonic from the value of the switching frequency, obtain the frequency difference, and then take the absolute value to obtain the beat frequency.

[0064] In one feasible implementation, the harmonic order can be calculated using the following preset harmonic order formula:

[0065] In the formula, Indicates the harmonic order. This indicates the switching frequency of the adjustable power management chip 30. Indicates the frequency of the load current. This indicates the rounding operation.

[0066] It should be noted that the harmonic order can be an integer multiple of the load current frequency, used to identify each harmonic component of the load current frequency, such as the fundamental frequency corresponding to the harmonic order 1, and the second harmonic corresponding to the harmonic order 2.

[0067] Understandably, by using a preset harmonic order formula, the switching frequency can be divided by the load current frequency, and the resulting value can be rounded to the nearest integer multiple of the load current frequency, i.e., the harmonic order. Multiplying this harmonic order by the load current frequency yields the coupled harmonics. For example, if =600.1kHz, =100kHz, then Divide by The value equals 6.001. After rounding to the nearest integer, we get 6. Multiplying 6 by 100kHz gives us the coupling harmonic closest to the switching frequency, which is 600kHz.

[0068] Furthermore, the beat frequency can be calculated using the following preset beat frequency formula:

[0069] In the formula, Indicates beat frequency. Indicates the harmonic order. This indicates the switching frequency of the adjustable power management chip 30. Indicates the frequency of the load current.

[0070] It should be noted that in the above preset beat frequency formula, This can represent the coupled harmonics. By using a preset beat frequency formula, the frequency difference between the switching frequency and the coupled harmonics can be calculated, and the absolute value can be taken to obtain the beat frequency.

[0071] In this embodiment, steps S31 to S33 are included before step S30: Step S31: Among the harmonic components of the refresh rate of the display panel, determine the harmonic component with the smallest frequency difference from the beat frequency as the reference harmonic.

[0072] It should be noted that the harmonic components of the display panel's refresh rate can be integer multiples of the refresh rate, such as one-time refresh rate, two-time refresh rate, three-time refresh rate, etc.

[0073] Understandably, the reference harmonic can be the harmonic frequency among the harmonic components of the refresh rate that is closest to the beat frequency in the frequency domain and is most likely to undergo frequency coupling.

[0074] In a specific implementation, the controller 10 can obtain the refresh rate of the display panel from the timing controller 20, and sequentially calculate the harmonic components of the beat frequency and the refresh rate, that is, the frequency difference between the refresh rate of one time, two times, three times and up to the preset highest multiple of the refresh rate, and find the minimum value from the calculated frequency difference. The harmonic component corresponding to the minimum value is the reference harmonic.

[0075] It should be noted that the timing controller 20 can be a chip used to generate reference timing signals for the display panel.

[0076] Step S32: Determine whether the frequency difference between the beat frequency and the reference harmonic is less than a preset difference value.

[0077] It should be noted that the preset difference can be a pre-set difference threshold, used to determine whether the beat frequency and the reference harmonic are close enough to form a frequency coupling relationship. For example, the preset difference can be set to five percent of the display panel's refresh rate, or set to a fixed frequency value.

[0078] Step S33: If the frequency difference between the beat frequency and the reference harmonic is less than a preset difference, it is determined that there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel.

[0079] In a specific implementation, after determining the reference harmonic, the controller 10 calculates the frequency difference between the beat frequency and the reference harmonic and compares this frequency difference with a preset difference. If the frequency difference between the beat frequency and the reference harmonic is less than the preset difference, the controller 10 determines that there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel; otherwise, if the frequency difference is greater than or equal to the preset difference, it determines that there is no frequency coupling relationship.

[0080] In one feasible implementation, the synchronization ratio can be calculated using the following preset ratio formula:

[0081] In the formula, Indicates the synchronization ratio. Indicates beat frequency. This indicates the refresh rate of the display panel.

[0082] It should be noted that the synchronization ratio is the ratio of the beat frequency to the display panel refresh rate. It represents the number of complete cycles that the brightness fluctuation caused by the beat frequency goes through in each frame cycle (i.e., the time it takes to refresh one frame of image), reflecting the synchronization multiple of the brightness fluctuation relative to the frame refresh. When the synchronization ratio is close to an integer, the brightness fluctuation and the frame refresh form a stable phase lock, and the water ripples are clearly visible; when the synchronization ratio is far from an integer, the fluctuation phase drifts every frame, and the water ripples are not easily noticed.

[0083] For example, if =1 means that with each frame refresh, the brightness fluctuates for exactly one complete cycle, the scrolling cycle of the water ripples is the same as the frame cycle, and the human eye sees stable scrolling stripes; if =0.5 means that the brightness fluctuates for only one complete cycle every two frames, and the water ripples scroll slowly; if =2 indicates that the brightness fluctuates for two complete cycles within each frame, and the water ripples roll relatively quickly.

[0084] Furthermore, the following inequality can be introduced:

[0085] In the formula, This indicates the preset multiplier threshold. Indicates the synchronization ratio. This indicates the rounding operation.

[0086] It should be noted that the preset multiplier threshold can be a pre-set value, such as 0.1, used to determine whether the synchronization multiplier is sufficiently close to an integer. Using the above inequality, the synchronization multiplier is first rounded to the nearest integer. Then, the difference between the synchronization multiplier and this nearest integer is calculated. If the absolute value of this difference is less than the preset multiplier threshold, i.e., the above inequality is satisfied, then the deviation of the synchronization multiplier from the integer is determined to be within the allowable range. In this case, the beat frequency and the integer multiple of the display panel's refresh rate are sufficiently close, and the frequency coupling relationship exists between them, indicating a high risk of water ripples. Conversely, if the difference is greater than or equal to the preset multiplier threshold, i.e., the above inequality is not satisfied, then the frequency coupling relationship does not exist, and there is no high risk of water ripples.

[0087] In this embodiment, step S40 includes steps S401 to S403: Step S401: Determine the adjustment amount of the switching frequency based on the frequency difference between the beat frequency and the reference harmonic.

[0088] It should be noted that the adjustment amount can be the amount by which the switching frequency needs to be changed.

[0089] In its implementation, the controller 10 first acquires the frequency difference between the calculated beat frequency and the reference harmonic. Then, it calculates the difference between the preset difference and the frequency difference, recording this difference as the required offset. Next, the controller 10 determines the adjustment amount of the switching frequency based on the required offset. The absolute value of the adjustment amount is equal to the required offset, and its sign is determined by the relationship between the beat frequency and the reference harmonic: if the beat frequency is greater than the reference harmonic, the adjustment amount is positive (indicating an increase in the switching frequency); if the beat frequency is less than the reference harmonic, the adjustment amount is negative (indicating a decrease in the switching frequency).

[0090] To prevent excessive adjustment from causing the switching frequency to exceed the allowable operating range, the controller 10 compares the adjustment amount with a maximum allowable single adjustment amount, and takes the smaller absolute value as the final adjustment amount. The maximum allowable single adjustment amount can be pre-stored in the controller's memory and can be calibrated according to the actual power supply characteristics.

[0091] Step S402: When the beat frequency is greater than the reference harmonic, the switching frequency is reduced by the adjustment amount to release the frequency coupling relationship and eliminate the water ripples.

[0092] Step S403: When the beat frequency is less than the reference harmonic, the switching frequency is increased by the adjustment amount to release the frequency coupling relationship and eliminate the water ripples.

[0093] In its implementation, the controller 10 first determines the relationship between the beat frequency and the reference harmonic. If the beat frequency is greater than the reference harmonic, it adjusts the absolute value and sends a frequency setting command to the adjustable frequency power management chip 30, instructing the chip to subtract the absolute value from the current switching frequency to obtain a reduced new switching frequency. If the beat frequency is less than the reference harmonic, it adjusts the absolute value and sends a frequency setting command to the chip, instructing it to add the absolute value to the current switching frequency to obtain an increased new switching frequency. Upon receiving the command, the adjustable frequency power management chip 30 immediately outputs a switching waveform according to the new switching frequency. Subsequently, the controller 10 reacquires the new switching frequency, recalculates the new beat frequency, and again determines whether the frequency difference between the new beat frequency and the reference harmonic is less than a preset difference. If the frequency difference between the new beat frequency and the reference harmonic is no longer less than the preset difference, the frequency coupling relationship has been released, and the water ripples on the display panel will be eliminated; if it is still less than the preset difference, the controller 10 will repeat steps S301 to S303 to continue adjusting until the water ripples are eliminated.

[0094] The switching waveform can be a periodic pulse signal output by the adjustable frequency power management chip 30 to control the switching transistor to turn on and off.

[0095] It should be understood that, after determining the adjustment amount of the switching frequency, if the beat frequency is greater than the reference harmonic, the frequency coupling relationship is released by reducing the switching frequency by adjusting the amount; if the beat frequency is less than the reference harmonic, the frequency coupling relationship is released by increasing the switching frequency by adjusting the amount. This ensures that the adjusted new beat frequency is no longer synchronously locked with the refresh rate of the display panel, and the brightness fluctuation cannot maintain a fixed phase repetition with the frame refresh rhythm, thereby accurately eliminating the scrolling ripples visible to the human eye.

[0096] Based on the first and second embodiments of this application, a third embodiment of this application is proposed. In this third embodiment, content that is the same as or similar to the first and second embodiments described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 5 , Figure 5 This is a flowchart illustrating the third embodiment of the method for eliminating water ripples on a display panel according to this application.

[0097] In this embodiment, steps S40 are followed by steps S51 to S55: Step S51: Obtain at least one peak phase of the load current.

[0098] In a specific implementation, the controller 10 can acquire the load current waveform through a load current detection circuit connected to the output of the adjustable frequency power management chip 30, and extract the time position of the current peak in each cycle from the load current waveform. The load current detection circuit may include a sampling resistor, a differential amplifier, a bandpass filter, and a hysteresis comparator to convert the load current into a square wave signal. The controller 10 uses a reference clock provided by an external crystal oscillator 50 to drive an internal counter to record the time difference between the rising edge of the square wave and the frame synchronization signal, thereby obtaining the peak phase. If the load current waveform contains multiple peaks within one line cycle, the controller 10 acquires the phase of each peak and records the number of peaks.

[0099] It should be noted that the external crystal oscillator 50 mentioned above can be a frequency source device that provides a high-precision reference clock, such as a quartz crystal oscillator. The external crystal oscillator 50 provides a stable and accurate clock signal to the timing controller 20 and the controller 10 for generating the scanning timing of the display panel and performing high-precision time measurements.

[0100] Step S52: Determine the starting time of pixel charging and the duration of charging.

[0101] It should be noted that the charging start time of a pixel can be the point at which each row of pixels begins to receive data voltage and charge its pixel capacitor. The charging start time can be determined by the source output enable signal and the gate clock signal output by the timing controller 20.

[0102] Understandably, the charging duration can be the length of time the pixel capacitor remains in a charging state. The charging duration can be determined by the configuration parameters of the timing controller 20.

[0103] In its implementation, controller 10 reads the row scanning parameters stored in the internal register of timing controller 20 via the internal bus. These parameters include the period of the gate clock signal, the rising edge position of the source output enable signal, and the effective high-level width of the source output enable signal. Controller 10 calculates the charging start time and charging duration for each row of pixels based on these parameters. For example, the charging start time can be the time difference between the rising edge of the source output enable signal and the row synchronization signal, and the charging duration can be the effective high-level duration of the source output enable signal. If the register of timing controller 20 already stores the values ​​of the charging start time and charging duration, controller 10 can directly read these parameters.

[0104] Step S53: Determine the charging window corresponding to the pixel based on the charging start time and the charging duration.

[0105] It should be noted that the charging window is the time interval during which a pixel can be effectively charged.

[0106] In a specific implementation, the controller 10 uses the charging start time as the starting boundary of the charging window, and adds the charging duration to the charging start time to obtain the ending boundary of the charging window. The time interval between the starting boundary and the ending boundary is the charging window.

[0107] Step S54: Determine whether at least one of the peak phases is within the charging window.

[0108] Step S55: If at least one of the peak phases is within the charging window, the peak phase within the charging window is shifted out of the charging window by adjusting the switching phase of the driving power supply.

[0109] It should be noted that the switching phase can be the time position of the turn-on and turn-off time of the internal switching transistor of the drive power supply (i.e., the frequency-modulated power management chip 30) relative to the synchronization signal (such as the frame synchronization signal or the line synchronization signal). Adjusting the switching phase changes the time offset of the switching transistor's action time.

[0110] In its implementation, the controller 10 compares the time value of each peak phase with the start and end boundaries of the charging window. If the time value of any peak phase is greater than or equal to the start boundary and less than or equal to the end boundary, it is determined that at least one peak phase is within the charging window. In this case, the controller 10 generates a phase adjustment command based on the time difference between the peak phase and the charging window boundary, and sends the phase adjustment command to the adjustable frequency power management chip 30 via the internal bus. The adjustable frequency power management chip 30 changes the output time of its switching phase according to the phase adjustment command, causing the peak phase of the switching ripple to shift, which in turn causes the peak phase of the load current to shift by the same amount, thus shifting the peak phase that was originally within the charging window out of the charging window.

[0111] In one feasible implementation, step S55 includes steps S551 to S553: Step S551: If at least one of the peak phases is within the charging window, then the phase offset is determined based on the time difference between the peak phase within the charging window and the boundary of the charging window.

[0112] It should be noted that the phase offset can be the amount of time required to adjust the switching phase of the drive power supply (i.e., the frequency-adjustable power management chip 30) in order to shift the peak phase out of the charging window.

[0113] In its implementation, the controller 10 first measures the distance from the peak phase to the starting boundary of the charging window, denoted as the first time difference; simultaneously, it measures the distance from the peak phase to the ending boundary of the charging window, denoted as the second time difference. Then, the controller 10 compares the magnitudes of the first and second time differences, selecting the smaller value as the reference time difference. Subsequently, the controller 10 adds a preset margin time to the reference time difference, using the sum of the reference time difference and the preset margin time as the phase offset. The preset margin time can be a pre-set duration, used to ensure that the adjusted peak phase can completely move out of the charging window without remaining on the boundary.

[0114] The direction of the phase offset is determined by the boundary corresponding to the reference time difference: if the reference time difference corresponds to the starting boundary, the phase offset direction is forward (that is, the peak phase is advanced); if the reference time difference corresponds to the ending boundary, the phase offset direction is backward (that is, the peak phase is delayed).

[0115] Step S552: Convert the phase offset into a phase delay value.

[0116] It should be noted that the phase delay value can be a digital quantity that the phase control register of the adjustable frequency power management chip 30 can recognize, and this digital quantity is proportional to the phase offset. For example, the adjustable frequency power management chip 30 may contain a delay phase-locked loop or a digital delay line, and the offset time of the switching phase can be controlled by writing different delay values.

[0117] In a specific implementation, the controller 10 can obtain a conversion coefficient that is pre-biased for the adjustable frequency power management chip 30. The conversion coefficient represents the actual time offset corresponding to a unit delay value. The controller 10 divides the phase offset by the conversion coefficient to obtain an intermediate value, and then rounds the intermediate value to the nearest integer to obtain the phase delay value.

[0118] If the phase control register of the adjustable frequency power management chip 30 only receives non-negative integers, the controller 10 maps the phase offset to the corresponding delay value range according to the direction (forward or backward) to obtain the corresponding phase delay value. For example, a forward offset corresponds to a smaller delay value, and a backward offset corresponds to a larger delay value.

[0119] Step S553: ​​Write the phase delay value into the phase control register of the drive power supply. The phase control register outputs the corresponding switching waveform based on the phase delay value, so that the switching phase of the drive power supply generates an offset corresponding to the phase offset.

[0120] The shift in the switching phase causes the peak phase within the charging window to shift out of the charging window.

[0121] It should be noted that the phase control register can be an internal register of the adjustable frequency power management chip 30 used to set the switching phase. Writing different phase delay values ​​to the phase control register will cause a corresponding time shift in the switching waveform.

[0122] In a specific implementation, the controller 10 can write the phase delay value into the phase control register of the adjustable frequency power management chip 30. The phase control register outputs a corresponding switching waveform according to the phase delay value, causing the switching phase of the adjustable frequency power management chip 30 to shift by a phase offset corresponding to the phase offset. The shift in the switching phase causes the peak phase of the load current to shift by the same amount, causing the peak phase, which was originally within the charging window, to shift out of the charging window and fall into the vertical blank area, thereby avoiding interference from the switching ripple to the pixel charging.

[0123] It should be noted that the aforementioned vertical blank interval can be the time period after the end of one frame of image scanning and before the start of the next frame of image scanning. During the vertical blank interval, the gate drive circuit stops outputting a valid line scan clock, and the source drive circuit also stops outputting data voltage to the pixel; therefore, there is no pixel charging operation. Shifting the peak phase into the vertical blank interval ensures that the switching ripple avoids the pixel's charging window, eliminating interference with the pixel charging voltage.

[0124] It should be understood that by acquiring at least one peak phase of the load current; determining the charging start time and charging duration of the pixel; determining the charging window corresponding to the pixel based on the charging start time and charging duration; determining whether there is at least one peak phase within the charging window; if at least one of the peak phases is within the charging window, then by adjusting the switching phase of the drive power supply, the peak phase within the charging window can be shifted out of the charging window, so that the peak interference of the switching ripple can actively avoid the pixel charging period, avoid the ripple peak causing the pixel charging voltage deviation within the charging window, thereby eliminating the fixed horizontal lines caused by phase coupling, and at the same time weakening the contrast of the rolling water ripples caused by frequency coupling, significantly improving the image quality stability and visual comfort of the display panel.

[0125] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the water ripple elimination method for display panels in this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0126] This application also provides a display panel water ripple elimination device, please refer to... Figure 6 , Figure 6 This is a schematic diagram of the module structure of the display panel water ripple elimination device of this application. The device includes: The data acquisition module 61 is used to acquire the switching frequency of the drive power supply and the load current frequency at the output terminal of the drive power supply.

[0127] Beat frequency determination module 62 is used to determine the beat frequency based on the switching frequency and the load current frequency.

[0128] The judgment module 63 is used to determine that there are water ripples on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel.

[0129] The water ripple elimination module 64 is used to eliminate the water ripples by adjusting the switching frequency to decouple the frequency coupling relationship.

[0130] The display panel ripple elimination device provided in this application, employing the display panel ripple elimination method described in the above embodiments, can solve the technical problem in the prior art where adjusting the switching frequency of the backlight source not only fails to eliminate ripples but may also introduce new flickering. Compared with the prior art, the beneficial effects of the display panel ripple elimination device provided in this application are the same as those of the display panel ripple elimination method provided in the above embodiments, and other technical features in the display panel ripple elimination device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0131] This application provides a display panel water ripple elimination device. The display panel water ripple elimination device includes a controller, the controller 10 including at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the display panel water ripple elimination method in the above embodiment 1.

[0132] like Figure 1 As shown, the display panel water ripple elimination device also includes: a timing controller 20, an adjustable frequency power management chip 30, a parameter detection module 40, and an external crystal oscillator 50.

[0133] The timing controller 20 is connected to the controller 10, the adjustable frequency power management chip 30 and the external crystal oscillator 50 respectively. The adjustable frequency power management chip 30 is connected to the controller 10 and the parameter detection module 40 respectively. The parameter detection module 40 is connected to the timing controller 20 and the controller 10 respectively.

[0134] The following is for reference. Figure 7 , Figure 7 This is a schematic diagram of the display panel ripple elimination device of this application. The display panel ripple elimination device in the embodiments of this application may include, but is not limited to, display driver boards, displays, etc. Figure 7The illustrated display panel water ripple elimination device is merely an example of a controller 10 and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0135] like Figure 7 As shown, the controller 10 of the display panel ripple removal device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the display panel ripple removal device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the display panel ripple elimination device to communicate wirelessly or wiredly with other devices to exchange data. Although display panel ripple elimination devices with various systems are shown in the figures, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0136] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0137] The display panel ripple elimination device provided in this application, employing the display panel ripple elimination method described in the above embodiments, can solve the technical problem in the prior art where adjusting the switching frequency of the backlight source not only fails to eliminate ripples but may also introduce new flickering. Compared with the prior art, the beneficial effects of the display panel ripple elimination device provided in this application are the same as those of the display panel ripple elimination method provided in the above embodiments, and other technical features of this display panel ripple elimination device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0138] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0139] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0140] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the display panel water ripple elimination method in the above embodiments.

[0141] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0142] The aforementioned computer-readable storage medium may be included in the display panel ripple elimination device; or it may exist independently and not assembled into the display panel ripple elimination device.

[0143] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the display panel ripple elimination device, the display panel ripple elimination device: acquires the switching frequency of the driving power supply and the load current frequency at the output terminal of the driving power supply; determines the beat frequency based on the switching frequency and the load current frequency; determines that ripples exist on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel; and eliminates the ripples by adjusting the switching frequency to decouple the frequency coupling relationship.

[0144] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0145] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0146] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0147] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described display panel water ripple elimination method. This solves the technical problem in the prior art where adjusting the switching frequency of the backlight source not only fails to eliminate water ripples but may also introduce new flickering. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the display panel water ripple elimination method provided in the above embodiments, and will not be repeated here.

[0148] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for eliminating water ripples on a display panel, characterized in that, The method includes: Obtain the switching frequency of the drive power supply and the load current frequency at the output terminal of the drive power supply; The beat frequency is determined based on the switching frequency and the load current frequency; When there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, it is determined that there are water ripples on the display panel; The water ripples are eliminated by adjusting the switching frequency to decouple the frequency coupling.

2. The method for eliminating water ripples on a display panel as described in claim 1, characterized in that, The step of determining the beat frequency based on the switching frequency and the load current frequency includes: Among the harmonic components of the load current frequency, the harmonic component with the smallest frequency difference from the switching frequency is identified as the coupling harmonic. The beat frequency is determined based on the frequency difference between the switching frequency and the coupled harmonic.

3. The method for eliminating water ripples on a display panel as described in claim 2, characterized in that, Before the step of determining the presence of water ripples on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, the method further includes: Among the harmonic components of the refresh rate of the display panel, the harmonic component with the smallest frequency difference from the beat frequency is determined as the reference harmonic. Determine whether the frequency difference between the beat frequency and the reference harmonic is less than a preset difference value; If the frequency difference between the beat frequency and the reference harmonic is less than a preset difference, it is determined that there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel.

4. The method for eliminating water ripples on a display panel as described in claim 3, characterized in that, The step of eliminating the water ripples by adjusting the switching frequency to decouple the frequency coupling relationship includes: The adjustment amount of the switching frequency is determined based on the frequency difference between the beat frequency and the reference harmonic. When the beat frequency is greater than the reference harmonic, the switching frequency is reduced by the adjustment amount to release the frequency coupling relationship and eliminate the water ripples; When the beat frequency is less than the reference harmonic, the switching frequency is increased by the adjustment amount to release the frequency coupling relationship and eliminate the water ripples.

5. The method for eliminating water ripples on a display panel as described in claim 1, characterized in that, After the step of adjusting the switching frequency to decouple the frequency when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel, the method further includes: Obtain at least one peak phase of the load current; Determine the start time of pixel charging and the duration of charging; The charging window corresponding to the pixel is determined based on the charging start time and the charging duration. Determine whether at least one of the peak phases is within the charging window; If at least one of the peak phases is within the charging window, the peak phase within the charging window will be shifted out of the charging window by adjusting the switching phase of the drive power supply.

6. The method for eliminating water ripples on a display panel as described in claim 5, characterized in that, The step of shifting the peak phase outside the charging window by adjusting the switching phase of the drive power supply if at least one of the peak phases is within the charging window includes: If at least one of the peak phases is within the charging window, the phase offset is determined based on the time difference between the peak phase within the charging window and the boundary of the charging window. Convert the phase offset into a phase delay value; The phase delay value is written into the phase control register of the drive power supply. The phase control register outputs a corresponding switching waveform based on the phase delay value, so that the switching phase of the drive power supply generates an offset corresponding to the phase offset. The shift in the switching phase causes the peak phase within the charging window to shift out of the charging window.

7. A device for eliminating water ripples on a display panel, characterized in that, The device includes: The data acquisition module is used to acquire the switching frequency of the drive power supply and the load current frequency at the output terminal of the drive power supply. A beat frequency determination module is used to determine the beat frequency based on the switching frequency and the load current frequency; The judgment module is used to determine that there are water ripples on the display panel when there is a frequency coupling relationship between the beat frequency and the refresh rate of the display panel; A water ripple elimination module is used to eliminate the water ripples by adjusting the switching frequency to decouple the frequency coupling relationship.

8. A device for eliminating water ripples on a display panel, characterized in that, The device includes at least a controller, the controller including a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the display panel water ripple elimination method as described in any one of claims 1 to 6.

9. The display panel water ripple elimination device as described in claim 8, characterized in that, The display panel water ripple elimination device also includes: a timing controller, an adjustable frequency power management chip, a parameter detection module, and an external crystal oscillator; The timing controller is connected to the controller, the adjustable frequency power management chip and the external crystal oscillator respectively. The adjustable frequency power management chip is connected to the controller and the parameter detection module respectively. The parameter detection module is connected to the timing controller and the controller respectively.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the display panel water ripple elimination method as described in any one of claims 1 to 6.

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