A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving units, and the nth gate driving unit comprises: a pull-up module configured to charge a driving control node of a current stage in response to an output signal of an nth-i gate driving unit received by a pull-up node of the current stage; an output module configured to output a stage transmission signal of the current stage and a gate driving signal of the current stage under the action of a voltage on the driving control node of the current stage and a current stage clock signal; and a discharge module configured to charge a pre-charge control node in a vertical blanking period of a previous scanning frame, and under the action of a voltage of the pre-charge control node of the current stage and a voltage of a noise reduction control node of the current stage in a current scanning frame, to pull down the pull-up node of the current stage and / or the driving control node of the current stage to a low potential. The gate driving circuit improves the screen flicker phenomenon after multiple stage transmissions.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In liquid crystal display technology, multiple cascaded array substrate row driver (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is propagated at regular intervals, and within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, a high-level signal is generated due to parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point). This causes a brief output of the gate drive signal and the propagation signal. As the propagation accumulates to a certain extent, the potential of the gate drive signal increases to the level driving the pixel, resulting in screen flicker.

[0003] Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the screen flicker problem caused by multiple stages of transmission in the gate driving circuit.

[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit including N cascaded gate driving units, wherein the nth gate driving unit includes: a pull-up module connected to the pull-up node of the current stage and the drive control node of the current stage, configured to: charge the drive control node of the current stage in response to the output signal of the nth gate driving unit received by the pull-up node of the current stage; and an output module connected to the drive control node of the current stage and the clock signal line of the current stage, configured to: output the current stage's current level ... The stage transmits signals and the gate drive signal of the current stage; the discharge module has a precharge control node connected to the noise reduction control node of the current stage, and also connected to the pull-up node and / or the drive control node of the current stage, and is configured to: charge the precharge control node during the vertical blanking period of the previous scan frame; and in the current scan frame, under the action of the voltage of the precharge control node and the voltage of the noise reduction control node of the current stage, pull down the pull-up node and / or the drive control node of the current stage to a low potential; wherein the voltage polarity of the noise reduction control node of the same stage is opposite to that of the drive control node.

[0006] Optionally, the discharge module includes: a pre-charge submodule, connected to the pre-charge control terminal and the pre-charge control node of the current stage, configured to: charge the pre-charge control node of the current stage according to the pre-charge control signal issued by the pre-charge control terminal during the vertical blanking period of the previous scan frame; a switching submodule, connected to the pre-charge control node, the noise reduction control node, and the discharge control node of the current stage, configured to: generate a voltage on the discharge control node of the current stage under the action of the voltage of the pre-charge control node and the voltage of the noise reduction control node of the current stage in the current scan frame; and a discharge submodule, connected to the discharge control node of the current stage and also to the pull-up node and / or the drive control node of the current stage, configured to: pull down the pull-up node and / or the drive control node of the current stage to a low potential under the action of the voltage of the discharge control node of the current stage.

[0007] Optionally, the precharge submodule includes: a first transistor and a first capacitor; the control terminal of the first transistor is connected to the precharge control terminal, the first terminal of the first transistor is connected to the precharge control terminal, the second terminal of the first transistor is connected to the first terminal of the first capacitor; the second terminal of the first capacitor is connected to the precharge control node of the current level.

[0008] Optionally, the switching submodule includes: a second transistor; the control terminal of the second transistor is connected to the noise reduction control node of the current stage, the first terminal of the second transistor is connected to the precharge control node of the current stage, and the second terminal of the second transistor is connected to the discharge control node of the current stage.

[0009] Optionally, the discharge submodule includes: a third transistor; the control terminal of the third transistor is connected to the discharge control node of the current stage, the first terminal of the third transistor is connected to the pull-up node of the current stage and / or the drive control node of the current stage, and the second terminal of the third transistor is connected to a low-level terminal.

[0010] Optionally, the nth gate drive unit further includes: a first reset module, connected to the reset control terminal and the precharge control node of the current stage, configured to: reset the precharge control node of the current stage according to the reset control signal issued by the reset control terminal during the vertical blanking period of the current scan frame; or, a second reset module, connected to the reset control terminal and the discharge control node of the current stage, configured to: reset the discharge control node of the current stage according to the reset control signal issued by the reset control terminal during the vertical blanking period of the current scan frame; wherein the effective periods of the precharge control signal and the reset control signal in the same scan frame are different, and the effective period of the reset control signal precedes that of the precharge control signal.

[0011] Optionally, the first reset module includes: a fourth transistor; the control terminal of the fourth transistor is connected to the reset control terminal, the first terminal of the fourth transistor is connected to the precharge control node of the current stage, and the second terminal of the fourth transistor is connected to a low-level terminal.

[0012] Optionally, the second reset module includes: a fifth transistor; the control terminal of the fifth transistor is connected to the reset control terminal, the first terminal of the fifth transistor is connected to the discharge control node of the current stage, and the second terminal of the fifth transistor is connected to a low-level terminal.

[0013] Optionally, the pull-up module includes: a sixth transistor; the control terminal of the sixth transistor is connected to the stage output terminal of the ni-th stage output module through the pull-up node of the current stage; the first terminal of the sixth transistor is connected to the stage output terminal of the ni-th stage output module through the pull-up node of the current stage; and the second terminal of the sixth transistor is connected to the drive control node of the current stage.

[0014] In a second aspect, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] This application connects a discharge module to the pull-up node of the current stage and / or the drive control node of the current stage. During the vertical blanking period of the previous scan frame, the pre-charge control node of the current stage is charged to store the control voltage in advance. Charging the pre-charge control node of the current stage during the vertical blanking period does not affect the normal scanning process. In the current scan frame, when the clock signal of the ni-th stage returns, the output module of the ni-th stage may experience a slight opening in its output voltage, and the pull-up node of the pull-up module of the current stage may receive a small high-level signal. Simultaneously, the clock signal of the current stage has not yet returned. If there is no voltage on the current stage's drive control node, and the voltage polarity of the noise reduction control node in the same stage is opposite to that of the drive control node, then the noise reduction control node in the current stage will have voltage. Under the influence of the voltage of the precharge control node and the voltage of the drive control node in the current stage, the pull-up node and / or the drive control node in the current stage will be pulled down to a low potential. There will be no voltage on the drive control node in the current stage, and the output module will not be turned on. This can prevent the stage transmission signal and gate drive signal generated in the non-scanning stage from being transmitted, thereby avoiding screen flicker on the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown.

[0020] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0021] Figure 4 A first operating timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A second timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0023] Figure 6 A third timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0024] Explanation of reference numerals in the attached figures: 100. Gate drive unit; 110. Pull-up module; 120. Output module; 130. Discharge module; 131. Precharge submodule; 132. Switch submodule; 133. Discharge submodule; 140. Pull-down module; 150. First reset module; 160. Second reset module; 170. Noise reduction module; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T 10. Tenth transistor; T11. Eleventh transistor; T12. Twelfth transistor; T13. Thirteenth transistor; T14. Fourteenth transistor; T15. Fifteenth transistor; C1. First capacitor; C2. Second capacitor; An. Pull-up node of the current stage; Bn. Precharge control node of the current stage; Cn. Discharge control node of the current stage; Qn. Drive control node of the current stage; Pn. Noise reduction control node of the current stage; SW. Precharge control terminal; Reset. Reset control terminal; LC. Noise reduction signal output terminal; VSS. Low level terminal. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] In liquid crystal display technology, multiple cascaded gate array (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is transmitted in stages over a certain period of time. Within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, due to the parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point), a high-level signal will be generated, thereby outputting a brief gate drive signal and transmission signal again. For example, in an 8CK circuit with 8 clock signal lines, when CK1~CK8 transmit clock signals to the corresponding GOA driving units in rows 1 to 8, when the GOA unit in row 9 receives the clock signal transmitted by CK1, the GOA unit in row 1 will again receive the clock signal transmitted by CK1. Due to the parasitic capacitance between the gate and drain of the cascade transistor and the driving transistor in the GOA unit, the cascade transistor and the driving transistor will be slightly open, resulting in a brief high-level signal output from the source of the cascade transistor and the source of the driving transistor. This high-level signal is then cascaded and stored in the pre-charge capacitor of the next stage. Due to the influence of the pre-charge capacitor and parasitic capacitance, the degree of slight opening of the cascade transistor and the driving transistor in the next stage will become larger and larger. For example, when the clock signal from row 10 returns to row 2, the potential of the brief gate driving signal and the cascade signal in row 2 will be larger than that in row 1. And so on. As the cascade generation accumulates to a certain extent, the potential of the gate driving signal will increase to drive the pixel, thus producing screen flicker. Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved.

[0029] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes a pull-up module 110, an output module 120, and a bleeder module 130. The pull-up module 110 is connected to the pull-up node An of the current stage and the drive control node Qn of the current stage. The output module 120 is connected to the drive control node Qn of the current stage and the clock signal line CKm of the current stage. The bleeder module 130 has a precharge control node and is connected to the noise reduction control node Pn of the current stage. The bleeder module 130 is also connected to the pull-up node An of the current stage and / or the drive control node Qn of the current stage.

[0030] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines; Fn-i represents the stage output terminal of the ni-th stage output module; Gn represents the drive output terminal of the current stage; and Fn represents the stage output terminal of the current stage.

[0031] In some embodiments, the pull-up module 110 is configured to charge the current stage drive control node Qn in response to the output signal of the nth stage gate drive unit 100 received by the pull-up node An of the current stage.

[0032] For example, the signal output by the ni-th stage gate drive unit 100 includes a gate drive signal and / or a stage transmission signal. The specific signal received is selected according to actual needs. When the pull-up module 110 receives the gate drive signal and / or stage transmission signal output by the ni-th stage gate drive unit 100, the pull-up module 110 will be turned on to charge the current stage's drive control node Qn. Specifically, i can be 2.

[0033] In some embodiments, the output module 120 is configured to output the current stage transmission signal and the current stage gate drive signal under the action of the voltage on the current stage drive control node Qn and the current stage clock signal.

[0034] For example, when the current stage's drive control node Qn is precharged and the current stage's clock signal arrives, the output module 120 will turn on and output the current stage's transmission signal to perform transmission, acting on the gate drive unit 100 of the adjacent stage, and will also output the current stage's gate drive signal to drive the pixel.

[0035] In some embodiments, the discharge module 130 is configured to: charge the precharge control node during the vertical blanking period of the previous scan frame; and in the current scan frame, under the action of the voltage of the precharge control node Bn of the current stage and the voltage of the noise reduction control node Pn of the current stage, pull down the pull-up node An of the current stage and / or the drive control node Qn of the current stage to a low potential; wherein the voltage polarity of the noise reduction control node of the same stage is opposite to that of the drive control node.

[0036] For example, the pre-charge control node Bn of the current stage is charged during the vertical blanking period of the previous scan frame to store the control voltage in advance, and charging the pre-charge control node Bn of the current stage during the vertical blanking period does not affect the normal scanning process; in the current scan frame, when the clock signal of the ni-th stage returns, the output voltage of the ni-th output module 120 may have a slight opening, and the pull-up node An of the pull-up module 110 of the current stage may receive a small high-level signal; at the same time, the clock signal of the current stage has not yet returned, and the drive control of the current stage... There is no voltage on node Qn. Since the voltage polarity of the noise reduction control node in the same stage is opposite to that of the drive control node, there is voltage on the noise reduction control node Pn of the current stage. Under the action of the voltage of the precharge control node Bn of the current stage and the voltage of the drive control node Qn of the current stage, the pull-up node An and / or the drive control node Qn of the current stage are pulled down to a low potential. There will be no voltage on the drive control node Qn of the current stage, and the output module 120 will not be turned on, thereby preventing the accumulation of small high-level signals and avoiding screen flicker.

[0037] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the discharge module 130 includes: a pre-charge submodule 131, a switch submodule 132, and a discharge submodule 133. The pre-charge submodule 131 and the pre-charge control terminal SW are connected to the pre-charge control node Bn of the current stage. The switch submodule 132 is connected to the pre-charge control node Bn, the noise reduction control node Pn, and the discharge control node Cn of the current stage. The discharge submodule 133 is connected to the discharge control node Cn of the current stage, and also to the pull-up node An and / or the drive control node Qn of the current stage.

[0038] In some embodiments, the precharge submodule 131 is configured to charge the current level precharge control node Bn according to the precharge control signal issued by the precharge control terminal SW during the vertical blanking period of the previous scan frame.

[0039] For example, the precharge control terminal SW can be the signal output terminal of the timing controller. During the vertical blanking period of the previous scan frame, the precharge control signal issued by the precharge control terminal SW charges the precharge control node Bn of the current level to act on the switch submodule 132.

[0040] In some embodiments, the switching submodule 132 is configured to generate a voltage on the discharge control node Cn of the current stage in the current scan frame, under the influence of the voltage of the precharge control node Bn of the current stage and the voltage of the noise reduction control node Pn of the current stage.

[0041] For example, in the current scan frame, when the clock signal of the nith stage returns, there is a voltage on the noise reduction control node Pn of the current stage. Under the action of the voltage of the precharge control node Bn of the current stage and the voltage of the noise reduction control node Pn of the current stage, a voltage is generated on the discharge control node Cn of the current stage.

[0042] In some embodiments, the discharge submodule 133 is configured to: pull down the pull-up node An and / or the drive control node Qn of the current stage to a low potential under the voltage action of the discharge control node Cn of the current stage.

[0043] For example, when the discharge control node Cn of the current stage has a voltage, it will pull down the pull-up node An and / or the drive control node Qn of the current stage to a low potential. When the pull-up node An or the drive control node Qn of the current stage is pulled down to a low potential, the small high-level signal output by the ni-th stage will not charge the drive control node Qn of the current stage, and the small high-level signal will not accumulate through the stage, thus avoiding screen flicker. When the discharge control node Cn of the current stage is connected to both the pull-up node An and the drive control node Qn of the current stage, it is possible to pull down both the pull-up node An and the drive control node Qn of the current stage simultaneously, which can further ensure that the small high-level signal will not accumulate through the stage.

[0044] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the precharge submodule 131 includes: a first transistor T1 and a first capacitor C1; the control terminal of the first transistor T1 is connected to the precharge control terminal SW, the first terminal of the first transistor T1 is connected to the precharge control terminal SW, the second terminal of the first transistor T1 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the precharge control node Bn of the current stage.

[0045] For example, Figure 4 This paper shows a first operating timing diagram of a gate driving circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 4 As shown, each scan frame includes a scanning period and a vertical blanking period. During the vertical blanking period, the first and second terminals of the first transistor T1 will receive a precharge control signal, and the first transistor T1 will be turned on to charge the first capacitor C1, generating a voltage at the precharge control node Bn of the current stage.

[0046] In some embodiments, please refer to Figure 3As shown, the switch submodule 132 includes: a second transistor T2; the control terminal of the second transistor T2 is connected to the noise reduction control node Pn of the current stage, the first terminal of the second transistor T2 is connected to the precharge control node Bn of the current stage, and the second terminal of the second transistor T2 is connected to the discharge control node Cn of the current stage.

[0047] For example, Figure 5 This paper shows a second timing diagram of a gate drive circuit according to an embodiment of the present application. Figure 6 This paper presents a third timing diagram of a gate driving circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 3 , Figure 5 and Figure 6 As shown, when the clock signal of the ni-th stage returns to the output module 120 and outputs a small high-level signal, the clock signal of the current stage has not yet arrived, and there is no voltage on the drive control node Qn of the current stage. Since the voltage polarities of the drive control node and the noise reduction control node of the same stage are opposite, there is a voltage on the noise reduction control node Pn of the current stage. Under the action of the voltage of the noise reduction control node Pn of the current stage and the voltage of the precharge control node Bn of the current stage, a voltage will be generated on the discharge control node Cn of the current stage.

[0048] It should be noted that, Figure 5 The diagram shown is the timing diagram for a clock signal of 8CK. Figure 6 The diagram shows the timing sequence for clock signal 6CK. There is an overlap of one hour (h) between clock signals of adjacent stages. Fn-2 in the diagram represents the output terminal of the (n-2)th stage output module. VGH in the diagram indicates that Bn continuously outputs a high-level voltage signal.

[0049] In some embodiments, please refer to Figure 3 As shown, the discharge submodule 133 includes: a third transistor T3; the control terminal of the third transistor T3 is connected to the discharge control node Cn of the current stage, the first terminal of the third transistor T3 is connected to the pull-up node An of the current stage and / or the drive control node Qn of the current stage, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0050] For example, please refer to Figure 3 , Figure 5 and Figure 6As shown, when the clock signal of the ni-th stage returns, the control terminal of the third transistor T3 will be turned on by receiving the voltage of the discharge control node, thereby pulling down the pull-up node An of the current stage and / or the drive control node Qn of the current stage to a low potential. When the pull-up node An of the current stage and / or the drive control node Qn of the current stage are pulled down to a low potential, the tiny high-level signal input from the ni-th stage to the pull-up node An of the current stage will not charge the drive control node Qn of the current stage, and the tiny high-level signal will not be transmitted to the pull-up node of the (n+i)-th stage. The tiny high-level signal will not accumulate, thus preventing screen flicker.

[0051] In some embodiments, the nth stage gate driving unit 100 further includes: a first reset module 150, connected to the reset control terminal Reset and the precharge control node Bn of the current stage, and configured to: reset the precharge control node Bn of the current stage according to the reset control signal issued by the reset control terminal Reset during the vertical blanking period of the current scan frame.

[0052] For example, please refer to Figure 2 and Figure 4 As shown, the reset control terminal Reset can be the signal output terminal of the timing controller. By setting the first reset module 150 to pull down the precharge control node Bn of the current stage to a low potential according to the reset control signal during the vertical blanking period of the current scan frame, the precharge control node Bn of the current stage is reset so that it can be charged in the current scan frame and act on the switch submodule 132 in the next scan frame.

[0053] In some embodiments, the nth-stage gate driving unit 100 further includes a second reset module 160, which is connected to the reset control terminal Reset and the discharge control node Cn of the current stage, and is configured to reset the discharge control node Cn of the current stage according to the reset control signal issued by the reset control terminal Reset during the vertical blanking period of the current scan frame.

[0054] For example, by setting the reset control signal issued by the second reset module 160 during the vertical blanking period of the current scan frame, the discharge control node Cn of the current stage is reset, so that the discharge submodule 133 is cut off, so as to ensure that the pull-up module 110 can receive the transmission signal to conduct during normal transmission, and realize the charging of the drive control node Qn of the current stage.

[0055] Among them, the effective periods of the precharge control signal and the reset control signal in the same scan frame are different, and the effective period of the reset control signal is earlier than that of the precharge control signal.

[0056] By different effective periods for the precharge control signal and the reset control signal, it is ensured that the precharge phase and the reset phase will not conflict. The effective period of the reset control signal precedes that of the precharge control signal, so that the current level precharge control node can be charged again after the current level precharge control node Bn is charged. After the current level discharge control node Cn is reset, the discharge submodule 133 is turned off in the next scan frame, so that the pull-up module 110 can charge the current level drive control node Qn.

[0057] It should be noted that, Figure 4 The first scan frame includes a valid frame signal for the precharge control signal and a valid frame signal for the reset control signal, because there is no voltage on the precharge control node in the first scan frame, so a reset control signal is not required.

[0058] In some embodiments, please refer to Figure 3 As shown, the first reset module 150 includes: a fourth transistor T4; the control terminal of the fourth transistor T4 is connected to the reset control terminal Reset, the first terminal of the fourth transistor T4 is connected to the precharge control node Bn of the current stage, and the second terminal of the fourth transistor T4 is connected to the low-level terminal VSS.

[0059] For example, please refer to Figure 3 and Figure 4 As shown, when the control terminal of the fourth transistor T4 receives the reset control signal issued by the reset control terminal Reset during the vertical blanking period, the fourth transistor T4 will turn on, thereby pulling down the precharge control node Bn of the current stage to a low potential to reset the precharge control node Bn of the current stage.

[0060] In some embodiments, please refer to Figure 3 As shown, the second reset module 160 includes: a fifth transistor T5; the control terminal of the fifth transistor T5 is connected to the reset control terminal Reset, the first terminal of the fifth transistor T5 is connected to the discharge control node Cn of the current stage, and the second terminal of the fifth transistor T5 is connected to the low-level terminal VSS.

[0061] For example, please refer to Figure 3 and Figure 4 As shown, when the control terminal of the fifth transistor T5 receives the reset control signal from the reset control terminal Reset, the fifth transistor T5 will turn on, thereby pulling down the discharge control node Cn of the current stage to a low potential and resetting the discharge control node Cn of the current stage. At this time, the control terminal of the third transistor T3 will be cut off when it receives a low-level signal, and will not pull down the pull-up node An of the current stage to a low potential.

[0062] In some embodiments, please refer to Figure 3As shown, the pull-up module 110 includes: a sixth transistor T6; the control terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the ni-th stage output module 120 through the pull-up node An of the current stage; the first terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the ni-th stage output module 120 through the pull-up node An of the current stage; and the second terminal of the sixth transistor T6 is connected to the drive control node Qn of the current stage.

[0063] For example, when the current stage is operating normally, when the control terminal and the first terminal of the sixth transistor T6 receive the stage transmission signal from the ni stage, the sixth transistor T6 will conduct, charging the drive control node Qn of the current stage. At this time, there is no voltage on the noise reduction control node Pn of the current stage, the second transistor T2 is off, and the third transistor T3 is also off. When the output module 120 of the ni stage receives the returned clock signal, the control terminal and the first terminal of the sixth transistor T6 of the current stage may also receive a small high-level signal from the output of the ni stage. There is voltage on the noise reduction control node Pn of the current stage, the second transistor T2 will conduct, thereby pulling down the pull-up node An of the current stage to a low potential. The sixth transistor T6 will not conduct, thus not charging the drive control node Qn of the current stage. It should be noted that the first terminal of the sixth transistor T6 and the control terminal of the sixth transistor T6 serve as the pull-up node An of the current stage. They can be connected to the first terminal of the third transistor T3 of the bleeder module 130 through either the first terminal of the sixth transistor T6 or the control terminal of the sixth transistor T6. Alternatively, the first terminal of the sixth transistor T6 and the control terminal of the sixth transistor T6 can be connected to the first terminal of the third transistor T3 of the bleeder module 130 simultaneously. When the first terminal of the sixth transistor T6 and the control terminal of the sixth transistor T6 are connected to the first terminal of the third transistor T3 of the bleeder module 130 simultaneously, it can be further ensured that the small high-level signal output by the ni-th stage output module 120 will not be output to the drive control node Qn of the current stage.

[0064] In some embodiments, please refer to Figure 3 As shown, the output module 120 includes: a seventh transistor T7, an eighth transistor T8, and a second capacitor C2. The control terminal of the seventh transistor T7, the control terminal of the eighth transistor T8, and the first terminal of the second capacitor C2 are connected to the drive control node Qn of the current stage. The first terminal of the seventh transistor T7 is connected to the clock signal line CKm of the current stage. The second terminal of the seventh transistor T7 serves as the stage transmission output terminal. The first terminal of the eighth transistor T8 is connected to the clock signal line CKm of the current stage. The second terminal of the eighth transistor T8 serves as the drive output terminal of the current stage.

[0065] For example, when the current stage's drive control node Qn is precharged and the current stage's clock signal arrives, the voltage on the second capacitor C2 will bootstrap the current stage's drive control node Qn, the seventh transistor T7 will turn on to output the current stage's stage transmission signal, and the eighth transistor T8 will turn on to output the current stage's gate drive signal.

[0066] In some embodiments, please refer to Figure 3 The nth-stage gate drive unit 100 further includes a pull-down module 140, which includes a ninth transistor T9 and a tenth transistor T10. The control terminals of the ninth transistor T9 and the tenth transistor T10 are connected to the stage transmission output terminal of the (n+j)th-stage output module 120. The first terminal of the ninth transistor T9 is connected to the drive control node Qn of the current stage. The second terminal of the ninth transistor T9 and the second terminal of the tenth transistor T10 are connected to the low-level terminal VSS. The first terminal of the tenth transistor T10 is connected to the drive output terminal Gn of the current stage.

[0067] For example, when the control terminals of the ninth transistor T9 and the tenth transistor T10 receive the stage transmission signal output by the (n+j)th stage output module 120, the ninth transistor T9 and the tenth transistor T10 will be turned on. The ninth transistor T9 will pull down the current stage's drive control node Qn to a low potential, and the tenth transistor T10 will pull down the current stage's drive output terminal Gn to a low potential, thereby controlling the current stage to no longer output a gate drive signal. Specifically, j can be 3.

[0068] In some embodiments, please refer to Figure 3 As shown, the nth-stage gate drive unit 100 further includes a noise reduction module 170, which includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15. The control terminal of the eleventh transistor T11 and the first terminal of the eleventh transistor T11 and the first terminal of the twelfth transistor T12 are connected to the noise reduction control terminal LC. The second terminal of the eleventh transistor T11 is connected to the control terminal of the twelfth transistor T12 and the first terminal of the thirteenth transistor T13. The second terminal of the thirteenth transistor T13 and the second terminal of the fourteenth transistor T14 and the second terminal of the fifteenth transistor T15 are connected to the low-level terminal VSS. The second terminal of the twelfth transistor T12 and the first terminal of the fourteenth transistor T14 and the control terminal of the fifteenth transistor T15 are connected to the noise reduction control node Pn of the current stage. The control terminal of the thirteenth transistor T13 and the control terminal of the fourteenth transistor T14 are connected to the drive control node Qn of the current stage. The first terminal of the fifteenth transistor T15 is connected to the drive control node Qn of the current stage.

[0069] For example, the noise reduction control terminal LC can be the signal output terminal of the timing controller. The noise reduction control signal output by the noise reduction control terminal LC is continuously a high-level signal. When there is no voltage on the current stage drive control node Qn, the eleventh transistor T11 and the twelfth transistor T12 receive the high-level signal and turn on, generating a voltage on the current stage noise reduction control node Pn. The current stage noise reduction control node Pn will control the fifteenth transistor T15 to turn on, thereby pulling the current stage drive control node Qn down to a low potential and performing noise reduction on the current stage noise reduction control node Pn. When there is voltage on the current stage's drive control node Qn, the thirteenth transistor T13 and the fourteenth transistor T14 will conduct, pulling down the current stage's noise reduction control node Pn to a low potential. When there is no voltage on the current stage's noise reduction control node Pn, the fifteenth transistor T15 will not conduct, thus preventing the current stage's drive control node Qn from being pulled down to a low potential. At the same time, when there is voltage on the current stage's drive control node Qn, and there is no voltage on the current stage's noise reduction control node Pn, the second transistor T2 will not conduct, preventing the current stage's pull-up node An or the current stage's drive control node Qn from being pulled down to a low potential, thus not affecting the normal stage transmission.

[0070] In some embodiments, this application also provides a display panel including a display area and a non-display area, the display area including a plurality of scan lines, the non-display area including the aforementioned gate driving circuit, and the output module 120 of the gate driving circuit being connected to at least one of the scan lines.

[0071] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0072] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0073] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the pull-up node of the current stage and the drive control node of the current stage, is configured to: charge the drive control node of the current stage in response to the output signal of the nith stage gate drive unit received by the pull-up node of the current stage. The output module, connected to the drive control node and clock signal line of the current stage, is configured to output the stage transmission signal and the gate drive signal of the current stage under the action of the voltage on the drive control node and the clock signal of the current stage. The discharge module includes: a pre-charge submodule, a switch submodule, and a discharge submodule; The pre-charge submodule, connected to the pre-charge control terminal and the current-level pre-charge control node, is configured to: charge the current-level pre-charge control node according to the pre-charge control signal issued by the pre-charge control terminal during the vertical blanking period of the previous scan frame. The switching submodule, connected to the current-level pre-charge control node, the current-level noise reduction control node, and the current-level discharge control node, is configured to generate a voltage on the current-level discharge control node during the current scan frame, under the influence of the voltages of the current-level pre-charge control node and the current-level noise reduction control node; wherein the voltage polarity of the noise reduction control node at the same level is opposite to that of the drive control node. The discharge submodule is connected to the discharge control node of the current stage, and also to the pull-up node and / or the drive control node of the current stage. It is configured to pull down the pull-up node and / or the drive control node of the current stage to a low potential under the voltage action of the discharge control node of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The pre-charge submodule includes: a first transistor and a first capacitor; The control terminal of the first transistor is connected to the precharge control terminal, the first terminal of the first transistor is connected to the precharge control terminal, and the second terminal of the first transistor is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the precharge control node of the current stage.

3. The gate driving circuit according to claim 1, characterized in that, The switching submodule includes: a second transistor; The control terminal of the second transistor is connected to the noise reduction control node of the current stage, the first terminal of the second transistor is connected to the precharge control node of the current stage, and the second terminal of the second transistor is connected to the discharge control node of the current stage.

4. The gate driving circuit according to claim 1, characterized in that, The discharge submodule includes: a third transistor; The control terminal of the third transistor is connected to the discharge control node of the current stage, the first terminal of the third transistor is connected to the pull-up node of the current stage and / or the drive control node of the current stage, and the second terminal of the third transistor is connected to the low-level terminal.

5. The gate driving circuit according to claim 1, characterized in that, The nth-stage gate driving unit further includes: The first reset module, connected to the reset control terminal and the precharge control node of the current level, is configured to: reset the precharge control node of the current level according to the reset control signal issued by the reset control terminal during the vertical blanking period of the current scan frame; Alternatively, a second reset module, connected to the reset control terminal and the discharge control node of the current stage, is configured to: reset the discharge control node of the current stage according to the reset control signal issued by the reset control terminal during the vertical blanking period of the current scan frame; The effective periods of the precharge control signal and the reset control signal in the same scan frame are different, and the effective period of the reset control signal precedes that of the precharge control signal.

6. The gate driving circuit according to claim 5, characterized in that, The first reset module includes: a fourth transistor; The control terminal of the fourth transistor is connected to the reset control terminal, the first terminal of the fourth transistor is connected to the precharge control node of the current stage, and the second terminal of the fourth transistor is connected to the low-level terminal.

7. The gate driving circuit according to claim 5, characterized in that, The second reset module includes: a fifth transistor; The control terminal of the fifth transistor is connected to the reset control terminal, the first terminal of the fifth transistor is connected to the discharge control node of the current stage, and the second terminal of the fifth transistor is connected to the low-level terminal.

8. The gate driving circuit according to claim 1, characterized in that, The pull-up module includes: a sixth transistor; The control terminal of the sixth transistor is connected to the stage output terminal of the ni-th stage output module through the pull-up node of the current stage. The first terminal of the sixth transistor is connected to the stage output terminal of the ni-th stage output module through the pull-up node of the current stage. The second terminal of the sixth transistor is connected to the drive control node of the current stage.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-8, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.

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