A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving units, and the nth gate driving unit comprises: a pull-up module configured to charge a driving control node of a current stage in response to an output signal of an nth-i gate driving unit; an output module configured to output a stage transmission signal of the current stage and a gate driving signal of the current stage under the action of a voltage on the driving control node of the current stage and a current stage clock signal; and a control module configured to output the stage transmission signal of the current stage or the gate driving signal of the current stage output by the output module in a scanning period of the current stage, and stop outputting the stage transmission signal of the current stage or the gate driving signal of the current stage output by the output module in a non-scanning period of the current stage and when a high-level signal is received by a clock signal line of the current stage. The screen flicker phenomenon after multiple stage transmissions in the gate driving circuit is improved.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In liquid crystal display technology, multiple cascaded array substrate row driver (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is propagated at regular intervals, and within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, a high-level signal is generated due to parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point). This causes a brief output of the gate drive signal and the propagation signal. As the propagation accumulates to a certain extent, the potential of the gate drive signal increases to the level driving the pixel, resulting in screen flicker.

[0003] Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the screen flicker problem caused by multiple stages of transmission in the gate driving circuit.

[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit including N cascaded gate driving units, wherein the nth gate driving unit includes: a pull-up module connected to the current stage's drive control node, configured to: charge the current stage's drive control node in response to the output signal of the nth gate driving unit; an output module connected to the current stage's drive control node and the current stage's clock signal line, configured to: output the current stage's stage transmission signal and the current stage's gate driving signal under the action of the voltage on the current stage's drive control node and the current stage's clock signal; and a control module connected to the output module's stage transmission output terminal or drive output terminal, configured to: during the current stage's scan period, issue the current stage's stage transmission signal or the current stage's gate driving signal output by the output module; and during the current stage's non-scan period and when the current stage's clock signal line receives a high-level signal, stop issuing the current stage's stage transmission signal or the current stage's gate driving signal output by the output module.

[0006] Optionally, the control module includes: a first control submodule, connected to the drive control node of the nj-th stage and also connected to the stage transmission output terminal or drive output terminal of the output module, configured to: under the voltage of the drive control node of the nj-th stage, issue the stage transmission signal or the gate drive signal of the current stage output by the output module; a second control submodule, connected to the first control submodule and the drive control node of the n+q-th stage respectively, configured to: under the voltage of the drive control node of the n+q-th stage, control the first control submodule to stop issuing the stage transmission signal or the gate drive signal of the current stage; wherein, j is less than i, and q represents the number of clock signal lines.

[0007] Optionally, the first control submodule includes: a first transistor; the control terminal of the first transistor is connected to the drive control node of the njth stage, the first terminal of the first transistor is connected to the stage transmission output terminal or drive output terminal of the output module, and the second terminal of the first transistor outputs the stage transmission signal of the current stage or the gate drive signal of the current stage.

[0008] Optionally, the second control submodule includes: a second transistor and a third transistor; the control terminal of the second transistor is connected to the drive control node of the (n+q)th stage, the first terminal of the second transistor is connected to the stage transmission output terminal or drive output terminal of the output module, and the second terminal of the second transistor is connected to the control terminal of the third transistor; the first terminal of the third transistor is connected to the output terminal of the first control submodule, and the second terminal of the third transistor is connected to a low-level terminal.

[0009] Optionally, the first control submodule includes: a first transistor and a first capacitor; the control terminal of the first transistor is connected to the drive control node of the njth stage and the first terminal of the first capacitor, the first terminal of the first transistor is connected to the stage transmission output terminal or drive output terminal of the output module, the second terminal of the first transistor is connected to the second terminal of the first capacitor, and outputs the stage transmission signal of the current stage or the gate drive signal of the current stage.

[0010] Optionally, the second control submodule includes: a second capacitor, a second transistor, and a third transistor; the first terminal of the second capacitor is connected to the drive control section of the (n+q)th stage; the control terminal of the second transistor is connected to the second terminal of the second capacitor, the first terminal of the second transistor is connected to the stage output terminal or drive output terminal of the output module, and the second terminal of the second transistor is connected to the control terminal of the third transistor; the first terminal of the third transistor is connected to the output terminal of the first control submodule, and the second terminal of the third transistor is connected to a low-level terminal.

[0011] Optionally, the second control submodule further includes: a fourth transistor; the control terminal of the fourth transistor is connected to the reset control terminal, the first terminal of the fourth transistor is connected to the second terminal of the second capacitor, and the second terminal of the fourth transistor is connected to the low-level terminal.

[0012] Optionally, the nth-stage gate drive unit further includes: a third control submodule, connected to the stage transmission output terminal or drive output terminal of the output module, and also connected to the drive control node of the current stage, the drive control node of the (n+q)th stage, and the discharge control node of the current stage, configured to: generate a voltage on the discharge control node of the current stage under the action of the voltage of the drive control node of the current stage, the stage transmission signal of the current stage, and the voltage of the drive control node of the (n+q)th stage, or under the action of the voltage of the drive control node of the current stage, the gate drive signal of the current stage, and the voltage of the drive control node of the (n+q)th stage; and a discharge submodule, connected to the discharge control node of the current stage and the drive control node of the current stage, configured to: pull down the drive control node of the current stage to a low potential under the action of the voltage of the discharge control node of the current stage.

[0013] Optionally, the third control submodule includes: a fifth transistor, a third capacitor, and a sixth transistor; the control terminal of the fifth transistor is connected to the stage transmission output terminal or drive output terminal of the output module, the first terminal of the fifth transistor is connected to the drive control node of the current stage, and the second terminal of the fifth transistor is connected to the first terminal of the third capacitor; the second terminal of the third capacitor and the first terminal of the sixth transistor are connected to the precharge control node of the current stage; the control terminal of the sixth transistor is connected to the drive control node of the (n+q)th stage, and the second terminal of the sixth transistor is connected to the discharge control node of the current stage; or / and, the discharge submodule includes: a seventh transistor; the control terminal of the seventh transistor is connected to the discharge control node of the current stage, the first terminal of the seventh transistor is connected to the drive control node of the current stage, and the second terminal of the seventh transistor is connected to a low-level terminal.

[0014] Secondly, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the gate driving circuit described in any of the first aspects. When the control module of the gate driving circuit is connected to the stage transmission output terminal of the output module, the drive output terminal of the output module is connected to at least one of the scan lines; or, when the control module of the gate driving circuit is connected to the drive output terminal of the output module, the control module is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects: This application connects the control module to the stage transmission output or drive output of the output module. During the scanning period of the current stage, it sends the stage transmission signal or gate drive signal of the current stage output by the output module. This ensures that the pull-up module of the (n+i)th stage can receive the stage transmission signal or gate drive signal of the current stage for stage transmission, and output the gate drive signal of the current stage to drive the pixel. During the non-scanning period of the current stage, when the clock signal of the current stage receives a high-level signal, the output module micro-opens. The stage transmission output and drive output of the output module may output a small high-level signal for stage transmission. By setting the control module to stop sending the stage transmission signal or gate drive signal of the current stage output by the output module, the stage transmission signal and gate drive signal of the current stage during the non-scanning period are small high-level signals. That is, the control module stops sending small high-level signals, and the small high-level signals will not accumulate for stage transmission and will not drive the pixel, thereby avoiding the occurrence of screen flicker. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0018] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 3 A circuit diagram of a first type of gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 4 The diagram shows a first operating timing diagram of a gate driving unit provided in an embodiment of this application.

[0021] Figure 5 A circuit diagram of a second gate driving unit provided in an embodiment of this application is shown.

[0022] Figure 6 A circuit diagram of a third gate driving unit provided in an embodiment of this application is shown.

[0023] Figure 7 A circuit diagram of a fourth gate driving unit provided in an embodiment of this application is shown.

[0024] Figure 8A circuit diagram of a fifth gate driving unit provided in an embodiment of this application is shown.

[0025] Figure 9 A second operating timing diagram of a gate driving unit provided in an embodiment of this application is shown.

[0026] Explanation of reference numerals in the attached figures: 100. Gate drive unit; 110. Pull-up module; 120. Output module; 130. Control module; 131. First control submodule; 132. Second control submodule; 133. Third control submodule; 134. Discharge submodule; 140. Pull-down module; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T1 0. Tenth transistor; T11. Eleventh transistor; T12. Twelfth transistor; T13. Thirteenth transistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; C4. Fourth capacitor; Qn. Current stage drive control node; Qn+q. Drive control node of stage n+q; Qn-j. Drive control node of stage nj; An. Current stage discharge control node; Bn. Current stage precharge control node; Fn. Current stage stage transmission output terminal; Gn. Current stage drive output terminal; Fn, the stage transmission signal output terminal of the current stage control module; G n, the drive signal output terminal of the current level control module; Reset, the reset control terminal; VSS, the low-level terminal. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0028] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0029] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0030] In liquid crystal display technology, multiple cascaded gate array (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is transmitted in stages over a certain period of time. Within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, due to the parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point), a high-level signal will be generated, thereby outputting a brief gate drive signal and transmission signal again. For example, in an 8CK circuit with 8 clock signal lines, when CK1~CK8 transmit clock signals to the corresponding GOA driving units in rows 1 to 8, when the GOA unit in row 9 receives the clock signal transmitted by CK1, the GOA unit in row 1 will again receive the clock signal transmitted by CK1. Due to the parasitic capacitance between the gate and drain of the cascade transistor and the driving transistor in the GOA unit, the cascade transistor and the driving transistor will be slightly open, resulting in a brief high-level signal output from the source of the cascade transistor and the source of the driving transistor. This high-level signal is then cascaded and stored in the pre-charge capacitor of the next stage. Due to the influence of the pre-charge capacitor and parasitic capacitance, the degree of slight opening of the cascade transistor and the driving transistor in the next stage will become larger and larger. For example, when the clock signal from row 10 returns to row 2, the potential of the brief gate driving signal and the cascade signal in row 2 will be larger than that in row 1. And so on. As the cascade generation accumulates to a certain extent, the potential of the gate driving signal will increase to drive the pixel, thus producing screen flicker. Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved.

[0031] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes a pull-up module 110, an output module 120, and a control module 130. The pull-up module 110 is connected to the current stage's drive control node Qn. The output module 120 is connected to the current stage's drive control node Qn and the current stage's clock signal line CKm. The control module 130 is connected to the stage transmission output terminal Fn or the drive output terminal Gn of the output module 120.

[0032] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, Fn-i represents the stage output of the ni-th stage, Gn-i represents the drive output of the ni-th stage, and F... ni represents the stage transmission signal output terminal of the ni-th stage control module 130. Figure 1 The diagram shows the connection between the control module 130 and the output module 120 at the stage transmission output.

[0033] In some embodiments, the pull-up module 110 is configured to charge the current stage drive control node Qn in response to the output signal of the nth stage gate drive unit 100.

[0034] For example, i can be 2, and the signal output by the ni-th stage gate drive unit 100 can be the stage transmission signal and / or the gate drive signal output by the ni-th stage. The specific signal to be selected can be set according to actual needs. When the pull-up module 110 receives the signal output by the ni-th stage gate drive unit 100, it pre-charges the drive control node Qn of the current stage to drive the output module 120.

[0035] In some embodiments, the output module 120 is configured to output the current stage transmission signal and the current stage gate drive signal under the action of the voltage on the current stage drive control node Qn and the current stage clock signal.

[0036] For example, when there is voltage on the drive control node and the current stage clock signal arrives, the output module 120 will be turned on, and the current stage transmission signal will be transmitted to drive the pixel.

[0037] In some embodiments, the control module 130 is configured to: during the scanning period of the current stage, issue the current stage transmission signal or the current stage gate drive signal output by the output module 120; and during the non-scanning period of the current stage and when the clock signal line CKm of the current stage receives a high-level signal, stop issuing the current stage transmission signal or the current stage gate drive signal output by the output module 120.

[0038] It should be noted that when the control module 130 is connected to the stage transmission output terminal of the output module 120, the stage transmission signal is output by the control module 130 for stage transmission, and the gate drive signal is output to the scan line to drive the pixel through the drive output terminal of the output module 120; when the control module 130 is connected to the drive output terminal of the output module 120, the gate drive signal is output to the scan line to drive the pixel through the control module 130, and the stage transmission signal is output by the stage transmission output terminal of the output module 120 for stage transmission.

[0039] It should be noted that in a scan signal frame, the scan period is the period during which the output module 120 receives the current stage clock signal and outputs the current stage gate drive signal and the current stage transmission signal under the action of the current stage drive control node voltage. The non-scan period is the remaining period.

[0040] For example, by connecting the control module 130 to the stage transmission output or drive output of the output module 120, the stage transmission signal or the gate drive signal of the current stage output by the output module 120 is emitted during the scanning period of the current stage. This ensures that the pull-up module 110 of the (n+i)th stage can receive the stage transmission signal or the gate drive signal of the current stage for stage transmission, and output the gate drive signal of the current stage to drive the pixel. During the non-scanning period of the current stage, when the clock signal of the current stage receives a high-level signal, the output module 120 is slightly turned on. The stage transmission output and drive output of the output module 120 may output a small high-level signal for stage transmission. By setting the control module 130 to stop emitting the stage transmission signal or the gate drive signal of the current stage output by the output module 120, the stage transmission signal and the gate drive signal of the current stage during the non-scanning period are small high-level signals. That is, the control module 130 stops emitting small high-level signals, and the small high-level signals will not accumulate for stage transmission and will not drive the pixel, thereby avoiding the occurrence of screen flicker.

[0041] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the control module 130 includes: a first control submodule 131 and a second control submodule 132. The first control submodule 131 is connected to the drive control node Qn-j of the nj-th level and is also connected to the stage transmission output or drive output of the output module 120. The second control submodule 132 is connected to the first control submodule 131 and the drive control node Qn+q of the n+q-th level, respectively.

[0042] In some embodiments, the first control submodule 131 is configured to: under the voltage action of the drive control node Qn-j of the njth stage, output the current stage transmission signal or the current stage gate drive signal output by the output module 120.

[0043] For example, j can be 1. When a voltage is generated on the drive control node Qn-j of the nj-th stage, the first control submodule 131 will be turned on in advance. When the clock signal of the current stage arrives, the output module 120 outputs the stage transmission signal or the gate drive signal of the current stage, and the first control submodule 131 will output the stage transmission signal or the gate drive signal of the current stage output by the output module 120. It should be noted that... Figure 2The diagram shows the connection between the first control submodule 131 and the stage transmission output terminal of the output module 120.

[0044] In some embodiments, the second control submodule 132 is configured to control the first control submodule 131 to stop outputting the current stage transmission signal or the current stage gate drive signal under the voltage action of the drive control node Qn+q of the n+q stage; where j is less than i and q represents the number of clock signal lines.

[0045] For example, q can be 6, and the clock signal is 6CK, indicating that there are 6 clock signal lines. When the clock signal of the (n+q)th stage returns, the clock signal line CKm of the current stage will also receive a high-level signal. When there is voltage at the drive control node Qn+q of the (n+q)th stage, it indicates that the clock signal of the (n+q)th stage is about to arrive. By setting the second control submodule 132 to be connected to the drive control node Qn+q of the (n+q)th stage, when the second control submodule 132 receives the voltage of the drive control node Qn+q of the (n+q)th stage, the second control submodule 132 will be turned on, controlling the first control submodule 131 to stop outputting the stage transmission signal or the gate drive signal of the current stage to cut off the stage transmission.

[0046] Figure 3 A circuit diagram of a first type of gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the first control submodule 131 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the drive control node Qn-j of the njth stage, the first terminal of the first transistor T1 is connected to the stage transmission output terminal Fn of the output module 120, and the second terminal of the first transistor T1 outputs the stage transmission signal of the current stage.

[0047] For example, Figure 4 This paper shows a first operating timing diagram of a gate driving unit according to an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 4 As shown, when the control terminal of the first transistor T1 receives the voltage of the drive control node Qn-j of the nj-th stage, it will conduct, and the stage transmission output terminal of the output module 120 will output the stage transmission signal. At the same time, the second terminal of the first transistor T1 will output the stage transmission signal of the current stage. In the figure, Qn-1 represents the drive control node of the (n-1)th stage, and Qn+6 represents the drive control node of the (n+6)th stage.

[0048] In some embodiments, the second control submodule 132 includes: a second transistor T2 and a third transistor T3; the control terminal of the second transistor T2 is connected to the drive control node Qn+q of the (n+q)th stage, the first terminal of the second transistor T2 is connected to the stage transmission output terminal of the output module 120, and the second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3; the first terminal of the third transistor T3 is connected to the output terminal of the first control submodule 131, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0049] For example, please refer to Figure 3 and Figure 4 As shown, when the control terminal of the second transistor T2 receives the voltage Qn+q from the drive control node of the (n+q)th stage, it indicates that the (n+q)th stage will receive a clock signal. The output module 120 of the current stage will also receive a high-level signal through the clock signal line CKm of the current stage. Due to parasitic capacitance, the output module 120 may be slightly turned on, and will output a small high-level signal for stage transmission. When the control terminal of the second transistor T2 receives the voltage Qn+q from the drive control node of the (n+q)th stage, the second transistor T2 will be turned on. When the small high-level signal output by the output module 120 is less than the turn-on threshold voltage of the third transistor T3... When the voltage of the third transistor T3 is not turned on, the voltage on the drive control node Qn-j of the nj stage is zero, and the first transistor T1 will not be turned on. Even if the first transistor T1 outputs a small high-level signal, it cannot turn on the pull-up module 110 of the n+i stage for cascading transmission. When the voltage of the small high-level signal output by the output module 120 is higher than the turn-on voltage threshold of the third transistor T3, the third transistor T3 will be turned on, pulling down the signal output terminal of the first control submodule 131 to a low potential. The first control submodule 131 will not output a small high-level signal for cascading transmission, thereby avoiding the occurrence of screen flicker.

[0050] In some embodiments, please refer to Figure 3 As shown, the pull-up module 110 includes an eighth transistor T8, the control terminal of the eighth transistor T8 is connected to the output terminal of the ni-th stage control module 130, and the first terminal of the eighth transistor T8 is connected to the drive output terminal of the ni-th stage output module 120.

[0051] For example, please refer to Figure 3 and Figure 4As shown, when the control terminal of the eighth transistor T8 receives the stage transmission signal output by the control module 130 of the ni-th stage, and the first terminal of the eighth transistor T8 receives the gate drive signal output by the drive output terminal of the output module 120 of the ni-th stage, the eighth transistor T8 is turned on to pre-charge the drive control node Qn of the current stage. It should be noted that when the control module 130 is connected to the drive output terminal of the output module 120, the control terminal of the eighth transistor T8 is connected to the stage transmission output terminal of the output module 120 of the ni-th stage, and the first terminal of the eighth transistor T8 is connected to the output terminal of the control module 130 of the ni-th stage. (Figure F) n-2 represents the transmission signal output terminal of the (n-2)th level control module, and Gn-2 represents the drive output terminal of the (n-2)th level output module.

[0052] In some embodiments, please refer to Figure 3 As shown, the output module 120 includes: a ninth transistor T9, a tenth transistor T10, and a fourth capacitor C4. The control terminals of the ninth transistor T9 and the tenth transistor T10 are connected to the first terminal of the fourth capacitor C4. The first terminal of the ninth transistor T9 is connected to the clock signal line CKm of the current stage, and the second terminal of the ninth transistor T9 serves as the stage output terminal. The first terminal of the tenth transistor T10 is connected to the clock signal line CKm of the current stage, and the second terminal of the tenth transistor T10 is connected to the second terminal of the fourth capacitor C4 and serves as the drive output terminal.

[0053] For example, when the voltage of the current stage's drive control node Qn is pre-charged, that is, the fourth capacitor C4 is pre-charged, when the current stage clock signal arrives, the fourth capacitor C4 will bootstrap the voltage of the current stage's drive control node Qn, the ninth transistor T9 and the tenth transistor T10 will be turned on, and the current stage transmission signal will be output for transmission. The tenth transistor T10 will output the current stage's gate drive signal to drive the pixel.

[0054] In some embodiments, the nth-level gate driving unit 100 further includes a pull-down module 140, which includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The control terminals of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are connected to the stage transmission output terminal Fn of the (n+k)th-level output module 120. The first terminal of the eleventh transistor T11 is connected to the drive control node Qn of the current level. The second terminals of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are connected to the low-level terminal VSS. The first terminal of the twelfth transistor T12 is connected to the output terminal of the control module 130, and the first terminal of the thirteenth transistor T13 is connected to the drive output terminal of the output module 120.

[0055] For example, when the control terminals of the eleventh transistor T11, twelfth transistor T12, and thirteenth transistor T13 receive the stage transmission signal of the (n+k)th stage, the eleventh transistor T11, twelfth transistor T12, and thirteenth transistor T13 will be turned on. The eleventh transistor T11 pulls down the current stage's drive control node Qn to a low potential, the twelfth transistor T12 pulls down the output terminal of the control module 130 to a low potential, and the thirteenth transistor T13 pulls down the drive output terminal of the output module 120 to a low potential, so as to precharge the current stage's drive control node Qn again when the next frame scan signal arrives. k can be 3, and Fn+3 in the figure represents the stage transmission output terminal of the (n+3)th stage output module.

[0056] Figure 5 A circuit diagram of a second type of gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 5 As shown, the first control submodule 131 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the drive control node Qn-j of the njth stage, the first terminal of the first transistor T1 is connected to the drive output terminal Gn of the output module 120, and the second terminal of the first transistor T1 outputs the gate drive signal of the current stage.

[0057] For example, please refer to Figure 5 and Figure 4 As shown, when the control terminal of the first transistor T1 receives the voltage of the drive control node Qn-j of the njth stage, the first transistor T1 will be turned on. When the output terminal of the output module 120 outputs the gate drive signal, the second terminal of the first transistor T1 will output the gate drive signal of the current stage.

[0058] In some embodiments, please refer to Figure 5 As shown, the second control submodule 132 includes a second transistor T2 and a third transistor T3; the control terminal of the second transistor T2 is connected to the drive control node Qn+q of the (n+q)th stage, the first terminal of the second transistor T2 is connected to the drive output terminal Gn of the output module 120, and the second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3; the first terminal of the third transistor T3 is connected to the output terminal of the first control submodule 131, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0059] For example, please refer to Figure 5 and Figure 4As shown, when the control terminal of the second transistor T2 receives the voltage Qn+q from the drive control node of the (n+q)th stage, it indicates that the (n+q)th stage will receive a clock signal. The output module 120 of the current stage will also receive a high-level signal through the clock signal line CKm of the current stage. Due to parasitic capacitance, the output module 120 may be slightly turned on, and will output a small high-level signal for stage transmission. When the control terminal of the second transistor T2 receives the voltage Qn+q from the drive control node of the (n+q)th stage, the second transistor T2 will be turned on. When the small high-level signal output by the output module 120 is less than the turn-on threshold voltage of the third transistor T3... When the voltage of the third transistor T3 is not turned on, the voltage on the drive control node Qn-j of the nj stage is zero, and the first transistor T1 will not be turned on. Even if the first transistor T1 outputs a small high-level signal, it cannot turn on the pull-up module 110 of the n+i stage for cascading transmission. When the voltage of the small high-level signal output by the output module 120 is higher than the turn-on voltage threshold of the third transistor T3, the third transistor T3 will be turned on, pulling down the signal output terminal of the first control submodule 131 to a low potential. The first control submodule 131 will not output a small high-level signal for cascading transmission, thereby avoiding the occurrence of screen flicker.

[0060] In some embodiments, please refer to Figure 5 As shown, the pull-up module 110 includes: an eighth transistor T8, the control terminal of the eighth transistor T8 is connected to the stage output terminal Fn of the ni-th stage output module 120, and the first terminal of the eighth transistor T8 is connected to the output terminal of the ni-th stage control module 130.

[0061] For example, when the control terminal of the eighth transistor T8 receives the stage transmission signal output from the stage transmission output terminal of the ni-th stage output module 120, and the first terminal of the eighth transistor T8 receives the gate drive signal output from the ni-th stage control module 130, the eighth transistor T8 is turned on to precharge the drive control node Qn of the current stage.

[0062] In some embodiments, the nth-level gate driving unit further includes a pull-down module 140, which includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The control terminals of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are connected to the stage transmission output terminal of the (n+k)th-level output module 120. The first terminal of the eleventh transistor T11 is connected to the driving control node Qn of the current level. The second terminals of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are connected to the low-level terminal VSS. The first terminal of the twelfth transistor T12 is connected to the stage transmission output terminal of the output module 120, and the first terminal of the thirteenth transistor T13 is connected to the output terminal of the control module 130.

[0063] For example, k can be 3. When the control terminals of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 receive the stage transmission signal of the (n+k)th stage, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 will be turned on. The eleventh transistor T11 pulls down the current stage drive control node Qn to a low potential, the twelfth transistor T12 pulls down the stage transmission output terminal of the output module 120 to a low potential, and the thirteenth transistor T13 pulls down the gate drive signal output terminal of the control module 130 to a low potential, so as to precharge the current stage drive control node Qn again when the next frame scan signal arrives.

[0064] Figure 6 A circuit diagram of a third type of gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 6 As shown, the first control submodule 131 includes: a first transistor T1 and a first capacitor C1; the control terminal of the first transistor T1 is connected to the drive control node Qn-j of the njth stage and the first terminal of the first capacitor C1, the first terminal of the first transistor T1 is connected to the stage transmission output terminal Fn or the drive output terminal Gn of the output module 120, the second terminal of the first transistor T1 is connected to the second terminal of the first capacitor C1, and outputs the stage transmission signal of the current stage or the gate drive signal of the current stage.

[0065] For example, please refer to Figure 6 As shown, by setting the first capacitor C1, when the control terminal of the first transistor T1 and the first terminal of the first capacitor C1 simultaneously receive the voltage on the drive control node Qn-j of the nj-th stage, the voltage on the drive control node Qn-j of the nj-th stage will precharge the first capacitor C1. When the output module 120 outputs the stage transmission signal or the gate drive signal of the current stage, it will promote the first transistor T1 to conduct. The stage transmission signal or the gate drive signal output by the output module 120 will quickly pass through the first transistor T1, and the first transistor T1 will quickly output the output stage transmission signal or the gate drive signal of the current stage. It should be noted that... Figure 6 This shows the connection between the control module 130 and the output module 120 at the stage transmission output terminal.

[0066] Figure 7 A circuit diagram of a fourth gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 7As shown, the second control submodule 132 includes: a second capacitor C2, a second transistor T2, and a third transistor T3; the first terminal of the second capacitor C2 is connected to the drive control node Qn+q of the (n+q)th stage; the control terminal of the second transistor T2 is connected to the second terminal of the second capacitor C2, the first terminal of the second transistor T2 is connected to the stage transmission output terminal Fn or the drive output terminal Gn of the output module 120, and the second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3; the first terminal of the third transistor T3 is connected to the output terminal of the first control submodule 131, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0067] For example, by setting a second capacitor C2, when there is voltage on the (n+q)th stage drive control node Qn+q, the second capacitor C2 will be charged. The voltage of the second capacitor C2 will be transmitted to the control terminal of the second transistor T2, and the second transistor T2 will be turned on. When the output module 120 stage output terminal or drive output terminal outputs a small high-level signal, it will be transmitted to the third transistor T3 through the second transistor T2. After the third transistor T3 is turned on, the second terminal of the first transistor T1 is pulled down to a low potential, and the first transistor T1 will not output a small high-level signal for cascading transmission. By setting the second capacitor C2, when the second capacitor C2 is pre-charged, it will continuously control the second transistor T2 to continue to be turned on, further ensuring that the third transistor T3 is turned on, pulling down the second terminal of the first transistor T1 to a low potential, thus ensuring that cascading transmission is avoided. It should be noted that... Figure 7 This shows the case where the first terminal of the second transistor T2 is connected to the stage output terminal of the output module 120.

[0068] In some embodiments, please refer to Figure 7 As shown, the second control submodule 132 further includes: a fourth transistor T4; the control terminal of the fourth transistor T4 is connected to the reset control terminal Reset, the first terminal of the fourth transistor T4 is connected to the second terminal of the second capacitor C2, and the second terminal of the fourth transistor T4 is connected to the low-level terminal VSS.

[0069] For example, the reset control terminal Reset can be the output terminal of the controller, and the controller can be a timing controller. When the control of the fourth transistor T4 receives the reset control signal output by the reset control terminal Reset during the vertical blanking period, the fourth transistor T4 pulls down the second terminal of the second capacitor C2 to a low potential, and the second transistor T2 will be turned off. In the next frame scan signal, the second transistor T2 remains disconnected from the third transistor T3, and the current stage's transmission signal or the current stage's gate drive signal can be output through the second terminal of the first transistor T1, and the second capacitor C2 is charged again when the clock signal line of the current stage receives a high-level signal.

[0070] Figure 8 A circuit diagram of the fifth gate driving unit provided in this application embodiment is shown. Please refer to [link / reference]. Figure 8 As shown, the nth stage gate drive unit 100 further includes a third control submodule 133, which is connected to the stage transmission output terminal Fn or the drive output terminal Gn of the output module 120, and is also connected to the current stage drive control node Qn, the (n+q)th stage drive control node Qn+q, and the current stage discharge control node An. It is configured to generate a voltage on the current stage discharge control node An under the action of the voltage of the current stage drive control node Qn, the stage transmission signal of the current stage, and the voltage of the (n+q)th stage drive control node Qn+q, or under the action of the voltage of the current stage drive control node Qn, the current stage gate drive signal, and the voltage of the (n+q)th stage drive control node Qn+q.

[0071] For example, Figure 9 This paper shows a second operating timing diagram of a gate driving unit according to an embodiment of this application. Please refer to [link / reference]. Figure 8 and Figure 9 As shown, when there is voltage on the current stage drive control node Qn, the current stage transmission signal and the current stage gate drive signal will be output simultaneously when the current stage clock signal arrives. q is the number of clock signal lines. When there is voltage on the (n+q)th stage drive control node Qn+q, it indicates that the (n+q)th stage drive control node Qn+q has been precharged. The (n+q)th stage clock signal will pass through, and the current stage clock signal will receive a high-level signal. When the third control submodule 133 receives the voltage on the current stage drive control node Qn and the current stage transmission signal, or receives the current stage drive control node Qn and the current stage gate drive signal, it can store the control voltage. Under the action of the (n+q)th stage drive voltage, a voltage is generated on the current stage discharge control node An to act on the discharge submodule 134.

[0072] In some embodiments, the discharge submodule 134, connected to the discharge control node An and the drive control node Qn of the current stage, is configured to pull down the drive control node Qn of the current stage to a low potential under the voltage action of the discharge control node An of the current stage.

[0073] For example, the voltage of the discharge control node An of the current stage is generated when there is a voltage on the drive control node Qn+q of the (n+q)th stage. Even when the clock signal of the (n+q)th stage returns to the current stage, under the action of the voltage of the discharge control node An of the current stage, the drive control node Qn of the current stage is pulled down to a low potential. When the drive control node of the output module 120 is pulled down to a low potential, the output module 120 will not be micro-conducted and will not output a small high-level signal, thus preventing stage transmission. At the stage transmission output terminal F of the current stage... When n is pulled down to a low potential, even if the output module 120 is slightly turned on, the current stage's transmission output terminal Fn will not output a small high-level signal, thus preventing transmission. When the current stage's drive output terminal Gn is pulled down to a low potential, even if the output module 120 is slightly turned on, the current stage's drive output terminal Gn will not output a small high-level signal, thus preventing transmission. The pull-up module 110 of the (n+i)th stage will not be turned on, avoiding the accumulation of small high-level signals and further preventing screen flicker on the display panel.

[0074] In some embodiments, the third control submodule 133 includes: a fifth transistor T5, a third capacitor C3, and a sixth transistor T6; the control terminal of the fifth transistor T5 is connected to the stage transmission output terminal Fn or the drive output terminal Gn of the output module 120, the first terminal of the fifth transistor T5 is connected to the drive control node Qn of the current stage, and the second terminal of the fifth transistor T5 is connected to the first terminal of the third capacitor C3; the second terminal of the third capacitor C3 and the first terminal of the sixth transistor T6 are connected to the precharge control node Bn of the current stage; the control terminal of the sixth transistor T6 is connected to the drive control node Qn+q of the (n+q)th stage, and the second terminal of the sixth transistor T6 is connected to the discharge control node An of the current stage.

[0075] In some embodiments, the discharge submodule 134 includes: a seventh transistor T7; the control terminal of the seventh transistor T7 is connected to the discharge control node An of the current stage, the first terminal of the seventh transistor T7 is connected to the drive control node Qn of the current stage, and the second terminal of the seventh transistor T7 is connected to the low-level terminal VSS.

[0076] For example, when the control terminal of the fifth transistor T5 receives the stage transmission signal or the gate drive signal of the current stage, it will charge the third capacitor C3, thereby generating a voltage at the pre-charge control node Bn of the current stage. When there is a voltage at the drive control node Qn+q of the n+q stage, the sixth transistor T6 will be turned on, thereby generating a voltage at the discharge control node An of the current stage. The discharge control node An of the current stage will control the seventh transistor T7 to be turned on, thereby pulling down the drive control node Qn of the current stage to a low potential. As a result, the output module 120 will not be micro-conducted and will not output a small high-level signal, further avoiding the screen flicker phenomenon.

[0077] In some embodiments, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the gate driving circuit described above. When the control module of the gate driving circuit is connected to the stage transmission output terminal of the output module, the drive output terminal of the output module is connected to at least one of the scan lines; or, when the control module of the gate driving circuit is connected to the drive output terminal of the output module, the output terminal of the control module is connected to at least one scan line.

[0078] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0079] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0080] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the current stage's drive control node, is configured to charge the current stage's drive control node in response to the output signal of the ni-th stage's gate drive unit. The output module, connected to the drive control node and clock signal line of the current stage, is configured to output the stage transmission signal and the gate drive signal of the current stage under the action of the voltage on the drive control node and the clock signal of the current stage. The control module includes: a first control submodule and a second control submodule; The first control submodule is connected to the drive control node of the njth stage and also to the stage transmission output terminal or drive output terminal of the output module. It is configured to: under the voltage action of the drive control node of the njth stage, output the stage transmission signal of the current stage or the gate drive signal of the current stage output by the output module. The second control submodule, which is connected to the first control submodule and the drive control node of the (n+q)th stage, is configured to: under the voltage action of the drive control node of the (n+q)th stage, control the first control submodule to stop issuing the stage transmission signal or the gate drive signal of the current stage; wherein, j is less than i, and q represents the number of clock signal lines; The discharge submodule, connected to the discharge control node and the drive control node of the current stage, is configured to pull the drive control node of the current stage down to a low potential under the voltage action of the discharge control node of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The first control submodule includes: a first transistor; The control terminal of the first transistor is connected to the drive control node of the njth stage, the first terminal of the first transistor is connected to the stage transmission output terminal or drive output terminal of the output module, and the second terminal of the first transistor outputs the stage transmission signal of the current stage or the gate drive signal of the current stage.

3. The gate driving circuit according to claim 1, characterized in that, The second control submodule includes: a second transistor and a third transistor; The control terminal of the second transistor is connected to the drive control node of the (n+q)th stage, the first terminal of the second transistor is connected to the stage transmission output terminal or drive output terminal of the output module, and the second terminal of the second transistor is connected to the control terminal of the third transistor. The first terminal of the third transistor is connected to the output terminal of the first control submodule, and the second terminal of the third transistor is connected to the low-level terminal.

4. The gate driving circuit according to claim 1, characterized in that, The first control submodule includes: a first transistor and a first capacitor; The control terminal of the first transistor is connected to the drive control node of the njth stage and the first terminal of the first capacitor. The first terminal of the first transistor is connected to the stage transmission output terminal or drive output terminal of the output module. The second terminal of the first transistor is connected to the second terminal of the first capacitor and outputs the stage transmission signal of the current stage or the gate drive signal of the current stage.

5. The gate driving circuit according to claim 1, characterized in that, The second control submodule includes: a second capacitor, a second transistor, and a third transistor; The first terminal of the second capacitor is connected to the drive control node of the (n+q)th stage; The control terminal of the second transistor is connected to the second terminal of the second capacitor, the first terminal of the second transistor is connected to the stage transmission output terminal or drive output terminal of the output module, and the second terminal of the second transistor is connected to the control terminal of the third transistor. The first terminal of the third transistor is connected to the output terminal of the first control submodule, and the second terminal of the third transistor is connected to the low-level terminal.

6. The gate driving circuit according to claim 5, characterized in that, The second control submodule also includes: a fourth transistor; The control terminal of the fourth transistor is connected to the reset control terminal, the first terminal of the fourth transistor is connected to the second terminal of the second capacitor, and the second terminal of the fourth transistor is connected to the low-level terminal.

7. The gate driving circuit according to claim 1, characterized in that, The nth-stage gate driving unit further includes: The third control submodule is connected to the stage transmission output or drive output of the output module, and is also connected to the drive control node of the current stage, the drive control node of the (n+q)th stage, and the discharge control node of the current stage. It is configured to generate a voltage on the discharge control node of the current stage under the action of the voltage of the drive control node of the current stage, the stage transmission signal of the current stage, and the voltage of the drive control node of the (n+q)th stage, or under the action of the voltage of the drive control node of the current stage, the gate drive signal of the current stage, and the voltage of the drive control node of the (n+q)th stage.

8. The gate driving circuit according to claim 7, characterized in that, The third control submodule includes: a fifth transistor, a third capacitor, and a sixth transistor; The control terminal of the fifth transistor is connected to the stage transmission output terminal or drive output terminal of the output module, the first terminal of the fifth transistor is connected to the drive control node of the current stage, and the second terminal of the fifth transistor is connected to the first terminal of the third capacitor. The second terminal of the third capacitor is connected to the first terminal of the sixth transistor at the precharge control node of the current stage; The control terminal of the sixth transistor is connected to the drive control node of the (n+q)th stage, and the second terminal of the sixth transistor is connected to the discharge control node of the current stage.

9. The gate driving circuit according to claim 1, characterized in that, The discharge submodule includes: a seventh transistor; The control terminal of the seventh transistor is connected to the discharge control node of the current stage, the first terminal of the seventh transistor is connected to the drive control node of the current stage, and the second terminal of the seventh transistor is connected to the low-level terminal.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein when the control module of the gate driving circuit is connected to the stage transmission output terminal of the output module, the drive output terminal of the output module is connected to at least one of the scan lines; or, when the control module of the gate driving circuit is connected to the drive output terminal of the output module, the output terminal of the control module is connected to at least one of the scan lines.

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