Method and apparatus for assembling memory modules

Abstract

The application discloses a memory module assembling method and equipment, and relates to the technical field of storage, and discloses that the memory module comprises a plurality of memory particles, and the memory module assembling method comprises the following steps: providing test excitation to the plurality of memory particles in sequence, when any memory particle receives the test excitation and is in an excitation state, controlling the rest of the plurality of memory particles to be in a dormant state; acquiring the current value of the input end of a power management chip when the memory particle is in the excitation state; calculating the power consumption value of the memory particle in the excitation state according to the current value of the input end of the power management chip; classifying the plurality of memory particles according to the power consumption value of each memory particle to obtain a classification result; and performing assembling processing on the plurality of memory particles according to the classification result. The application is beneficial to improving the production quality and stability of the memory module and guaranteeing the reliable operation of equipment.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a method and apparatus for assembling memory modules. Background Technology

[0002] During the use of a memory module, operating parameters (such as operating current and operating temperature) are evenly distributed across all memory chips. If the operating parameters of one memory chip differ significantly from those of the other memory chips, the problem cannot be detected from the average data of the operating parameters. This results in the inability to guarantee the consistency of the chips in the entire memory module, leading to a decrease in the reliability of the memory module.

[0003] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this invention is to provide a method and equipment for assembling memory modules, which aims to improve the production quality and stability of memory modules and ensure the reliable operation of the equipment.

[0005] To achieve the above objectives, the present invention proposes a method for assembling a memory module, wherein the memory module comprises multiple memory chips, and the method for assembling the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When the memory chip is in an energized state, obtain the current value at the input terminal of the power management chip; The power consumption of the memory chip in the energized state is calculated based on the current value at the input terminal of the power management chip. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

[0006] This invention proposes a method for assembling a memory module, the memory module comprising multiple memory chips and a power management chip; the method for assembling the memory module comprises: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a sleep state, the current value at the input terminal of the power management chip is obtained and recorded as the first current value. When the memory chip is in an energized state, the current value at the input terminal of the power management chip is obtained and recorded as the second current value; Calculate the power consumption of the memory chip in the excited state based on the first current value and the second current value; The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

[0007] This invention proposes a method for assembling a memory module, the memory module comprising multiple memory chips and a power management chip; the method for assembling the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a sleep state, the power consumption value at the input terminal of the power management chip is obtained and recorded as the first power consumption value. When the memory chip is in an energized state, the power consumption value at the input terminal of the power management chip is obtained and recorded as the second power consumption value; Calculate the power consumption value of the memory chip in the energized state based on the first power consumption value and the second power consumption value; The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

[0008] This invention proposes a method for assembling a memory module, the memory module comprising multiple memory chips, a power management chip, and a register clock driver; the method for assembling the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a dormant state, the current value at the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller to obtain the current consumption value of the register clock driver. When the memory chip is in an energized state, the current value at the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller, so as to obtain the current value of the memory chip in the energized state and the register clock driver. The power consumption of the memory chip in the energized state is calculated based on the current consumption value and the current values ​​of the memory chip in the energized state and the register clock driver. Alternatively, when all memory chips in multiple memory chips are in a sleep state, the power consumption value of the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller to obtain the power consumption value of the register clock driver. When the memory chip is in an excited state, the power consumption value at the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller, so as to obtain the power consumption value of the memory chip in the excited state and the register clock driver. The power consumption value of the memory chip in the energized state is calculated based on the current consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

[0009] This invention proposes a method for assembling a memory module, the memory module comprising multiple memory chips, a power management chip, and a register clock driver; the method for assembling the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a dormant state, the voltage value of the input terminal of the memory chip is obtained through an ADC sampler and a microcontroller, and the current consumption value of the register clock driver is calculated based on the voltage value. When the memory chip is in an excited state, the voltage value at the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to obtain the current value of the memory chip in the excited state and the register clock driver based on the voltage value. The power consumption of the memory chip in the energized state is calculated based on the current consumption value and the current values ​​of the memory chip in the energized state and the register clock driver. Alternatively, when all memory chips in multiple memory chips are in a sleep state, the power consumption value of the input terminal of the memory chip is obtained through an ADC sampler and a microcontroller, and the power consumption value of the register clock driver is calculated based on the power consumption value of the input terminal of the memory chip. When the memory chip is in an excited state, the power consumption value at the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to obtain the power consumption value of the memory chip in the excited state and the register clock driver based on the power consumption value at the input terminal of the memory chip. The power consumption value of the memory chip in the energized state is calculated based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

[0010] This invention proposes a method for assembling a memory module, the memory module comprising multiple memory chips, a power management chip, and a register clock driver; the method for assembling the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a sleep state, the processor obtains the current value of the output terminal of the power management chip through the power management chip, and calculates the power consumption value of the register clock driver based on the current value. When the memory chip is in an energized state, the processor obtains the current value at the output terminal of the power management chip through the power management chip, and obtains the power consumption value of the memory chip in the energized state and the register clock driver based on the current value. The power consumption value of the memory chip in the energized state is calculated based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. Alternatively, when all memory chips in multiple memory chips are in a sleep state, the processor obtains the current and voltage values ​​at the output terminal of the power management chip through the power management chip, and calculates the power consumption value of the register clock driver based on the current and voltage values ​​at the output terminal of the power management chip. When the memory chip is in an energized state, the processor obtains the current and voltage values ​​at the output terminal of the power management chip through the power management chip, so as to obtain the power consumption values ​​of the memory chip and the register clock driver in the energized state based on the current and voltage values ​​at the output terminal of the power management chip. The power consumption value of the memory chip in the energized state is calculated based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

[0011] This invention proposes a method for assembling a memory module, the memory module comprising multiple memory chips; the method for assembling the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. Obtain the static power consumption value of the memory module when all memory chips in multiple memory chips are in a sleep state; Obtain the power consumption value of the memory module when any memory chip is under test stimulus; The power consumption value of the memory chip in the activated state is calculated based on the operating power consumption value and the static power consumption value. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

[0012] In one embodiment, the step of classifying the multiple memory chips according to the power consumption value of each memory chip specifically includes: Calculate the power consumption difference between each of the memory chips; When the power consumption difference between any memory chip and the other memory chips is not greater than a preset difference, the corresponding memory chip is classified as a first-class memory chip. When the power consumption difference between any memory chip and the other memory chips is greater than the preset difference, the corresponding memory chip is classified as a second type of memory chip.

[0013] In one embodiment, the step of classifying the multiple memory chips according to the power consumption value of each memory chip specifically includes: Calculate the power consumption difference between each of the memory chips and the memory chip with the lowest power consumption value among the plurality of memory chips; When the power consumption difference is not greater than a preset difference, the corresponding memory chip is classified as a first type of memory chip; When the power consumption difference is greater than the preset difference, the corresponding memory chip is classified as a second type of memory chip.

[0014] In one embodiment, the step of classifying the multiple memory chips according to the power consumption of each memory chip specifically includes: Calculate the relative power consumption deviation between each memory chip and the other memory chips, and compare the relative power consumption deviation between each memory chip and the other memory chips with a preset threshold; When the relative power consumption deviation is not greater than a preset deviation threshold, the corresponding memory chip is classified as a first type of memory chip; When the relative power consumption deviation is greater than the preset deviation threshold, the corresponding memory chip is classified as a second type of memory chip.

[0015] In one embodiment, the memory module further includes a PCB, and the memory chips are mounted on the PCB. The step of assembling multiple memory chips according to the classification result specifically includes: Perform margin testing on the data retention capability of memory particles classified as Category II; When the data retention capability of memory chips classified as Category II is not within a preset range, the memory chip is removed from the PCB; and / or, the refresh frequency of memory chips classified as Category II is updated; and / or, the temperature threshold for frequency refresh of memory chips classified as Category II is adjusted.

[0016] In one embodiment, the step of classifying the multiple memory chips according to the power consumption value of each memory chip specifically includes: The power consumption value of each memory chip is matched with a preset power consumption value range to classify the multiple memory chips. Alternatively, the power consumption values ​​of each memory chip can be input into a clustering model to classify the multiple memory chips.

[0017] In one embodiment, the memory module further includes a PCB, and the step of assembling the multiple memory chips according to the classification result specifically includes: Memory chips of the same type are mounted on the same PCB.

[0018] In one embodiment, test stimuli are provided to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state, a timer is started, and the power consumption value of the memory chip in the stimulated state is obtained. When the power consumption value of the memory chip in the excited state reaches the target power consumption value, stop timing and obtain the time consumed by the memory chip in the excited state. The memory chips are classified according to the consumption time of the memory chips in the energized state; Based on the classification results, multiple memory chips are assembled.

[0019] The present invention also proposes an assembly device for a memory module, comprising: The test driver unit is used to provide test stimuli to the memory chips on the memory module. The temperature chamber is used to provide the temperature testing environment required for testing memory chips on the memory module; the assembly equipment also includes: The memory, the processor, and a computer program stored on the memory chip and executable on the processor, the computer program being configured to implement the steps of the assembly method for the memory module as described above.

[0020] This invention can be applied before or after memory module assembly to ensure that the operating temperature of each memory chip in the memory module is as uniform as possible. This avoids data loss, system instability, or crashes caused by uneven temperature due to large differences in power consumption parameters of memory chips during the use of the memory module. In addition, it can screen memory modules with a small number of chips that have abnormal power consumption due to the assembly process, thereby improving the production quality and stability of memory modules, ensuring reliable operation of equipment, and facilitating practical application and promotion. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating the first embodiment of the assembly method for the memory module of the present invention. Figure 2 A flowchart illustrating the assembly method of the memory module of the present invention in a second embodiment; Figure 3 This is a flowchart illustrating the third embodiment of the assembly method for the memory module of the present invention. Figure 4 This is a flowchart illustrating the fourth embodiment of the assembly method for the memory module of the present invention. Figure 5 This is a flowchart illustrating the fifth embodiment of the assembly method for the memory module of the present invention. Figure 6 This is a flowchart illustrating the sixth embodiment of the assembly method for the memory module of the present invention. Figure 7 This is a flowchart illustrating the seventh embodiment of the assembly method for the memory module of the present invention. Figure 8 This is a flowchart illustrating the eighth embodiment of the assembly method for the memory module of the present invention. Figure 9 This is a flowchart illustrating the ninth embodiment of the assembly method for the memory module of the present invention. Figure 10 This is a flowchart illustrating the tenth embodiment of the assembly method for the memory module of the present invention. Figure 11 for Figure 10 In step S200, a detailed flowchart of Example 1 is provided; Figure 12 for Figure 10 In step S200, a detailed flowchart of Example 2 is provided; Figure 13 for Figure 10 In step S300, a detailed flowchart of Example 1 is provided; Figure 14 This is a flowchart illustrating a second embodiment of the assembly method for the memory module of the present invention. Figure 15 This is a schematic diagram of the circuit structure of the memory module under test, which is connected to the BMC, BIOS and ADC sampler of the present invention. Figure 16 This is a temperature-data retention capability curve of memory chips tested using the assembly method of the memory module of the present invention; Figure 17 A schematic diagram of the circuit structure of the memory module under test connected to an ADC sampler; Figure 18 A comparison chart of current data of three memory chips tested using the assembly method of the memory module of the present invention; Figure 19 This is a schematic diagram of the hardware operating environment involved in the structural diagram of the memory module assembly equipment provided in Embodiment 1 of the present invention. Figure 20 A power consumption classification diagram of memory chips tested using the assembly method of the memory module of the present invention; Figure 21 The current sampling curve of the memory chip tested using the assembly method of the memory module of the present invention is shown. Figure 22 This is a schematic diagram of the hardware operating environment involved in the assembly equipment of the memory module in this embodiment of the invention.

[0024] The objectives, functional characteristics, and optimal time periods of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the present invention and are not intended to limit the present invention.

[0026] To better understand the technical solution of the present invention, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0027] This invention proposes a method for assembling memory modules, applied in the production of memory modules. Each memory module includes a PCB (Printed Circuit Board), memory chips mounted on the PCB, and a power management IC (PMIC) mounted on the PCB for supplying power to the memory chips. The memory module can be a DIMM (Intelligent Registered Dual In-line Memory Module). Depending on the memory size, each memory module can have a different number of memory chips mounted, which can be DRAM (Dynamic Random Access Memory). During use, the operating parameters (e.g., operating current, operating temperature) of the memory module are evenly distributed across all memory chips. If the operating parameters of one memory chip differ significantly from those of the other chips, the problem cannot be detected from the average data of the operating parameters. This leads to a lack of consistency in the overall memory module's components, resulting in reduced reliability.

[0028] Taking DRAM as an example, DRAM stores data using small internal capacitors. These capacitors are prone to leakage under real-world conditions. The charge retention capability of these capacitors is collectively expressed as the DRAM's Data Retention parameter; a higher value indicates stronger charge retention. Due to device variability, different devices have different Data Retention values. Testing requires identifying devices that do not meet the JEDEC standard. Furthermore, Data Retention is strongly correlated with operating temperature. To compensate for leakage, DRAM employs a refresh mechanism, using regular refresh cycles to prevent data loss. To simplify testing and ensure safety, JEDEC defines temperature-based processing strategies. For example, when the temperature exceeds 85°C, faster refresh is initiated. When using DRAM memory in a system, the refresh strategy is simplified to execute a refresh strategy at temperatures ≤85°C, rather than relaxing refresh based on the Data Retention curve. Similarly, when the temperature rises above 85°C, the refresh rate does not gradually increase along the curve but doubles. Therefore, DRAM chips require quality control at 85°C during factory testing to ensure the safety of customer system applications. However, when DRAM chips are assembled into DRAM modules, the temperature control of the DRAM module does not measure the temperature of each individual DRAM chip, but rather the temperature of the entire module. If a memory chip overheats, the system will sense the temperature of the memory module based on the average value. In this case, the system refreshes at the normal temperature. However, if the temperature of individual memory chips exceeds the standard threshold, a higher refresh rate is required to avoid data loss. Refreshing at the normal temperature will lead to instability during the use of the memory module, thus affecting the overall operating status of the device. For example, the Trefi (Time Refresh Interval) of the DRAM chips used in a certain DRAM memory module depends on the case temperature. When the case temperature is ≤85℃, the maximum average refresh interval is Trefi; when 85℃ < case temperature ≤95℃, the maximum average refresh interval is Trefi / 2.

[0029] The temperature of memory chips is positively correlated with their power consumption; that is, the higher the power consumption of a memory chip, the higher its temperature. Due to the compact spatial layout and small size of memory modules, it is difficult to measure the temperature of individual memory chips. Usually, the overall temperature of the memory module is measured, and the refresh rate is determined based on the overall temperature of the memory module. The diagram shows the temperature distribution of the memory chips in a memory module. The second memory chip has a significantly higher operating temperature than the others. The system detects a problem with the memory module based on the average temperature and refreshes at the normal temperature. However, because the second memory chip's operating temperature is significantly higher than the others, refreshing at the normal temperature may result in the loss of data stored in the second memory chip, affecting the overall operation of the device.

[0030] Reference Figure 1 In one embodiment of the present invention, the assembly method of the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. In this embodiment, the test stimulus can be provided by a test driver unit. The test driver unit generates a high dynamic power consumption test stimulus, putting the memory chips in an excited state, allowing them to run at the highest possible power consumption. During the test, the first memory chip can be configured to leave its sleep state, while the remaining chips remain in sleep state. Simultaneously, the test driver unit is activated to use a high-power stimulus to make the first memory chip work, and its power consumption value is measured. Then, the second memory chip is configured to leave its sleep state, while the remaining chips remain in sleep state, and its power consumption value is measured. This process is repeated until the last memory chip is measured, obtaining the power consumption values ​​of all memory chips.

[0031] Step S111: With the memory chip in an energized state, obtain the current value at the input terminal of the power management chip; Step S112: Calculate the power consumption of the memory chip in the energized state based on the current value at the input terminal of the power management chip.

[0032] In this embodiment, the power management chip typically converts the input DC power supply into the operating power required by the memory chips on the memory module, thus powering the memory chips. For example, it converts 12V or 5V DC to 1.1V DC and outputs it to the memory chips. Since the power management chip needs to power multiple memory chips, the internal space of the memory module is small, and the power consumption of the module is generated by combining circuits, making it impossible to directly measure the power consumption of a single chip from the module interface, it is impossible to measure the current of each memory chip individually. This makes it impossible to know the power consumption value of an individual memory chip.

[0033] Since the power consumption of a power management chip can be divided into two parts—its own power consumption and the power output to the memory chips—the power consumption of the power management chip is the same or similar when the memory chips are operating under the same conditions. Therefore, the power consumption of the power management chip can be considered a fixed value. With a constant voltage, the current input to the power management chip over a period of time is measured. Specifically, a current detection circuit can be set at the input terminal of the power management chip to obtain the input current. Based on the power consumption calculation formula, the power consumption values ​​of the power management chip and the memory chips can be determined. When calculating the difference between the power consumption values ​​of the two memory chips, since the power consumption value of the power management chip remains constant, the difference cancels out the influence of the power management chip's power consumption value. This difference is the power consumption difference between the two memory chips. This indirect method of determining the power consumption difference between memory chips solves the problem that the power consumption of the module is generated by the combined circuit, making it impossible to directly measure the power consumption of a single chip from the module interface, thus preventing the individual measurement of the current of each memory chip and thus making it impossible to know the power consumption value of an individual memory chip. The current detection circuit can be implemented using discrete components such as resistors. The current value detected by the current detection circuit can be output to the processor, which calculates the power consumption value according to the power consumption calculation formula.

[0034] Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; In this embodiment, memory chips with the same power consumption value can be grouped into the same category, or memory chips with power consumption values ​​within the same power range can be grouped into the same category, or clustering algorithms can be used to classify multiple memory chips. The power consumption values ​​of memory chips within the same category can all be high or all be low. For example, memory chips with consistently high power consumption values ​​can be grouped into the first category, and the other memory chips can be grouped into the second category.

[0035] Step S300: Based on the classification results, assemble the multiple memory chips.

[0036] In this embodiment, different assembly processes can be adopted depending on whether the memory chips are mounted on the PCB. Furthermore, different assembly processes are applied after the memory chips are mounted on the PCB, based on different classification results. For example, before mounting the memory chips on the PCB (i.e., before assembly), memory chips of the same type can be mounted on the same PCB. After mounting the memory chips (i.e., after assembly), if the power consumption of the memory chips is inconsistent based on the power consumption value, memory chips of different types can be discarded. Alternatively, depending on the specific power consumption of the second type of memory chip, the refresh rate can be increased, and the temperature threshold at which the refresh rate is decreased can be adjusted. If the power consumption is sufficient to withstand the temperature rise and will not negatively impact the data retention capability of the memory chip, then the second type of memory chip can continue to be mounted on the PCB without any further processing.

[0037] This invention can be applied before or after memory module assembly to ensure that the operating temperature of each memory chip in the memory module is as uniform as possible. This avoids data loss, system instability, or crashes caused by uneven temperature due to large differences in power consumption parameters of memory chips during the use of the memory module. In addition, it can screen memory modules with a small number of chips that have abnormal power consumption due to the assembly process, thereby improving the production quality and stability of memory modules, ensuring reliable operation of equipment, and facilitating practical application and promotion.

[0038] The second embodiment, referred to Figure 2 The present invention also proposes a method for assembling a memory module, wherein the memory module further includes a power management chip; the method for assembling the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S121: When all memory chips in multiple memory chips are in a sleep state, obtain the current value at the input terminal of the power management chip and record it as the first current value. Step S122: With the memory chip in an energized state, obtain the current value at the input terminal of the power management chip and record it as the second current value; Step S123: Calculate the power consumption of the memory chip in the energized state based on the first current value and the second current value. In practical applications, all memory chips can be controlled to be in a sleep state. The current at the power input terminal of the power management chip is measured by a current sampling circuit, such as an ADC, and recorded as the first current. Ip=I PMIC+SLEEP (1) One memory chip at a time was de-energized from its sleep state and brought into the active state. While in the active state, the current at the power input terminal of the power management chip was measured and denoted as I. PMIC+DRAM（A） I PMIC+DRAM（B） I PMIC+DRAM（A） I PMIC+DRAM（B） ... I p +a =I PMIC+DRAM(A) (2) Among them, I p +a This represents the current at the power input terminal of the power management chip, i.e., the first current value, I. PMIC+DRAM(A) This represents the current flowing through the power management chip and memory chip A, i.e., the second current value; Subtracting equations (1) and (2) from each other, we obtain the current of each memory chip, denoted as: Ia = Ip + a - Ip According to P=V I. Calculate the power consumption value of each memory chip: Pa=V Ia Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble the multiple memory chips. The working principles and technical effects of steps S100, S200, and S300 in this embodiment are the same as in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0039] The third embodiment, referred to Figure 3 The present invention also proposes a method for assembling a memory module, the memory module comprising multiple memory chips and a power management chip; the method for assembling the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S131: When all memory chips in multiple memory chips are in a sleep state, obtain the power consumption value at the input terminal of the power management chip and record it as the first power consumption value. Step S132: When the memory chip is in an excited state, obtain the power consumption value at the input terminal of the power management chip and record it as the second power consumption value; Step S133: Calculate the power consumption value of the memory chip in the energized state based on the first power consumption value and the second power consumption value.

[0040] Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble the multiple memory chips. The working principles and technical effects of steps S100, S200, and S300 in this embodiment are the same as in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0041] In this embodiment, power can also be directly measured using an ADC sampler with computational capabilities. For example, when the memory chip is in sleep mode, the power consumption of the PMIC, i.e., the power consumption value at the input terminal of the power management chip, can be measured using an ADC sampler. Pp = PMIC + SLEEP [+RCD] (3) Release one memory chip from sleep mode sequentially, and measure the power consumption of PMIC+DRAM(A)[+RCD], PMIC+DRAM(B)[+RCD], PMIC+DRAM(C)[+RCD], and PMIC+DRAM(D)[+RCD]. For example: Pp+a=PMIC+DRAM(A)[+RCD](4) Subtracting equations (3) and (4) from each yields the power consumption of each DRAM chip: Pa = Pp + a - Pp; Where Pa is the power consumption of each DRAM chip, Pp + a is the second power consumption value, and Pp is the first power consumption value.

[0042] Fourth embodiment, referring to Figure 4 The present invention also proposes a method for assembling a memory module, wherein the memory module further includes a power management chip and a register clock driver; the method for assembling the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S141: When all memory chips in multiple memory chips are in a sleep state, the current value of the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller to obtain the current consumption value of the register clock driver. Step S142: When the memory chip is in an excited state, the current value of the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller, so as to obtain the current value of the memory chip in the excited state and the register clock driver. Step S143: Calculate the power consumption value of the memory chip in the energized state based on the current consumption value and the current values ​​of the memory chip in the energized state and the register clock driver. Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble the multiple memory chips. The working principles and technical effects of steps S100, S200, and S300 in this embodiment are the same as in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0043] In this embodiment, Vdimm is the conversion source voltage input of the DIMM's PMIC, outputting target voltages VDD, VDDQ, and VPP. VDD, VDDQ, and VPP power all memory chips in the memory module. A Registered Clock Driver (RCD) is installed in the memory module. The VDDQ pin of the PMIC is also connected to the power input pin of the RCD, and the PMIC also powers the RCD. Therefore, when testing the power consumption of memory chips, the RCD also affects the calculation of DRAM power consumption, and the impact of VDDQ pin powering the RCD on DRAM power consumption measurement needs to be subtracted. VIN_MGMT serves as the operating power supply for the DIMM's PMIC, converted to a 1.8V / 1.0V output voltage. 1.8V powers the SPD HUB, TS0, and TS1. 1.0V powers the I3C interface modules of the SPD HUB, TS0, TS1, and RCD. The VIN_MGMT voltage signal does not power the DRAM and is not included in DRAM power consumption; therefore, the impact of VDDQ powering the RCD on DRAM power consumption measurement needs to be reduced.

[0044] Reference Figure 15It's understandable that the ADC sampler integrates a current-sensing resistor. This resistor detects the current and voltage at the power input of the power management chip. When all DRAMs are in deep sleep, only the RCD consumes VDDQ. The microcontroller, which can be a BMC (Baseboard Management Controller), MCU (Microcontroller Unit), or SoC (System on Chip), inputs the current value collected by the ADC sampler into the microcontroller. The microcontroller then calculates the power consumption of the memory chips based on this current value. Optionally, the microcontroller collects the voltage Vshunt across the current-sensing resistor R1 integrated in the ADC. Based on the resistance of the current-sensing resistor and the collected voltage, it calculates the current IDD at the power management chip's input. This IDD is the sum of the current consumed by the RCD and the current consumed by the PMIC's Voltage Regulator (VR), i.e., the current when the DIMM is unloaded, referred to here as IRCD. This IDD is subtracted when calculating the power consumption of each DRAM chip. Then, a wake-up method is used to test the current value of the woken DRAM, for example: The first DRAM is woken up and enters normal operation, while the remaining DRAMs remain in deep sleep (ignoring the current consumption during deep sleep). At this time, the microcontroller calculates the current I1 by obtaining the voltage V1 across the current sensing resistor R1 integrated in the ADC. Therefore, the current consumed by the first DRAM can be calculated using the formula: IDRAM1 = I1 - IRCD; Wherein, IDRAM1 is the current flowing through the first DRAM, I1 is the current of the memory chip in the active state and the register clock driver, and IRCD is the current consumed by the register clock driver. Similarly, when measuring the second DRAM, the second DRAM is woken up, and the other DRAMs are placed in deep sleep mode, and the current values ​​are obtained using the above method. Then, according to the power calculation formula in the above embodiment, the power consumption of the memory chip in the active state can be obtained.

[0045] Fifth embodiment, referring to Figure 5 The present invention also proposes a method for assembling a memory module, the method comprising: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S151: When all memory chips in multiple memory chips are in a sleep state, the power consumption value of the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller to obtain the power consumption value of the register clock driver. Step S152: When the memory chip is in an excited state, the power consumption value of the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller, so as to obtain the power consumption value of the memory chip in the excited state and the register clock driver. Step S153: Calculate the power consumption value of the memory chip in the energized state based on the current consumption value and the power consumption value of the memory chip in the energized state and the register clock driver. Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble the multiple memory chips. The working principles and technical effects of steps S100, S200, and S300 in this embodiment are the same as in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0046] It is understandable that the ADC sampler's own calculation function can be used to collect the current value at the input terminal of the power management chip, and the power consumption value of the register clock driver and the power consumption value of the memory chip in the energized state and the register clock driver can be calculated based on the current value. Thus, the power consumption value of the memory chip in the energized state can be calculated based on the collected current value. Specifically, the total power consumption value P, the power consumption value Pp in the fully sleep state, and the power consumption value when the first DRAM (a) is woken up and enters normal working state, while the remaining DRAMs are still in deep sleep state (ignoring the current consumption of deep sleep), i.e., when DRAM (a) is working and the others are in sleep state, are obtained from the ADC sampler. At this time, the power consumption of the first DRAM, i.e., DRAM (a), can be calculated using the following formula: Pa = Pp + a - Pp.

[0047] The sixth embodiment, referring to Figure 6 and Figure 15 In one embodiment, the memory module further includes a power management chip and a register clock driver; the assembly method of the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S161: When all memory chips in the multiple memory chips are in a dormant state, the voltage value of the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to calculate the current consumption value of the register clock driver based on the voltage value. Step S162: When the memory chip is in an excited state, the voltage value at the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to obtain the current value of the memory chip in the excited state and the register clock driver based on the voltage value. Step S163: Calculate the power consumption value of the memory chip in the energized state based on the current consumption value and the current values ​​of the memory chip in the energized state and the register clock driver. Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble multiple memory chips. The working principle and technical effects of steps S100, S200 and S300 in this embodiment are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0048] In this embodiment, it can be understood that the ADC acquisition unit can acquire the voltage U and current I of the load (PMIC, RCD, DRAM). The DRAM power consumption value can be obtained by acquiring the voltage U and current I of the power management chip's output terminal through the ADC acquisition unit, or the DRAM power consumption P can be directly acquired through the ADC acquisition unit. When calculating the DRAM power consumption value by acquiring the output voltage value of the power management chip through the current sensing resistor integrated in the ADC sampler, all DRAMs are in deep sleep mode. At this time, only the RCD consumes VDDQ. The current value I0 (Ip) at the input terminal of the memory chip is calculated using the voltage acquired by the ADC. This I0 is the sum of the current consumed by the RCD and the current consumed by the PMIC's Voltage Regulator (VR), i.e., the current when the DIMM is unloaded, referred to here as I0. This is subtracted when calculating the power consumption of each DRAM chip. Then, a wake-up method is used to test the current value of the woken DRAM, for example: The first DRAM is woken up and enters normal operation, while the remaining DRAMs remain in deep sleep (ignoring the current consumption during deep sleep). At this time, the microcontroller samples the voltage VDDQ across the current sensing resistor R1 and calculates the current IDDQ(Ip+a). Therefore, the current consumed by the first DRAM can be calculated using the formula: IDRAM1(a) = IDDQ - I0; Wherein, IDRAM1 is the current value flowing through the first DRAM, IDDQ is the current value of the memory chip in the active state and the registered clock driver, and I0 is the current consumption value of the registered clock driver. Similarly, when measuring the second DRAM, the second DRAM is woken up, and the other DRAMs are placed in deep sleep mode, and the current values ​​are obtained using the above method. Idd, Iddq, Ipp, Vdd, Vddq, Vpp are obtained through ADC0, ADC1, and ADC2 respectively, and Pdd, Pddq, and Ppp are calculated using P=UI. The three are added together to obtain the total power consumption value P. Following the above steps, the total power consumption value P is calculated as follows: Full sleep state: Pp; DRAM(a) working and other sleep states: Pp+a; Power consumption of DRAM(a): Pa=Pp+a-Pp...; Thus, the power consumption value of the memory chip in the active state can be obtained.

[0049] The seventh embodiment, referring to Figure 7 The memory module further includes a power management chip and a register clock driver; the assembly method of the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S171: When all memory chips in multiple memory chips are in a sleep state, the power consumption value of the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to calculate the power consumption value of the register clock driver based on the power consumption value of the input terminal of the memory chip. Step S172: When the memory chip is in an excited state, the power consumption value of the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to obtain the power consumption value of the memory chip in the excited state and the register clock driver based on the power consumption value of the input terminal of the memory chip. Step S173: Calculate the power consumption value of the memory chip in the energized state based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble the multiple memory chips.

[0050] The working principle and technical effects of steps S100, S200 and S300 in this embodiment are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0051] It is understandable that the ADC sampler can utilize its own calculation function to collect the current value at the input terminal of the memory chip, and calculate the power consumption value of the register clock driver and the power consumption value of the memory chip and the register clock driver in the energized state based on the current value. Thus, the power consumption value of the memory chip in the energized state can be calculated based on the collected current value.

[0052] In practical applications, three ADC samplers (ADC0, ADC1, and ADC2) can be set up at the VDD, VDDQ, and VPP power outputs of the PMIC respectively. Pdd, Pddq, and Ppp can be directly obtained from the ADC samplers. The total power consumption value P can be calculated using P = Pdd + Pddq + Ppp. Following the above steps, the total power consumption value P is calculated as follows: in full sleep mode: Pp; in DRAM(a) working and other sleep modes: Pp + a; the power consumption of DRAM(a) Pa = Pp + a - Pp...

[0053] Eighth embodiment, referring to Figure 8 In one embodiment, the memory module further includes a power management chip and a register clock driver; the assembly method of the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S181: When all memory chips in multiple memory chips are in a sleep state, the processor obtains the current value of the output terminal of the power management chip through the power management chip, and calculates the power consumption value of the register clock driver based on the current value. Step S182: When the memory chip is in an energized state, the processor obtains the current value of the output terminal of the power management chip through the power management chip, so as to obtain the power consumption value of the memory chip in the energized state and the register clock driver based on the current value. Step S183: Calculate the power consumption value of the memory chip in the energized state based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble the multiple memory chips.

[0054] The working principle and technical effects of steps S100, S200 and S300 in this embodiment are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0055] Reference Figure 17 or Figure 19 In this embodiment, the processor may integrate a Basic Input Output System (BIOS). The BIOS can calculate the power consumption of the memory chips. It is understood that the PMIC itself supports reading the output voltage and current. In this embodiment, the PMIC itself supports reading the output voltage and current. The read voltage and current can be output to the BIOS via a communication line. The BIOS reads Idd, Iddq, Ipp, Vdd, Vddq, Vpp from the PMIC, and then calculates Pdd, Pddq, and Ppp using P=UI. The three are added together to obtain the total power consumption value P. Specifically, the output voltage and current values ​​of the power management chip can be directly obtained through the PMIC. When all DRAMs are in deep sleep, only the RCD consumes VDDQ. The BIOS calculates the current value I0 (Ip) at the input terminal of the memory chip based on the voltage collected by the PMIC. This I0 is the sum of the current consumed by the RCD and the current consumed by the PMIC's Voltage Regulator (VR), i.e., the current when the DIMM is unloaded, referred to here as I0. When calculating the power consumption of each DRAM chip, subtract it. Then, use a wake-up-by-wake method to test the current value of the woken DRAM, for example: The first DRAM is woken up and enters normal operation, while the remaining DRAMs remain in deep sleep (ignoring the current consumption during deep sleep). At this time, the BMC samples the voltage VDDQ across the current sensing resistor R1 and calculates the current IDDQ(Ip+a). Therefore, the current consumed by the first DRAM can be calculated using the formula: IDRAM1(a) = IDDQ - I0; Wherein, IDRAM1 is the current value flowing through the first DRAM, IDDQ is the current value of the memory chip in the active state and the registered clock driver, and I0 is the current consumption value of the registered clock driver. Similarly, when measuring the second DRAM, the second DRAM is woken up, and the other DRAMs are placed in deep sleep mode, and the current values ​​are obtained using the above method. Idd, Iddq, Ipp, Vdd, Vddq, Vpp are obtained through the power management chip, and Pdd, Pddq, and Ppp are calculated using P=UI. The three are added together to obtain the total power consumption value P. Following the above steps, the total power consumption value P is calculated as follows: Full sleep state: Pp; DRAM(a) working and other sleep states: Pp+a; Power consumption of DRAM(a): Pa = Pp+a - Pp...; Thus, the power consumption value of the memory chip in the active state can be obtained.

[0056] Or, refer to Figure 9 The assembly method of the memory module includes: Step S100: Provide test stimuli to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, control the remaining memory chips in the multiple memory chips to be in the sleep state. Step S191: When all memory chips in multiple memory chips are in a sleep state, the processor obtains the current and voltage values ​​at the output terminal of the power management chip through the power management chip, and calculates the power consumption value of the register clock driver based on the voltage value. Step S192: When the memory chip is in an energized state, the processor obtains the current and voltage values ​​at the output terminal of the power management chip through the power management chip, so as to obtain the power consumption value of the memory chip in the energized state and the register clock driver based on the voltage value. Step S193: Calculate the power consumption value of the memory chip in the energized state based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. Step S200: Classify multiple memory chips according to the power consumption value of each memory chip to obtain classification results; Step S300: Based on the classification results, assemble the multiple memory chips.

[0057] The working principle and technical effects of steps S100, S200 and S300 in this embodiment are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0058] It is understandable that the PMIC's own computing function can be used to collect the current value at the input terminal of the memory chip (the power output terminal of the PMIC), and the power consumption value of the register clock driver and the power consumption value of the memory chip and the register clock driver in the energized state can be calculated based on the current value. Thus, the power consumption value of the memory chip in the energized state can be calculated based on the collected current value.

[0059] In practical applications, the PMIC directly reads Pdd, Pddq, and Ppp from the PMIC power output terminal and calculates the total power consumption value P using P = Pdd + Pddq + Ppp. Following the above steps, the total power consumption value P is calculated as follows: Full sleep state: Pp; DRAM(a) working and other sleep states: Pp + a; Power consumption of DRAM(a): Pa = Pp + a - Pp...

[0060] In the above embodiments, the average value method is used for the analysis of the sampled data. The average value is calculated by combining the data samples collected from the BMC side and the BIOS side, as shown in Table 1.

[0061] Table 1

[0062] Among them, the memory chip ID0 collects data from all DRAM deep sleep states. IDD0 represents the current consumption detected by the BMC side, and I0 represents the current consumption detected by the BIOS side. During all DRAM deep sleep states, the main current-consuming devices are the Voltage Regulator and RCD in the PMIC. The current detected by the BMC is the sum of the current consumed by IDD, IDDQ, IPP, and the VR of the PMIC; the current consumption detected by the BIOS side is the sum of IDD, IDDQ, and IPP; the current during DRAM deep sleep is negligible. Therefore, IDD0 can be used as the base for the current consumption detected by the BMC side, and I0 can be used as the base for the current consumption detected by the BIOS side. (Refer to...) Figure 18 , Figure 18 This is a comparison chart of DRAM current consumption calculated by the BMC and BIOS sides. This example uses data sampling from 10 DRAM chips, extracting data from 3 of them for illustration. These 3 memory chips are designated as memory chip ID1, memory chip ID2, and memory chip ID3. The minimum quantization unit of the PMIC is 125mA / LSB, and the PMIC error is ±1~2LSB.

[0063] BMC's formula for calculating DRAM current consumption: BMC_IDD = avgIDDi-IDD0 PMIC formula for calculating DRAM current consumption: PMIC_IDD=avgIi-I0 Based on BMC sampling data, the current consumption is calculated to be between 100 and 119 mA, while based on BIOS sampling data, the current consumption is calculated to be between 13.7 and 15.2 mA. By sampling the DRAM current consumption data from both BMC and BIOS, it can be observed that the data fluctuates within a certain range. After multiple samplings, the data tends to stabilize within a certain range, and the characteristics of DRAM current consumption can be reflected in the collected data.

[0064] Reference Figure 10 In one embodiment, the step of obtaining the power consumption value of the memory chip in the activated state specifically includes: Step S1101: Obtain the static power consumption value of the memory module when all memory chips in multiple memory chips are in a sleep state; Step S1102: Obtain the power consumption value of the memory module when any memory chip is under test stimulus; Step S1103: Calculate the power consumption value of the memory chip in the excited state based on the operating power consumption value and the static power consumption value.

[0065] Given that chip power consumption mainly consists of static power consumption and dynamic power consumption, static power consumption is typically used to provide a benchmark for memory modules, while the high temperature rise of memory chips is primarily due to dynamic power consumption. Furthermore, since the power consumption of a module is generated by the combined circuit, it is impossible to directly measure the power consumption of a single chip from the module interface. Therefore, this solution mainly measures the differences in dynamic power consumption. In practical applications, the test drive unit first stops driving the module under test, allowing the module to sleep. The static operating current of the memory module is then sampled, and the sampled static operating current is integrated. The integration result is divided by the sampling time to obtain the static power consumption value of the memory module.

[0066] Different memory chips exhibit different power consumption values ​​under the same test stimulus. The power consumption unit measures the current consumed. Specifically, an ADC can be added after the power management chip (VDD, VDDQ, VPP) to achieve measurement. The ADC supports reading power consumption, current, and voltage. The supply voltage of the memory chip is fixed. According to P=I·V, the instantaneous power of the memory chip can be calculated. By integrating the current over a certain period of time, that is, by integrating the current value over the sampling time with a specified start and end point, the operating power consumption value of the tested memory chip can be obtained. Subtracting the static power consumption value from the operating power consumption value yields the dynamic power consumption value of each memory chip, that is, the power consumption value of the memory chip under the stimulated state.

[0067] Reference Figure 11In one embodiment, the step of classifying the multiple memory chips according to the power consumption value of each memory chip specifically includes: Step S211: Calculate the power consumption difference between each memory chip; Step S212: When the power consumption difference between any memory chip and the other memory chips is not greater than a preset difference, the corresponding memory chip is classified as a first-class memory chip. Step S213: When the power consumption difference between any memory chip and the other memory chips is greater than the preset difference, the corresponding memory chip is classified as a second type of memory chip.

[0068] In this embodiment, the number of memory chips arranged on the PCB of the memory module is typically 10, 20, or 40, and the memory chips are usually located on both sides of the power management chip. Taking a memory module with 10 memory chips on the PCB as an example, 5 of the 10 memory chips are located on one side of the power management chip, and the other 5 are located on the other side. When the power consumption difference between any two memory chips in the 10 memory modules is no greater than a preset difference, it can be determined that the power consumption consistency of the 10 memory chips is good, and the 10 memory chips can be classified into the same category, type I memory chips. At this time, the power consumption consistency of the 10 memory chips is good, and even if the power consumption of all 10 memory chips is high, it will not affect the other memory chips. When there is a group of memory chips with a power consumption difference or multiple groups of memory chips with a power consumption difference greater than the preset difference, it can be determined that there are one or more memory chips with a higher power consumption value than the other memory chips. For example, if the power consumption difference between one memory chip and another is 10mW, while the difference is 20mW, it means that the power consumption difference between this memory chip and at least one of the other memory chips is greater than a preset difference. Therefore, this memory chip is either high or low power consumption, and is classified as a high-power (second category) memory chip. Subsequently, the assembly method can be determined based on the specific power consumption of this memory chip compared to other memory chips. For example, if this memory chip has low power consumption while other memory chips have high power consumption, it can be replaced from the PCB and a higher-power memory chip can be installed. Conversely, if this memory chip has high power consumption while other memory chips have low power consumption, it can be replaced from the PCB and a lower-power memory chip can be installed. Alternatively, the overall impact of this memory chip on the memory module can be determined to decide whether to increase the refresh rate of this memory chip or not to replace it and not to increase the refresh rate.

[0069] In one embodiment, the step of classifying the multiple memory chips according to the power consumption value of each memory chip specifically includes: Calculate the power consumption difference between each of the memory chips and the memory chip with the lowest power consumption value among the plurality of memory chips; When the power consumption difference is not greater than a preset difference, the corresponding memory chip is classified as a first type of memory chip; When the power consumption difference is greater than the preset difference, the corresponding memory chip is classified as a second type of memory chip.

[0070] In this embodiment, taking a memory module PCB with 10 memory chips as an example, after determining the memory chip with the lowest power consumption, the power consumption values ​​of the remaining 9 chips are compared with the power consumption value of the lowest-power-consumption chip. This difference is then compared to a preset difference. If the power consumption difference between any memory chip and the lowest-power-consumption chip is not greater than the preset difference, the power consumption consistency of the 10 memory chips is considered good, and they can be classified as first-category memory chips. If the power consumption difference between any memory chip and the lowest-power-consumption chip is greater than the preset difference, then a memory chip with higher power consumption exists, indicating inconsistent power consumption. This higher-power-consumption memory chip can be classified as second-category memory chips. After classifying the 10 memory chips based on the comparison between their power consumption differences and the preset difference, the subsequent assembly method can be determined based on the classification results. For example, if the power consumption difference between all nine memory chips and the chip with the lowest power consumption is greater than a preset difference, then it can be determined that only one memory chip has low power consumption, while the other memory chips have high power consumption. In this case, the memory chip with lower power consumption can be removed from the PCB and replaced with a memory chip with higher power consumption. If one or more of the nine memory chips have a power consumption difference greater than a preset difference compared to the chip with the lowest power consumption, while the other memory chips have low power consumption, then that memory chip can be removed from the PCB and replaced with a memory chip with lower power consumption. Alternatively, the overall impact of that memory chip on the memory module can be further determined to decide whether to increase the refresh rate of that memory chip or not to replace it and not to increase the refresh rate.

[0071] Reference Figure 12 In one embodiment, the step of classifying the multiple memory chips according to the power consumption value of each memory chip specifically includes: Step S221: Calculate the relative power consumption deviation between each memory chip and the other memory chips, and compare the relative power consumption deviation between each memory chip and the other memory chips with a preset threshold. Step S222: When the relative power consumption deviation is not greater than a preset deviation threshold, the corresponding memory chip is classified as a first type of memory chip; Step S222: When the relative power consumption deviation is greater than the preset deviation threshold, the corresponding memory chip is classified as a second type of memory chip.

[0072] In this embodiment, the relative power consumption deviation between the memory chip and the other memory chips can be calculated using the following formula: Relative deviation = 100% (P) 颗粒动态功耗 -P 平均动态功耗 ) / P 平均动态功耗 Among them, P 颗粒动态功耗 P represents the power consumption of the memory chip. 平均动态功耗 This is the average operating power consumption value of all memory chips in the memory module. The preset deviation threshold can be set to 5%-10%, which can be tightened or relaxed according to different requirements.

[0073] Taking a memory module PCB with 10 memory chips as an example, if the relative power consumption deviation of the 10 memory chips is no greater than a preset deviation threshold, then the power consumption consistency of the 10 memory chips is good, and they can be classified as Category I memory chips. In this case, even if the power consumption of all 10 memory chips is relatively high, it will not affect the other memory chips. If the relative power consumption deviation of one or more memory chips exceeds the preset deviation threshold, then one or more memory chips have higher power consumption values ​​than the other memory chips, and these higher-power-value memory chips can be classified as Category II memory chips. Subsequently, the assembly method can be determined based on the specific power consumption of this memory chip compared to other memory chips. For example, if the power consumption of this memory chip is low, while the power consumption of other memory chips is high, then this memory chip can be removed from the PCB and replaced with a higher-power-value memory chip. If a memory chip has high power consumption while other memory chips have low power consumption, it can be replaced from the PCB with a lower-power memory chip. Alternatively, the overall impact of this memory chip on the memory module can be determined to decide whether to increase its refresh rate or not, and therefore neither replacement nor refresh rate increase is necessary.

[0074] Reference Figure 13 , Figures 19 to 21 In one embodiment, the memory module further includes a PCB, and the memory chips are mounted on the PCB. The step of assembling multiple memory chips according to the classification result specifically includes: Step S310: Perform a margin test on the data retention capability of memory particles classified as the second type; Step S320: When the data retention capability of memory chips classified as the second type is not within a preset range, remove the memory chip from the PCB; and / or update the refresh frequency of memory chips classified as the second type; and / or adjust the temperature threshold when refreshing the frequency of memory chips classified as the second type.

[0075] Reference Figure 16 In this embodiment, when performing a margin test on the memory chips, such as Figure 16 For example, if the measured data retention parameter of the memory module is more than twice that of the testing and control standard, then the memory module is considered to have sufficient data retention margin to resist the effects of temperature deviations. Figure 16 Example 2 illustrates this: if the memory module lacks sufficient data retention margin to withstand the effects of temperature variations, a power consumption deviation description parameter needs to be added to the memory parameters. This informs the system using the memory module that when it reads a memory module with poor power consumption deviation parameters, it should proactively adjust the refresh strategy to lower the temperature threshold for faster refresh, for example, updating from 85℃ to 75℃. Alternatively, when the system reads a memory module with poor power consumption deviation parameters, it should proactively adjust the refresh frequency. For example, when the memory module's casing temperature is ≤85℃, the maximum average refresh interval is Trefi; when 85℃ < casing temperature ≤95℃, the maximum average refresh interval is Trefi / 2.

[0076] Reference Figure 14 , Figures 19 to 21 In one embodiment, the step of classifying the multiple memory chips according to the power consumption value of each memory chip specifically includes: Step S230: Match the power consumption value of each memory chip with a preset power consumption value range to classify the multiple memory chips; or, input the power consumption value of each memory chip into a clustering model to classify the multiple memory chips. In this embodiment, multiple power consumption value ranges can be set, and the width of each power consumption value range can be set to be relatively small, for example, 0.1W, that is, a power consumption value range is set every 0.1W. After measuring the power consumption value of each memory chip, the power consumption value of each memory chip can be matched with the preset power consumption value range to determine the power consumption value range in which the power consumption value of the memory chip falls. Then, based on the power consumption value range in which the power consumption value of the memory chip falls, it can be determined which category the memory chip belongs to.

[0077] During testing, a clustering model for power consumption classification can be pre-established. After measuring the power consumption of each memory chip, the value is input into the clustering model, which then classifies the memory chips. For example, memory chips not falling within the same power consumption range can be grouped into a second category, while memory chips within the same range, or those with the same power consumption value, can be grouped into the same first category. (Refer to...) Figure 20 In the diagram, 11 memory chips with a power consumption of 500mW or less, and 18 memory chips with a power consumption of 1500mW or greater, are classified as Category II memory chips. Based on this classification, a normal distribution diagram of the memory chips can be obtained, revealing the power consumption range within which the memory chip power consumption values ​​are concentrated. This allows for appropriate assembly processing based on the normal distribution of memory chip power consumption.

[0078] The memory module also includes a PCB, and the step of assembling multiple memory chips according to the classification result specifically includes: Step S400: Mount memory chips of the same type onto the same PCB.

[0079] In this embodiment, the number of memory chips mounted on the memory module can be set according to requirements, such as 8, 16, 20, etc. This embodiment takes 20 memory chips mounted on each memory module as an example for explanation. To assemble memory chips with highly consistent power consumption parameters into the same memory module, a common practice is to limit the maximum power consumption parameter deviation of the memory chips within the same module. For example, limiting the maximum power consumption deviation to 0.1W, testing might yield a group of memory chips: 9 at 1.0W, 11 at 1.1W, 8 at 1.2W, 40 at 1.3W, and 12 at 1.4W. The production assembly strategy could then mount memory chips with a power consumption deviation of 1.0W and those with a deviation of 1.1W onto the same PCB, for example, (1.0W x 9 + 1.1W x 11), (1.2W x 8 + 1.3W x 12), or (1.3W x 8 + 1.4W x 12), or mount chips with the same power consumption deviation onto the same PCB, for example, (1.3W x 20). This can produce four qualified modules. Of course, for manufacturers with large production volumes, directly assembling chips with identical values ​​into the same module yields even better results.

[0080] In one embodiment, the assembly method of the memory module further includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, the remaining memory chips in the multiple memory chips are controlled to enter the sleep state, the timer is started, and the power consumption value of the memory chip in the stimulated state is obtained. When the power consumption value of the memory chip in the excited state reaches the target power consumption value, stop timing and obtain the time consumed by the memory chip in the excited state. The memory chips are classified according to the consumption time of the memory chips in the energized state; Based on the classification results, multiple memory chips are assembled.

[0081] In this embodiment, the method for calculating the total power consumption value P can refer to the above embodiment, and will not be repeated here. For example, the PMIC output Idd, Iddq, Ipp, Vdd, Vddq, Vpp can be read by the PMIC, and then Pdd, Pddq, and Ppp can be calculated using P=UI. The three are then added together to obtain the total power consumption value P. The total power consumption value P is calculated according to the above steps.

[0082] Before testing, set the target power consumption: Ptarget. Start DRAM(a) and start timing, while the other DRAMs are in sleep mode. Record the startup time as Ta0. After startup, the BIOS repeatedly acquires and calculates the total power consumption value Pa and compares it with the target power consumption Ptarget. When the total power consumption value Pa is detected to be equal to the target power consumption Ptarget, record the time as Ta. Record the elapsed time. Ta = Ta - Ta0. Similarly, when DRAM(b) is started and timed while the other DRAMs are in sleep mode, the startup time is recorded as Tb0. After startup, the BIOS repeatedly acquires and calculates the total power consumption value Pb and compares it with the target power consumption Ptarget. When the total power consumption value Pb is detected to be equal to the target power consumption Ptarget, the time is recorded as Tb, and the elapsed time is recorded. Tb = Tb - Tb0. Finally, compare the time consumed. The shorter the time consumed, the greater the power consumption of the DRAM chip.

[0083] When classifying memory chips based on their consumption time, the consumption time can be compared with the target time. Memory chips with a consumption time longer than the target time are classified as Class I memory chips, and memory chips with a consumption time shorter than the target time are classified as Class II memory chips.

[0084] It should be noted that the above examples are only for understanding the present invention and do not constitute a limitation on the assembly method of the memory module of the present invention. Any simple modifications based on this technical concept are within the protection scope of the present invention.

[0085] The present invention also proposes an assembly device for a memory module, comprising: The test driver unit is used to provide test stimuli to the memory chips on the memory module. The temperature chamber is used to provide the temperature testing environment required for testing memory chips on the memory module; the assembly equipment also includes: The memory, the processor, and a computer program stored on the memory chip and executable on the processor, the computer program being configured to implement the steps of the assembly method for the memory module as described above.

[0086] The recommended testing environment is as follows: ambient temperature should conform to JEDEC standards. Taking a certain DRAM as an example, 85℃ should be used. The testing equipment needs to operate under the same high-load conditions for all memory chips. Consistency in temperature and workload ensures fairness in testing each chip. Power consumption can then be measured. The testing equipment should have the capability to test current consumption, and combined with the operating voltage defined by JEDEC, the corresponding power consumption parameters can be measured. Providing high-load operating conditions means maximizing the DRAM's operation. Each testing manufacturer has its own high-load testing capabilities and standards, which will not be elaborated here, but the testing conditions must be consistent and fair for each chip.

[0087] The memory module assembly equipment provided by this invention, employing the memory module assembly method described in the above embodiments, can solve the technical problem of memory module assembly. Compared with the prior art, the beneficial effects of the memory module assembly equipment provided by this invention are the same as those of the memory module assembly method provided in the above embodiments, and other technical features in the memory module assembly equipment are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0088] The present invention provides a memory module assembly apparatus, which further includes: at least one processor; and a memory chip communicatively connected to the at least one processor; wherein the memory chip stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the memory module assembly method in the above embodiment 1.

[0089] The following is for reference. Figure 22 The diagram illustrates a structural schematic of an assembly device suitable for implementing a memory module in an embodiment of the present invention. The assembly device for the memory module in this embodiment may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 22The assembly equipment for the memory module shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0090] like Figure 22 As shown, the memory module assembly device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the memory module assembly device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. The communication device 1009 allows the memory module assembly equipment to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows an assembly equipment for memory modules with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented alternatively.

[0091] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this invention.

[0092] The memory module assembly equipment provided by this invention, employing the memory module assembly method described in the above embodiments, can solve the technical problem of memory module assembly. Compared with the prior art, the beneficial effects of the memory module assembly equipment provided by this invention are the same as those of the memory module assembly method provided in the above embodiments, and other technical features of this memory module assembly equipment are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0093] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or special times can be combined in any suitable manner in one or more embodiments or examples.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0095] The present invention provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, the computer-readable program instructions being used to execute the assembly method of the memory module in the above embodiments.

[0096] The computer-readable storage medium provided by this invention may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical fibers, portable compact disk read-only memory (CD-ROM), optical memory devices, magnetic memory devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0097] The aforementioned computer-readable storage medium may be included in the assembly equipment of the memory module; or it may exist independently in the assembly equipment not assembled into the memory module.

[0098] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the memory module assembly device, cause the memory module assembly device to become a memory module assembly method.

[0099] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. During this period, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0101] The modules described in the embodiments of the present invention can be implemented in software or hardware. The names of the modules do not necessarily limit the specific unit itself.

[0102] The readable storage medium provided by this invention is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described memory module assembly method, thereby solving the technical problem of memory module assembly. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by this invention are the same as those of the memory module assembly method provided in the above embodiments, and will not be repeated here.

[0103] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the memory module assembly method described above.

[0104] The computer program product provided by this invention can solve the technical problem of assembling memory modules. Compared with the prior art, the beneficial effects of the computer program product provided by this invention are the same as the beneficial effects of the memory module assembly method provided in the above embodiments, and will not be repeated here.

[0105] The above description is only a part of the embodiments of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made under the technical concept of the present invention using the contents of the present invention specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method of assembling a memory module, comprising: The memory module includes multiple memory chips and a power management chip; The memory module includes multiple memory chips, and the assembly method of the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a sleep state, the current value at the input terminal of the power management chip is obtained and recorded as the first current value. When the memory chip is in an energized state, the current value at the input terminal of the power management chip is obtained and recorded as the second current value; Calculate the power consumption of the memory chip in the excited state based on the first current value and the second current value; The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

2. A method of assembling a memory module, comprising: The memory module includes multiple memory chips and a power management chip; The assembly method of the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a sleep state, the power consumption value at the input terminal of the power management chip is obtained and recorded as the first power consumption value. When the memory chip is in an energized state, the power consumption value at the input terminal of the power management chip is obtained and recorded as the second power consumption value; Calculate the power consumption value of the memory chip in the energized state based on the first power consumption value and the second power consumption value; The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

3. A method of assembling a memory module, comprising: The memory module includes multiple memory chips, a power management chip, and a register clock driver. The assembly method of the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a dormant state, the current value at the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller to obtain the current consumption value of the register clock driver. When the memory chip is in an energized state, the current value at the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller, so as to obtain the current value of the memory chip in the energized state and the register clock driver. The power consumption of the memory chip in the energized state is calculated based on the current consumption value and the current values ​​of the memory chip in the energized state and the register clock driver. Alternatively, when all memory chips in multiple memory chips are in a sleep state, the power consumption value of the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller to obtain the power consumption value of the register clock driver. When the memory chip is in an excited state, the power consumption value at the input terminal of the power management chip is obtained through the ADC sampler and the microcontroller, so as to obtain the power consumption value of the memory chip in the excited state and the register clock driver. The power consumption value of the memory chip in the energized state is calculated based on the current consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

4. A method for assembling a memory module, characterized in that, The memory module includes multiple memory chips, a power management chip, and a register clock driver. The assembly method of the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a dormant state, the voltage value of the input terminal of the memory chip is obtained through an ADC sampler and a microcontroller, and the current consumption value of the register clock driver is calculated based on the voltage value. When the memory chip is in an excited state, the voltage value at the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to obtain the current value of the memory chip in the excited state and the register clock driver based on the voltage value. The power consumption of the memory chip in the energized state is calculated based on the current consumption value and the current values ​​of the memory chip in the energized state and the register clock driver. Alternatively, when all memory chips in multiple memory chips are in a sleep state, the power consumption value of the input terminal of the memory chip is obtained through an ADC sampler and a microcontroller, and the power consumption value of the register clock driver is calculated based on the power consumption value of the input terminal of the memory chip. When the memory chip is in an excited state, the power consumption value at the input terminal of the memory chip is obtained through the ADC sampler and the microcontroller, so as to obtain the power consumption value of the memory chip in the excited state and the register clock driver based on the power consumption value at the input terminal of the memory chip. The power consumption value of the memory chip in the energized state is calculated based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

5. A method for assembling a memory module, characterized in that, The memory module includes multiple memory chips, a power management chip, and a register clock driver. The assembly method of the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. When all memory chips in multiple memory chips are in a sleep state, the processor obtains the current value of the output terminal of the power management chip through the power management chip, and calculates the power consumption value of the register clock driver based on the current value. When the memory chip is in an energized state, the processor obtains the current value at the output terminal of the power management chip through the power management chip, and obtains the power consumption value of the memory chip in the energized state and the register clock driver based on the current value. The power consumption value of the memory chip in the energized state is calculated based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. Alternatively, when all memory chips in multiple memory chips are in a sleep state, the processor obtains the current and voltage values ​​at the output terminal of the power management chip through the power management chip, and calculates the power consumption value of the register clock driver based on the current and voltage values ​​at the output terminal of the power management chip. When the memory chip is in an energized state, the processor obtains the current and voltage values ​​at the output terminal of the power management chip through the power management chip, so as to obtain the power consumption values ​​of the memory chip and the register clock driver in the energized state based on the current and voltage values ​​at the output terminal of the power management chip. The power consumption value of the memory chip in the energized state is calculated based on the power consumption value and the power consumption values ​​of the memory chip in the energized state and the register clock driver. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

6. A method for assembling a memory module, characterized in that, The memory module includes multiple memory chips; The assembly method of the memory module includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives a test stimuli and is in an stimulated state, the remaining memory chips among the multiple memory chips are controlled to be in a sleep state. Obtain the static power consumption value of the memory module when all memory chips in multiple memory chips are in a sleep state; Obtain the power consumption value of the memory module when any memory chip is under test stimulus; The power consumption value of the memory chip in the activated state is calculated based on the operating power consumption value and the static power consumption value. The memory chips are classified according to their power consumption values ​​to obtain a classification result. Based on the classification results, multiple memory chips are assembled.

7. The assembly method of the memory module as described in claim 6, characterized in that, The step of classifying multiple memory chips according to the power consumption value of each memory chip specifically includes: Calculate the power consumption difference between each of the memory chips; When the power consumption difference between any memory chip and the other memory chips is not greater than a preset difference, the corresponding memory chip is classified as a first-class memory chip. When the power consumption difference between any memory chip and the other memory chips is greater than the preset difference, the corresponding memory chip is classified as a second type of memory chip.

8. The assembly method of the memory module as described in claim 6, characterized in that, The step of classifying multiple memory chips according to the power consumption value of each memory chip specifically includes: Calculate the power consumption difference between each of the memory chips and the memory chip with the lowest power consumption value among the plurality of memory chips; When the power consumption difference is not greater than a preset difference, the corresponding memory chip is classified as a first type of memory chip; When the power consumption difference is greater than the preset difference, the corresponding memory chip is classified as a second type of memory chip.

9. The assembly method of the memory module as described in claim 6, characterized in that, The step of classifying multiple memory chips according to the power consumption of each memory chip specifically includes: Calculate the relative power consumption deviation between each memory chip and the other memory chips, and compare the relative power consumption deviation between each memory chip and the other memory chips with a preset threshold; When the relative power consumption deviation is not greater than a preset deviation threshold, the corresponding memory chip is classified as a first type of memory chip; When the relative power consumption deviation is greater than the preset deviation threshold, the corresponding memory chip is classified as a second type of memory chip.

10. The assembly method of a memory module according to any one of claims 7 to 9, wherein the memory module further includes a PCB, and the memory chips are mounted on the PCB, characterized in that, The step of assembling multiple memory chips according to the classification result specifically includes: Perform margin testing on the data retention capability of memory chips classified as Category II; when the data retention capability of memory chips classified as Category II is not within a preset range, remove the memory chips from the PCB; and / or update the refresh frequency of memory chips classified as Category II; and / or adjust the temperature threshold when refreshing the frequency of memory chips classified as Category II.

11. The assembly method of the memory module as described in claim 6, characterized in that, The step of classifying multiple memory chips according to the power consumption value of each memory chip specifically includes: The power consumption value of each memory chip is matched with a preset power consumption value range to classify the multiple memory chips. Alternatively, the power consumption values ​​of each memory chip can be input into a clustering model to classify the multiple memory chips.

12. The assembly method of the memory module as described in claim 11, characterized in that, The memory module also includes a PCB, and the step of assembling multiple memory chips according to the classification result specifically includes: Memory chips of the same type are mounted on the same PCB.

13. The assembly method of the memory module as described in claim 6, characterized in that, The assembly method of the memory module further includes: Test stimuli are provided to multiple memory chips in sequence. When any memory chip receives the test stimuli and is in the stimulated state, the remaining memory chips in the multiple memory chips are controlled to enter the sleep state, the timer is started, and the power consumption value of the memory chip in the stimulated state is obtained. When the power consumption value of the memory chip in the excited state reaches the target power consumption value, stop timing and obtain the time consumed by the memory chip in the excited state. The memory chips are classified according to the consumption time of the memory chips in the energized state; Based on the classification results, multiple memory chips are assembled.

14. An assembly device for a memory module, characterized in that, include: The test driver unit is used to provide test stimuli to the memory chips on the memory module. A temperature chamber is used to provide the temperature testing environment required for testing memory chips on memory modules. The assembly equipment also includes: The memory, the processor, and the computer program stored on the memory chip and executable on the processor, the computer program being configured to implement the steps of the assembly method of the memory module as described in any one of claims 1 to 13.

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