Wide gain control method for ac-dc distribution network power router cllc converter

Abstract

The application provides a wide gain control method of an AC-DC power distribution network electric energy router CLLC converter, and relates to the technical field of power electronics. The method comprises the following steps: providing an acquisition circuit to acquire the output voltage of the CLLC converter, inputting a frequency error amplifier to obtain a normalized switching frequency; according to the different sizes of the normalized switching frequency, selecting a PFM control mode or an SR active control mode, generating a carrier input driving circuit, and generating a driving signal for controlling each switch tube of the CLLC converter secondary side. The method can guarantee that the switching frequency is close to the optimal resonance point when coping with the extreme high gain condition of wide voltage fluctuation of the power grid, can inhibit the reactive current circulation in the CLLC converter, and can improve the overall conversion efficiency of the electric energy router. In addition, the early conduction of each switch tube of the CLLC converter secondary side can reduce the design difficulty of the driving control circuit, and can provide higher voltage gain to meet the adaptability requirement of the electric energy router to the wide voltage fluctuation.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a wide-gain control method for AC / DC power distribution network power router CLLC converters. Background Technology

[0002] CLLC converters, due to their symmetrical topology, ability to achieve high-frequency electrical isolation and soft switching across the entire load range, and excellent bidirectional energy transfer capabilities, are ideal isolation-level topologies for constructing flexible interconnection core hub equipment such as Energy Routers in AC / DC distribution networks. However, with the integration of a high proportion of distributed renewable energy sources and the deepening interaction between power sources, grids, loads, and storage, the bus voltages at various nodes in the distribution network are highly susceptible to significant deviations due to drastic power fluctuations. This necessitates that isolated bidirectional DC-DC converters, which serve as the key energy transfer link within the Energy Router, possess a wider operating voltage gain range to ensure stable power exchange and reliable control between different voltage levels or regions even during grid voltage fluctuations.

[0003] Traditional CLLC converters have significant limitations in widening the voltage gain range: at the topology level, additional auxiliary devices or cascaded circuits are typically required, leading to increased hardware complexity, larger size, and higher system conduction losses in the power router; at the control level, traditional strategies often employ single pulse frequency modulation (PFM) to regulate the output voltage, but when dealing with extreme high-gain conditions of wide voltage fluctuations in the power grid, the switching frequency often needs to deviate significantly from the optimal resonant point, resulting in a significant increase in reactive circulating current within the converter and severely impacting the overall conversion efficiency of the power router. Furthermore, PFM control significantly increases the design complexity of the drive control circuit; the voltage gain improvement provided by single PFM control is extremely limited and cannot fully meet the adaptability requirements of flexible interconnection in distribution networks to wide voltage fluctuations. Summary of the Invention

[0004] To address the aforementioned technical problems in existing technologies, this invention provides a wide-gain control method for CLLC converters in AC / DC power distribution networks. This method ensures that the switching frequency is close to the optimal resonant point under extreme high-gain operating conditions with wide voltage fluctuations in the power grid, suppresses reactive circulating currents within the CLLC converter, and improves the overall conversion efficiency of the power router. Specifically, the technical solution is as follows:

[0005] A wide-gain control method for a CLLC converter in an AC / DC power distribution network, wherein the primary side terminals are connected to the emitters of transistor Q1 and the collectors of transistor Q2, the non-primary side terminals are connected to the emitters of transistor Q3 and the collectors of transistor Q4, the secondary side terminals are connected to the emitters of transistor S1 and the collectors of transistor S2, and the non-secondary side terminals are connected to the emitters of transistor S3 and the collectors of transistor S4; including:

[0006] The acquisition circuit acquires the output voltage of the CLLC converter. The input frequency error amplifier is used to obtain the normalized switching frequency. ;

[0007] like Then the CLLC converter enters PFM control mode, and the output frequency... and a carrier whose amplitude remains at 1 Otherwise, the CLLC converter enters the SR active control mode, adjusting the lead conduction angle of switches S1 to S4. Output frequency and output voltage ;in, Minimum switching frequency;

[0008] frequency Input to a sawtooth wave generator to generate a sawtooth carrier wave. Input the non-inverting input of the second comparator; convert the output voltage and carrier Input carrier generator to generate carrier Input the inverting input of the second comparator;

[0009] A drive signal is generated based on the output of the second comparator. and drive signal drive signal Control switches S1 and S4, drive signals Control switching transistors S2 and S3.

[0010] Compared to existing technologies, the technical solution provided by this invention can pre-activate the secondary-side switches of the CLLC converter, causing the output voltage to form a reverse clamping effect on the secondary-side resonant cavity voltage. This causes the secondary-side resonant current to turn from zero to positive, triggering a reverse energy flow from the load end back to the resonant cavity. This ensures that the CLLC converter maintains a switching frequency close to the optimal resonant point when dealing with extreme high-gain conditions of wide grid voltage fluctuations, suppressing reactive power circulating currents within the CLLC converter and improving the overall conversion efficiency of the power router. Furthermore, pre-activating the secondary-side switches of the CLLC converter reduces the design complexity of the drive control circuit and, by providing higher voltage gain, perfectly matches the power router's adaptability requirements to wide voltage fluctuations. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the topology of a CLLC converter.

[0012] Figure 2 This is the circuit topology diagram of the control system corresponding to the wide gain control method used in the CLLC converter of this invention.

[0013] Figure 3 This is a key waveform diagram of the CLLC converter using wide gain control in this invention.

[0014] Figure 4 This is a key waveform diagram of the underresonance state of the CLLC converter in this invention.

[0015] Figure 5 This is the equivalent circuit diagram of the P-mode, O-mode and F-mode of the CLLC converter in this invention.

[0016] Figure 6 This is a timing diagram showing the driving modulation of each switch on the secondary side of the CLLC converter in this invention under wide gain control.

[0017] Figure 7 This is the equivalent circuit diagram of the CLLC converter in P mode in this invention.

[0018] Figure 8 This is the equivalent circuit diagram of the CLLC converter in O mode in this invention.

[0019] Figure 9 This is the equivalent circuit diagram of the CLLC converter in mode F of the present invention.

[0020] Figure 10 These are key waveforms of the CLLC converter in the P-mode, O-mode, and F-mode of this invention.

[0021] Figure 11 This is a surface plot showing the relationship between the normalized switching frequency, voltage gain, and lead conduction angle of the CLLC converter in the P-mode, O-mode, and F-mode of this invention.

[0022] Figure 12 This is a schematic diagram comparing the voltage gain of the CLLC converter in the PF mode and PO mode in this invention.

[0023] Figure 13 This is a comparison chart of the current curves of the CLLC converter in this invention when the normalized switching frequency is 0.6 and the lead conduction angle is 20°.

[0024] Figure 14 This is a comparison of the current curves of the CLLC converter in this invention when the normalized switching frequency is 0.6 and the lead conduction angle is 40°.

[0025] Figure 15 This is a graph showing the relationship between voltage gain and lead conduction angle in the CLLC converter of this invention. Detailed Implementation

[0026] The technical solution provided by the present invention will be further described in detail below with reference to the accompanying drawings.

[0027] I. Closed-loop control strategy considering active control on the secondary side—wide gain control method.

[0028] Specifically, the topology diagram of the CLLC converter is as follows: Figure 1 As shown, where, The input voltage amplitude, For input current, This is the voltage of the primary resonant network (primary resonant cavity voltage). This is the voltage of the secondary resonant network (secondary resonant cavity voltage). This refers to the output voltage amplitude. The transformer turns ratio is denoted as... , For primary resonant inductance, This is the primary-side resonant capacitor. For secondary resonant inductance, It is the secondary resonant capacitor. The circuit is a magnetizing inductor. Switches Q1 and Q3 are the upper transistors, and switches Q2 and Q4 are the lower transistors. The secondary-side rectification is composed of four switches, S1 to S4. The primary-side terminals with the same name are connected to the emitter of switch Q1 and the collector of switch Q2, while the primary-side terminals with different names are connected to the emitter of switch Q3 and the collector of switch Q4. The secondary-side terminals with the same name are connected to the emitter of switch S1 and the collector of switch S2, while the secondary-side terminals with different names are connected to the emitter of switch S3 and the collector of switch S4.

[0029] Under conventional operating conditions, a CLLC converter may contain three basic operating modes within a single switching cycle: P-mode (positive clamping), N-mode (negative clamping), and O-mode (discontinuous). In P-mode, the primary resonant inductor... resonant capacitor with primary side Resonance occurs, and the voltage of the secondary resonant cavity... clamped in In N-mode, the primary resonant inductance resonant capacitor with primary side Similarly, at resonance, the voltage of the secondary resonant cavity... clamped in During the O mode, the magnetizing inductance Primary resonant inductor resonant capacitor with primary side When all three resonate together, there is no energy transfer between the input and output sides.

[0030] During a half-switching cycle, the CLLC converter can form various operating states through combinations of different basic operating modes, typical modes including PO, PON, PN, NP, NOP, and OPO. Among these, the PO mode is often used for boost mode. In this mode, the converter can easily achieve zero voltage switching (ZVS) and also has low reactive power loss. In addition, the voltage gain of the PO mode monotonically increases as the switching frequency decreases, which is beneficial to the stability of the closed-loop control system. Therefore, under conventional operating conditions, to achieve boost operation, the CLLC should be resonant to make the converter operate in the PO mode.

[0031] Traditional CLLC converters employ a single PFM control, which has a wide switching frequency range, resulting in low utilization of magnetic components and complex drive and control circuit design—the crux of the problem lies in insufficient control freedom. To overcome this limitation and expand the gain range, such as Figure 2 As shown, this invention proposes a hybrid closed-loop control strategy combining PFM and secondary-side active control, namely a wide-gain control method. The core of this control method lies in introducing a minimum normalized switching frequency. Based on the required voltage gain changes in the distribution network, the control system will automatically and smoothly switch between two consecutive adjustment ranges.

[0032] Specifically, in the control system, the acquisition circuit acquires the output voltage of the CLLC converter. Input frequency error amplifier EA1 (Error Amplifier, EA) to calculate the subtraction of the reference voltage. The difference is then used for PI (Proportional-Integral Controller) control to obtain the normalized switching frequency. ;like Then the CLLC converter enters PFM control mode, and the output frequency... and a carrier whose amplitude remains at 1 Otherwise, the CLLC converter enters the SR active control mode, adjusting the lead conduction angle of switches S1 to S4. Output frequency and output voltage ;in, This is the minimum normalized switching frequency.

[0033] frequency Input to a sawtooth wave generator to generate a sawtooth carrier wave. Input the non-inverting input of the second comparator; convert the output voltage and carrier Input carrier generator to generate carrier The input is connected to the inverting input of the second comparator; the output of the second comparator is connected to the clock input of the D flip-flop; the D input of the D flip-flop is connected to the NOT Q input, the NOT Q input is connected to the first input of the second AND gate via the second NOT gate, the Q input is connected to the first input of the first AND gate via the first NOT gate, and the clock input is connected to the second inputs of the first and second AND gates; the outputs of the first and second AND gates are respectively connected to the first and second driving circuits; the first driving circuit generates the driving signal. The second drive circuit controls switches S1 and S4, and generates drive signals. Control switches S2 and S3. Drive signal. and drive signal The duty cycles are the same, but the phases are 180° apart.

[0034] The acquisition circuit includes resistors R1 and R2, and the driving circuit includes a gate driver chip, an isolation power supply, and a gate driver resistor.

[0035] One end of resistor R1 is connected to the positive terminal of the CLLC converter load, and the other end is connected to the negative terminal of the CLLC converter load via resistor R2; the voltage acquisition point is located between resistor R1 and resistor R2.

[0036] Gate driver chip: The PWM signal output by the resonant controller has weak voltage and current capabilities, and cannot directly and quickly drive the gate capacitance of the MOSFET / IGBT. The gate driver chip plays a role in power amplification and electrical isolation.

[0037] Isolated power supply: Provides an independent, floating power supply for the secondary side of an isolated gate driver chip.

[0038] Gate drive resistor: Connected between the gate drive chip and the isolation power supply (i.e., the three are connected in series), it is used to limit the gate charging current and control the switching speed.

[0039] Zone 1: Traditional PFM frequency converter control zone (medium and low gain operating conditions).

[0040] In the initial stage of boost operation or when the required voltage gain is relatively low, the CLLC converter preferentially uses traditional PFM control. In this range, the control system sets the lead conduction angle of the secondary-side rectifier switch. Locked to 0, relying solely on reducing the normalized switching frequency Increase voltage gain At this point, the CLLC converter operates in a traditional underresonant state, and voltage fluctuation requirements within the normal range can be met by frequency adjustment.

[0041] Interval 2: Active control region of fixed-frequency variable-phase POF mode (high-gain operating condition).

[0042] When the voltage of the distribution network bus fluctuates drastically, a higher voltage gain is required from the CLLC converter. Furthermore, the control system loop will normalize the switching frequency. Reduce to the set minimum normalized switching frequency If the target voltage is still not reached, the control system will trigger mode switching. To prevent the switching frequency from continuing to drop, which could lead to a surge in reactive circulating current and saturation of magnetic components, the normalized switching frequency is rigidly clamped at the minimum normalized switching frequency. It remains unchanged. Subsequently, the control system seamlessly switches the adjustment command to the phase control dimension, adjusting the lead conduction angle of the secondary rectifier's switching transistor. This, in turn, adjusts the output voltage of the CLLC converter. With the lead conduction angle... The increase of voltage gain This allows for further increases, thus enabling wide voltage gain regulation within a limited frequency range.

[0043] The control system mainly consists of a voltage outer loop, which samples the output voltage. With reference voltage The error is used to generate a normalized switching frequency command via a PI controller, i.e., the normalized switching frequency. The instruction then enters the mode allocation module.

[0044] If the normalized switching frequency Greater than the set minimum normalized switching frequency Then the CLLC converter enters PFM control mode. The specific implementation principle is as follows:

[0045] The frequency of the frequency conversion command output by the mode allocation module And maintain carrier . Multiply by 2 after entering the sawtooth wave generator Obtain frequency signal The formula is as follows:

[0046] ;

[0047] ;

[0048] In the formula, The resonant frequency of the CLLC converter. This is the current switching frequency of the CLLC converter.

[0049] frequency signal The signal is sent to the Reset module (reset button). The Reset module can integrate its input signal and has a reset control terminal: when the input below it is set to logic 1, the module's output is immediately reset to zero. Therefore, when the frequency signal... Once entered, the output of the Reset module will increase linearly over time, forming a slope of... The output is then fed to a third comparator and compared with a reference voltage of 1V. The comparison is performed. Once the integral output value is greater than 1, the third comparator outputs a high level (logic 1). This high level is sent to the reset input of the Reset module (i.e., the input below), thus resetting the output value of the Reset module to zero. This process repeats continuously, eventually generating a frequency of... sawtooth carrier The signal is fed into the first comparator and compared with the reference level 0, thus obtaining a frequency that is also [value missing]. square wave signal Subsequently, square wave signal The signal is fed into a JK flip-flop for processing, thereby driving the primary-side switches Q1, Q2, Q3, and Q4 to conduct alternately. Ultimately, the overall switching frequency of the CLLC converter is... .

[0050] In short, frequency signal Enter the reset button to generate a sawtooth carrier. ; Sawtooth carrier Input the non-inverting input of the third comparator to the reference voltage with an amplitude of 1V. Input the inverting input of the third comparator; the input of the third comparator is connected to the reset button.

[0051] Specifically, the sawtooth carrier The input is the non-inverting input of the first comparator; the inverting input of the first comparator is grounded, and its output is connected to the clock input of the JK flip-flop; in the JK flip-flop, both the J and K terminals are connected to the power supply voltage. The Q input is connected to the clock input of the D flip-flop and the first input of the third AND gate, while the non-Q inputs are connected to the second input of the fourth AND gate. The Q input of the D flip-flop is connected to the second input of the third AND gate and the first input of the fourth AND gate. The output of the third AND gate is connected to the third driving circuit, and the output of the fourth AND gate is connected to the fourth driving circuit. The third driving circuit generates the driving signal. The fourth drive circuit controls switching transistors Q1 and Q4, and generates drive signals. Control switching transistors Q2 and Q3.

[0052] In PFM control mode, the OR gate inside the carrier generator switches to the PFM control port. At this time, the output carrier... equal to carrier carrier wave It is then fed into a second comparator, and compared with the sawtooth carrier. Comparison. Due to sawtooth carrier. The value is always less than or equal to 1, therefore the second comparator cannot output a high level, and its output is the control signal for the secondary-side switch. Maintain a state with no output signal.

[0053] If the normalized switching frequency Less than or equal to the set minimum normalized switching frequency Then the CLLC converter enters the SR (Synchronous Rectification) active control mode, and the switching frequency is normalized. Maintain minimum normalized switching frequency Operation. The specific implementation principle is as follows: the mode allocation module outputs the frequency of the fixed-frequency command. ,frequency The output switching frequency after inputting the sawtooth wave generator is sawtooth carrier Sawtooth carrier After passing through the first comparator and the driver circuit, the CLLC converter is ultimately controlled to maintain its switching frequency. run.

[0054] Since the CLLC converter is operating at its lowest switching frequency, traditional PFM control cannot meet the gain requirements, so it is necessary to switch to an active SR control strategy. At this point, the output voltage has not yet reached the reference voltage. Therefore, the output voltage The signal is fed into the modulation error amplifier EA2, and after PI regulation, the output carrier wave meets the gain requirements. In this control mode, the OR gate of the carrier generator selects the SR active control port, therefore the carrier wave output by the modulator is... carrier wave Subsequently with sawtooth carrier Both are fed into the third comparator for comparison: if The third comparator outputs a high level, generating a control signal for the secondary-side switching transistor. Control signals The input drive circuit is used to control the switching transistors S1, S2, S3 and S4 to conduct alternately.

[0055] like Figure 3 As shown, when the reference voltage At lower levels, the normalized switching frequency The set minimum normalized switching frequency has not yet been reached. At this time, the carrier Always greater than or equal to the sawtooth carrier wave Therefore, without applying active control signals to the secondary-side switches, the CLLC converter operates in PFM control mode, functioning in an underresonant state. When the reference voltage... Further increases allow the CLLC converter to operate even at the minimum normalized switching frequency. If the gain requirement is still not met, the converter will fix the switching frequency at the minimum normalized switching frequency. During operation, the active control signal of the secondary-side switching transistor is received. This phenomenon begins to appear, forcing a change in the operating mode of the CLLC converter. This control method can significantly improve the voltage gain of the converter. Among other things, and These represent the switching frequencies of the CLLC converter at different times.

[0056] Although both frequency error amplifier EA1 and modulation wave error amplifier EA2 receive the same output voltage error at their input terminals. However, the transfer functions of the controlled objects they face are completely different, which dictates that they must output control commands of different dimensions. In PFM control mode, the control system relies on adjusting the normalized switching frequency to change the resonant cavity gain, and its control-output transfer function exhibits strong nonlinearity. In contrast, in SR active control mode, the control system relies on adjusting the conduction phase of the secondary rectifier switch to control the gain, exhibiting completely different dynamic response characteristics. To ensure the stability and dynamic performance of their respective closed-loop control ranges, completely independent proportional-integral (PI) parameters must be designed for these two error amplifiers. Specifically, the output target of the frequency error amplifier EA1 is the normalized switching frequency command, and its control law equation is determined as follows:

[0057] ;

[0058] In the formula, This is the proportional coefficient corresponding to frequency conversion control. The integral coefficient corresponding to the frequency converter control. The integral symbol is used. For time.

[0059] The output target of the modulation error amplifier EA2 is the carrier wave. The governing law equation is determined as follows:

[0060] ;

[0061] In the formula, The proportional coefficient is independently tuned for fixed-frequency phase-changing control. The integral coefficient is the independently tuned integral coefficient for fixed-frequency phase-change control.

[0062] In short, the output voltage and carrier Input carrier generator to generate carrier :

[0063] Output voltage Input the modulation wave error amplifier and calculate the subtraction of the reference voltage. The difference is used to obtain the carrier wave through PI control. The first input of the OR gate; converts the carrier wave... The second input of the OR gate; when At that time, the OR gate outputs a carrier. As a carrier Otherwise, the OR gate outputs a carrier. As a carrier .

[0064] II. Analysis of the boost principle.

[0065] Under normal underresonant operating conditions, this converter can be decomposed into two fundamental resonant states, P and O, within a complete switching cycle. During state P, only the primary-side resonant inductor... resonant capacitor with primary side Participating in dual-element resonance, the voltage of the secondary resonant cavity at this time They will be rigidly clamped in When the circuit is switched to state O, the magnetizing inductance... Release the clamp and add a resonant network, resonating with the primary-side inductor. and primary resonant capacitor Together, they form a three-element resonance process. A significant characteristic of this stage is the complete cessation of energy interaction between the input and output terminals. For example... Figure 4 As shown, the secondary resonant cavity voltage Primary resonant inductor current Secondary resonant inductor current and excitation current The dynamic trajectory of change.

[0066] The wide-gain control method provided by this invention actively controls the secondary-side switching transistor, creating a novel resonant state. Its equivalent circuit diagram is shown below. Figure 5 As shown. This mechanism forces the rectifier diode to turn on a specific phase earlier than the normal timing. Within this early turn-on interval, the voltage amplitude... Will affect the voltage of the secondary resonant cavity This creates a reverse clamping effect, where the secondary resonant current changes from 0 to positive, causing a physical phenomenon where energy flows back from the load end to the resonant cavity. This is defined in this invention as the "F-mode". By reordering the F-mode with the inherent fundamental resonant state in terms of timing, the system can construct a new POF operating mode, thereby effectively widening the voltage gain of the CLLC converter.

[0067] like Figure 6 As shown, to clearly illustrate the specific implementation logic of the F-mode, this invention provides a detailed driving modulation timing sequence for each switch in the secondary-side synchronous rectification. Meanwhile, as... Figure 7 , Figure 8 and Figure 9 As shown, the topological evolution of the equivalent circuit diagrams corresponding to the P-mode, O-mode, and F-mode of the CLLC converter is presented intuitively within a positive switching cycle.

[0068] Phase 1 Inside, as the primary-side switching transistors Q1 and Q4... With simultaneous activation, the CLLC converter officially enters the positive half-cycle of its switching cycle. During this period, since the secondary-side rectifier switches S1 and S4 remain on, the port voltages of the primary and secondary resonant cavities are clamped to the input voltage amplitude, respectively. and output voltage amplitude The CLLC converter thus operates in its fundamental resonant state P. As time progresses... Time (i.e., entering) The second stage), excitation current Rise to the resonant inductor current of the primary side The current on the secondary side is equal, causing it to naturally cross zero and turn off switches S1 and S4. At this time, the magnetizing inductor... Release the clamp and engage the resonant circuit, resonating with the primary resonant inductor. and primary resonant capacitor Together, they form a three-element resonance, and the CLLC converter smoothly transitions to the traditional resonant state O. Subsequently, in The third stage starting point ( At a specific moment, the control method actively intervenes, prematurely driving the secondary-side synchronous rectification switches S2 and S3 to turn on. This operation causes the secondary-side resonant cavity voltage to... Subject to output voltage amplitude The reverse clamping effect excites the converter to switch to the F mode and maintain it until... At this point, the CLLC converter enters the negative half-cycle. Under this operating mechanism, the phase interval spanned by the F mode is equivalent to the quantifiable lead conduction angle of the synchronous rectification switch. The formula is as follows:

[0069] ;

[0070] ;

[0071] In the formula, This represents the switching cycle of the CLLC converter.

[0072] By adjusting the lead-in conduction angle By performing continuous modulation, flexible control and effective enhancement of the converter's output voltage gain can be achieved.

[0073] The introduction of the F-mode brings dual optimizations to the CLLC converter in terms of soft-switching performance and control. At the electrical characteristic level, this state induces the primary-side resonant inductor current... At the instant the switching transistor is about to turn on, it can accumulate and provide a more sufficient reverse current, thereby greatly improving the physical conditions for the primary-side switching device to achieve zero-voltage turn-on (ZVS). On the other hand, by maintaining a continuous lead conduction angle for the F-mode... Active adjustment essentially introduces an additional control parameter to the CLLC converter. Combining this new degree of control freedom with PFM control allows for the construction of a multi-dimensional composite modulation strategy. This joint control mechanism not only significantly broadens the control system's control over the output voltage... The adjustment margin also significantly narrows the switching frequency variation range of the CLLC converter under all operating conditions, thus creating favorable conditions for the optimized design of high-frequency magnetic components and the improvement of the overall system operating efficiency.

[0074] III. Temporal modeling.

[0075] Since the fundamental frequency analysis method equates the input and output signals to sine waves, it is only applicable to the region near the resonant frequency. The gain deviation is significant when deviating from the resonant point, making it unsuitable for designing wide-range output circuits and even less suitable for modeling and analyzing the new modes constructed in this invention. Time-domain analysis, compared to the traditional fundamental frequency analysis method, is more suitable for analyzing time-varying systems and offers higher accuracy. This invention employs a time-domain analysis method, namely, establishing a time-domain model through numerical calculation.

[0076] Key waveforms of the POF mode, such as Figure 10 As shown, where, This is the voltage of the primary resonant capacitor. This is the voltage of the secondary resonant capacitor.

[0077] like Figure 5 As shown, the current-voltage characteristic equations of the resonant cavity in P-mode, O-mode, and F-mode can be listed respectively. Taking P-mode as an example, its circuit state equation is determined as follows:

[0078] ;

[0079] In the formula, This refers to the primary resonant inductor current in the P-mode. The excitation current in P mode. This is the primary-side resonant capacitor voltage in P-mode. This refers to the secondary resonant inductor current in the P-mode. This is the secondary resonant capacitor voltage in the P-mode.

[0080] Applying the Laplace transform and inverse Laplace transform to the above equation, we obtain the normalized time-domain expressions for the resonant inductor current and resonant capacitor voltage in the P-mode, as follows:

[0081] ;

[0082] ;

[0083] ; ; ;

[0084] In the formula, For the current time The phase angle (in radians) that the voltage and current in the lower resonant cavity travel during one complete resonant cycle. for The primary resonant capacitor voltage at the phase angle of the P-mode. for The primary resonant inductor current in the P-mode at the phase angle. for The secondary resonant capacitor voltage at the phase angle in P-mode. for The secondary resonant inductor current in the P-mode at the phase angle. This represents the voltage gain of the resonant cavity. and This is for intermediate calculations; , , and The unknown integral constant is determined by the initial state of the resonant circuit and is only related to the initial state of the resonant circuit. It can reflect the energy storage state at the beginning of the P mode. Z base The impedance reference value, The primary impedance is... U base This is the voltage reference value. I base This is the current reference value. f base This is the reference value for the switching frequency.

[0085] Similarly, the normalized time-domain expressions for the F-mode resonant inductor current and resonant capacitor voltage are determined as follows:

[0086] ;

[0087] In the formula, for The primary resonant capacitor voltage at the phase angle of the F-mode. for The primary resonant inductor current in the F-mode at the phase angle. for The secondary resonant capacitor voltage at the phase angle of the F-mode. for Secondary resonant current in F-mode at phase angle. , , and The integral constant is an unknown quantity determined by the initial state of the resonant circuit. It is only related to the initial state of the resonant circuit and can reflect the energy storage state at the beginning of the F mode.

[0088] Similarly, the normalized time-domain expressions for the O-mode resonant inductor current and resonant capacitor voltage are determined as follows:

[0089] ;

[0090] ;

[0091] In the formula, for The primary resonant capacitor voltage at phase angle O in mode O. for The primary resonant inductor current at phase angle O in mode O. This is for intermediate calculations; and The integral constant is an unknown quantity determined by the initial state of the resonant circuit and is only related to the initial state of the resonant circuit.

[0092] Due to the primary resonant inductor current and secondary resonant inductor current Primary resonant capacitor voltage and secondary resonant capacitor voltage and excitation inductor current The converter is symmetrical within both positive and negative half-switching cycles, therefore, the operating characteristics can be obtained by analyzing only the positive half-switching cycle. When the CLLC converter transitions from one operating mode to another, the resonant inductor current and resonant capacitor voltage cannot change abruptly. Therefore, the continuity conditions for the resonant inductor current and resonant capacitor voltage (transcendental equations 1 to 7) are as follows:

[0093] ;

[0094] In the formula, For the continuous phase of the P mode, This is the continuous phase of the O mode. This refers to the primary resonant inductor current during the P-mode phase. This represents the primary resonant inductor current in mode O at the initial moment. This refers to the primary resonant inductor current during the O-mode phase. This refers to the primary resonant inductor current during the initial F-mode. This refers to the secondary resonant inductor current during the P-mode phase. This represents the secondary resonant inductor current in mode O at the initial moment. This refers to the secondary resonant inductor current during the O-mode phase. The initial resonant inductor current of mode F; This is the primary resonant capacitor voltage during the P-mode phase. This represents the primary resonant capacitor voltage in mode O at the initial moment. This is the primary-side resonant capacitor voltage during the O-mode phase. This represents the resonant capacitor voltage on the primary side of mode F at the initial moment; This is the secondary resonant capacitor voltage during the P-mode phase. The voltage of the secondary resonant capacitor in mode O at the initial moment. This represents the secondary resonant capacitor voltage during the O-mode phase. This is the voltage of the secondary resonant capacitor at the initial moment when the F mode is in operation.

[0095] Due to the symmetry of the CLLC converter, the resonant inductor current is within half a switching cycle. Resonant inductor current Resonant capacitor voltage and resonant capacitor voltage The initial and final values ​​are opposite. Therefore, the symmetry conditions for the resonant inductor current and resonant capacitor voltage (transcendental equations 8 to 11) are as follows:

[0096] ;

[0097] In the formula, For the continuous phase of the F mode, This represents the primary resonant inductor current in mode P at the initial moment. This refers to the primary resonant inductor current during the F-mode phase. This represents the primary resonant capacitor voltage of the P-mode at the initial moment. This is the primary resonant capacitor voltage during the F-mode phase; This represents the secondary resonant inductor current of mode P at the initial moment. This refers to the secondary resonant inductor current during the F-mode phase. This represents the secondary resonant capacitor voltage of the P-mode at the initial moment. This is the secondary resonant capacitor voltage during the F-mode phase.

[0098] Since the P mode, O mode, and F mode form the POF mode within half a period, the sum of the durations of each mode is half a period, as shown in the following formula (transcendental equation 12):

[0099] .

[0100] Continuous phase By leading conduction angle The only certainty is that if the lead-in conduction angle is... Given, then the sustained phase Satisfies the following formula (transcendental equation 13):

[0101] .

[0102] Because when the CLLC converter operates in O mode, the secondary resonant inductor current... It does not flow through the load. Therefore, the actual output current of the CLLC converter is determined. The formula is as follows (transcendental equation 14):

[0103] ;

[0104] ;

[0105] In the formula, Normalized output current, with normalized switching frequency Input voltage amplitude Actual output current Leading conduction angle and transformer turns As a known quantity, the voltage gain G, as well as the corresponding resonant current and voltage variables, are obtained by solving transcendental equations 1 to 14, including the unknown integral constant. Unknown integral constant Unknown integral constant Unknown integral constant Unknown integral constant Unknown integral constant Unknown integral constant Unknown integral constant Unknown integral constant Unknown integral constant Continuous phase Continuous phase and continuous phase .

[0106] Given the resonance parameters and system parameters as shown in Table 1, the normalized switching frequency under the above-mentioned novel operating mode is constructed by solving the time-domain model. The sustained phase of the F-mode is the lead conduction angle. and the voltage gain of the resonant cavity. Three-dimensional relational surfaces, such as Figure 11 As shown in the figure. It can be seen that, at the same switching frequency, the voltage gain... With leading conduction angle The normalized switching frequency increases with the increase of the frequency. Voltage gain in PO mode Only 1.212; keep the switching frequency constant and increase the lead conduction angle. Up to 20°, the CLLC converter operates in POF mode, voltage gain Increased to 1.283; further increase the lead conduction angle. At 52.665°, state O completely transitions to F mode, and the CLLC converter operates in the critical point PF mode, at which point the voltage gain... The maximum value of 2.51 is the voltage gain in PO mode. It is 2.071 times that of the standard. This demonstrates that the introduction of the F-mode can significantly improve the voltage gain range while compressing the switching frequency range, making it suitable for wide-voltage-range operation scenarios.

[0107] Table 1 Specifications and Resonance Parameters .

[0108] To further verify the limiting voltage gain improvement effect of the novel operating mode under extreme conditions (i.e., the F-mode continuous phase reaches its maximum value), this invention plots the voltage gain of the converter in the PF mode and the traditional PO mode based on a time-domain model. With normalized switching frequency Relationship curves, such as Figure 12 As shown, to achieve the same voltage gain, the PF mode can effectively compress the switching frequency range. At the same switching frequency, the voltage gain capability of the PF mode is always greater than that of the PO mode. Therefore, the introduction of the F mode can significantly improve the voltage gain capability of the CLLC converter, making it suitable for wide-range voltage regulation scenarios.

[0109] IV. Simulation Verification.

[0110] To further illustrate the correctness and feasibility of the time-domain modeling analysis theory of CLLC converters and the proposed novel operating modes, this invention constructed a simulation model using simulation software. The simulation results are compared with the time-domain modeling results, as shown in the figure below. Figures 13-14 As shown in the figure, the blue curve represents the primary resonant inductor current during half a switching cycle. The green curve represents the secondary-side resonant inductor current during half a switching cycle. The red curve represents the auxiliary magnetizing inductor current during half a switching cycle. The solid and dashed lines represent the simulation results and the time-domain analysis results, respectively. Figures 13-14 The normalized switching frequency is shown respectively. At that time, the sustained phase of the F mode is the lead conduction angle. The comparison results for 20° and 40° show that the time-domain analysis model established in this invention has high accuracy.

[0111] Voltage gain of the converter at a fixed switching frequency fs=12kHz The sustained phase with the F mode (i.e., the lead conduction angle) The relationship curve diagram, such as Figure 15 As shown. It can be seen that with the continuous phase, i.e., the leading conduction angle... As the voltage gain increases, the voltage gain of the converter also gradually increases, fully verifying the effectiveness of the wide-gain control method provided by this invention in improving the voltage gain of the converter, and adding new degrees of control freedom for subsequent closed-loop control.

[0112] As can be seen, the new mode construction of the CLLC converter does not change the CLLC converter topology or add any components. It only involves advancing the turn-on of the secondary rectifier switch arm, enabling the converter to operate in F-mode during the lead-on period. F-mode effectively improves the converter's voltage gain. Compared to traditional PFM control, the provided wide-gain control method is more adaptable to a wider voltage range and exhibits higher stability. In terms of time-domain modeling: a time-domain model of the F-mode converter is constructed, which can accurately characterize the voltage and current waveforms, switching frequency, and ZVS performance across multiple time scales, including the switching cycle and power frequency cycle.

[0113] In summary, compared to existing technologies, the technical solution provided by this invention can pre-activate the secondary-side switches of the CLLC converter, causing the output voltage to form a reverse clamping effect on the secondary-side resonant cavity voltage. This causes the secondary-side resonant current to turn from zero to positive, triggering a reverse energy flow from the load end back to the resonant cavity. This ensures that the CLLC converter maintains a switching frequency close to the optimal resonant point when dealing with extreme high-gain conditions of wide grid voltage fluctuations, suppressing reactive circulating currents within the CLLC converter and improving the overall conversion efficiency of the power router. Furthermore, pre-activating the secondary-side switches of the CLLC converter reduces the design complexity of the drive control circuit and, by providing higher voltage gain, perfectly matches the power router's adaptability requirements to wide voltage fluctuations.

Claims

1. A wide-gain control method for a CLLC converter in an AC / DC power distribution network, wherein in the CLLC converter, the primary side terminals of the same name are connected to the emitter of switch Q1 and the collector of switch Q2, the primary side terminals of different name are connected to the emitter of switch Q3 and the collector of switch Q4, the secondary side terminals of the same name are connected to the emitter of switch S1 and the collector of switch S2, and the secondary side terminals of different name are connected to the emitter of switch S3 and the collector of switch S4; characterized in that, include: The acquisition circuit acquires the output voltage of the CLLC converter. The input frequency error amplifier is used to obtain the normalized switching frequency. ; like Then the CLLC converter enters PFM control mode, and the output frequency... and a carrier whose amplitude remains at 1 Otherwise, the CLLC converter enters the SR active control mode, adjusting the lead conduction angle of switches S1 to S4. Output frequency and output voltage ;in, Minimum normalized switching frequency; frequency Input to a sawtooth wave generator to generate a sawtooth carrier wave. Input the non-inverting input of the second comparator; convert the output voltage and carrier Input carrier generator to generate carrier Input the inverting input of the second comparator; A drive signal is generated based on the output of the second comparator. and drive signal drive signal Control switches S1 and S4, drive signals Control switching transistors S2 and S3.

2. The wide-gain control method for the AC / DC distribution network power router CLLC converter according to claim 1, characterized in that, The acquisition circuit includes resistor R1 and resistor R2; One end of resistor R1 is connected to the positive terminal of the CLLC converter load, and the other end is connected to the negative terminal of the CLLC converter load via resistor R2; the voltage acquisition point is located between resistor R1 and resistor R2.

3. The wide-gain control method for the CLLC converter of the AC / DC distribution network power router according to claim 1, characterized in that, The output voltage After inputting the frequency error amplifier, the difference between the input voltage and the reference voltage is calculated. The difference is used to perform PI control, resulting in the normalized switching frequency. .

4. The wide-gain control method for the CLLC converter of the AC / DC distribution network power router according to claim 1, characterized in that, The frequency Input to a sawtooth wave generator to generate a sawtooth carrier wave. Specifically, it includes: For frequency Proportional control is performed to obtain the frequency signal. The formula is as follows: ； ； In the formula, The resonant frequency of the CLLC converter. The current switching frequency of the CLLC converter. For the primary resonant inductance of the CLLC converter, This is the primary resonant capacitor of the CLLC converter; frequency signal Enter the reset button to generate a sawtooth carrier. ; sawtooth carrier Input the non-inverting input of the third comparator to the reference voltage with an amplitude of 1V. Input the inverting input of the third comparator; the input of the third comparator is connected to the reset button.

5. The wide-gain control method for the CLLC converter of the AC / DC distribution network power router according to claim 1, characterized in that, The output voltage and carrier Input carrier generator to generate carrier Specifically, it includes: Output voltage Input the modulation wave error amplifier and calculate the subtraction of the reference voltage. The difference is used to obtain the carrier wave through PI control. The first input of the OR gate; converts the carrier wave... The second input terminal of the input OR gate; when At that time, the OR gate outputs a carrier. As a carrier Otherwise, the OR gate outputs a carrier wave. As a carrier .

6. The wide-gain control method for the CLLC converter of the AC / DC distribution network power router according to claim 1, characterized in that, The output of the second comparator generates a drive signal. and drive signal drive signal Control switches S1 and S4, drive signals Controlling switching transistors S2 and S3 includes: The second comparator outputs a control signal. To the clock input of the D flip-flop; The D terminal of the D flip-flop is connected to the non-Q terminal, the non-Q terminal is connected to the first input terminal of the second AND gate via the second NOT gate, the Q terminal is connected to the first input terminal of the first AND gate via the first NOT gate, and the clock terminal is connected to the second input terminals of the first AND gate and the second AND gate; the output terminals of the first AND gate and the second AND gate are respectively connected to the first driving circuit and the second driving circuit. The first driving circuit generates a driving signal. The second driving circuit generates a driving signal. .

7. The wide-gain control method for the CLLC converter of the AC / DC distribution network power router according to claim 1, characterized in that, It also includes control methods for switching transistors Q1, Q2, Q3, and Q4: sawtooth carrier The input is the non-inverting input of the first comparator; the inverting input of the first comparator is grounded, and the output is connected to the clock input of the JK flip-flop. In the JK flip-flop, both the J and K terminals are connected to the power supply voltage, the Q terminal is connected to the clock terminal of the D flip-flop and the first input terminal of the third AND gate, and the non-Q terminals are connected to the second input terminal of the fourth AND gate respectively; the Q terminal of the D flip-flop is connected to the second input terminal of the third AND gate and the first input terminal of the fourth AND gate. The output of the third AND gate is connected to the third driving circuit, and the output of the fourth AND gate is connected to the fourth driving circuit. The third driving circuit generates driving signals. The fourth drive circuit controls switching transistors Q1 and Q4, and generates drive signals. Control switching transistors Q2 and Q3.

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