A phase-shift control method for full-bridge isolated DC-DC converter

Abstract

The application provides a phase shift control method of a full-bridge isolated DC / DC converter, comprising: obtaining a current switching frequency of the converter, an actual output power and a phase shift step amplitude to be executed, determining a power level span amplitude between adjacent operating conditions, and extracting a phase shift angle step amount corresponding to a working mode switching instruction trigger time; according to a primary side and secondary side switching time sequence displacement caused by a phase shift angle step from a switching front phase shift angle jump to a switching rear phase shift angle, identifying a time sequence interval distance therebetween to obtain a first time sequence interval distance; when the first primary side and secondary side voltage reversal time sequence interval distance exceeds a preset time sequence threshold value, calculating a first voltage variation rate under an initial transition zone phase shift step amplitude according to an equivalent parasitic capacitance between transformer windings and the first primary side and secondary side voltage reversal time sequence interval distance.

Description

Technical Field

[0001] This invention relates to the field of information technology, and in particular to a phase shift control method for a full-bridge isolated DC-DC converter. Background Technology

[0002] A full-bridge isolated DC-DC converter, a power conversion device that transforms a DC input into a DC output via an isolation transformer, plays a crucial role in modern power conversion systems. The stability of its internal control strategy directly determines the safe and reliable operation of the entire device. Current conventional control approaches often focus on reducing the number of voltage flips per unit time by lowering the switching frequency, thereby reducing overall interference energy. However, this limitation of focusing solely on steady-state frequency regulation while ignoring the abrupt state changes during operating mode transitions results in a significant step change in phase shift adjustment during switching, making the device highly susceptible to severe electromagnetic shocks when undergoing complex operating condition transitions. This shock stems from the fact that while the converter lowers the switching frequency to suppress steady-state interference, the energy transfer capacity per cycle in each operating mode increases accordingly, but the power state difference between adjacent operating modes is widened invisibly. In a phase-shift modulation full-bridge converter, the switching between different operating modes is achieved by changing the driving timing difference of the primary side bridge arm. The lower the switching frequency and the longer the duration of a single switching cycle, the greater the absolute timing offset calculated by the same change in phase angle. When the load condition changes abruptly due to equipment start-up / shutdown, load switching, or output power level switching, the control system must complete a significant phase angle adjustment within a limited switching time. This causes a sudden, step-like increase in the timing interval between the voltage reversal time at the midpoint of the primary side bridge arm and the voltage reversal time of the secondary side rectified voltage, instantly disrupting their voltage synchronization. This asynchrony in voltage timing causes the potential difference across the dielectric layer between the primary and secondary windings to fluctuate drastically in a very short time, directly affecting the originally small parasitic capacitance between the transformer coils and forcing it to withstand extremely steep voltage change shocks. Under such a drastic voltage change rate, the parasitic capacitance will instantly generate a strong abnormal current. This instantaneous surge of common-mode current spike will directly enter the grounding loop, severely damaging the stability of the entire system. Summary of the Invention

[0003] This invention provides a phase shift control method for a full-bridge isolated DC-DC converter, mainly comprising: The system acquires the current switching frequency, actual output power, and phase shift step amplitude to be executed of the converter; determines the power level jump amplitude between adjacent operating conditions; and extracts the phase shift angle step corresponding to the trigger time of the operating mode switching command. Based on the primary and secondary switching timing displacement caused by the phase shift angle step, it identifies the primary and secondary voltage reversal timing interval to obtain the first timing interval. When the first timing interval exceeds a preset timing threshold, it calculates the first voltage rate under the initial transition region phase shift step amplitude based on the pre-calibrated equivalent parasitic capacitance between transformer windings and the first timing interval. Based on the first voltage rate and the equivalent parasitic capacitance value, it calculates the first common-mode spike injected into the grounding loop. The first common-mode spike is compared with a preset spike threshold. If it exceeds the threshold, the phase shift resolution corresponding to the switching frequency is used as the compression lower limit to compress the transition region phase shift step amplitude, thus obtaining the compressed transition region phase shift step amplitude. The driving timing is regenerated based on the compressed transition region phase shift step amplitude, and the primary and secondary voltage switching timing interval is identified again to obtain a second timing interval that is smaller than the first timing interval. The second voltage rate is recalculated using the second timing interval and the equivalent parasitic capacitance value, and the second common-mode spike is determined accordingly. After verifying that the second common-mode spike is lower than the preset spike threshold, the compressed transition region phase shift step amplitude is determined as the hybrid phase shift control step amplitude.

[0004] Furthermore, the acquisition of the current switching frequency, actual output power, and phase shift step amplitude to be executed of the converter includes: acquiring the switching frequency of the current drive signal, extracting the actual output power from the primary current sampling circuit and the secondary voltage sampling circuit, and reading the phase shift step amplitude to be executed from the host instruction, wherein the phase shift step amplitude corresponds to the phase adjustment amount of the primary bridge arm drive signal.

[0005] Furthermore, determining the power level span between adjacent operating conditions and extracting the phase shift angle step corresponding to the trigger time of the operating mode switching command includes: obtaining the current operating condition coordinate point by combining the switching frequency and the actual output power; querying a pre-calibrated operating condition and power comparison table based on the current operating condition coordinate point to obtain the power level span; and extracting the difference between the phase shift angle before and after the switching from the control register to obtain the phase shift angle step.

[0006] Furthermore, the step of identifying the primary and secondary side voltage reversal timing interval based on the primary and secondary side switching timing displacement caused by the phase shift angle step, and obtaining the first timing interval, includes: converting the single-cycle duration determined by the phase shift angle step and the switching frequency into a migration distance on the time axis according to the proportion of the phase shift angle step to the whole cycle, to obtain the primary and secondary side switching timing displacement; extracting the moment of the transition edge of the midpoint square wave voltage from the primary side bridge arm midpoint voltage sampling circuit to obtain the primary side bridge arm midpoint voltage reversal moment; extracting the moment of the transition edge of the rectified square wave voltage from the secondary side rectified output voltage sampling circuit to obtain the secondary side rectified voltage reversal moment; marking and aligning the primary side bridge arm midpoint voltage reversal moment and the secondary side rectified voltage reversal moment according to the same reference clock, and taking the maximum difference within the switching cycle at the moment of switching as the first timing interval.

[0007] Furthermore, when the first timing interval exceeds a preset timing threshold, the following steps are taken: The preset timing threshold is called within the main control chip for the first timing interval. The preset timing threshold is the maximum synchronization deviation of the primary and secondary voltage reversal allowed by the dielectric layer of the transformer winding, which is jointly defined by the transformer insulation class and the rated operating voltage. When the first timing interval is greater than the preset timing threshold, an equivalent parasitic capacitance call instruction is triggered; otherwise, the original drive timing is maintained.

[0008] Furthermore, after triggering the equivalent parasitic capacitance call instruction, the process includes: according to the equivalent parasitic capacitance call instruction, the main control chip reads the pre-calibrated equivalent parasitic capacitance value between transformer windings from the transformer parameter table in the non-volatile memory area. The equivalent parasitic capacitance value is pre-stored in the transformer parameter table after an impedance analyzer applies a sweep frequency small signal between the primary and secondary windings and performs capacitive reactance segment fitting on the phase characteristic curve; the voltage jump amplitude across the equivalent parasitic capacitance is obtained by combining the potential difference amplitude between the primary and secondary windings at the moment of switching; the first voltage rate under the initial transition region phase shift step amplitude is obtained by dividing the voltage jump amplitude by the first timing interval.

[0009] Furthermore, the step of calculating the first common-mode spike injected into the grounding loop based on the first voltage change rate and the equivalent parasitic capacitance value includes: performing a product operation based on the first voltage change rate and the equivalent parasitic capacitance value according to the displacement current coupling relationship to obtain the first common-mode spike injected into the grounding loop.

[0010] Furthermore, the step of comparing the first common-mode peak with a preset peak threshold, and compressing the transition region phase shift step amplitude using the phase shift resolution corresponding to the switching frequency as the compression lower limit when the threshold is exceeded, to obtain the compressed transition region phase shift step amplitude, includes: comparing the first common-mode peak with the preset peak threshold value, and activating a phase shift step compression command when the first common-mode peak exceeds the preset peak threshold; obtaining the phase shift resolution corresponding to the switching frequency according to the phase shift step compression command, wherein the phase shift resolution is the smallest phase shift adjustment step size that the phase shift timer can distinguish within a single switching cycle, and using the phase shift resolution as the compression lower limit; and successively reducing the initial transition region phase shift step amplitude by a preset decreasing step size until the reduced value is not lower than the compression lower limit, to obtain the compressed transition region phase shift step amplitude.

[0011] Furthermore, the step of regenerating the drive timing based on the compressed transition region phase shift step amplitude and re-identifying the primary and secondary voltage reversal timing interval to obtain a second timing interval smaller than the first timing interval includes: the main control chip phase shift control unit sends a phase adjustment command to the drive channels of the four power switches on the primary side; the phase shift timer loads the comparison register according to the discrete counting beat corresponding to the compressed transition region phase shift step amplitude to obtain the regenerated primary side bridge arm drive timing; the step of the midpoint square wave voltage is extracted again from the primary side bridge arm midpoint voltage sampling circuit; the step of the rectified square wave voltage is extracted again from the secondary side rectified output voltage sampling circuit; the difference between the two reversal times, the midpoint square wave voltage step and the rectified square wave voltage step, is taken as the second timing interval.

[0012] Furthermore, the second voltage rate is recalculated using the second timing interval and the equivalent parasitic capacitance value, and the second common-mode peak is determined accordingly. After verifying that the second common-mode peak is lower than a preset peak threshold, the compressed transition region phase shift step amplitude is determined as the hybrid phase shift control step amplitude, including: dividing the potential difference amplitude of the primary and secondary windings at the moment of switching by the second timing interval to obtain the second voltage rate; multiplying the second voltage rate and the equivalent parasitic capacitance value to obtain the second common-mode peak; comparing the second common-mode peak with the preset peak threshold value, and outputting a phase shift step locking command when the second common-mode peak is lower than the preset peak threshold value; and writing the compressed transition region phase shift step amplitude to the hybrid phase shift control step register according to the phase shift step locking command.

[0013] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: This invention discloses a phase shift control method for a full-bridge isolated DC-DC converter. Addressing the problem of phase shift angle step causing timing misalignment of the primary and secondary switches in the power switching transition region, leading to excessively high voltage fluctuations on the parasitic capacitance of the transformer windings and injecting common-mode spikes into the grounding loop, the method obtains the current switching frequency, output power, and the amplitude of the phase shift step to be executed. It extracts the phase shift angle step at the moment of operating mode switching and identifies the first timing interval between the voltage reversal moment at the midpoint of the primary bridge arm and the voltage reversal moment of the secondary rectified voltage. When this interval exceeds a preset threshold, a pre-defined control method is invoked. The first voltage rate under the initial transition region phase shift step is calculated by determining the equivalent parasitic capacitance between windings, and then the first common-mode peak is calculated. If it exceeds the preset peak threshold, the phase shift resolution corresponding to the switching frequency is used as the compression lower limit to compress the phase shift step amplitude in the transition region, and the drive timing is regenerated to obtain a smaller second timing interval. The second voltage rate and the two common-mode peaks are recalculated using the same parasitic capacitance. After verifying that it is lower than the threshold, the compressed value is determined as the amplitude of the mixed phase shift control step in the transition region, thereby effectively suppressing common-mode interference, improving power switching smoothness and electromagnetic compatibility. Attached Figure Description

[0014] Figure 1 This is a flowchart of a phase shift control method for a full-bridge isolated DC-DC converter according to the present invention.

[0015] Figure 2 This is a schematic diagram of a phase shift control method for a full-bridge isolated DC-DC converter according to the present invention.

[0016] Figure 3 This is another schematic diagram of a phase shift control method for a full-bridge isolated DC-DC converter according to the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0018] like Figures 1-3 This embodiment of a phase shift control method for a full-bridge isolated DC-DC converter may specifically include: Step S101: Obtain the current switching frequency, actual output power, and phase shift step amplitude to be executed of the converter; determine the power level jump amplitude between adjacent operating conditions; and extract the phase shift angle step corresponding to the trigger time of the working mode switching command.

[0019] The switching frequency of the current drive signal is acquired through the converter's main control interface. The actual output power is extracted from the primary-side current sampling circuit and the secondary-side voltage sampling circuit. The phase shift step amplitude to be executed in the upper-level instruction is read, and the phase shift step amplitude corresponds to the phase adjustment amount of the primary-side bridge arm drive signal. Combining the switching frequency and the actual output power, the current operating condition coordinate point is obtained, consisting of the frequency value and the power value. Then, using the phase shift step amplitude as the step size, one step is extrapolated along the frequency axis or power axis to determine the adjacent operating condition coordinate point corresponding to the current coordinate point. Based on the coordinates of the current operating condition and the adjacent operating condition, a pre-calibrated operating condition and power comparison table is consulted. This table takes frequency and power combinations as input and single-cycle energy transfer capacity as output, obtaining the energy transfer capacity E1 of the current coordinate point and the energy transfer capacity E2 of the adjacent coordinate point. The difference between these two values ​​is then calculated using ΔP = E2 - E1 to obtain the power level jump between adjacent operating conditions. E1 and E2 are both in joules per cycle, and ΔP reflects the change in transferable power within a single cycle when switching from the current operating condition to the adjacent operating condition. At the moment the operating mode switching instruction is triggered, the current phase shift angle register value in the main control chip's interrupt service routine latches as the pre-switching phase shift angle θ1, and simultaneously reads the target phase shift angle carried by the upper-level instruction as the post-switching phase shift angle θ2. The difference between these two values ​​is calculated using Δθ = θ2 - θ1 to obtain the phase shift angle step.

[0020] In one embodiment, the full-bridge isolated DC-DC converter is applied to scenarios such as communication power supplies and energy storage converters. Its primary side consists of two bridge arms composed of four power switching transistors, and the secondary side is rectified and connected to the load. The converter's main control interface is exemplarily handled by a digital signal processing chip. The time interval between the rising edges of the current drive signal is read by a timer capture unit, and the reciprocal is taken to obtain the switching frequency. The primary side current sampling circuit connects a current transformer in series at the input of the primary side transformer, and the secondary side voltage sampling circuit connects a resistor divider network in parallel at the rectified output. The instantaneous current value and instantaneous voltage value are sent to the analog-to-digital conversion channel of the main control chip, and the product is low-pass filtered to obtain the actual output power.

[0021] Specifically, the current operating condition coordinate point is a discrete point on a two-dimensional plane with the switching frequency as the horizontal axis and the actual output power as the vertical axis.

[0022] In one possible implementation, the operating condition and power comparison table is pre-calibrated during the production line debugging phase by sweeping frequency and adding stepped load. Different combinations of frequency and power values ​​are applied to the converter, and the corresponding single-cycle energy transmission capacity is recorded to form a discrete mapping relationship and stored in the non-volatile memory area of ​​the main control chip.

[0023] It should be noted that the power level jump between adjacent operating conditions is obtained by subtracting the energy transfer capacity corresponding to two sets of adjacent coordinate points. When the operating mode switching instruction arrives, the interrupt service routine of the main control chip latches the phase shift angle register value in the current control register as the phase shift angle before switching, and at the same time reads the target phase shift angle carried by the upper-level instruction as the phase shift angle after switching. The difference between the two is the phase shift angle step, which, together with the power level jump, serves as the input basis for subsequent timing determination.

[0024] Step S102: Based on the timing displacement of the primary and secondary switches caused by the phase shift angle step change from the phase shift angle before switching to the phase shift angle after switching, identify the timing interval between the two and obtain the first timing interval.

[0025] Based on the phase shift angle step and the single-cycle duration determined by the switching frequency, the migration distance on the time axis is calculated according to the proportion of the phase shift angle step to the whole cycle, thus obtaining the primary and secondary side switching timing displacement. The primary and secondary side switching timing displacement represents the positional offset of the two primary side bridge arm drive signal edges on the time axis before and after switching. Based on the primary and secondary side switching timing displacement, the moment of the transition edge of the adjusted midpoint square wave voltage is extracted from the primary side bridge arm midpoint voltage sampling circuit to obtain the primary side bridge arm midpoint voltage flipping moment; the moment of the transition edge of the adjusted rectified square wave voltage is extracted from the secondary side rectified output voltage sampling circuit to obtain the secondary side rectified voltage flipping moment. The primary side bridge arm midpoint voltage flipping moment and the secondary side rectified voltage flipping moment are marked and aligned according to the same reference clock. The difference between the two corresponding flipping moments is calculated, and the maximum difference within the switching cycle at the moment of switching is taken as the first timing interval.

[0026] In one embodiment, based on the phase shift angle step and the single-cycle duration determined by the switching frequency, the migration distance on the time axis is calculated as the proportion of the phase shift angle step to the entire cycle, yielding the primary-side bridge arm drive edge displacement. This displacement represents the positional offset on the time axis of the rising and falling edges of the primary-side leading and lagging bridge arm drive signals before and after the step switching. The primary-side comparator and the secondary-side comparator are respectively connected to the primary-side bridge arm midpoint voltage sampling circuit and the secondary-side rectified output voltage sampling circuit. After low-pass filtering, a square wave signal is obtained, whose zero-crossing reference level corresponds to the median of the bridge arm midpoint voltage and the rectified output voltage. The comparator output edge is the transition edge of the square wave. Combining the above displacement, the transition edge time is extracted from the primary-side comparator output to obtain the primary-side bridge arm midpoint voltage reversal time tpk; the transition edge time is extracted from the secondary-side comparator output to obtain the secondary-side rectified voltage reversal time tsk, where k is the sequence number of the edge within the switching cycle. The two switching moments are timestamped at 10ns increments using the same FPGA reference clock. They are paired according to the rule of "same polarity, same sequence number," meaning the rising edge of the primary side is paired with the nearest rising edge of the secondary side, and vice versa for falling edges. The pairing window is limited to no more than half a switching cycle to avoid cross-cycle mismatch. For each pair of switching moments, a difference operation dtk = tsk - tpk is performed. All pairing results within the switching cycle at the instant of switching are iterated through, and the one with the largest absolute value is taken as the maximum timing interval for the switching transient, i.e., the first timing interval, to reflect the worst-case scenario of timing mismatch between the primary and secondary sides during the step transition. In one embodiment, the primary side of the full-bridge isolated DC-DC converter consists of two sets of diagonal bridge arms formed by four power switches. The two ends of the primary transformer winding are connected to the midpoints of the two sets of bridge arms, and the secondary side is rectified by the full-bridge converter and output to the load. The voltage at the midpoint of the primary arm and the rectified voltage of the secondary side are both square waves. Their flip edges maintain a fixed phase relationship during steady-state operation. The phase shift angle jump at the moment of switching the operating mode will disturb this phase relationship, causing the flip times of the primary and secondary sides to be misaligned on the time axis.

[0027] Specifically, the conversion from the phase shift angle step to the time axis migration distance follows the following relationship: Let the switching frequency be f, the single cycle duration determined by the switching frequency be T=1 / f, and the phase shift angle step be denoted as Δφ. Then, the timing displacement of the primary and secondary switches is Δt=Δφ×T / 360, where Δφ is measured in degrees.

[0028] In one possible implementation, the main control chip reads the current driver timer's division value and count limit. The value T is calculated as: T = clock period × division value × count limit. For example, when the system clock period is 10 nanoseconds, the division value is 8, and the count limit is 1000, then T = 10 × 8 × 1000 nanoseconds. After obtaining the value T, the difference between the phase shift angle register before and after the switch is substituted into Δφ, and Δt is calculated according to the ratio Δt = T × Δφ ÷ 360° and stored in the main control chip's intermediate result register. Δt corresponds to the position offset of the two bridge arm drive signal edges on the time axis before and after the switch.

[0029] It should be noted that the switching frequency remains unchanged before and after the operating mode switch; only the phase shift angle changes. Therefore, T is considered a constant in the calculation. Furthermore, the timing of the primary-side bridge arm midpoint voltage reversal is obtained using the high-speed comparator channel of the main control chip. The primary-side bridge arm midpoint voltage sampling circuit connects a resistor divider network at the midpoint of the two bridge arms. The divided voltage is sent to the non-inverting input of the comparator, the inverting input is connected to a 0V reference level, and the comparator output is connected to the input capture unit of the main control chip. Each time the rising edge of the square wave crosses the reference level, a timestamp latch is triggered. The difference between two consecutive rising edge timestamps is the half-cycle duration of the primary-side bridge arm midpoint voltage within that switching cycle. The maximum difference among multiple cycles is taken as the timing of the primary-side bridge arm midpoint voltage reversal. The reversal timing of the secondary-side rectified voltage is obtained in the same way. The secondary-side rectified output voltage sampling circuit is sent to another comparator and input capture unit for recording after passing through an isolation amplifier.

[0030] Preferably, a primary-side comparator is provided on the primary side to receive the drive signal from the primary-side bridge arm, shape it into a square wave, and then send it to the primary-side input capture unit; a secondary-side comparator is provided on the secondary side to receive the control signal from the secondary-side rectification, shape it into a square wave, and then send it to the secondary-side input capture unit. The zero-crossing reference levels of the primary-side and secondary-side comparators are selected according to 50% of their respective square wave amplitudes to avoid false triggering caused by ripples with amplitudes less than 5% of the peak value of the square wave appearing in the flat-top section of the square wave.

[0031] For example, when the square wave amplitude is 5V and the zero-crossing reference level is set to 2.5V, the ripple of the flat-top segment amplitude between 4.75V and 5V will not cause the comparator output to flip.

[0032] In one embodiment, reference clock alignment is accomplished using a global counter within the main control chip. This global counter operates freely at a clock frequency significantly higher than the switching frequency. Both the primary-side input capture unit and the secondary-side input capture unit read the count value from this global counter and mark it with a flag when their respective comparator output edges arrive. The flip-off moment of the primary-side bridge arm midpoint voltage crossing the zero reference level and the flip-off moment of the secondary-side rectified output voltage crossing the zero reference level are thus mapped to the same time base, both provided by the same comparator link, eliminating the need for switching of the detection object. The so-called operating mode switching specifically refers to the instant the controller transitions from a phase-shifted full-bridge mode under heavy load to a fixed-frequency PWM mode under light load. At this time, the primary-side duty cycle and phase shift angle undergo simultaneous step changes. Combined with the release of energy stored in the transformer leakage inductance and the commutation delay of the secondary-side rectifier diodes, this results in an observable lag between the secondary-side square wave flip-off edge and the primary-side square wave flip-off edge. This lag is typically on the order of 50ns to 500ns, hence the term "following behind." Within the switching cycle at the moment of switching, the primary side square wave has one rising edge and one falling edge, for a total of two flips. The secondary side square wave also has two flips. By pairing up the rising edges and the falling edges, and subtracting them, a difference sequence containing two elements is obtained.

[0033] It is understandable that the phase shift adjustment at the moment of switching is presented in a step-like manner. The mismatch between the primary and secondary sides reaches its maximum at the first few flip points of the transition, and gradually returns to a steady state as the subsequent cycles progress. The maximum value of the difference sequence within the switching cycle at the moment of switching is taken as the first timing interval. This value objectively reflects the maximum degree of mismatch in the synchronization relationship between the primary and secondary voltages at the moment of switching.

[0034] Step S103: When the timing interval between the first primary and secondary voltage reversals exceeds the preset timing threshold, the first voltage rate under the initial transition zone phase shift step amplitude is calculated based on the pre-calibrated equivalent parasitic capacitance between transformer windings and the timing interval between the first primary and secondary voltage reversals.

[0035] For the first timing interval, a preset timing threshold is invoked within the main control chip. This timing threshold is the maximum synchronization deviation of the primary and secondary voltage reversal allowed by the transformer winding dielectric layer, defined jointly by the transformer insulation class and rated operating voltage. If the first timing interval is greater than the timing threshold, an equivalent parasitic capacitance invoke command is triggered; otherwise, the original drive timing is maintained. According to the equivalent parasitic capacitance invoke command, the main control chip reads the pre-calibrated equivalent parasitic capacitance value between transformer windings from the transformer parameter table in the non-volatile memory area. This equivalent parasitic capacitance value is pre-stored in the transformer parameter table after an impedance analyzer applies a sweep frequency small signal between the primary and secondary windings and performs capacitive reactance segment fitting on the phase characteristic curve. By combining the potential difference amplitude of the primary and secondary windings at the moment of switching, the voltage jump amplitude across the equivalent parasitic capacitance is obtained. The potential difference amplitude is obtained by combining the DC bus voltage of the converter and the transformer turns ratio. The first voltage rate under the initial transition region phase shift step amplitude is obtained by dividing the voltage jump amplitude by the first timing interval. The initial transition region phase shift step amplitude corresponds to the original phase shift angle step required by the switching command. The equivalent parasitic capacitance value and the first voltage rate are stored together.

[0036] In one embodiment, the voltage reversal and desynchronization of the primary and secondary sides of the full-bridge isolated DC-DC converter during the moment of operating mode switching will couple to the ground loop through the dielectric layer between the primary and secondary windings of the transformer. In the equivalent model, the dielectric layer appears as a small capacitor connected between the primary and secondary sides, and the rapid change in voltage across its terminals will induce a displacement current injected into the grounding path. The first timing interval is a direct measure of the degree of primary-secondary side reversal and desynchronization. Setting a preset timing threshold for the first timing interval and judging it serves as the entry condition for entering the subsequent voltage rate calculation branch.

[0037] Specifically, the timing threshold is obtained by consulting a preset threshold mapping table, which uses the transformer insulation class and rated operating voltage as dual-parameter indices. The transformer insulation class corresponds to the polarization relaxation time constant τ of the dielectric layer. This parameter characterizes the time required for the internal polarization state of the dielectric to reach a new equilibrium after a sudden change in the electric field. A larger τ value means a slower dielectric response, and the internal electric field distribution is more prone to local distortion during rapid voltage switching, thereby reducing the partial discharge initiation voltage. The rated operating voltage U determines the voltage amplitude reference that the dielectric experiences at the moment of switching. The amplitude i of the displacement current excited under the same timing misalignment Δt is proportional to U. In the threshold mapping table, for a transformer with an insulation class of 10 kV and τ of 50 microseconds, the corresponding timing threshold is set to 8 milliseconds when the rated operating voltage is 10 kV; when the rated operating voltage is increased to 35 kV, the timing threshold needs to be reduced to 3 milliseconds under the same insulation class to ensure that the displacement current does not exceed the safety limit. In another possible implementation, the non-volatile memory area of ​​the main control chip is divided into two parts: a nameplate parameter partition and a threshold mapping partition. The former is used to write model information such as insulation class code and rated operating voltage level during the factory debugging of the converter. The latter stores the preset timing thresholds mentioned above and organizes them into a two-dimensional lookup table with the insulation class code and rated operating voltage level as a joint index. Each cell corresponds to a set of turn-on timing thresholds and turn-off timing thresholds. The threshold values ​​in each cell are determined during the converter model finalization stage according to the following process: Select no fewer than 10 prototype units of the same model. Under rated load and maximum allowable ambient temperature conditions, continuously collect the actual turn-on delay from the rising edge of the drive signal to the drain-source voltage of the main power transistor dropping below 10%, and the actual turn-off delay from the turn-off command to the drain-source voltage rising back above 90% of the rated value. Take 1000 samples for each, record the mean as t0 and the standard deviation as s. Calculate the statistical upper limit by adding 3*s to t0, and then multiply it by the margin coefficient k to obtain the final threshold value written to the cell. The value of k ranges from 1.15 to 1.25. The higher the insulation class and the higher the rated voltage, the closer k is to the upper limit. For example, for Class F insulation and a rated voltage of 400 volts, the statistical upper limit of the measured turn-on delay is 1.8 microseconds. Multiplying this by k (equal to 1.2) results in a threshold value of 2.16 microseconds written to the cell. During the power-on self-test, the main control chip first reads the insulation class and rated voltage fields in the nameplate parameter partition, then uses the two as a joint index to access the threshold mapping partition, retrieves the timing threshold of the corresponding cell, and loads it into the comparison register.

[0038] It should be noted that the timing threshold is not directly related to the switching frequency, but only to the dielectric properties and voltage level of the transformer itself. Furthermore, the pre-calibration of the equivalent parasitic capacitance is accomplished using an impedance analyzer.

[0039] In one embodiment, the transformer to be calibrated is placed on the impedance analyzer test bench before installation. The primary winding is short-circuited and serves as the first test port, while the secondary winding is short-circuited and serves as the second test port. The two test ports of the impedance analyzer are connected to the first and second ports, respectively. The impedance analyzer applies a sweep frequency signal with an amplitude of 0.5% to 1% of the rated voltage to both ends, typically with an amplitude of 100mV, and a frequency sweep range of 10kHz to 5MHz. The complex impedance magnitude and phase angle between the two ends are recorded point by point. When the sweep frequency is in the capacitive reactance-dominated range, the phase angle is close to -90°, and the complex impedance magnitude decreases as the frequency increases. The data in this range is fitted using the capacitive reactance formula |Z|=1 / (2πfC) using least squares fitting, where |Z| is the complex impedance magnitude, f is the frequency, and C is the equivalent parasitic capacitance value to be determined. The value of C is obtained by minimizing the objective function Σ(|Z_measured|-|Z_fitted|)². The equivalent parasitic capacitance value, along with the corresponding transformer model code, is written into the transformer parameter table in the non-volatile memory area of ​​the main control chip. Another method for determining the equivalent parasitic capacitance involves performing a least-squares fit on the segment data using the capacitive reactance formula |Z|=1 / (2πfC). Then, the phase angles of adjacent frequency points are checked sequentially. A continuous frequency range where θ is within −90°±δ (e.g., δ=5°) and |Z| monotonically decreases with f is selected as the fitting data segment. For each frequency point fi within this segment and its corresponding measured modulus |Zi|, a least-squares fit is performed according to the capacitive reactance relationship of an ideal capacitor. The fitting process uses the desired capacitance value Cp as the sole parameter, constructing an error sum-of-squares function: Where Cp represents the optimal parasitic capacitance estimate, |Zi| represents the measured impedance modulus, and fi represents the frequency point. Setting dE / dCp = 0, the optimal estimate is obtained, or equivalently, the intercept at slope −1 is obtained by performing a linear regression on ln|Z| and lnf. The calculated capacitance value is the equivalent parasitic capacitance of the transformer. When the equivalent parasitic capacitance call command arrives, the main control chip uses the currently installed transformer model code as the index key to look up the parameter table, retrieves the equivalent parasitic capacitance value from the corresponding cell, and loads it into the arithmetic register.

[0040] Specifically, the potential difference amplitude at the moment of switching between the primary and secondary windings is obtained by combining the DC bus voltage of the converter and the transformer turns ratio. Let the DC bus voltage be Udc, and the turns ratio of the transformer primary and secondary windings be n. Then, the voltage amplitude carried by the primary winding is Udc, and the reflected voltage amplitude presented by the secondary rectification stage is Udc / n. The potential difference amplitude formed when the two act on the two ends of the dielectric layer between the windings is ΔU = Udc + Udc / n. At the moment of switching, the square waves of the primary and secondary windings flip sequentially due to the timing misalignment. The voltage across the equivalent parasitic capacitance jumps from one polarity to the opposite polarity within the first timing interval Δt. The voltage jump amplitude is taken as twice the potential difference amplitude.

[0041] In one embodiment, the voltage rate is obtained by dividing the voltage jump amplitude by the time interval, i.e., the voltage rate value is equal to 2ΔU / Δt, where ΔU is the potential difference between the equivalent parasitic capacitance at the beginning and end of the transition region, and Δt is the time interval occupied by the transition region after the switching command is triggered, in volts per second. The transition region refers to the initial period after the main controller issues a switching command via the communication bus, during which the potential across the equivalent parasitic capacitance migrates from the original steady state to the new steady state, typically ranging from 50 to 200 microseconds. The initial transition region phase shift step amplitude is the phase shift angle step superimposed on the phase shift branch during this period, in degrees, typically ranging from 5 to 30 degrees. As an input control quantity, it directly determines the magnitude of ΔU, thus affecting the output result of the voltage rate; the two are positively correlated. When the target phase shift value sent by the main controller is not compressed by slope limiting or step subdivision, it will be directly applied to the phase shift branch in the form of a single complete step, so that the voltage rate reaches the peak. If it is compressed, the single step is split into several sub-steps and sent down in sequence, which can effectively reduce the voltage rate.

[0042] Preferably, the equivalent parasitic capacitance value and the first voltage rate are stored together in the transition region parameter cache of the main control chip in the form of key-value pairs, waiting to be called in the subsequent common-mode spike estimation stage.

[0043] It is understood that the timing threshold is pre-stored in a register by the main control chip based on the synchronous deviation tolerance of the transformer winding dielectric layer, with the unit being microseconds. The typical value range is 0.5 to 2.0 microseconds, and in this embodiment, it is 1.2 microseconds. The first timing interval is the absolute value of the time difference obtained by the main control chip after comparing the rising edge of the primary-side drive pulse with the rising edge of the secondary-side sampling pulse. The unit is also microseconds, and it is obtained by accumulating the values ​​using an on-chip high-speed counter with a minimum resolution of 20 nanoseconds. This serves as the threshold for determining whether to enter the voltage rate calculation branch. The synchronous deviation tolerance is measured by the ratio t / T of the time difference t between the primary and secondary pulse edges to the transformer primary-side period T. In this embodiment, the upper limit of the ratio allowed by the winding dielectric layer is 0.8%, which corresponds to a 1.2 microsecond timing threshold, i.e., a mapped judgment threshold. When the first timing interval does not exceed the timing threshold, the primary and secondary voltage synchronization relationship remains within the aforementioned tolerance. The main control chip does not issue a capacitor call command to the subsequent compensation capacitor array, i.e., it does not execute the action of switching the spare compensation capacitor in parallel to the primary resonant circuit. This differs from the phase shift step compression command used to adjust the driving phase granularity; it only maintains the current driving timing operation. The timing threshold is defined using a lookup table and correction method: first, the reference timing Tb is located in the threshold mapping table according to the transformer insulation level. Insulation level A corresponds to Tb=120 nanoseconds, level B corresponds to Tb=80 nanoseconds, level F corresponds to Tb=50 nanoseconds, and level H corresponds to Tb=30 nanoseconds; then, a correction coefficient k is applied to Tb according to the rated operating voltage Ur, k=Ur0 / Ur, where Ur0 is the reference voltage under this insulation level. Finally, the timing threshold Tth=Tb*k, thereby making the allowable synchronization deviation smaller when the insulation is lower and the rated voltage is higher. If the first timing interval is greater than Tth, an equivalent parasitic capacitance call command is triggered; if it is not greater than Tth, the original drive timing is maintained. According to the equivalent parasitic capacitance call command, the main control chip reads the pre-calibrated equivalent parasitic capacitance value between transformer windings from the transformer parameter table in the non-volatile memory area. This equivalent parasitic capacitance value is pre-stored in the transformer parameter table after an impedance analyzer applies a sweep frequency small signal between the primary and secondary windings and performs capacitive reactance segment fitting on the phase characteristic curve. Combined with the potential difference amplitude between the primary and secondary windings at the moment of switching, the voltage jump amplitude across the equivalent parasitic capacitance is obtained. This potential difference amplitude is derived from the converter DC bus voltage and the transformer turns ratio. The initial transition region refers to the transient stage from the moment the switching command is issued until the voltage polarity of the primary and secondary windings completes the reversal. During this stage, the main control chip uses the initial phase shift step amplitude Δφ0 required by the switching command as the initial transition region phase shift step amplitude. Δφ0 is measured in electrical degrees and reflects the first step span of the aforementioned step phase shift adjustment. The first voltage rate dv1 under the condition Δφ0 is obtained by dividing the voltage jump amplitude by the first timing interval.

[0044] Step S104: Calculate the first common-mode spike injected into the grounding loop based on the first voltage change rate and parasitic capacitance value. Compare the first common-mode spike with a preset spike threshold. If it exceeds the threshold, use the phase shift resolution corresponding to the switching frequency as the compression lower limit to compress the phase shift step amplitude in the transition region and obtain the compressed phase shift step amplitude in the transition region.

[0045] Based on the first voltage change rate and the equivalent parasitic capacitance value, a product operation is performed according to the displacement current coupling relationship, that is, the first voltage change rate is multiplied by the equivalent parasitic capacitance value to obtain the first common-mode spike injected into the grounding loop. The first common-mode spike has the dimension of amperes. The spike threshold preset inside the main control chip is called. The spike threshold is jointly defined by the converter electromagnetic compatibility level and the upper limit of the allowable common-mode current of the grounding loop. The first common-mode spike is compared with the spike threshold. If the first common-mode spike exceeds the spike threshold, the phase shift step compression command is activated; if it does not exceed the threshold, the initial transition region phase shift step amplitude is maintained without modification. According to the phase shift step compression command, the phase shift resolution corresponding to the switching frequency is obtained. The phase shift resolution is the smallest phase shift adjustment step size that the phase shift timer can distinguish in a single switching cycle. The phase shift resolution is used as the compression lower limit. The initial transition region phase shift step amplitude is reduced successively by a preset decreasing step size until the reduced value is not lower than the compression lower limit, thus obtaining the compressed transition region phase shift step amplitude.

[0046] In one embodiment, during the switching of the operating mode of the full-bridge isolated DC-DC converter, the desynchronization caused by the voltage flipping between the primary and secondary sides will couple out a displacement current through the equivalent parasitic capacitance between the transformer windings. This displacement current is injected into the ground along the secondary side shield ground or chassis ground path, forming a spike disturbance at the common-mode terminal, namely the first common-mode spike. The amplitude of the first common-mode spike directly corresponds to the intensity of electromagnetic interference generated by the converter at the switching instant.

[0047] Specifically, the first common-mode spike is derived according to the displacement-current coupling relationship of the capacitive element. Let the equivalent parasitic capacitance be Cp, and the first voltage variation be dv / dt, then the instantaneous current amplitude injected into the ground loop is i = Cp × dv / dt.

[0048] In one possible implementation, the arithmetic logic unit of the main control chip reads the first voltage change rate and equivalent parasitic capacitance value stored in the transition region parameter cache, performs a single-precision floating-point multiplication operation according to the aforementioned displacement-current coupling relationship, and writes the operation result into the common-mode spike cache register and marks it with the initial transition region phase shift step amplitude. The operation result is the first common-mode spike, with the dimension in amperes. This operation process does not involve any actual sampling of external signals; all data comes from the pre-calibrated capacitance value and the voltage change rate calculated at the moment of this switching. The operation delay is controlled to be completed within one switching cycle.

[0049] It should be noted that the displacement-current coupling relationship only holds during voltage changes. In steady state, dv / dt approaches zero, and the first common-mode spike also approaches zero. Therefore, the first common-mode spike specifically refers to the peak amplitude at the moment of switching. Furthermore, the spike threshold is jointly defined by the converter's electromagnetic compatibility (EMC) level and the upper limit of the allowable common-mode current in the grounding loop. The EMC level of the converter represents the acceptable level for both immunity and emission limits. Common levels are determined by the applicable equipment category; a higher level indicates a more stringent limit on the radiated common-mode current. The upper limit of the allowable common-mode current in the grounding loop is the allowed peak amplitude of the common-mode current flowing from the converter chassis ground through the test network, weighted in the frequency spectrum.

[0050] In one embodiment, the main control chip stores a spike threshold mapping table in its non-volatile memory area. Using the electromagnetic compatibility level code and the allowed common-mode current upper limit as a joint index, each cell stores the corresponding single-precision floating-point threshold. During the power-on self-test (POST), the main control chip reads the selected cell and writes it to the spike threshold register Vth. Thereafter, all comparison steps use this register as the sole source of thresholds, eliminating the need for a separate preset calling channel. The first common-mode spike Vp, output from the preceding single-precision floating-point multiplier, is fed into the same floating-point comparator as Vth. The value is directly determined according to the IEEE 754 single-precision format, and a flag bit F is output: F is set to 1 when Vp is greater than Vth, activating the phase-shift step compression instruction; F is cleared to 0 when Vp is less than or equal to Vth. The initial transition zone refers to the dynamic adjustment phase of the converter from power-on until the output voltage enters the regulated window, generally lasting 3 to 8 switching cycles. The phase shift step amplitude Δφ in this phase is the step increment of the phase shift angle between two adjacent switching cycles. Following the previous step-based phase shift adjustment method, its value ranges from 2 to 6 degrees. When F is cleared to 0, Δφ is directly loaded into the phase shift control register of the next switching cycle according to the current setting. When F is set to 1, Δφ is reduced by a compression command before being loaded, with a reduction factor of 0.4 to 0.6.

[0051] Specifically, the phase shift resolution reflects the smallest granularity at which the phase shift timer discretely adjusts the phase shift angle within a single switching cycle.

[0052] In one embodiment, the total value of the phase-shift timer of the main control chip within one switching cycle is denoted as N. The minimum resolvable adjustment step of the phase shift angle corresponds to the angle obtained by dividing 360 degrees by N, which is the phase shift resolution. When the switching frequency remains constant, N is a fixed value, and the phase shift resolution is uniquely determined. The phase shift resolution serves as the lowest value to which the phase shift step amplitude can converge during this compression process, preventing the compression depth from exceeding the physical resolvable limit of the phase shift timer.

[0053] It is understandable that phase shift resolution refers to the minimum phase increment that the main control chip can address within a switching cycle. It is determined by the reciprocal of the switching frequency and the bit width of the phase shifter. Once the switching frequency is determined, it is fixed as a physical constant, forming a hard constraint lower limit for deducting the phase shift step amplitude in the transition region. The step value after any round of deduction must not be lower than this resolution; otherwise, compression will stop and the current value will be locked.

[0054] Specifically, the step amplitude reduction compression is carried out in the scheduling channel of the main control chip in an iterative deduction manner. Each round takes the step amplitude output from the previous round as input, and after deduction by a fixed step size, the phase shift step amplitude of the transition region after compression in this round is obtained, and then sent to the next round for judgment, until the lower limit of phase shift resolution is reached or the convergence condition is met, and then it exits. For example, if the initial step amplitude is 0.5 degrees, the fixed step size is 0.05 degrees, and the phase shift resolution is 0.1 degrees, then when the deduction is reduced to 0.1 degrees in the 8th round, the output is latched and no further compression is carried out.

[0055] In one embodiment, a preset decreasing step size is pre-set according to a certain proportion of the initial transition region phase shift step amplitude. The proportion is determined by actual measurement during the converter model finalization stage. The initial transition region phase shift step amplitude is deducted by one preset decreasing step size in each iteration within the scheduling channel. The deducted step amplitude is immediately compared with the compression lower limit. If it is higher than the compression lower limit, the value is retained and the next iteration begins. If it is lower than the compression lower limit, the iteration reverts to the previous iteration result and stops. The step amplitude retained at the time of stopping is the compressed transition region phase shift step amplitude. In another embodiment, during the converter model finalization stage, the proportional relationship between the preset decreasing step size and the initial transition region phase shift step amplitude is determined by actual measurement.

[0056] For example, assuming the amplitude of the phase shift step in the initial transition region is A0=100, with the unit being degree or nanosecond, and the proportional coefficient k=15% selected through actual measurement, then the preset decreasing step Δ=A0×k=15. Meanwhile, the compression lower limit Amin=30 is set, indicating that the step amplitude is not allowed to be lower than this value. Every time an iteration is completed in the scheduling channel, a preset decreasing step Δ is subtracted from the current step amplitude Acur to obtain a candidate value Anext=Acur−Δ. Then Anext is immediately compared with the compression lower limit Amin: if Anext>Amin, the value is accepted and the next iteration is entered; if Anext<Amin, the iteration result of the previous round Acur is rolled back to, and the iteration is terminated. The following is the iteration process taking the above numerical values as an example. Round 1: A1=100−15=85, 85>30, retained, continue; Round 2: A2=85−15=70, 70>30, retained; Round 3: A3=70−15=55, 55>30, retained; Round 4: A4=55−15=40, 40>30, retained; Round 5: A5=40−15=25, 25<30, failing to meet the condition, roll back to the result of the previous round 40, stop the iteration. The phase shift step amplitude of the transition region after compression is 40. This value not only realizes the successive decreasing of the step amplitude, but also avoids system instability caused by exceeding the compression lower limit, and ensures the reliability and smoothness of the converter operating in the transition region.

[0057] Preferably, the preset decreasing step remains constant during the iteration, and the decreasing compression presents a linear convergence trend; in another embodiment, the preset decreasing step decreases with the number of iteration rounds, and the decreasing compression presents a decaying convergence trend. Both trends can make the phase shift step amplitude of the transition region after compression stably converge above the compression lower limit.

[0058] Step S105: regenerate the driving timing according to the compressed phase shift step amplitude of the transition region, collect the flipping moment of the midpoint voltage of the primary bridge arm and the flipping moment of the secondary rectified voltage again, identify the timing interval between the flipping moment of the midpoint voltage of the primary bridge arm and the flipping moment of the secondary rectified voltage, and obtain a second timing interval smaller than the first timing interval.

[0059] Based on the compressed transition region phase shift step amplitude, the main control chip phase shift control unit sends a phase adjustment command to the drive channels of the four power switches on the primary side. The phase shift timer loads the comparison register according to the discrete counting beat corresponding to the compressed transition region phase shift step amplitude to obtain the regenerated primary side bridge arm drive timing. Based on the regenerated primary side bridge arm drive timing, the moment of the transition edge of the midpoint square wave voltage is extracted again from the primary side bridge arm midpoint voltage sampling circuit to obtain the moment when the primary side bridge arm midpoint voltage flips again; the moment of the transition edge of the rectified square wave voltage is extracted again from the secondary side rectified output voltage sampling circuit to obtain the moment when the secondary side rectified voltage flips again. The difference between the corresponding moment when the primary side bridge arm midpoint voltage flips again and the moment when the secondary side rectified voltage flips again is calculated, and the maximum difference within the switching cycle after the switch is taken as the second timing interval, which is less than the first timing interval.

[0060] In one embodiment, for a full-bridge isolated DC-DC converter, the transition region refers to the phase switching window during the alternation of the drive signals of the two sets of primary-side bridge arms, during which the secondary-side rectifier bridge voltage flips accordingly. The phase shift step amplitude of the transition region is the electrical angle adjustment in degrees for each step within this window, with an initial value typically set to 8 to 12 degrees. When the compressed step amplitude replaces the initial step amplitude, the drive phase difference between the two sets of primary-side bridge arms decreases, and the timing interval between the primary and secondary voltage flips shortens accordingly. The degree of desynchronization is measured by the reduction in this timing interval, and the two form a causal relationship; the shorter the timing interval, the more moderate the desynchronization. The compressed step amplitude is provided by a transition region parameter cache allocated within the main control chip. This cache is a dedicated storage partition in the on-chip register, indexed according to the bridge arm number and load level. At the moment of switching, the phase shift control unit reads the corresponding entry through the address pointer, loads the retrieved degree value as the effective phase shift adjustment amount into the PWM comparator register, and completes a single step transmission.

[0061] Specifically, the main control chip phase shift control unit sends phase adjustment commands to the drive channels of the four power switching transistors on the primary side. The phase offset of the phase adjustment commands is filled according to the amplitude of the phase shift step in the compressed transition region.

[0062] In one possible implementation, the two power switches of one bridge arm on the primary side are directly connected to the output of the master reference timer of the main control chip, while the two power switches of the other bridge arm are connected to the output of the phase shift timer. The comparator register of the phase shift timer stores the delay count value relative to the master reference timer, which is the discrete counting cycle number corresponding to the amplitude of the compressed transition region phase shift step.

[0063] For example, if the total number of counting cycles corresponding to a single switching cycle is N after the switching frequency is determined, and the amplitude of the compressed transition region phase shift step is denoted as φ2, then the delay count value K = N × φ2 / 360, where K is an integer number of counting cycles. The main control chip writes K into the comparison register of the phase shift timer. Whenever the phase shift timer count value is equal to K, it outputs a drive toggle pulse. The drive toggle pulse is sent to the input terminal of the gate driver chip of another set of bridge arm power switches to obtain the regenerated primary side bridge arm drive timing.

[0064] It is understandable that the regenerated primary-side bridge arm drive timing starts driving the primary-side circuit from the beginning of the switching cycle at the moment of switching. The method for obtaining the moment when the voltage at the midpoint of the primary-side bridge arm flips again and the moment when the secondary-side rectified voltage flips again is the same as the acquisition process performed during the first synchronous acquisition after system startup, i.e., the acquisition of the voltage flip time difference before and after the first switching, and both reuse the same set of sampling and capture hardware.

[0065] Specifically, the main control chip is configured with two independent input capture units, corresponding to the primary and secondary sampling channels respectively. The primary sampling circuit connects a 10:1 resistor divider network at the midpoint of the two bridge arms. The divided voltage is sent to the non-inverting input of the first comparator, and the zero-crossing reference level is sent to its inverting input. The secondary rectified output voltage is connected to the second comparator after passing through a voltage divider network of the same specification. The outputs of the two comparators are respectively connected to the capture pins of the corresponding input capture units of the main control chip. Whenever the midpoint square wave voltage or the secondary rectified voltage crosses the zero-crossing reference level, the comparator output generates a rising or falling edge. When this edge arrives, the hardware circuit of the input capture unit automatically latches the current value of the timer's free-running counter into the capture register and sets the capture interrupt flag. The main control chip reads the value of the capture register in the interrupt service routine and stores it in the corresponding timestamp variable. The read value is the time when the primary bridge arm midpoint voltage and the secondary rectified voltage flip again.

[0066] It should be noted that the second acquisition uses the same hardware circuit and the same zero-crossing reference level as the first acquisition, and the two sampling data are consistent in terms of range and sampling accuracy.

[0067] Specifically, the timing of the primary side bridge arm midpoint voltage reversal and the timing of the secondary side rectified voltage reversal are both marked with a global counter. This global counter is a 32-bit free-running counter, with a clock source of 125 MHz time base signal obtained by dividing the system clock by 8. The counter value is automatically latched by the input capture module at the voltage reversal trigger moment, with a unit time resolution of 8 nanoseconds. The two are paired in corresponding order, and the difference is calculated for each pair of reversal times to obtain a set of differences within the switching cycle after the switch. The largest of these differences is taken as the second timing interval, which is smaller than the first timing interval. When the secondary side rectifier switching noise is large, causing the single-cycle difference fluctuation to exceed 10% of the first timing interval, the arithmetic mean of the largest differences within 5 consecutive switching cycles can be taken as the second timing interval; when a fast response to transient conditions is required, only the pair of differences corresponding to the first transition can be taken as the second timing interval. In another implementation, starting from the first switching cycle after the switch, the main control chip continuously collects the difference values ​​of the subsequent 5 to 10 switching cycles, and takes the average of the maximum difference values ​​among multiple cycles as the second timing interval to reduce the disturbance of occasional noise on the sampling results. In yet another implementation, the main control chip only takes the pair of differences corresponding to the first transition as the second timing interval within the first switching cycle after the switch. In the above three implementations, since the compression of the step amplitude makes the rising edge and falling edge of the PWM waveform closer on the time axis, and the time interval between adjacent transition edges is shortened, the value of the second timing interval is less than the first timing interval before compression, regardless of whether the maximum difference, average value, or first difference value is used, which conforms to the value rule of judging the step state by the change of timing interval. In another implementation of obtaining the second timing interval, according to the compressed transition region phase shift step amplitude, the phase shift control unit of the main control chip issues a phase adjustment command to the drive channel of the four power switches on the primary side, and the phase shift timer loads the comparison register according to the discrete counting beat corresponding to the compressed transition region phase shift step amplitude to obtain the regenerated primary side bridge arm drive timing. Based on the regenerated primary-side bridge arm drive timing, the moment of the transition edge of the midpoint square wave voltage is extracted again from the primary-side bridge arm midpoint voltage sampling circuit to obtain the moment when the primary-side bridge arm midpoint voltage flips again; the moment of the transition edge of the rectified square wave voltage is extracted again from the secondary-side rectified output voltage sampling circuit to obtain the moment when the secondary-side rectified voltage flips again. The difference between the corresponding moments when the primary-side bridge arm midpoint voltage flips again and the corresponding moments when the secondary-side rectified voltage flips again is calculated, and the maximum difference within the switching cycle after the phase shift step amplitude compression is taken as the second timing interval.Since the phase shift step amplitude after compression is smaller than the phase shift step amplitude before compression, the phase difference between the leading and lagging bridge arms on the primary side is reduced by Δφ = φ before compression - φ after compression. This reduction in phase difference causes the time deviation between the voltage reversal time of the primary side bridge arm midpoint and the voltage reversal time of the secondary side rectified voltage to decrease accordingly by ΔT = Δφ / 360 × T switching cycle, thereby making the second timing interval smaller than the first timing interval.

[0068] Step S106: Recalculate the second voltage rate using the second timing interval and the same equivalent parasitic capacitance value, thereby determining the second common-mode peak. After verifying that the second common-mode peak is lower than the preset peak threshold, determine the compressed transition region phase shift step amplitude as the hybrid phase shift control step amplitude of the full-bridge isolated DC-DC converter in the power switching transition region.

[0069] Based on the second timing interval, the potential difference amplitude of the primary and secondary windings at the moment of switching is divided by the second timing interval to obtain the second voltage rate across the equivalent parasitic capacitance. Let the potential difference amplitude be ΔU, and the second timing interval be denoted as Δt2. Then, the second voltage rate across the equivalent parasitic capacitance is ΔU ÷ Δt2. The second voltage rate is the rate of voltage change borne by the dielectric layer between the transformer windings under the compressed transition region phase shift step amplitude, measured in volts per second. The arithmetic logic unit performs a single-precision floating-point division operation according to the ΔU ÷ Δt2 division relationship. Based on the second voltage rate and the equivalent parasitic capacitance value, the second common-mode spike injected into the ground loop under the compressed transition region phase shift step amplitude is obtained by multiplying the second voltage rate by the equivalent parasitic capacitance value. The second common-mode spike is numerically compared with the spike threshold. If the second common-mode spike is lower than the spike threshold, a phase shift step locking command is output. According to the phase shift step locking instruction, the main control chip phase shift control unit writes the compressed transition region phase shift step amplitude to the hybrid phase shift control step register. This amplitude is the hybrid phase shift control step amplitude of the full-bridge isolated DC-DC converter in the power switching transition region.

[0070] In one embodiment, the phase shift step amplitude of the full-bridge isolated DC-DC converter in the power switching transition region must simultaneously meet two requirements: first, it must not cause excessively steep voltage change excitation to the parasitic capacitance between transformer windings; second, it must not be lower than the physical resolvable limit of the phase shift timer. The compressed transition region phase shift step amplitude, after decreasing compression, falls between these two boundaries. Performing secondary voltage rate and common-mode spike recalculation on the compressed transition region phase shift step amplitude is a necessary verification step to formally define it as the control step value for the transition region.

[0071] Specifically, the potential difference amplitude of the primary and secondary windings at the moment of switching is obtained by combining the DC bus voltage of the converter and the transformer turns ratio. Let the potential difference amplitude be ΔU, and the second timing interval be denoted as Δt2. Then the second voltage rate across the equivalent parasitic capacitance is ΔU÷Δt2, with the dimension in volts per second.

[0072] In one possible implementation, the arithmetic logic unit of the main control chip reads the second timing interval from the input capture buffer, reads the potential difference amplitude from the transformer parameter table, performs a single-precision floating-point division operation according to the division relationship ΔU÷Δt2, and stores the operation result in the second slot of the voltage rate buffer. The operation result is the second voltage rate.

[0073] It is understood that the second timing interval is smaller than the first timing interval, and under the same potential difference amplitude, the second voltage rate is smaller than the first voltage rate. Further, the arithmetic logic unit of the main control chip reads the equivalent parasitic capacitance value from the transformer parameter table, and reads the second voltage rate from the second slot of the voltage rate cache. It performs a single-precision floating-point multiplication operation according to the displacement-current coupling relationship, and stores the result in the second slot of the common-mode spike cache. This result is the second common-mode spike.

[0074] In one embodiment, the second common-mode spike and the spike threshold are compared bit by bit in the comparator. If the second common-mode spike is lower than the spike threshold, the comparator flag is set and a phase shift step lock command is output. If the second common-mode spike is not lower than the spike threshold, the main control chip reverts to the previous round of decreasing compression action, reduces the decreasing step size by a certain ratio, and re-enters the compression process.

[0075] It should be noted that the phase shift step lock instruction is sent to the write enable terminal of the hybrid phase shift control step register in the form of an interrupt signal.

[0076] Specifically, the hybrid phase shift control step register is a hardware register within the main control chip's phase shift control unit dedicated to storing the step values ​​in the transition region, and it is set up in parallel with the steady-state step register. During steady-state operation, the phase shift control unit reads the step values ​​from the steady-state step register, while in the power switching transition region, the phase shift control unit reads the step values ​​from the hybrid phase shift control step register. The compressed transition region phase shift step amplitude, after being written into the hybrid phase shift control step register, is determined as the hybrid phase shift control step amplitude of the full-bridge isolated DC-DC converter in the power switching transition region.

[0077] It is understandable that the meaning of "hybrid" is that the phase shift step amplitude in the steady state period is selected according to the requirements of frequency reduction and disturbance suppression, and the phase shift step amplitude in the transition region is selected according to the requirements of suppressing the voltage reversal and loss of synchronization of the primary and secondary sides. The two sets of step values ​​are respectively carried by the steady state step register and the hybrid phase shift control step register. The phase shift control unit automatically switches and reads according to the current operating section to form a hybrid phase shift adjustment trend that coordinates the steady state and the transition region.

[0078] Preferably, in another embodiment, the hybrid phase shift control step register stores the compressed transition zone phase shift step amplitude and adds a timestamp. Each time the transition zone is triggered, the timestamp is checked to see if it matches the update time of the transformer parameter table. If they do not match, the voltage rate recalculation process is restarted. In yet another embodiment, the hybrid phase shift control step register is divided into multiple sub-units according to the converter output power level. Each sub-unit independently stores the transition zone step value under the corresponding level. The phase shift control unit looks up the value of the corresponding sub-unit according to the current actual output power level.

[0079] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. The present invention has been described in detail with reference to preferred embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications and substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A phase shift control method for a full-bridge isolated DC-DC converter, characterized in that, The method includes: acquiring the current switching frequency, actual output power, and phase shift step amplitude to be executed of the converter; determining the power level span between adjacent operating conditions; and extracting the phase shift angle step corresponding to the trigger time of the working mode switching command. Based on the primary and secondary switching timing displacement caused by the phase shift angle step, the primary and secondary voltage reversal timing interval is identified to obtain a first timing interval. When the first timing interval exceeds a preset timing threshold, the first voltage rate under the initial transition region phase shift step amplitude is calculated based on the pre-calibrated equivalent parasitic capacitance between transformer windings and the first timing interval. The first common mode injected into the grounding loop is calculated based on the first voltage rate and the equivalent parasitic capacitance value. For the first common-mode peak, compare it with a preset peak threshold. If it exceeds the threshold, compress the transition region phase shift step amplitude using the phase shift resolution corresponding to the switching frequency as the compression lower limit to obtain the compressed transition region phase shift step amplitude. Regenerate the drive timing based on the compressed transition region phase shift step amplitude, and re-identify the primary and secondary voltage switching timing interval to obtain a second timing interval that is smaller than the first timing interval. Recalculate the second voltage rate using the second timing interval and the equivalent parasitic capacitance value to determine the second common-mode peak. After verifying that the second common-mode peak is lower than the preset peak threshold, the compressed transition region phase shift step amplitude is determined as the hybrid phase shift control step amplitude.

2. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, The process of acquiring the current switching frequency, actual output power, and phase shift step amplitude to be executed of the converter includes: acquiring the switching frequency of the current drive signal, extracting the actual output power from the primary current sampling circuit and the secondary voltage sampling circuit, and reading the phase shift step amplitude to be executed from the host instruction, wherein the phase shift step amplitude corresponds to the phase adjustment amount of the primary bridge arm drive signal.

3. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, The step of determining the power level span between adjacent operating conditions and extracting the phase shift angle step corresponding to the trigger time of the operating mode switching command includes: obtaining the current operating condition coordinate point by combining the switching frequency and the actual output power; obtaining the power level span by querying a pre-calibrated operating condition and power comparison table based on the current operating condition coordinate point; and extracting the difference between the phase shift angle before and after the switching from the control register to obtain the phase shift angle step.

4. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, The step of identifying the primary and secondary side voltage reversal timing interval based on the primary and secondary side switching timing displacement caused by the phase shift angle step, and obtaining the first timing interval, includes: converting the single cycle duration determined by the phase shift angle step and the switching frequency into a migration distance on the time axis according to the proportion of the phase shift angle step to the whole cycle, to obtain the primary and secondary side switching timing displacement; extracting the moment of the transition edge of the midpoint square wave voltage from the primary side bridge arm midpoint voltage sampling circuit to obtain the primary side bridge arm midpoint voltage reversal moment; extracting the moment of the transition edge of the rectified square wave voltage from the secondary side rectified output voltage sampling circuit to obtain the secondary side rectified voltage reversal moment; marking and aligning the primary side bridge arm midpoint voltage reversal moment and the secondary side rectified voltage reversal moment according to the same reference clock, and taking the maximum difference within the switching cycle at the moment of switching as the first timing interval.

5. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, When the first timing interval exceeds the preset timing threshold, the following steps are taken: calling the preset timing threshold internally set by the main control chip for the first timing interval. The preset timing threshold is the maximum synchronization deviation of the primary and secondary voltage reversal allowed by the dielectric layer of the transformer winding, which is jointly defined by the transformer insulation class and the rated operating voltage. When the first timing interval is greater than the preset timing threshold, an equivalent parasitic capacitance calling instruction is triggered; otherwise, the original driving timing is maintained.

6. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 5, characterized in that, After triggering the equivalent parasitic capacitance call instruction, the process includes: according to the equivalent parasitic capacitance call instruction, the main control chip reads the pre-calibrated equivalent parasitic capacitance value between transformer windings from the transformer parameter table in the non-volatile memory area, and obtains the voltage jump amplitude across the equivalent parasitic capacitance by combining the potential difference amplitude between the primary and secondary windings at the moment of switching; and obtains the first voltage rate under the initial transition region phase shift step amplitude by dividing the voltage jump amplitude by the first timing interval.

7. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, The step of calculating the first common-mode spike injected into the grounding loop based on the first voltage change rate and the equivalent parasitic capacitance value includes: performing a product operation based on the first voltage change rate and the equivalent parasitic capacitance value according to the displacement current coupling relationship to obtain the first common-mode spike injected into the grounding loop.

8. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, The step of comparing the first common-mode peak with a preset peak threshold and compressing the transition region phase shift step amplitude using the phase shift resolution corresponding to the switching frequency as the compression lower limit to obtain the compressed transition region phase shift step amplitude includes: comparing the first common-mode peak with the preset peak threshold value; activating a phase shift step compression command when the first common-mode peak exceeds the preset peak threshold value; obtaining the phase shift resolution corresponding to the switching frequency according to the phase shift step compression command, wherein the phase shift resolution is the smallest phase shift adjustment step size that the phase shift timer can distinguish within a single switching cycle, and using the phase shift resolution as the compression lower limit; and successively reducing the initial transition region phase shift step amplitude by a preset decreasing step size until the reduced value is not lower than the compression lower limit to obtain the compressed transition region phase shift step amplitude.

9. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, The step of regenerating the drive timing based on the compressed transition region phase shift step amplitude and re-identifying the primary and secondary voltage reversal timing interval to obtain a second timing interval smaller than the first timing interval includes: the main control chip phase shift control unit sends a phase adjustment command to the drive channels of the four power switches on the primary side; the phase shift timer loads the comparison register according to the discrete counting beat corresponding to the compressed transition region phase shift step amplitude to obtain the regenerated primary side bridge arm drive timing; the step of the transition edge of the midpoint square wave voltage is extracted again from the primary side bridge arm midpoint voltage sampling circuit; the step of the transition edge of the rectified square wave voltage is extracted again from the secondary side rectified output voltage sampling circuit; the difference between the two reversal times, the step of the midpoint square wave voltage and the step of the rectified square wave voltage, is taken as the second timing interval.

10. The phase shift control method for a full-bridge isolated DC-DC converter according to claim 1, characterized in that, The process involves recalculating the second voltage rate using the second timing interval and the equivalent parasitic capacitance value, thereby determining the second common-mode spike. After verifying that the second common-mode spike is lower than a preset spike threshold, the compressed transition region phase shift step amplitude is determined as the hybrid phase shift control step amplitude. This includes: dividing the potential difference amplitude of the primary and secondary windings at the moment of switching by the second timing interval to obtain the second voltage rate; multiplying the second voltage rate by the equivalent parasitic capacitance value to obtain the second common-mode spike; comparing the second common-mode spike with the preset spike threshold value, and outputting a phase shift step locking command when the second common-mode spike is lower than the preset spike threshold value; and writing the compressed transition region phase shift step amplitude to the hybrid phase shift control step register according to the phase shift step locking command.

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