A device package structure and a device package method

Abstract

The application provides a device packaging structure and a device packaging method. The device packaging structure comprises a substrate, a bump provided on the substrate, and a device electrically connected to the substrate through the bump. The substrate comprises a substrate, an electrode layer, a thickening layer, a temperature compensation layer, a frequency modulation layer, and an electrical interconnection layer which are sequentially arranged on the top of the substrate. The electrode layer comprises a first electrode layer and a second electrode layer. The thickening layer is arranged on the top of the first electrode layer, and the projection of the thickening layer on the substrate is at least within the projection of the first electrode layer on the substrate. The temperature compensation layer is arranged on the top of the second electrode layer. The electrical interconnection layer is electrically connected to the electrode layer through the thickening layer, and the projection of the electrical interconnection layer on the substrate at least overlaps with the projection of the first electrode layer on the substrate in any cross section away from the substrate. The bump is electrically connected to the electrical interconnection layer and the device respectively.

Description

Technical Field

[0001] This application relates to the field of device packaging technology, and in particular to a device packaging structure and a device packaging method. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not to be construed as prior art simply because it is included in this section.

[0003] In existing technologies, temperature-compensated surface acoustic wave (TC-SAW) filters typically employ a double-layer organic dry film photolithography process to fabricate cavities on the wafer surface. However, this approach suffers from several significant drawbacks: First, the stress difference between the two thin films creates residual stress on the wafer surface, leading to unintended frequency deviations in the resonator and consequently reducing device performance and production yield. Second, the size of the cavity structure formed by the dry film is limited; excessively large cavities are prone to structural collapse. Furthermore, the cavity surface created by this process cannot be rewired and lacks an effective heat dissipation enhancement mechanism, making it difficult to meet the application requirements of high-power devices.

[0004] Therefore, there is an urgent need to propose a device packaging structure and its fabrication method to solve the above-mentioned technical problems. Summary of the Invention

[0005] This application provides a device packaging structure and a device packaging method in several aspects, so as to ensure the reliability of the device packaging structure while ensuring its good heat dissipation performance and miniaturization.

[0006] In a first aspect, this application proposes a device packaging structure, the device packaging structure comprising: a substrate, bumps disposed on the substrate, and a device electrically connected to the substrate through the bumps; The substrate includes: a substrate and an electrode layer, a thickening layer, a temperature compensation layer, a frequency modulation layer, and an electrical interconnection layer stacked on top of the substrate; The electrode layer includes a first electrode layer and a second electrode layer; The thickened layer is located on top of the first electrode layer, and the projection of the thickened layer onto the substrate is at least within the projection of the first electrode layer onto the substrate; The temperature compensation layer is located on top of the second electrode layer; The electrical interconnect layer is electrically connected to the electrode layer through the thickened layer, and the projection of any cross section of the electrical interconnect layer onto the substrate in the direction away from the substrate overlaps at least with the projection of the first electrode layer onto the substrate. The bumps are electrically connected to the electrical interconnect layer and the device, respectively.

[0007] Furthermore, the electrical interconnection layer includes an electrical interconnection structure and an insulating dielectric layer; the electrical interconnection structure includes a first electrical interconnection structure and a second electrical interconnection structure; the first electrical interconnection structure is embedded in the insulating dielectric layer, and the second electrical interconnection structure is disposed on the top of the insulating dielectric layer for electrically connecting the bump.

[0008] Furthermore, the frequency modulation layer includes a first frequency modulation layer, a second frequency modulation layer, and a third frequency modulation layer from the direction away from the substrate, and the density of the second frequency modulation layer is lower than the density of the first frequency modulation layer and the density of the third frequency modulation layer.

[0009] Furthermore, the material of the first frequency modulation layer includes silicon nitride; the material of the second frequency modulation layer includes silicon dioxide; and the material of the third frequency modulation layer includes silicon nitride.

[0010] Furthermore, the thickness of the first frequency modulation layer is less than 0.1 micrometers; the thickness of the second frequency modulation layer ranges from 0.1 micrometers to 1.5 micrometers; and the thickness of the third frequency modulation layer is equal to or greater than 1.5 micrometers.

[0011] Furthermore, the projection of the temperature compensation layer onto the substrate is located within the projection of the frequency modulation layer onto the substrate, and the projection of the frequency modulation layer onto the substrate partially overlaps with the projection of the first electrode layer onto the substrate.

[0012] Furthermore, the first electrical interconnection structure includes a first rewiring layer, and the second electrical interconnection structure includes a second rewiring layer; when the thickness of the electrical interconnection layer exceeds a preset value, the first rewiring layer includes multiple layers.

[0013] Furthermore, when the first redistribution layer is multilayered, the first electrical interconnect structure further includes redistribution vias; when the first electrical interconnect structure includes redistribution vias, the projection of the target redistribution layer on the substrate completely covers the projection of the target redistribution via on the substrate, and the projection area of ​​the target redistribution layer on the substrate is equal to or greater than the projection area of ​​the target redistribution via on the substrate, and the target redistribution via and the target redistribution layer include adjacent redistribution vias and redistribution layers along the direction away from the substrate.

[0014] Furthermore, the projection portions of the first redistribution layers of any two adjacent layers overlap on the substrate; and / or, the overlapping projections of the first redistribution layers of any two adjacent layers on the substrate overlap with the projections of the redistribution vias on the substrate.

[0015] Furthermore, the size of the top surface of the thickened layer is smaller than the size of the bottom surface of the thickened layer in a direction parallel to the top surface of the substrate, and the size of the thickened layer in the first direction varies linearly from the direction away from the substrate; and / or, the distance between the top surface of the frequency modulation layer and the substrate is less than or equal to the distance between the top surface of the thickened layer and the substrate.

[0016] Furthermore, the material of the temperature compensation layer includes silicon dioxide; both the second frequency modulation layer and the third frequency modulation layer include alternating layers of silicon dioxide and silicon nitride.

[0017] Furthermore, the thickness of the first frequency modulation layer is 20nm~80nm; and / or, the uniformity of the first frequency modulation layer is less than 5%.

[0018] Secondly, this application provides a device packaging method for fabricating the aforementioned device packaging structure, the device packaging method comprising: Prepare a substrate; A second electrical interconnect structure for bonding bumps to the substrate, and bonding devices to the bumps; The preparation of a substrate includes: Provide a substrate; After an electrode layer is formed on top of the substrate, a temperature compensation layer and a thickening layer are formed. A frequency modulation layer is deposited on top of the temperature compensation layer, wherein the distance from the top surface of the frequency modulation layer to the substrate is less than or equal to the distance from the top surface of the thickened layer to the substrate; The electrical interconnect layer is formed by alternately fabricating an insulating dielectric layer and a first electrical interconnect structure in a direction away from the substrate. The first electrical interconnect structure is electrically connected to the electrode layer through the thickened layer. The first electrical interconnect structure includes a first redistribution layer and a redistribution via. Any two adjacent first redistribution layers are electrically connected through the redistribution via. A second electrical interconnect structure is fabricated on top of the substrate to form the substrate.

[0019] Further, the alternating fabrication of an insulating dielectric layer and a first electrical interconnect structure in a direction away from the substrate to form the electrical interconnect layer includes: sputtering an insulating dielectric layer to the top of the frequency modulation layer and the thickened layer; forming a first electrical interconnect structure electrically connected to the thickened layer in the insulating dielectric layer based on photolithography and electroplating processes; sputtering an insulating dielectric layer in the first electrical interconnect structure to embed the first electrical interconnect structure in the insulating dielectric layer.

[0020] This application proposes a device packaging structure and a device packaging method. The device packaging structure includes a substrate, bumps disposed on the substrate, and a device electrically connected to the substrate through the bumps. The substrate includes: a substrate and an electrode layer, a thickening layer, a temperature compensation layer, a frequency modulation layer, and an electrical interconnect layer stacked on top of the substrate. The electrode layer includes a first electrode layer and a second electrode layer. The thickening layer is located on top of the first electrode layer, and the projection of the thickening layer onto the substrate is at least within the projection of the first electrode layer onto the substrate. The temperature compensation layer is located on top of the second electrode layer. The electrical interconnect layer is electrically connected to the electrode layer through the thickening layer, and the projection of any cross-section of the electrical interconnect layer onto the substrate in any direction away from the substrate overlaps at least with the projection of the first electrode layer onto the substrate. The bumps are electrically connected to the electrical interconnect layer and the device, respectively. The device packaging structure proposed in this application overcomes the limitations of existing cavity design by sequentially fabricating layers on a substrate, effectively optimizing the layout efficiency of the device packaging structure and significantly reducing the device size. Secondly, the low stress concentration between the stacked layers effectively reduces residual stress and asynchronous frequency offset, ensuring stable device performance. Thirdly, the solid surface supports the deposition of a high thermal conductivity film, significantly improving heat dissipation and thus increasing the power capacity of the device. Finally, the integrated circuit redistribution technology proposed in this application supports surface redistribution and integrated matching inductors within the device, further enabling miniaturization of the device packaging structure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of a device packaging structure proposed in this application; Figure 2 A step-by-step structural diagram (I) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 3 This is a step-by-step structural diagram (II) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 4 This is a step-by-step structural diagram (III) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 5 A step-by-step structural diagram (IV) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 6 A step-by-step structural diagram (V) of the device packaging structure prepared based on the device packaging method proposed in this application; Figure 7 A step-by-step structural diagram (VI) shows the device packaging structure prepared based on the device packaging method proposed in this application. Figure 8 A step-by-step structural diagram (VII) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 9 This is a step-by-step structural diagram (VIII) of a device packaging structure prepared based on a device packaging method proposed in this application. Figure 10 A step-by-step structural diagram (IX) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 11 A step-by-step structural diagram (X) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 12 XI. A step-by-step structural diagram of a device packaging structure prepared based on a device packaging method proposed in this application. Figure 13 A step-by-step structural diagram (XII) of a device packaging structure prepared based on a device packaging method proposed in this application; Figure 14 This is a step-by-step structural diagram (XIII) of a device packaging structure prepared based on a device packaging method proposed in this application. Figure 15 This is a diagram showing the correspondence between the second frequency modulation layer and the frequency in this application; The same or similar reference numerals in the accompanying drawings represent the same or similar parts.

[0023] 10. Substrate; 11. Electrode layer; 111. First electrode layer; 112. Second electrode layer; 12. Thickened layer; 13. Temperature compensation layer; 14. Frequency modulation layer; 141. First frequency modulation layer; 142. Second frequency modulation layer; 143. Third frequency modulation layer; 15. Electrical interconnect layer; 151. First electrical interconnect structure; 152. Second electrical interconnect structure; 16. Bump; 17. Photoresist. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] like Figure 1 The embodiment shown provides a device packaging structure, which includes: a substrate, bumps 16 disposed on the substrate, and a device electrically connected to the substrate through the bumps 16; The substrate includes: a substrate 10 and an electrode layer 11, a thickening layer 12, a temperature compensation layer 13, a frequency modulation layer 14, and an electrical interconnect layer 15 stacked on top of the substrate 10.

[0027] The electrode layer 11 includes a first electrode layer 111 and a second electrode layer 112; The thickened layer 12 is located on top of the first electrode layer 111, and the projection of the thickened layer 12 onto the substrate 10 is at least within the projection of the first electrode layer 111 onto the substrate 10. The temperature compensation layer 13 is located on top of the second electrode layer 112; The electrical interconnect layer 15 is electrically connected to the electrode layer 11 through the thickened layer 12, and the projection of any cross section of the electrical interconnect layer 15 onto the substrate 10 in any direction away from the substrate 10 overlaps at least with the projection of the first electrode layer 111 onto the substrate 10. The bump 16 is electrically connected to the electrical interconnect layer 15 and the device, respectively.

[0028] In one embodiment, the device packaging structure is applied to the wafer-level packaging of a temperature-compensated surface acoustic wave filter for the manufacture of a high-performance, small-size radio frequency filter.

[0029] In one embodiment, the substrate 10 may include a silicon substrate, a glass substrate, a silicon carbide substrate, or a gallium arsenide substrate, etc.; the electrode layer 11 may include an Al layer, a Cu layer, a Pt layer, or a Mo layer, etc., and the formation process may include a physical vapor deposition process, etc.

[0030] In one embodiment, the electrode layer 11 may be an interdigital transducer, which includes interdigital electrode leads (corresponding to the first electrode layer 111 of this application) and a plurality of interdigital electrodes (corresponding to the second electrode layer 112 of this application). The plurality of interdigital electrodes extend in a first direction and are arranged in a second direction, which are parallel to the top surface of the substrate 10 and intersect each other (e.g., are approximately perpendicular to each other). Figure 1 For example, the second direction is the left and right direction, and the first direction is the front and back direction.

[0031] In one embodiment, the second electrical interconnect structure 152 of this application is recessed on the top surface of the insulating dielectric layer (i.e., the bottom surface of the second electrical interconnect structure 152 is lower than the top surface of the insulating dielectric layer), and a portion of the bump 16 is disposed in the recess of the second electrical interconnect structure 152. On the one hand, this can effectively reduce the manufacturing difficulty of the bump 16 (because the recess has the properties of a mold), and on the other hand, it can improve the stability of the bump 16 and thus improve the reliability of the device packaging structure.

[0032] In one embodiment, the electrical interconnect layer 15 includes an electrical interconnect structure and an insulating dielectric layer; the electrical interconnect structure includes a first electrical interconnect structure 151 and a second electrical interconnect structure 152; the first electrical interconnect structure 151 is embedded in the insulating dielectric layer, and the second electrical interconnect structure 152 is disposed on the top of the insulating dielectric layer for electrically connecting the bump 16.

[0033] In practical applications, exposed conductor tips are prone to electric field concentration, which can lead to discharge or breakdown. By embedding the first electrical interconnect structure 151 within the insulating dielectric layer, the electric field distribution can be smoothed, effectively mitigating the problem of highly uneven electric field distribution and thus improving the external insulation strength, resulting in higher reliability for high-power devices. Furthermore, by embedding the first electrical interconnect structure 151 within the insulating dielectric layer, the composite structure formed by the first electrical interconnect structure 151 and the insulating dielectric layer provides mutual support, effectively preventing cavity collapse and providing space for rewiring on the device package surface, significantly improving the mechanical stability and integration of the device package structure.

[0034] Specifically, the insulating dielectric layer may be made of one or more of silicon dioxide and silicon nitride. Based on the aforementioned insulating dielectric material, patterns for setting electrical interconnect structures can be formed by photolithography and etching. Preferably, the insulating dielectric layer can be prepared by stacking silicon dioxide and silicon nitride, and the overall stress and dielectric properties can be adjusted by multilayer stacking and etching.

[0035] In one embodiment, the insulating dielectric layer has insulation and high thermal conductivity. The first electrical interconnect structure 151 is embedded in the insulating dielectric layer. The heat generated by the embedded first electrical interconnect structure 151 can be quickly conducted to the insulating dielectric layer and then conducted from the insulating dielectric layer to the outside of the device packaging structure, thereby achieving insulation heat dissipation and effectively improving the heat dissipation capability of the device packaging structure, especially the high-power device packaging structure.

[0036] In one embodiment, the material of the conductive interconnect structure may include one or more of copper, gold, aluminum, or silver; alternatively, the material of the conductive interconnect structure may also be a conductive paste such as silver paste or conductive ink, or a carbon-based material such as graphene.

[0037] In one embodiment, the frequency modulation layer 14 includes a first frequency modulation layer 141, a second frequency modulation layer 142, and a third frequency modulation layer 143 in the direction away from the substrate 10. The density of the second frequency modulation layer 142 is lower than that of the first frequency modulation layer 141 and the third frequency modulation layer 143. The main function of the first frequency modulation layer 141 is to adjust the operating frequency of the device package structure to achieve a preset design target.

[0038] Preferably, the density of the first frequency modulation layer 141 is equal to the density of the third frequency modulation layer 143. By designing the density relationship of the first frequency modulation layer 141, the second frequency modulation layer 142, and the third frequency modulation layer 143, the density of the frequency modulation layer 14 in the direction away from the substrate 10 presents a high-low-high stacking relationship. Furthermore, silicon dioxide layers and silicon nitride layers are alternately deposited to form the second frequency modulation layer 142 and the third frequency modulation layer 143 with reflective properties, so as to achieve the compensation of the first frequency modulation layer 141 by the second frequency modulation layer 142 and the third frequency modulation layer 143, while reducing the adverse effects of the electrical interconnect layer 15 on the frequency of the device packaging structure.

[0039] In one embodiment, the material of the first frequency modulation layer 141 includes silicon nitride or the like, and the thickness of the first frequency modulation layer 141 is less than 0.1 micrometers; the material of the second frequency modulation layer 142 includes silicon dioxide or the like, and the thickness of the second frequency modulation layer 142 ranges from 0.1 micrometers to 1.5 micrometers; the material of the third frequency modulation layer 143 includes silicon nitride or the like, and the thickness of the third frequency modulation layer 143 is equal to or greater than 1.5 micrometers.

[0040] Specifically, the thickness of the second frequency modulation layer 142 corresponds to the frequency as follows: Figure 15 As shown, those skilled in the art can make reasonable selections regarding the thickness of the second frequency modulation layer 142 based on relevant limitations such as the target frequency.

[0041] Furthermore, the projection of the temperature compensation layer 13 onto the substrate 10 is located within the projection of the frequency modulation layer 14 onto the substrate 10, and the projection of the frequency modulation layer 14 onto the substrate 10 overlaps with the projection of the first electrode layer 111 onto the substrate 10.

[0042] Specifically, the temperature compensation layer 13 increases in size along any cross-section (parallel to the plane defined by the first and second directions) in the direction away from the substrate 10, and the frequency modulation layer 14 increases in size along any cross-section (parallel to the plane defined by the first and second directions) in the direction away from the substrate 10; the cross-section of the frequency modulation layer 14 near the substrate 10 is equal to or greater than the cross-section of the temperature compensation layer 13 away from the substrate 10.

[0043] Furthermore, the first electrical interconnection structure 151 includes a first rewiring layer, and the second electrical interconnection structure 152 includes a second rewiring layer; when the thickness of the electrical interconnection layer 15 exceeds a preset value, the first rewiring layer includes multiple layers.

[0044] In one embodiment, the determination of the preset value includes: determining the preset value from multiple perspectives, such as the actual process and the optimal thickness of the redistribution layer; specifically, the larger the size of the first redistribution layer, the greater its negative impact on the heat dissipation performance of the device packaging structure; the larger the size of the first redistribution layer, the higher the cost; the first redistribution layer usually uses conductive materials to achieve conductivity, and the insulating dielectric layer used to embed the first redistribution layer usually uses insulating materials. Conductive materials and insulating materials have different coefficients of thermal expansion. When the size of the first redistribution layer is too large (especially when the thickness is too thick), the difference in the degree of expansion or contraction of the two materials will be greater when the device heats up during operation or undergoes temperature cycling, thereby generating huge thermal stress at the interface between the two, which will lead to serious mechanical stress and reliability problems in the device packaging structure.

[0045] It should be understood that this application does not limit the specific size of the preset value, and those skilled in the art can make a reasonable selection based on the actual application scenario.

[0046] Furthermore, when the first redistribution layer is multilayered, the first electrical interconnect structure 151 further includes redistribution vias; when the first electrical interconnect structure 151 includes redistribution vias, the projection of the target redistribution layer on the substrate 10 completely covers the projection of the target redistribution via on the substrate 10, and the projection area of ​​the target redistribution layer on the substrate 10 is equal to or greater than the projection area of ​​the target redistribution via on the substrate 10, and the target redistribution via and the target redistribution layer include adjacent redistribution vias and redistribution layers along the direction away from the substrate 10.

[0047] In one embodiment, the redistribution layer and its adjacent redistribution vias form a "T" shape, and the insulating dielectric layer can provide efficient support for the redistribution layer and its adjacent redistribution vias, thereby effectively improving the reliability of the device packaging structure.

[0048] By completely covering the projection of the target redistribution layer on the substrate 10 with the projection of the target redistribution via on the substrate 10, the electrical conductivity and electrical capacity are effectively improved.

[0049] In one embodiment, the projection of the bump 16 on the substrate 10 does not overlap with the projection of the thickened layer 12 on the substrate 10, and the projection area of ​​the target redistribution layer on the substrate 10 is equal to or greater than the projection area of ​​the target redistribution via on the substrate 10. By designing the target redistribution layer as described above and changing the original vertical electrical conduction method to a method that can conduct electricity in the horizontal direction, the utilization rate of the substrate is further improved.

[0050] Furthermore, the projection portions of the first redistribution layers of any two adjacent layers on the substrate 10 overlap; and / or, the overlapping projections of the first redistribution layers of any two adjacent layers on the substrate 10 overlap with the projections of the redistribution vias on the substrate 10.

[0051] Furthermore, the size of the top surface of the thickened layer 12 is smaller than the size of the bottom surface of the thickened layer 12 in a direction parallel to the top surface of the substrate 10, and the size of the thickened layer 12 in the first direction varies linearly from the direction away from the substrate 10; and / or, the distance between the top surface of the frequency modulation layer 14 and the substrate 10 is less than or equal to the distance between the top surface of the thickened layer 12 and the substrate 10.

[0052] Specifically, the size of the top surface of the thickened layer 12 is set to be smaller than the size of the bottom surface of the thickened layer 12 along a direction parallel to the top surface of the substrate 10, and the size of the thickened layer 12 in the first direction is set to change linearly from the direction away from the substrate 10, thus constructing an inverted trapezoidal structure on the substrate 10 with the thickened layer 12. This structure has a geometric feature where the bottom size is larger than the top size. This top-large and bottom-small sidewall morphology can effectively avoid step shading or shadowing effects in vertical deposition processes (such as the fabrication of the temperature compensation layer 13 and the frequency modulation layer 14), thereby ensuring the uniformity of film coverage and thickness consistency on the sidewalls and bottom, significantly improving fabrication accuracy and device yield.

[0053] In one embodiment, the temperature compensation layer 13 is made of silicon dioxide; the second frequency modulation layer 142 and the third frequency modulation layer 143 both comprise alternating layers of silicon dioxide and silicon nitride.

[0054] In one embodiment, the thickness of the first frequency modulation layer 141 is 20 nm to 80 nm; and / or, the uniformity of the first frequency modulation layer 141 is less than 5%.

[0055] In one embodiment, the device packaging structure further includes a heat dissipation film layer covering the outer wall of the device and / or the substrate. On the one hand, this can improve the airtightness of the device and prevent moisture from seeping into the interior of the device packaging structure. On the other hand, it can enhance the thermal conductivity of the device packaging structure and thus improve the power of the device packaging structure.

[0056] In one embodiment, the material of bump 16 includes one or more conductive materials selected from gold, copper, or tin.

[0057] Another aspect of this application provides a device packaging method for fabricating the aforementioned device packaging structure, the device packaging method comprising at least the following steps: Step S1: Prepare a substrate; Step S2: Bond the bump 16 to the second electrical interconnect structure 152 of the substrate, and bond the device to the bump 16; Among them, such as Figures 2-14 This diagram illustrates the steps involved in fabricating a device packaging structure based on the device packaging method proposed in this embodiment. The fabrication of a substrate includes: Step S101: Provide a substrate 10; Step S102: After forming the electrode layer 11 on the top of the substrate 10, a temperature compensation layer 13 and a thickening layer 12 are formed; Step S103: Deposit frequency modulation layer 14 to the top of temperature compensation layer 13, wherein the distance from the top surface of frequency modulation layer 14 to substrate 10 is less than or equal to the distance from the top surface of thickened layer 12 to substrate 10; Step S104: An insulating dielectric layer and a first electrical interconnect structure 151 are alternately prepared from the direction away from the substrate 10 to form the electrical interconnect layer 15. The first electrical interconnect structure 151 is electrically connected to the electrode layer 11 through the thickened layer 12. The first electrical interconnect structure 151 includes a first redistribution layer and a redistribution via. Any two adjacent first redistribution layers are electrically connected through the redistribution via. Step S105: Prepare a second electrical interconnect structure 152 to form the substrate on top of the substrate.

[0058] The device packaging method proposed in this application revolutionizes the fabrication process of wafer-level device packaging structures, reduces process errors and residual stress, reduces asynchronous frequency offset of device packaging structures, and improves device reliability. Furthermore, the device packaging method proposed in this application effectively enhances the thermal conductivity of device packaging structures while reducing the size of device packaging structures, achieving a balance between high performance and miniaturization, and realizing a performance leap in device packaging structures.

[0059] Further, the alternating fabrication of an insulating dielectric layer and a first electrical interconnect structure 151 in a direction away from the substrate 10 to form the electrical interconnect layer 15 includes: sputtering an insulating dielectric layer onto the top of the frequency modulation layer 14 and the thickened layer 12; forming a first electrical interconnect structure 151 electrically connected to the thickened layer 12 on the insulating dielectric layer based on photolithography and electroplating processes; sputtering an insulating dielectric layer onto the first electrical interconnect structure 151 to embed the first electrical interconnect structure 151 in the insulating dielectric layer.

[0060] In one embodiment, forming a first electrical interconnect structure 151 electrically connected to the thickened layer 12 on the insulating dielectric layer based on photolithography and electroplating processes includes: sputtering an insulating dielectric layer on top of the thickened layer 12 and the frequency modulation layer 14; coating a photoresist 17 on top of the insulating dielectric layer; performing a photolithography process based on the photoresist 17 to expose the insulating dielectric layer at the location where the electrical interconnect structure is to be fabricated, and etching the exposed insulating dielectric layer to form the target structure; removing the remaining photoresist 17 and electroplating a conductive material (such as copper) at least partially within the target structure to form the first electrical interconnect structure 151.

[0061] In one embodiment, the method further includes: removing the remaining photoresist 17, electroplating a conductive material on the top surface of the target structure and the insulating dielectric layer, and then removing the conductive material at the non-target structure to form at least a portion of the first electrical interconnect structure 151.

[0062] The above provides a detailed description of a device packaging structure and a device packaging method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0063] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0064] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device packaging structure, characterized in that, The device packaging structure includes: a substrate, bumps disposed on the substrate, and a device electrically connected to the substrate through the bumps; The substrate includes: a substrate and an electrode layer, a thickening layer, a temperature compensation layer, a frequency modulation layer, and an electrical interconnect layer stacked on top of the substrate; The electrode layer includes a first electrode layer and a second electrode layer; The thickened layer is located on top of the first electrode layer, and the projection of the thickened layer onto the substrate is at least within the projection of the first electrode layer onto the substrate; The temperature compensation layer is located on top of the second electrode layer; The electrical interconnect layer is electrically connected to the electrode layer through the thickened layer, and the projection of any cross section of the electrical interconnect layer onto the substrate in any direction away from the substrate overlaps at least with the projection of the first electrode layer onto the substrate. The bumps are electrically connected to the electrical interconnect layer and the device, respectively.

2. The device packaging structure according to claim 1, characterized in that, The electrical interconnection layer includes an electrical interconnection structure and an insulating dielectric layer; The electrical interconnection structure includes a first electrical interconnection structure and a second electrical interconnection structure; The first electrical interconnection structure is embedded in the insulating dielectric layer, and the second electrical interconnection structure is disposed on the top of the insulating dielectric layer for electrically connecting the bump.

3. The device packaging structure according to claim 1, characterized in that, The frequency modulation layer includes a first frequency modulation layer, a second frequency modulation layer, and a third frequency modulation layer from the direction away from the substrate. The density of the second frequency modulation layer is lower than the density of the first frequency modulation layer and the density of the third frequency modulation layer.

4. The device packaging structure according to claim 3, characterized in that, The first frequency modulation layer is made of silicon nitride; the second frequency modulation layer is made of silicon dioxide; and the third frequency modulation layer is made of silicon nitride.

5. The device packaging structure according to claim 3 or 4, characterized in that, The thickness of the first frequency modulation layer is less than 0.1 micrometers; the thickness of the second frequency modulation layer ranges from 0.1 micrometers to 1.5 micrometers; and the thickness of the third frequency modulation layer is equal to or greater than 1.5 micrometers.

6. The device packaging structure according to claim 2, characterized in that, The projection of the temperature compensation layer onto the substrate is located within the projection of the frequency modulation layer onto the substrate, and the projection of the frequency modulation layer onto the substrate partially overlaps with the projection of the first electrode layer onto the substrate.

7. The device packaging structure according to claim 2, characterized in that, The first electrical interconnect structure includes a first wiring layer, and the second electrical interconnect structure includes a second wiring layer; When the thickness of the electrical interconnect layer exceeds a preset value, the first rewiring layer comprises multiple layers.

8. The device packaging structure according to claim 7, characterized in that, When the first redistribution layer is multi-layered, the first electrical interconnection structure further includes redistribution vias; When the first electrical interconnect structure includes a redistribution via, the projection of the target redistribution layer on the substrate completely covers the projection of the target redistribution via on the substrate, and the projection area of ​​the target redistribution layer on the substrate is equal to or greater than the projection area of ​​the target redistribution via on the substrate. The target redistribution via and the target redistribution layer include adjacent redistribution vias and redistribution layers along the direction away from the substrate.

9. The device packaging structure according to claim 8, characterized in that, The first redistribution layers of any two adjacent layers overlap in the projection portion of the substrate; And / or, The overlapping projection of the first redistribution layer of any two adjacent layers on the substrate overlaps with the projection of the redistribution via on the substrate.

10. The device packaging structure according to claim 1 or 3, characterized in that, The size of the top surface of the thickened layer is smaller than the size of the bottom surface of the thickened layer in a direction parallel to the top surface of the substrate, and the size of the thickened layer in the first direction varies linearly from the direction away from the substrate; And / or, the distance between the top surface of the frequency modulation layer and the substrate is less than or equal to the distance between the top surface of the thickened layer and the substrate.

11. The device packaging structure according to claim 3, characterized in that, The material of the temperature compensation layer includes silicon dioxide; Both the second and third frequency modulation layers comprise alternating layers of silicon dioxide and silicon nitride.

12. The device packaging structure according to claim 3 or 11, characterized in that, The thickness of the first frequency modulation layer is 20nm~80nm; And / or, the uniformity of the first frequency modulation layer is less than 5%.

13. A device packaging method, characterized in that, The device packaging method is used to prepare the device packaging structure according to any one of claims 1 to 12, wherein the device packaging method comprises: Prepare a substrate; A second electrical interconnect structure for bonding bumps to the substrate, and bonding devices to the bumps; The preparation of a substrate includes: Provide a substrate; After an electrode layer is formed on top of the substrate, a temperature compensation layer and a thickening layer are formed. A frequency modulation layer is deposited on top of the temperature compensation layer, wherein the distance from the top surface of the frequency modulation layer to the substrate is less than or equal to the distance from the top surface of the thickened layer to the substrate; The electrical interconnect layer is formed by alternately fabricating an insulating dielectric layer and a first electrical interconnect structure in a direction away from the substrate. The first electrical interconnect structure is electrically connected to the electrode layer through the thickened layer. The first electrical interconnect structure includes a first redistribution layer and a redistribution via. Any two adjacent first redistribution layers are electrically connected through the redistribution via. A second electrical interconnect structure is fabricated on top of the substrate to form the substrate.

14. The device packaging method according to claim 13, characterized in that, The electrical interconnect layer is formed by alternately fabricating an insulating dielectric layer and a first electrical interconnect structure in a direction away from the substrate, including: Sputtering an insulating dielectric layer onto the top of the frequency modulation layer and the thickened layer; A first electrical interconnect structure electrically connected to the thickened layer is formed on the insulating dielectric layer based on photolithography and electroplating processes; Sputtering an insulating dielectric layer onto the first electrical interconnect structure to embed the first electrical interconnect structure into the insulating dielectric layer.

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