A three-node flip-to-recovery radiation-resistant latch

Abstract

This application relates to a three-node flip-over self-recovering radiation-resistant latch, which includes a clock input terminal, a data input terminal, a clock control transmission module, a main feedback recovery loop, and a control node recovery loop. In transparent mode, the clock control transmission module writes the input signal D and its inverted signal DB into multiple internal redundant nodes; in hold mode, it cuts off the input path. When any one, two, or three sensitive nodes experience a transient flip, the unaffected nodes utilize the characteristic of maintaining the output state when the C unit input is inconsistent to block error propagation, and recover the affected nodes step by step through the interlocked feedback path, thereby achieving self-recovery for single-node flips, dual-node flips, and three-node flips. This structure achieves complete three-node flip tolerance while reducing dynamic power consumption and propagation delay, making it suitable for aerospace, nuclear energy, high-energy physics experiments, low-power processors, and other high-reliability integrated circuit systems.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology and relates to a three-node flip-over self-recovering radiation-resistant latch. Background Technology

[0002] As semiconductor manufacturing processes continue to evolve towards deep submicron and nanoscale, the feature size of integrated circuits is constantly shrinking, and node capacitance and operating voltage are gradually decreasing, significantly reducing the critical charge that circuit nodes can withstand. When integrated circuits in aerospace, nuclear energy industry, high-energy physics experiments, and high-reliability embedded systems are bombarded by high-energy particles such as neutrons, protons, alpha particles, heavy ions, electrons, and muons, electron-hole pairs are generated in sensitive areas, forming transient current pulses that may cause abnormal flips in the logic state of circuit nodes. These non-permanent faults typically manifest as single-event transients, single-node flips, and multi-node flips.

[0003] Under advanced process technology, due to reduced device spacing, enhanced charge sharing effects, and shorter physical distances between multiple sensitive nodes on the layout, the incidence of a single particle no longer causes only a single node to flip, but may simultaneously affect two or even three nodes. Two-node and three-node flips can disrupt the stored state of traditional latches, resulting in erroneous values ​​at the output. For spacecraft control units, satellite payload processors, nuclear radiation monitoring systems, and high-reliability on-chip systems, such soft errors pose serious system reliability risks.

[0004] Existing radiation-hardened latches are typically hardened using C-cells, DICE cells, Schmitt triggers, redundant feedback loops, or triple-modulus redundancy. Single-node flip-flop tolerant latches primarily address transient disturbances in a single sensitive node, while dual-node flip-flop tolerant or self-recovering latches further improve reliability. However, when all three nodes are simultaneously disturbed, existing structures often require the introduction of numerous redundant nodes and complex voting logic, or the adoption of triple-modulus redundancy, resulting in a significant increase in area, power consumption, and latency overhead.

[0005] Therefore, there is an urgent need for a latch structure that can achieve three-node flip-and-recovery with low hardware overhead, so that it can maintain low power consumption and high speed while having complete self-recovery capability for single-node flip-and-recovery, two-node flip-and-recovery, and three-node flip-and-recovery. Summary of the Invention

[0006] To address the problems of high power consumption, large latency, high area overhead, and complex recovery path in existing radiation-hardened latches when achieving three-node flip-over tolerance, this invention proposes a three-node flip-over self-recovering radiation-hardened latch.

[0007] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a three-node flip-over self-recovering radiation-resistant latch is provided, comprising: The clock input terminal is used to receive the clock signal CLK and provide the clock signal CLK to the clock control transmission module and the clock gate C unit.

[0008] The data input terminal is used to receive the input signal D and generate an inverted signal DB through an inverter.

[0009] The clock-controlled transmission module is used to transmit the input signal to the output node Q and internal nodes N1, N3 and N5 through the transmission gate under the control of the clock signal CLK, and to transmit the inverted signal DB to the internal nodes N6 and N7.

[0010] The main feedback recovery loop includes two three-input C units CE1 and CE3, and two clock-gated three-input C units CE2 and CE4. CE1, CE2, CE3, and CE4 form a loop. The first input terminals of CE1 and CE3 are connected to the inverting control node a, and the first input terminals of CE2 and CE4 are connected to the inverting control node b. The third input terminals of CE1, CE2, CE3, and CE4 are connected to the internal nodes N5, N6, N3, and N7, respectively.

[0011] The control node recovery loop is used to form an interlocked recovery network by connecting internal nodes N1 to N7, output node Q, and control nodes A and B through two four-input C units and two inverters.

[0012] In one embodiment, the clock-controlled transmission module includes six transmission gates TG1 to TG6.

[0013] The input terminals of TG1 to TG4 all receive the input signal D. The output terminals of TG1 to TG4 are connected to internal nodes N1, N3 and N5 respectively, and output Q. The clock input terminals of TG1 to TG6 all receive the clock signal CLK. The inverting clock input terminals of TG1 to TG6 all receive the inverting clock signal NCK.

[0014] The inputs of TG5 and TG6 both receive the inverted signal DB, and the outputs of TG5 and TG6 are connected to internal nodes N6 and N7, respectively.

[0015] In one embodiment, each transmission gate includes an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor and the source of the PMOS transistor are connected together, and the resulting connection point is used as the input terminal of the transmission gate. The drain of the NMOS transistor and the source of the PMOS transistor are connected together, and the resulting connection point is used as the output terminal of the transmission gate. The gate of the NMOS transistor is used as the clock input terminal, and the gate of the PMOS transistor is used as the inverting clock input terminal.

[0016] In one embodiment, the control node recovery loop includes two four-input C units CE5 and CE6, and two inverters INV1 and INV2.

[0017] The four input terminals of CE5 are connected to internal nodes N1, N3, N5 and output node Q respectively. The output terminal of CE5 and the input terminal of INV1 are both connected to control node A. The output terminal of INV1 is connected to inverting control node a. The four input terminals of CE6 are connected to internal nodes N2, N4, N6 and N7 respectively. The output terminal of CE6 and the input terminal of INV2 are both connected to control node B. The output terminal of INV2 is connected to inverting control node b.

[0018] In one embodiment, in the main feedback recovery loop, the output of CE1 and the second input of CE2 are both connected to internal node N2; the output of CE2 and the second input of CE3 are both connected to output node Q; the output of CE3 and the second input of CE4 are both connected to internal node N4; the output of CE4 and the second input of CE1 are both connected to internal node N1; the first inputs of CE1 and CE3 are both connected to inverting control node a; the first inputs of CE2 and CE4 are both connected to inverting control node b; the third inputs of CE1, CE2, CE3, and CE4 are respectively connected to internal nodes N5, N6, N3, and N7; and the clock control terminals of CE2 and CE4 are connected to the clock signal CLK.

[0019] In one embodiment, when CLK=1, the latch is in transparent operating mode. In transparent operating mode, TG1 to TG6 are all turned on. The input signal D is written to internal nodes N1, N3, N5 and output node Q via TG1, TG2, TG3 and TG4 respectively, and the input inverted signal DB is written to internal nodes N6 and N7 via TG5 and TG6 respectively.

[0020] Internal nodes N1, N3, and N5, along with output node Q, work together on the four-input C unit CE5 to enable control node A to establish a stable logic state corresponding to the current input data.

[0021] Nodes N2, N4, N6, and N7 work together on the four-input C unit CE6, enabling control node B to establish a stable logic state corresponding to the current input data.

[0022] Control nodes A and B are then converted into nodes a and b via inverters INV1 and INV2, respectively, to provide initial conditions for feedback recovery in hold mode.

[0023] In one embodiment, when CLK=0, the latch is in hold mode. In hold mode: TG1 to TG6 are all off, input signal D and inverted input signal DB are isolated from the internal storage node, and changes in external input will not directly affect the state of the internal node. CE2 and CE4 are enabled by the clock signal, and CE1, CE2, CE3, CE4, CE5 and CE6 together form an interlock feedback network; the interlock feedback network is used to maintain the original latched data, and also to block error propagation when a sensitive node is bombarded by particles and causes a transient flip, and to restore the flipped node to the correct logic value.

[0024] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned three-node flip-over self-recovering radiation-resistant latch includes a clock input, a data input, a clock control transmission module, a main feedback recovery loop, and a control node recovery loop. In transparent mode, the clock control transmission module writes the input signal D and its inverted signal DB into multiple internal redundant nodes; in hold mode, it cuts off the input path. When any one, two, or three sensitive nodes experience a transient flip, the unaffected nodes utilize the characteristic of maintaining the output state when the C unit input is inconsistent to block error propagation and gradually recover the affected nodes through the interlocked feedback path, thereby achieving self-recovery for single-node flips, dual-node flips, and three-node flips. This structure achieves complete three-node flip tolerance while reducing dynamic power consumption and propagation delay, making it suitable for aerospace, nuclear energy, high-energy physics experiments, low-power processors, and other high-reliability integrated circuit systems. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the principle of a three-node flip-up self-recovering radiation-resistant latch in one embodiment; Figure 2 This is a schematic diagram of the clock-gated three-input C unit CE2 in one embodiment; Figure 3 This is a schematic diagram of the principle of the four-input C unit CE5 in one embodiment; Figure 4 This is a schematic diagram of the state of each node after single-node injection in a simulation experiment of one embodiment; Figure 5 This is a schematic diagram of the state of each node after dual-node injection in a simulation experiment of one embodiment; Figure 6 This is a schematic diagram of the state of each node after three-node injection in a simulation experiment of one embodiment; Figure 7 This is a schematic diagram illustrating the simulation results of delay variation under different process angles, power supply voltages, and temperatures in one embodiment. Figure 8 This is a schematic diagram illustrating the simulation results of power consumption changes under different process angles, power supply voltages, and temperatures in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0029] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0030] The C-cell used in this application refers to a logic cell with state retention capability. Specifically, when the logic states of its input terminals are consistent, the C-cell outputs the corresponding inverted logic value; when the logic states of its input terminals are inconsistent, the C-cell maintains its original output state, thereby preventing erroneous logic from propagating to subsequent stages. A clock-gated C-cell refers to a C-cell controlled by a clock signal. In the enabled state, it executes the C-cell logic function; in the disabled state, it maintains its original state or is isolated from preceding and following stages to reduce invalid flips and dynamic power consumption.

[0031] In this application, a single-node flip is denoted as SNU, a two-node flip as DNU, and a three-node flip as TNU. The term "self-recovery" means that when one or more sensitive nodes inside the latch are bombarded by particles and cause a transient flip, the latch can restore the disturbed node to its original correct logic value by relying on its internal interlocking feedback network without external refresh or additional error correction coding circuitry.

[0032] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] In one embodiment, such as Figure 1 As shown, a three-node flip-flop self-recovering radiation-resistant latch is provided, comprising: The clock input terminal is used to receive the clock signal CLK and provide the clock signal CLK to the clock control transmission module and the clock gate C unit.

[0034] The data input terminal is used to receive the input signal D and generate an inverted signal DB through an inverter.

[0035] The clock-controlled transmission module is used to transmit the input signal to the output node Q and internal nodes N1, N3 and N5 through the transmission gate under the control of the clock signal CLK, and to transmit the inverted signal DB to the internal nodes N6 and N7.

[0036] Specifically, the clock-controlled transmission module is used to transmit the input signal D to the first internal node N1, the third internal node N3, the fifth internal node N5, and the output node Q in transparent operating mode, and to transmit the inverted signal DB to the sixth internal node N6 and the seventh internal node N7. The main feedback recovery loop includes the first three-input C unit CE1 and the second three-input C unit CE3, the first clock-gated three-input C unit CE2 and the second clock-gated three-input C unit CE4; the first three-input C unit CE1, the first clock-gated three-input C unit CE2, the second three-input C unit CE3 and the second clock-gated three-input C unit CE4 form a loop. The first input terminals of the first three-input C unit CE1 and the second three-input C unit CE3 are both connected to the inverting control node a, the first input terminals of the first clock-gated three-input C unit CE2 and the second clock-gated three-input C unit CE4 are both connected to the inverting control node b, and the third input terminals of the first three-input C unit CE1, the first clock-gated three-input C unit CE2, the second three-input C unit CE3 and the second clock-gated three-input C unit CE4 are respectively connected to internal nodes N5, N6, N3 and N7.

[0037] Specifically, the first three-input C unit CE1, the second three-input C unit CE3, the first clock-gated three-input C unit CE2, and the second clock-gated three-input C unit CE4 constitute a cross-coupled main feedback recovery loop; the first three-input C unit CE1 is used to recover internal node N2, the second three-input C unit CE3 is used to recover internal node N4, the first clock-gated C unit CE2 is used to recover output node Q, and the second clock-gated C unit CE4 is used to recover internal node N1.

[0038] The C unit is an inverting C unit; when all its inputs are at the first logic level, the output is at the second logic level; when all its inputs are at the second logic level, the output is at the first logic level; when the logic levels of its inputs are inconsistent, the output remains in the state before the flip.

[0039] The schematic diagram of the clock-gated three-input C unit CE2 is as follows: Figure 2 As shown. In Figure 2 In the circuit shown, from top to bottom, the gate of the fifth PMOS transistor MP5 is connected to b, the source is connected to Vdd, and the drain is connected to the source of the sixth PMOS transistor MP6; the gate of the sixth PMOS transistor MP6 is connected to N2, the source is connected to the drain of the fifth PMOS transistor MP5, and the drain is connected to the source of the seventh PMOS transistor MP7; the gate of the seventh PMOS transistor MP7 is connected to N6, the source is connected to the drain of the sixth PMOS transistor, and the drain is connected to the source of the eighth PMOS transistor MP8; the gate of the eighth PMOS transistor MP8 is connected to CLK, the source is connected to the drain of the seventh PMOS transistor MP7, and the drain is connected to the drain of the fifth NMOS transistor MN5. From top to bottom, the gate of the fifth NMOS transistor MN5 is connected to NCK, the source is connected to the drain of the sixth NMOS transistor MN6, and the drain is connected to the drain of the eighth PMOS transistor MN8; the gate of the sixth NMOS transistor MN6 is connected to N6, the source is connected to the drain of the seventh NMOS transistor MN7, and the drain is connected to the source of the fifth NMOS transistor MN5; the gate of the seventh NMOS transistor MN7 is connected to N2, the source is connected to the drain of the eighth NMOS transistor MN8, and the drain is connected to the source of the sixth NMOS transistor MN6; the gate of the eighth NMOS transistor MN8 is connected to b, the source is connected to GND, and the drain is connected to the source of the eighth PMOS transistor MN8.

[0040] The control node recovery loop is used to form an interlocked recovery network by connecting internal nodes N1 to N7, output node Q, and control nodes A and B through two four-input C units and two inverters.

[0041] Specifically, by utilizing the characteristic of maintaining the output state when the input of the C unit is inconsistent, transient flips are logically isolated to prevent errors from spreading in the feedback loop; a multi-path interlock recovery network is formed by four-input C units and three-input C units to recover single-node, dual-node, and three-node flips without the need for external error correction coding or refresh control; and clock-gated C units reduce invalid flips and dynamic power consumption during the hold phase.

[0042] The sensitive nodes include internal nodes N1, N2, N4, control node A, control node B, and output node Q. When any one, any two, or any three of the sensitive nodes undergo a transient flip, output node Q maintains its original logical state or recovers to its original logical state within a short period of time.

[0043] The latch is implemented using CMOS technology and is suitable for space electronic systems, aerospace electronic systems, nuclear radiation environment electronic systems, high-energy physics experimental electronic systems, low-power processors, memory peripheral timing units, and data retention units in high-reliability on-chip systems.

[0044] The aforementioned three-node flip-over self-recovering radiation-resistant latch includes a clock input, a data input, a clock control transmission module, a main feedback recovery loop, and a control node recovery loop. In transparent mode, the clock control transmission module writes the input signal D and its inverted signal DB into multiple internal redundant nodes; in hold mode, it cuts off the input path. When any one, two, or three sensitive nodes experience a transient flip, the unaffected nodes utilize the characteristic of maintaining the output state when the C unit input is inconsistent to block error propagation and gradually recover the affected nodes through the interlocked feedback path, thereby achieving self-recovery for single-node flips, dual-node flips, and three-node flips. This structure achieves complete three-node flip tolerance while reducing dynamic power consumption and propagation delay, making it suitable for aerospace, nuclear energy, high-energy physics experiments, low-power processors, and other high-reliability integrated circuit systems.

[0045] In one embodiment, the clock control transmission module includes six transmission gates, specifically: the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, the fifth transmission gate TG5, and the sixth transmission gate TG6; The input terminals of TG1 to TG4 all receive the input signal D. The output terminals of TG1 to TG4 are connected to internal nodes N1, N3 and N5 respectively, and output Q. The clock input terminals of TG1 to TG6 all receive the clock signal CLK. The inverting clock input terminals of TG1 to TG6 all receive the inverting clock signal NCK.

[0046] The inputs of TG5 and TG6 both receive the inverted signal DB, and the outputs of TG5 and TG6 are connected to internal nodes N6 and N7, respectively.

[0047] In one embodiment, each transmission gate includes an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor and the source of the PMOS transistor are connected together, and the resulting connection point is used as the input terminal of the transmission gate. The drain of the NMOS transistor and the source of the PMOS transistor are connected together, and the resulting connection point is used as the output terminal of the transmission gate. The gate of the NMOS transistor is used as the clock input terminal, and the gate of the PMOS transistor is used as the inverting clock input terminal.

[0048] In one embodiment, the control node recovery loop includes a first four-input C unit CE5 and a second four-input C unit CE6, a first inverter INV1 and a second inverter INV2.

[0049] The four inputs of the first four-input C unit CE5 are connected to internal nodes N1, N3, N5, and output node Q, respectively. The output of the first four-input C unit CE5 and the input of the first inverter INV1 are both connected to control node A. The output of the first inverter INV1 is connected to inverting control node a. The four inputs of the second four-input C unit CE6 are connected to internal nodes N2, N4, N6, and N7, respectively. The output of the second four-input C unit CE6 and the input of the second inverter INV2 are both connected to control node B. The output of the second inverter INV2 is connected to inverting control node b.

[0050] Specifically, the first four-input C unit CE5 and the second four-input C unit CE6 constitute a control node recovery loop; when control node A or control node B experiences a transient flip, the control node recovery loop restores control node A or control node B according to the state of the undisturbed internal nodes.

[0051] The schematic diagram of the four-input C unit CE5 is as follows: Figure 3 As shown. In Figure 3In the circuit shown, from top to bottom, the gate of the first PMOS transistor MP1 is connected to N1, its source is connected to Vdd, and its drain is connected to the source of the second PMOS transistor MP2; the gate of the second PMOS transistor MP2 is connected to N3, its source is connected to the drain of the first PMOS transistor MP1, and its drain is connected to the source of the third PMOS transistor MP3; the gate of the third PMOS transistor MP3 is connected to N5, its source is connected to the drain of the second PMOS transistor MP2, and its drain is connected to the source of the fourth PMOS transistor MP4; the gate of the fourth PMOS transistor MP4 is connected to Q, its source is connected to the drain of the third PMOS transistor MP3, and its drain is connected to the first NMOS transistor MN1. The drain of the first NMOS transistor MN1 is connected to Q from top to bottom. Its source is connected to the drain of the second NMOS transistor MN2, and its drain is connected to the drain of the fourth PMOS transistor MP4. The gate of the second NMOS transistor MN2 is connected to N5, and its source is connected to the drain of the third NMOS transistor MN3, and its drain is connected to the source of the first NMOS transistor MN1. The gate of the third NMOS transistor MN3 is connected to N3, and its source is connected to the drain of the fourth NMOS transistor MN4, and its drain is connected to the source of the second NMOS transistor MN2. The gate of the fourth NMOS transistor MN4 is connected to N1, its source is connected to GND, and its drain is connected to the source of the fourth PMOS transistor MN4.

[0052] When the clock signal CLK is at the hold level, the clock control transmission module is turned off, and the main feedback recovery loop and the control node recovery loop together form an interlocked feedback network. When any three sensitive nodes in the interlocked feedback network experience a transient flip, the non-flipped node blocks error propagation through the state retention characteristic of the C unit and recovers the transiently flipped node through the interlocked feedback path.

[0053] The first clock-gated C unit CE2 and the second clock-gated C unit CE4 are turned off or kept unupdated in transparent operating mode to reduce invalid flips of internal nodes; they are enabled in hold operating mode to participate in data hold and error recovery of the interlocked feedback network.

[0054] In the main feedback recovery loop, the output of CE1 and the second input of CE2 are both connected to internal node N2; the output of CE2 and the second input of CE3 are both connected to output node Q; the output of CE3 and the second input of CE4 are both connected to internal node N4; the output of CE4 and the second input of CE1 are both connected to internal node N1; the first inputs of CE1 and CE3 are both connected to inverting control node a; the first inputs of CE2 and CE4 are both connected to inverting control node b; the third inputs of CE1, CE2, CE3, and CE4 are connected to internal nodes N5, N6, N3, and N7, respectively; and the clock control terminals of CE2 and CE4 are connected to the clock signal CLK.

[0055] In one embodiment, when CLK=1, the latch is in a transparent operating mode.

[0056] In transparent operating mode, TG1 to TG6 are all turned on. The input signal D is written to internal nodes N1, N3, N5 and output node Q via TG1, TG2, TG3 and TG4 respectively. The input inverted signal DB is written to internal nodes N6 and N7 via TG5 and TG6 respectively.

[0057] Internal nodes N1, N3, and N5, along with output node Q, work together on the four-input C unit CE5 to enable control node A to establish a stable logic state corresponding to the current input data.

[0058] Nodes N2, N4, N6, and N7 work together on the four-input C unit CE6, enabling control node B to establish a stable logic state corresponding to the current input data.

[0059] Control nodes A and B are then converted into nodes a and b via inverters INV1 and INV2, respectively, to provide initial conditions for feedback recovery in hold mode.

[0060] Specifically, when CLK=1, the circuit is in transparent mode. That is, the latches in the circuit change their input values ​​via the input signal D. The clock-gated transmission gates TG1 to TG6 are open. Nodes N1, N3, N5, and Q are directly driven by input D, while nodes N6 and N7 are directly driven by input DB. Simultaneously, node A is driven by the four nodes N1, N3, N5, and Q. Node N2 is driven by the combined action of the three inputs N1, N5, and a of CE1. Similarly, node N4 is driven by the combined action of the three inputs N3, Q, and a of CE3. Nodes A and B are driven by the input nodes of CE5 and CE6. Ultimately, each node writes data to the latches in this way.

[0061] In one embodiment, when CLK=0, the latch is in hold mode.

[0062] In hold mode: TG1 to TG6 are all off, and input signal D and inverted input signal DB are isolated from the internal storage nodes. Changes in external input will not directly affect the state of the internal nodes. CE2 and CE4 are enabled by the clock signal. CE1, CE2, CE3, CE4, CE5, and CE6 together form an interlocked feedback network. The interlocked feedback network is used to maintain the original latched data and also to block error propagation when a sensitive node is bombarded by particles and undergoes a transient flip, and to restore the flipped node to the correct logic value.

[0063] Specifically, when CLK=0, the circuit is in a hold state. That is, all transmission gates are off, and nodes N1, N3, N5, N6, N7, and Q are unaffected by the input signal. However, CE2 and CE4 are activated by the clock signal, causing the four three-input C elements from CE1 to CE4 to interact and form a feedback phase-locked loop, thus maintaining the circuit's robustness. When the circuit is in the hold state, there are a total of six sensitive nodes: N1, N2, N4, A, B, and Q. Next, we will consider the circuit's tolerance capabilities for SNU, DNU, and TNU under different conditions. These units together constitute a ring-shaped interlocked recovery structure.

[0064] In one embodiment, such as Figure 1 As shown, this application provides a three-node flip-to-recovery low-power radiation-hardened latch, including a signal input terminal, a clock control transmission module, a main feedback recovery loop, and a control node recovery loop. The data inverted signal DB is generated by the input signal D via an inverter, and the inverted clock signal NCK is generated by the clock signal CLK via a clock inverter. The clock control transmission module includes six transmission gates TG1 to TG6, all of which are controlled by CLK and NCK. When CLK is high, TG1 to TG6 are turned on, and the latch is in transparent operation mode; when CLK is low, TG1 to TG6 are turned off, and the latch is in hold operation mode.

[0065] In this configuration, TG1 receives input signal D at its input terminal, and its output terminal is connected to internal node N1; TG2 receives input signal D at its input terminal, and its output terminal is connected to internal node N3; TG3 receives input signal D at its input terminal, and its output terminal is connected to internal node N5; TG4 receives input signal D at its input terminal, and its output terminal is connected to output node Q. TG5 receives an inverted input signal DB at its input terminal, and its output terminal is connected to internal node N6; TG6 receives an inverted input signal at its input terminal, and its output terminal is connected to internal node N7. Therefore, in transparent mode, input signal D can be written simultaneously to N1, N3, N5, and Q, and inverted input signal DB can be written simultaneously to internal nodes N6 and N7.

[0066] The main feedback recovery loop includes the first three-input C unit CE1, the first clock-gated C unit CE2, the second three-input C unit CE3, and the second clock-gated C unit CE4; the control node recovery loop includes the first four-input C unit CE5, the second four-input C unit CE6, inverter INV1, and inverter INV2.

[0067] The first three-input C unit CE1 has its three inputs connected to node a, internal node N1, and internal node N5, respectively, and its output connected to internal node N2. The second three-input C unit CE3 has its three inputs connected to node a, output node Q, and internal node N3, respectively, and its output connected to the fourth internal node N4. The first four-input C unit CE5 has its four inputs connected to nodes N1, N3, N5, and Q, respectively, and its output connected to control node A. Control node A, after being inverted by the first inverter INV1, generates an inverted control node a. The second four-input C unit CE6 has its four inputs connected to internal nodes N2, N4, N6, and N7, respectively, and its output connected to control node B. Control node B, after being inverted by the second inverter INV2, generates an inverted control node b. The input of the first clock-gated C unit CE2 is connected to the inverting control node b and the relevant internal node obtained from the feedback of the previous stage. Its output is used to drive or hold the output node Q. The input of the second clock-gated C unit CE4 is connected to the inverting control node b and the relevant internal node obtained from the feedback of the previous stage. Its output is used to drive or hold the internal node N1. Through the above connections, CE1 to CE6 form a cross-coupled multipath interlocked feedback network.

[0068] The first clock-gated C unit CE2 receives logic information from inverting control nodes b, N2, and N6, and participates in the recovery and holding of output node Q in hold mode. The second clock-gated C unit CE4 receives logic information from inverting control nodes b, N4, and N7, and participates in the recovery and holding of node N1 in hold mode. Since the first clock-gated C unit CE2 and the second clock-gated C unit CE4 are controlled by clock signals, their feedback is suppressed in transparent mode to avoid unnecessary feedback contention during the data writing phase. In hold mode, they are enabled and together with the first three-input C unit CE1, the second three-input C unit CE3, the first four-input C unit CE5, and the second four-input C unit CE6, they form a self-recovering feedback loop.

[0069] When CLK=1, the latch is in transparent operating mode. At this time, TG1 to TG6 are all turned on. The input signal D is written to nodes N1, N3, N5, and Q via TG1, TG2, TG3, and TG4 respectively, while the inverted input signal DB is written to nodes N6 and N7 via TG5 and TG6 respectively. Since the input data directly drives multiple internal nodes, the latch can quickly complete data writing. Simultaneously, nodes N1, N3, N5, and Q work together on the four-input C unit CE5, enabling control node A to establish a stable logic state corresponding to the current input data; nodes N2, N4, N6, and N7 work together on the second four-input C unit CE6, enabling control node B to establish a stable logic state corresponding to the current input data. Control nodes A and B then generate nodes a and b via inverters INV1 and INV2 respectively, providing initial conditions for feedback recovery in hold mode.

[0070] When CLK=0, the latch is in hold mode. At this time, TG1 to TG6 are all off, and the inputs of input signal D and the inverted input signal DB are isolated from the internal storage nodes. Changes in external inputs will not directly affect the state of the internal nodes. CE2 and CE4 are enabled by the clock signal. CE1, CE2, CE3, CE4, CE5, and CE6 together form an interlock feedback network. This interlock feedback network is used to maintain the original latched data and to block error propagation when a sensitive node experiences a transient flip due to particle bombardment, restoring the flipped node to the correct logic value.

[0071] The sensitive nodes of the latch in hold mode include N1, N2, N4, A, B, and Q. Due to the symmetry and complementarity of the circuit structure, all possible single-node, dual-node, and triple-node switching scenarios can be summarized into several typical cases for explanation. For other switching combinations not explicitly listed, those skilled in the art can infer their recovery process based on the same interlocking feedback relationship and symmetrical recovery mechanism. Typical cases include: (1) When a single-node flip occurs in internal node N1, the inverting control node a and internal node N5 remain in the correct state. Due to the inconsistency at the input of CE1, CE1 maintains its original output state, thereby preventing the error from propagating from internal node N1 to internal node N2. At the same time, the feedback path related to internal node N1 is not disrupted, and CE4, in hold mode, re-drives internal node N1 based on the correct information provided by the undisturbed node, restoring internal node N1 to the correct logic value before the flip. Therefore, when a single-node flip occurs in internal node N1, the error is confined to internal node N1, and the output node Q does not experience an erroneous flip.

[0072] (2) When a single node flips in control node A, the inverting control node a changes with the flip of A, but nodes N1, N3, N5, and Q remain in the correct state. At this time, CE1 and CE3, due to inconsistent input states, keep their output nodes N2 and N4 unchanged, thus preventing the error from propagating to the main feedback link. Meanwhile, the four input nodes N1, N3, N5, and Q of CE5 all remain in the correct logic state, so CE5 can re-drive control node A, restoring control node A to the correct logic value. After control node A recovers, the inverting control node a recovers via INV1, and CE1 and CE3 re-enter the normal working state, keeping the entire latch stable. Therefore, when a SNU occurs in control node A, output node Q can still remain in the correct state.

[0073] (3) The sensitive nodes of the latch in hold mode include internal node N1, internal node N2, internal node N4, control node A, control node B, and output node Q. Due to the symmetry and complementarity of the circuit structure, all possible single-node, dual-node, and triple-node switching situations can be summarized into several typical cases for explanation. For other switching combinations not explicitly listed, those skilled in the art can infer their recovery process based on the same interlocking feedback relationship and symmetrical recovery mechanism.

[0074] (4) When a single-node flip occurs in internal node N1, the inverting control node a and internal node N5 remain in the correct state. Due to the inconsistency at the input of CE1, CE1 maintains its original output state, thereby preventing the error from propagating from internal node N1 to internal node N2. At the same time, the feedback path related to internal node N1 is not disrupted, and CE4, in hold mode, re-drives node N1 based on the correct information provided by the undisturbed node, restoring internal node N1 to the correct logic value before the flip. Therefore, when a single-node flip occurs in internal node N1, the error is confined to internal node N1, and the output node Q does not experience an erroneous flip.

[0075] (5) When a single node flips in control node A, the inverting control node a changes with the flip of control node A, but internal nodes N1, N3, N5 and output node Q remain in the correct state. At this time, CE1 and CE3, due to inconsistent input states, keep their output nodes N2 and N4 unchanged, thus preventing the error from propagating to the main feedback link. Meanwhile, the four input nodes N1, N3, N5 and Q of CE5 all remain in the correct logic state, so CE5 can re-drive control node A, restoring control node A to the correct logic value. After control node A recovers, the inverting control node a recovers via INV1, and CE1 and CE3 re-enter the normal working state, and the entire latch remains stable. Therefore, when a SNU occurs in control node A, output node Q can still maintain the correct state.

[0076] (6) When node pairs<N1,N2> When a double-node flip occurs, CE2 uses the undisturbed control information at its input to protect the output node Q, ensuring that output node Q is unaffected by the erroneous states of internal nodes N1 and N2. Simultaneously, CE4 restores internal node N1 through the undisturbed node. Once N1 is restored, the input conditions of CE1 return to normal, and CE1 further restores internal node N2 to its correct state. Thus, the node pair...<N1,N2> The DNU can be recovered step by step.

[0077] (7) When node pairs<N2,A> When a dual-node flip occurs, the flip of control node A causes the inverting control node a to change in reverse phase. Since there is still an unaffected correct node at the input of CE3, CE3 enters a hold state, preventing internal node N4 from being affected by the error. CE5 re-drives control node A based on the correct logic relationship between internal nodes N1, N3, N5, and output node Q, restoring control node A to its correct state. After control node A recovers, the inverting control node a recovers synchronously, and CE1 then resumes normal output, pulling internal node N2 back to its correct logic value. Therefore, the node pair...<N2,A> When a DNU occurs, the error will not propagate to the output node Q.

[0078] (8) When node pairs<A,B> When a dual-node flip occurs, control node A and control node B affect the inverting control nodes a and b via INV1 and INV2, respectively. However, because CE1, CE3, CE2, and CE4 all have the characteristic of maintaining their original state when inputs are inconsistent, internal nodes N2 and N4, output node Q, and internal node N1 will not be immediately flipped due to the error. Simultaneously, CE5 restores control node A based on the unaffected internal nodes N1, N3, N5, and output node Q, and CE6 restores control node B based on the unaffected internal nodes N2, N4, N6, and N7. After control nodes A and B are restored, inverting control nodes a and b are restored synchronously, and the entire feedback loop stabilizes again.

[0079] (9) When node pairs<A,Q> When a dual-node flip occurs, CE3 maintains node N4 unchanged due to input inconsistency, blocking the propagation of errors caused by both Q and A. CE2 restores output node Q based on the unaffected nodes, and CE5 restores control node A based on the logical relationship between internal nodes N1, N3, N5, and output node Q. After control node A is restored, the inverting control node a is restored via INV1, and CE1 and CE3 resume normal operation. Thus, the node pair...<A,Q> The DNU can be fully recovered.

[0080] (10) In hold mode, the latch of this application can tolerate three-node flipping. When the node group<N1,N2,Q> When a three-node flip occurs simultaneously, CE3 maintains its internal node N4 unchanged based on its unaffected input, preventing the erroneous state of output node Q from propagating further. CE4 uses the unaffected node to restore internal node N1; after internal node N1 is restored, the input relationship of CE1 returns to normal, and CE1 restores internal node N2 to the correct state; subsequently, CE2 restores output node Q to the correct logic value based on the restored feedback conditions. In the above recovery process, the error is first blocked by CE3, and then gradually restored through CE4, CE1, and CE2, ultimately achieving...<N1,N2,Q> Everything has been restored to its original state.

[0081] (11) When the node group<N1,A,N2> When three nodes flip simultaneously, CE3 keeps N4 unchanged, and CE2 ensures that the output node Q is unaffected by the error. CE4 first restores the internal node N1 based on the unaffected nodes. After the internal node N1 is restored, the input conditions of CE5 once again satisfy the correct logical relationship, and CE5 restores the control node A; after the control node A is restored, the inverting control node a is restored via INV1, and CE1 regains the correct input and restores the internal node N2. Thus, the node group...<N1,A,N2> The TNU was eliminated in stages.

[0082] (12) When the node group<N1,A,B> When three nodes flip simultaneously, the flipping of control nodes A and B causes changes in the inverting control nodes a and b, respectively. At this point, CE1, CE2, CE3, and CE4 all utilize the characteristic of maintaining state when the inputs of unit C are inconsistent to intercept the error, preventing it from propagating to critical nodes such as N2, N4, and Q. CE6 restores control node B based on its undisturbed input; after control node B is restored, inverting control node b is restored. After inverting control node b is restored, CE4 obtains the correct feedback conditions and restores N1. After N1 is restored, CE5 restores control node A using the correct relationship between N1, N3, N5, and Q. Ultimately, control nodes A, B, and internal node N1 are all restored to their correct states.

[0083] (13) When the node group<N1,A,Q> When three nodes flip simultaneously, CE3 keeps N4 unchanged, and CE1 keeps N2 unchanged, thus preventing the error from propagating in the main feedback path. CE4 restores internal node N1 through the undisturbed node, CE2 restores output node Q through the undisturbed node, and CE5 restores control node A through the feedback relationship between internal nodes N1, N3, N5, and output node Q. After internal node N1, output node Q, and control node A are successively restored, inverting control nodes a and b also return to the correct state, and the latch re-enters the stable holding state.

[0084] As can be seen from the analysis of the above typical scenarios, the core recovery mechanism of this application does not rely on a single path, but rather on an interlocked feedback network formed by multiple C units. When any one, two, or three sensitive nodes experience a transient flip, at least one set of undisturbed nodes maintains the original correct logical value. The undisturbed nodes, on the one hand, put the relevant C units into a hold state to block error propagation, and on the other hand, re-drive the disturbed nodes through the feedback path, restoring the disturbed nodes to their correct state before the flip. Therefore, this application can achieve self-recovery of SNU, DNU, and TNU.

[0085] To verify the radiation resistance of the latch in this application, a double exponential current source was used to simulate the transient current pulse caused by a single-event event. The double exponential current source can be expressed as: in, The current amplitude parameter is related to the charge deposited by particle bombardment. and These represent the time constants during the charge collection process. In one specific embodiment, the rise time constant is set to 5 ps and the fall time constant to 45 ps. The current is set to 780 μA. By injecting this double-exponential current pulse into the sensitive node, the transient flip-flop process caused by particle bombardment can be simulated.

[0086] To further improve verification accuracy, a TCAD hybrid simulation was used to model and verify the latch of this application. Specifically, a three-dimensional TCAD model including PMOS and NMOS devices was established, and the IV characteristics of the devices were calibrated using a 55 nm CMOS process design kit to ensure consistency between the TCAD model and the process model. In one specific embodiment, the heavy ion track length was set to 10 μm, the track radius was set to 50 nm, and the LET value was set to 60 MeV·cm² / mg. The particles bombarded the drain region of the off-state transistor in a vertical direction to simulate the most unfavorable charge collection situation at the sensitive node.

[0087] In one embodiment, SNU, DNU, and TNU injection simulations were performed on the latch of this application. The simulation results show that when a single sensitive node, two sensitive nodes, or three sensitive nodes are subjected to transient disturbances, the internal nodes may experience brief voltage fluctuations, but the output node Q can maintain its original logic value or recover to its original logic value within a short time, proving that the latch has a three-node toggle self-recovery capability. Figures 4 to 6 The images show the state of each node after single-node, double-node, and triple-node injection, respectively, demonstrating that the circuit can recover after being disturbed.

[0088] To verify the performance of the latch in this application, circuit-level simulations were performed under the conditions of 55 nm CMOS process, 1.2 V power supply voltage, 27℃ temperature, and 500MHz operating frequency. Simulation results show that in a specific embodiment, the total power consumption of the latch in this application is approximately 8.551 μW, the DQ propagation delay is approximately 30.79 ps, the layout area is approximately 50.27 μm², and the number of transistors is approximately 60. Compared with existing three-node flip-flop tolerant latches, this application maintains the TNU self-recovery capability while reducing power consumption, delay, power-delay product (PDP), and power-delay-area product (PDAP), demonstrating superior overall performance.

[0089] Simulations were also performed on the latch of this application under variations in process technology, voltage, and temperature. The process corners included TT, FF, and SS; the power supply voltage varied from 0.8 V to 1.6 V; and the temperature varied from 0 °C to 80 °C. The simulation results for the changes in delay and power consumption under different process corners, power supply voltages, and temperatures are shown below. Figure 7 and 8 As shown, the power consumption and latency of the latch in this application remain within an acceptable range, indicating that it has good PVT robustness.

[0090] In one embodiment, Monte Carlo simulation can also be used to verify the stability of the latch in this application to random process deviations and device mismatches. In one specific embodiment, 2000 Monte Carlo simulations were performed. The results showed that the power consumption and delay distribution of the latch in this application were relatively stable, and no abnormal situations occurred that led to latch failure or loss of self-recovery function. This indicates that the latch is suitable for application in high-reliability, low-power space electronic systems, aerospace electronic systems, electronic systems in nuclear radiation environments, and other integrated circuit systems sensitive to soft errors.

[0091] In other embodiments, the latch structure of this application is not limited to 55 nm CMOS process and can be migrated to other CMOS process nodes. Depending on different processes, power supply voltages, load conditions, and application requirements, the sizes of PMOS and NMOS transistors in the C-cells, transmission gates, and inverters can be scaled proportionally or locally optimized. As long as it still uses multi-input C-cells to form an interlocked feedback network and blocks error propagation and recovers from disturbed nodes through undisturbed nodes, it should be considered to fall within the protection scope of this application.

[0092] The number of C-cells, transmission gates, node naming conventions, and transistor sizes in this application can be adjusted according to actual circuit requirements. For example, without changing the basic interlocking feedback concept, some three-input C-cells can be replaced with equivalent logic structures, some clock-gated C-cells can be replaced with logic cells that have the same hold and enable functions, or a buffer stage can be added to the output nodes to improve driving capability. All of the above equivalent substitutions do not affect the essence of this application's three-node flip-and-recovery mechanism achieved through multi-input C-cell interlocking feedback.

[0093] In summary, the three-node toggle self-recovering low-power radiation-hardened latch provided in this application achieves fast data writing in transparent mode through six transmission gates, forms an interlocked feedback network in hold mode through multiple three-input, four-input, and clock-gated C-cells, and utilizes the characteristic of holding the state when the C-cell inputs are inconsistent to achieve error interception, and uses feedback drive from undisturbed nodes to achieve error recovery. This structure can achieve SNU, DNU, and TNU self-recovery under low power consumption and low latency conditions, and is suitable for high-reliability, low-power integrated circuit designs.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A three-node flip-over self-recovering radiation-resistant latch, characterized in that, include: The clock input terminal is used to receive the clock signal CLK and provide the clock signal CLK to the clock control transmission module and the clock gate C unit; The data input terminal is used to receive the input signal D and generate an inverted signal DB through an inverter. The clock-controlled transmission module is used to transmit the input signal to the output node Q and internal nodes N1, N3 and N5 through the transmission gate under the control of the clock signal CLK, and to transmit the inverted signal DB to internal nodes N6 and N7. The main feedback recovery loop includes two three-input C units CE1 and CE3, and two clock-gated three-input C units CE2 and CE4. CE1, CE2, CE3, and CE4 form a loop. The first input terminals of CE1 and CE3 are connected to the inverting control node a, and the first input terminals of CE2 and CE4 are connected to the inverting control node b. The third input terminals of CE1, CE2, CE3, and CE4 are connected to the internal nodes N5, N6, N3, and N7, respectively. A control node recovery loop is used to form an interlocked recovery network connecting internal nodes N1 to N7, output node Q, and control nodes A and B through two four-input C units and two inverters. The control node recovery loop includes two four-input C units CE5 and CE6, and two inverters INV1 and INV2. The four inputs of CE5 are connected to internal nodes N1, N3, N5, and output node Q, respectively. The output of CE5 and the input of INV1 are both connected to control node A. The output of INV1 is connected to the inverting control node a. The four inputs of CE6 are connected to internal nodes N2, N4, N6, and N7, respectively. The output of CE6 and the input of INV2 are both connected to control node B. The output of INV2 is connected to the inverting control node b. In the main feedback recovery loop, the output of CE1 and the second input of CE2 are both connected to internal node N2; the output of CE2 and the second input of CE3 are both connected to output node Q; the output of CE3 and the second input of CE4 are both connected to internal node N4; the output of CE4 and the second input of CE1 are both connected to internal node N1; the first inputs of CE1 and CE3 are both connected to inverting control node a; the first inputs of CE2 and CE4 are both connected to inverting control node b; the third inputs of CE1, CE2, CE3, and CE4 are connected to internal nodes N5, N6, N3, and N7, respectively; and the clock control terminals of CE2 and CE4 are connected to the clock signal CLK.

2. The three-node flip-over self-recovering radiation-resistant latch according to claim 1, characterized in that, The clock-controlled transmission module includes six transmission gates TG1 to TG6; The input terminals of TG1 to TG4 all receive the input signal D. The output terminals of TG1 to TG4 are connected to internal nodes N1, N3 and N5 respectively, and output Q. The clock input terminals of TG1 to TG6 all receive the clock signal CLK. The inverting clock input terminals of TG1 to TG6 all receive the inverting clock signal NCK. The inputs of TG5 and TG6 both receive the inverted signal DB, and the outputs of TG5 and TG6 are connected to internal nodes N6 and N7, respectively.

3. A three-node flip-over self-recovering radiation-resistant latch according to claim 1, characterized in that, Each transmission gate includes an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor and the source of the PMOS transistor are connected together, and the resulting connection point is used as the input terminal of the transmission gate. The drain of the NMOS transistor and the source of the PMOS transistor are connected together, and the resulting connection point is used as the output terminal of the transmission gate. The gate of the NMOS transistor is used as the clock input terminal, and the gate of the PMOS transistor is used as the inverting clock input terminal.

4. A three-node flip-over self-recovering radiation-resistant latch according to claim 2, characterized in that, When CLK=1, the latch is in transparent operating mode; In transparent working mode, TG1 to TG6 are all turned on. The input signal D is written to the internal nodes N1, N3, N5 and output node Q via TG1, TG2, TG3 and TG4 respectively. The input inverted signal DB is written to the internal nodes N6 and N7 via TG5 and TG6 respectively. Internal nodes N1, N3, and N5, along with output node Q, work together to enable control node A to establish a stable logic state corresponding to the current input data. Nodes N2, N4, N6, and N7 work together on the four-input C unit CE6, enabling control node B to establish a stable logic state corresponding to the current input data; Control nodes A and B are then converted into nodes a and b via inverters INV1 and INV2, respectively, to provide initial conditions for feedback recovery in hold mode.

5. A three-node flip-over self-recovering radiation-resistant latch according to claim 2, characterized in that, When CLK=0, the latch is in hold mode; In the operating mode: TG1 to TG6 are all turned off, input signal D and inverted input signal DB are isolated from the internal storage nodes, and changes in external input will not directly affect the state of the internal nodes. CE2 and CE4 are enabled by the clock signal. CE1, CE2, CE3, CE4, CE5 and CE6 together form an interlocked feedback network. The interlocked feedback network is used to maintain the original latched data and also to block error propagation when a sensitive node is bombarded by particles and undergoes a transient flip, and to restore the flipped node to the correct logic value.

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