A dynamic level clamping circuit for improving CMTI and a capacitive isolation driving chip

Abstract

The application provides a dynamic level clamping circuit for improving CMTI and a capacitive isolation driving chip. The application solves the technical problem that the input common mode level of a preamplifier in a capacitive isolation driving chip is prone to drift under strong common mode transient interference, which leads to invalidation of the working point of the preamplifier, gain reduction and failure of OOK signal demodulation. Through the cooperative design scheme including a precise voltage biasing circuit and a fast response active clamping circuit, the voltage biasing circuit establishes a unified and stable working reference for the whole system, and the active clamping circuit can detect and quickly clamp the abnormal input common mode level in real time, ensuring that the preamplifier always works in the linear region under a harsh noise environment, thereby guaranteeing the continuous reliability of the signal link and the correctness of demodulation, and significantly improving the common mode transient immunity of the chip and the system stability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a dynamic level clamping circuit and a capacitive isolation driver chip for improving CMTI. Background Technology

[0002] Capacitive isolation driver chips are widely used in high-voltage scenarios such as power management and motor drives, primarily achieving cross-domain signal transmission through isolation capacitors. In this process, common-mode interference is a core factor affecting system stability. To ensure signal integrity, the chip typically employs on-off keying (OOK) modulation technology, modulating the input signal and coupling it through the isolation barrier, then demodulating and recovering it at the receiving end.

[0003] Existing capacitive isolation driver chips typically employ a differential signal transmission architecture to address noise challenges. The system uses an internal oscillator clock to perform OOK modulation on the input digital bitstream, generating a signal which is then transmitted through an isolation capacitor. At the receiving end, a preamplifier amplifies the attenuated, weak signal, which is subsequently demodulated by an envelope detector to retrieve the original digital signal. This architecture, through the physical layer's isolation barrier and the inherent characteristics of differential circuitry, achieves relatively good signal transmission under normal operating conditions.

[0004] However, in practical high-voltage applications, the rapid switching of power devices (such as SiC and GaN) generates drastic voltage changes, triggering strong common-mode transient interference. This interference is coupled into the chip through the parasitic parameters of the isolation capacitor, causing a drastic drift in the common-mode level at the input node of the preamplifier. Relying solely on the inherent noise immunity of the differential structure will result in severe misalignment when faced with extremely high common-mode noise slew rates: when the input common-mode level drift exceeds the linear input range of the preamplifier, the differential pair will exit the saturation region, leading to a sharp drop in gain and signal distortion, ultimately causing demodulation failure or system mistriggers. Therefore, a circuit scheme that can actively suppress common-mode interference and quickly stabilize the input common-mode level is urgently needed to prevent signal transmission interruptions caused by level drift. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a dynamic level clamping circuit and a capacitive isolation driver chip to improve CMTI (Common Mode Interference). This solves the problem in existing technologies where common-mode transient interference is generated under high-voltage scenarios, leading to preamplifier input common-mode level drift and subsequent signal demodulation failure.

[0006] According to an embodiment of the present invention, a dynamic level clamping circuit for improving CMTI is applied to the clamping protection of the preamplifier in a capacitive isolation driver IC, comprising a voltage biasing circuit and an active clamping circuit, wherein:

[0007] The active clamping circuit includes a first clamping unit and a second clamping unit, both of which include a pull-up clamping circuit and a pull-down clamping circuit;

[0008] The voltage bias circuit includes a reference bias branch, a reference level branch, and a high-pass filter module.

[0009] The reference bias branch provides bias voltage to the pull-up clamping circuit and the pull-down clamping circuit in the first clamping unit and the second clamping unit. The bias voltage is used to control the clamping state switching of the pull-up clamping circuit and the pull-down clamping circuit.

[0010] The reference level branch is used to generate a common-mode reference level that matches the bias voltage and provides it to the differential input of the preamplifier;

[0011] The high-pass filter module is used to filter out low-frequency components in the signal transmitted to the input of the preamplifier and to superimpose the filtered signal with the common-mode reference level.

[0012] The superimposed level provides bias for the pull-up clamping circuit and pull-down clamping circuit in the first clamping unit and the second clamping unit, so that the first clamping unit and the second clamping unit do not enter the clamping state when there is no transient interference; when there is transient interference, the pull-up clamping circuit and pull-down clamping circuit in the first clamping unit and the second clamping unit switch to enter the pull-up or pull-down clamping state.

[0013] Furthermore, the pull-down clamping circuits in both the first clamping unit and the second clamping unit include a first pull-down clamping branch and a second pull-down clamping branch. The first pull-down clamping branch is used to pull down and clamp to protect the input terminal of the preamplifier, and the second pull-down clamping branch is used to pull down and clamp the far point of the common resistor or common equivalent resistor of the differential circuit in the preamplifier. When the first pull-down clamping branch pulls down and clamps, it triggers the clamping action of the second pull-down clamping branch.

[0014] Furthermore, the first pull-down clamping branch includes a first pull-down MOSFET and a first pull-down resistor. The reference bias branch provides a gate bias voltage for the first pull-down MOSFET. The source of the first pull-down MOSFET is connected to the input terminal of the preamplifier, and the drain is connected to one end of the first pull-down resistor. The other end of the first pull-down resistor is grounded.

[0015] The second pull-down clamping branch includes a second pull-down MOS transistor and a third pull-down MOS transistor. The source of the third pull-down MOS transistor is grounded, its gate is connected to the drain of the first pull-down MOS transistor, and its drain is connected to the source of the second pull-down MOS transistor and the source of the preamplifier tail current source transistor.

[0016] The gate and source of the second pull-down MOSFET are shorted, and the drain is connected to the input of the preamplifier.

[0017] Furthermore, the pull-up clamping circuit includes a first pull-up MOSFET and a second pull-up MOSFET;

[0018] The reference bias branch provides a gate bias voltage for the second pull-up MOS transistor. The drain of the second pull-up MOS transistor is connected to the source of the first pull-up MOS transistor, and the source is connected to the source of the first pull-down MOS transistor, and they are all connected to the input terminal of the preamplifier.

[0019] The drain of the first pull-up MOSFET is connected to the second power supply, and the gate is connected to the first power supply.

[0020] Furthermore, the reference bias branch includes a first bias MOSFET, a second bias MOSFET, a first bias resistor, and a second bias resistor;

[0021] The gate and drain of the first biased MOS transistor are connected, and the source is connected to the source of the second biased MOS transistor. The gate and drain of the second biased MOS transistor are connected, forming a diode connection structure.

[0022] The first bias resistor is connected in series between the drain of the first bias MOSFET and the first power supply, and the second bias resistor is connected in series between the drain of the second bias MOSFET and the ground terminal.

[0023] Furthermore, the reference bias branch provides a gate bias voltage for the reference level branch, and the reference level branch includes a first reference MOS transistor and a second reference MOS transistor;

[0024] The source of the first reference MOSFET is connected to the source of the second reference MOSFET, the drain of the first reference MOSFET is connected to the first power supply, and the drain of the second reference MOSFET is grounded.

[0025] Furthermore, the reference bias branch and the reference level branch also include a first capacitor and a second capacitor. The first capacitor is connected in parallel between the source of the first bias MOSFET and the ground line, and the second capacitor is connected in parallel between the source of the second reference MOSFET and the ground line, for filtering out high-frequency noise in the bias voltage.

[0026] Furthermore, the drain of the first bias MOSFET is connected to the gate of the first reference MOSFET, and the drain of the second bias MOSFET is connected to the gate of the second reference MOSFET, thereby providing gate bias voltage for the first reference MOSFET and the second reference MOSFET.

[0027] Furthermore, the total channel width of the second bias MOSFET is set to twice the total channel width of the first bias MOSFET, and the total channel width of the second reference MOSFET is set to twice the total channel width of the first reference MOSFET, thereby making the common-mode reference level equal to the bias voltage and providing a stable DC operating point for the preamplifier.

[0028] Furthermore, the high-pass filter module includes a first filter unit and a second filter unit with identical structures and symmetrically arranged, and both the first filter unit and the second filter unit include a passive filter circuit.

[0029] The passive filter circuit includes a high-pass filter capacitor, a first high-pass filter resistor, and a second high-pass filter resistor. The high-pass filter capacitor and the first high-pass filter resistor are connected in parallel. One end of the high-pass filter capacitor is connected to the pre-stage isolation capacitor to receive the first AC input signal, and the other end is connected to the input terminal of the preamplifier through the second high-pass filter resistor.

[0030] Secondly, according to another embodiment of the present invention, a capacitive isolation driver chip is also provided, the isolation driver chip internally including a dynamic level clamping circuit and a preamplifier for improving CMTI as described in any of the above aspects, wherein the dynamic level clamping circuit dynamically clamps at least the input of the preamplifier.

[0031] The technical principle of this invention is as follows: a bias voltage matching the common-mode reference level of the preamplifier is generated by a voltage bias circuit, and this bias voltage is used to control an active clamping circuit. When common-mode transient interference occurs, the active clamping circuit detects the voltage fluctuation at the input of the preamplifier in real time: if the input level drifts due to interference, the clamping circuit conducts through a pull-up or pull-down path to force the input common-mode level to be clamped nearby; at the same time, it coordinates the adjustment of the source potential of the preamplifier tail current source to ensure that it always operates in the linear amplification region.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] This invention addresses the technical problem of preamplifier input common-mode level drift, leading to operating point failure and OOK demodulation failure in capacitor-isolated driver chips under strong common-mode transient interference by employing a collaborative design scheme that includes a precision voltage bias circuit and a fast-response active clamping circuit. The voltage bias circuit generates and locks equal bias voltage and common-mode reference level through a current mirror structure, providing a unified and stable operating reference for the system. Based on this reference, the active clamping circuit immediately conducts the corresponding pull-up or pull-down current path when it detects an abnormal shift in the input level due to common-mode transient interference, quickly forcing the potential back to the normal range. This invention achieves active and dynamic clamping of the preamplifier input common-mode level and tail current source node, ensuring continuous and stable operation of the signal amplification link in harsh noise environments and fundamentally improving the reliability of the isolation chip. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a conventional isolated channel transmission structure according to an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the circuit structure principle of an embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of the voltage and current waveforms at key nodes in an embodiment of the present invention. Detailed Implementation

[0037] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] like Figure 1 The diagram illustrates a simplified receiver structure of a traditional capacitor-isolated driver chip. After coupling via an isolation capacitor, the signal directly provides the operating point for the preamplifier through a simple bias resistor, followed by amplification and demodulation. This structure suffers from severe voltage fluctuations at the preamplifier input node when faced with strong common-mode transient interference (as indicated by the dashed arrow). Lacking any active protection mechanism, this can easily lead to operating point failure and demodulation errors. To address these issues, this invention provides a circuit scheme that actively suppresses common-mode interference and quickly stabilizes the input common-mode level to prevent signal transmission interruptions caused by voltage level drift.

[0039] like Figure 2 As shown, this embodiment of the invention proposes a dynamic level clamping circuit to improve CMTI (Continuous Level Induction). This circuit system mainly consists of a voltage biasing circuit and an active clamping circuit, with its output connected to a subsequent preamplifier. Wherein:

[0040] 1. Voltage bias circuit:

[0041] The voltage bias circuit is the foundation of the entire active clamping system. It includes a reference bias branch, a reference level branch, and a high-pass filter module. Its core function is to generate two key reference voltages: one is to provide a precise bias voltage Vb1 to the active clamping circuit, and the other is to provide a stable common-mode reference level Vref to the subsequent preamplifier, so that the preamplifier can operate in a suitable DC bias state and effectively amplify the differential signal after it has been attenuated by the isolation capacitor.

[0042] 1.1 Reference bias branch:

[0043] While direct resistor voltage division is simple in integrated circuit design, it is highly susceptible to power supply fluctuations and temperature variations. This embodiment selects a structure with a diode-connected MOSFET and a resistor in series. By utilizing the threshold voltage characteristic of the MOSFET and combining it with resistor voltage division, a reference current that is insensitive to power supply voltage fluctuations can be generated, thereby producing a stable Vb1.

[0044] This reference bias branch includes a first bias MOSFET MN1 (NMOS transistor), a second bias MOSFET MP1 (PMOS transistor), a first bias resistor R1, a second bias resistor R2, and a first capacitor C1. One end of R1 is connected to the first power supply VDD1, and the other end is connected to the drain of MN1. The gate and drain of MN1 are shorted (forming a diode connection), and its source is connected to the source of MP1. The gate and drain of MP1 are also shorted (also forming a diode connection), and its drain is connected to one end of resistor R2. The other end of resistor R2 is grounded (VEE). C1 is connected in parallel between the source connection node of MN1 and MP1 and ground.

[0045] This is a typical self-biased circuit. A series branch is formed by the current flowing through R1, MN1, MP1, and R2. The diode connection of MN1 and MP1 forces them to operate in the saturation region, where their gate-source voltage VGS equals their drain-source voltage VDS. This voltage serves as the reference potential for node Vb1. Its specific operating process is as follows:

[0046] After being stepped down by R1, power supply VDD1 flows to ground through the current path formed by MN1 and MP1. Due to the specific design of the channel length and width of MN1 and MP1, the node voltage is locked. C1 is used to filter out high-frequency noise, prevent Vb1 fluctuations, and ensure the purity of the bias voltage.

[0047] This invention generates a low-noise, high-stability bias voltage Vb1 through a reference bias branch, providing a precise reference standard for subsequent clamping operations. It should be understood that the circuit structure for generating the stable bias voltage Vb1 is not limited to this; those skilled in the art can also implement it using other common bias structures such as bandgap references, current mirrors, and resistor dividers.

[0048] 1.2 Reference Level Branch:

[0049] The preamplifier needs to operate at a specific DC bias point to linearly amplify the signal. Since the input signal is an AC signal coupled through an isolation capacitor, its DC component is lost. Therefore, a DC operating point must be artificially provided. A source follower structure composed of NMOS and PMOS transistors is chosen, which features high input impedance and low output impedance, effectively isolating interference between the preceding and following stages.

[0050] This reference level branch includes a first reference MOSFET MN2 (NMOS transistor), a second reference MOSFET MP2 (PMOS transistor), and a second capacitor C2. Wherein:

[0051] The gate of MN2 is connected to the drain of MN1 (i.e., the node of the reference bias branch). The source of MN2 is connected to the source of MP2 and to the input of the subsequent preamplifier (which is also the output of the high-pass filter module). The drain of MP2 is grounded to GND. C2 is connected in parallel between the source connection node of MN2 and MP2 and the ground terminal.

[0052] MN2 and MP2 form a source follower with a current mirror load. The gate of MN2 receives a control signal from the reference branch. By adjusting the current flowing through MN2, its source voltage, i.e., the common-mode reference level Vref, is adjusted.

[0053] The reference level branch of this invention provides a stable DC operating point for the subsequent preamplifier, ensuring that the preamplifier is already in the optimal amplification state when there is no signal input.

[0054] To ensure that the voltage drop across MN1 and MP1 is consistent due to the current in the reference branch, in this embodiment, the channel widths of MN1, MN2, MP1, and MP2 are... and channel length All remain consistent, with the reference bias branch consisting of MN1, MP1, R1, R2, and C1, where MP1 is set to... For MN1 Twice that, the calculation formula is as follows:

[0055]

[0056] Where Wtotal is the total width of the transistor; The number of transistors connected in parallel. The gate index is the number of gates for a single transistor.

[0057] The voltage level of Vb1 is controlled by adjusting the ratio and resistance value of R1 and R2, and C1 is a voltage regulator capacitor; the reference level branch composed of MN2, MP2, and C2 is also configured with MP2. For MN2 Twice that of C2, which is a voltage regulator capacitor; after adjustment, Vb1 = Vref is a suitable DC potential. Since current will be drawn and injected at Vref due to common-mode transient interference events, therefore MN2 and MP2 Typically, a larger value is set to meet the requirements, and the area of ​​the voltage regulator capacitor C2 is also set to be larger.

[0058] This invention achieves precise matching between the bias voltage and the reference voltage by adjusting the channel length and width of the MOSFET. This matching is a prerequisite for the subsequent active clamping circuit to accurately determine "when to start operating." If the two are not equal, the clamping circuit may malfunction under normal signals or react slowly when interference occurs.

[0059] 1.3 High-pass filter module:

[0060] The function of the isolation capacitor is to block direct current (DC) and allow only alternating current (AC) to pass through. After the input signal passes through the isolation capacitor, its DC component is lost, leaving only AC fluctuations. In order for the signal to be recognized by the preamplifier, a DC bias (i.e., Vref) must be superimposed. Therefore, this invention incorporates a high-pass filter module between the voltage bias circuit and the preceding isolation capacitor to process the input signal.

[0061] The high-pass filter module of the present invention includes a first filter unit and a second filter unit with identical structures and symmetrical arrangement. Both the first filter unit and the second filter unit include a passive filter circuit. The passive filter circuit includes a high-pass filter capacitor, a first high-pass filter resistor and a second high-pass filter resistor.

[0062] In this embodiment, the high-pass filter capacitor of the first filter unit is Cin+, the first high-pass filter resistor is Rin+, and the second high-pass filter resistor is R3, which are connected to the positive input terminal V+ of the preamplifier; the first high-pass filter resistor of the second filter unit is Rin−, the high-pass filter capacitor is Cin−, and the second high-pass filter resistor is R4, which are connected to the negative input terminal V− of the preamplifier, wherein:

[0063] One end of Cin+ is connected to the pre-amplifier isolation capacitor (receiving the signal IN+), and the other end is connected to one end of R3. The other end of R3 is connected to the positive input terminal V+ of the preamplifier. Rin+ is connected in parallel across Cin+. The connection of Cin−, Rin−, and R4 is symmetrical to the above, processing the negative input signal IN−. Its specific working process is as follows:

[0064] The differential AC input signals IN+ and IN- from the previous stage are high-pass filtered by Cin+ and Cin−, respectively, to remove DC components and low-frequency drift. The filtered AC signals flow through R3 and R4 and are superimposed on the common-mode reference level Vref.

[0065] In the present invention, the high-pass filtering module re-rises the DC operating point of the AC signal to the linear amplification region of the preamplifier, forming an AC signal with stable DC bias, ensuring that the signal can be correctly amplified by the subsequent-stage circuit.

[0066] 2. Active clamp circuit:

[0067] The active clamp circuit is the core of the present invention, which is used to forcibly pull the voltage back to a safe range when common-mode transient interference occurs (CMTI refers to common-mode transient immunity). The active clamp circuit comprises a first clamping path unit and a second clamping path unit, and both the first clamping path unit and the second clamping path unit comprise an pull-up clamp circuit and a pull-down clamp circuit.

[0068] 2.1 Pull-up clamp circuit (for negative transient interference):

[0069] When negative common-mode transient interference occurs, the voltage at the input terminal will be pulled down instantaneously, which may cause the preamplifier to cut off. A conductive path from the power supply to the input terminal is required to "pull up" the voltage.

[0070] The pull-up clamp circuit comprises a first pull-up MOS transistor and a second pull-up MOS transistor, wherein the first pull-up MOS transistor of the pull-up clamp circuit of the first clamping path unit is MN3, and the second pull-up MOS transistor is MN4, which is connected to the non-inverting input terminal V+ of the preamplifier; the first pull-up MOS transistor of the pull-up clamp circuit of the second clamping path unit is MN7, and the second pull-up MOS transistor is MN8, which is connected to the inverting input terminal V− of the preamplifier.

[0071] The drain of MN4 is connected to the source of MN3. The drain of MN3 is connected to power supply VDD2, and the gate is connected to power supply VDD1, which keeps MN3 normally on as a tail current source or a pull-up load. The connection relationship of MN7 and MN8 is symmetrical to that of MN3 and MN4. The principle of the present invention is to use MN4 as a detection transistor. According to the conduction condition of NMOS, the transistor conducts when VGS>Vth. The specific working process is as follows:

[0072] Normal state: Vb1=Vref. The gate of MN4 is Vb1, and the source of MN4 is Vref. At this time, VGS=Vb1−Vref=0, which is less than the threshold voltage Vth, so MN4 is cut off, and the pull-up circuit does not work.

[0073] When common-mode transient interference occurs (negative interference): if the V+ node suddenly drops due to the interference, so that V+<Vb1−Vth; at this time, the VGS of MN4 is greater than Vth, and the transistor conducts. Current flows from VDD2 to the V+ node through MN3 and MN4 for pull-up. The same applies to the V- node.

[0074] The pull-up clamping circuit of this invention charges the input terminal V of the preamplifier when negative interference is generated, preventing its voltage from dropping further and clamping it near Vb1−Vth, ensuring that the input common-mode level of the preamplifier is not lower than its operating range.

[0075] 2.2 Pull-down clamping circuit (for positive transient interference):

[0076] Forward common-mode transient interference can momentarily raise the input voltage, potentially causing the preamplifier to enter the saturation region or break down. Simple diode clamping cannot provide sufficient discharge capability and requires protection of the tail current source in the subsequent stage. Therefore, the pull-down clamping circuit of this invention adopts a cascaded control method, which not only clamps the input terminal but also controls the potential of the tail current source in conjunction with the input.

[0077] The first pull-down clamping branch of this invention is used to pull down and clamp to protect the input terminal of the preamplifier, and the second pull-down clamping branch is used to pull down and clamp the far point of the common resistor or common equivalent resistor of the differential circuit in the preamplifier. The first pull-down clamping branch includes a first pull-down MOSFET and a first pull-down resistor, and the second pull-down clamping branch includes a second pull-down MOSFET and a third pull-down MOSFET.

[0078] In this embodiment, the first pull-down MOSFET in the first clamping unit is MP3, the first pull-down resistor is R5, the second pull-down MOSFET is MN5, and the third pull-down MOSFET is MN6, connected to the positive input terminal V+ of the preamplifier; the first pull-down MOSFET in the second clamping unit is MP4, the first pull-down resistor is R6, the second pull-down MOSFET is MN9, and the third pull-down MOSFET is MN10, connected to the negative input terminal V− of the preamplifier. Wherein:

[0079] The gate of MP3 is connected to the bias voltage Vb1, and the source is connected to V+. The drain of MP3 is connected to one end of R5 and the gate of MN6; the other end of R5 is grounded; the source of MN6 is grounded, and its drain is connected to the source of MN5; the gate and source of MN5 are shorted (diode connection), and its drain is connected to V+. MP4, R6, MN10, and MN9 are symmetrically connected to the negative input terminal V− of the preamplifier. The specific working process is as follows:

[0080] Normal state: Vb1 = Vref. At this time, the source of MP3 is Vref, the gate is Vb1, VSG = 0, which is less than Vth, so MP3 is cut off. There is no current through R5, and the gate of MN6 is 0, also cut off. MN5 is a diode connection, but since there is no driver, it does not affect normal operation.

[0081] When a common-mode transient disturbance occurs (forward disturbance): If the voltage at the V+ node rises instantaneously due to the disturbance, exceeding the potential of Vb1, causing VSG > Vth, MP3 will conduct. Current will flow through R5, generating a voltage drop across R5.

[0082] Cascade operation: the voltage drop across R5 raises the gate potential of MN6, and when the potential exceeds the threshold of MN6, MN6 is turned on. After MN6 is turned on, it pulls the source of MN5 (which is also the drain of MN6) towards ground potential.

[0083] Bidirectional clamping: on one hand, MP3 directly discharges the excess charge of V+; on the other hand, the conduction of MN6 pulls down the source potential of MN5. Since MN5 is diode-connected, the potential of its drain (i.e., V+) will also be forced to follow the change of the source potential. The same principle applies to the V- node.

[0084] The pull-down clamping circuit of the present invention rapidly turns on MP3 to discharge the overshoot voltage at the input node; controls MN5 through R5 and MN6, and adjusts the source potential Vs of the tail current source transistor (MA3) of the pre-amplifier. When the input terminal voltage is raised, the source potential of the tail current source is pulled down, thereby maintaining the stability of VDS of the internal differential pair transistors of the pre-amplifier and preventing them from exiting the saturation region.

[0085] 3. Overall working process of the circuit and common-mode transient response mechanism:

[0086] as shown in Figure 3 , the specific response process of the present invention under a forward common-mode transient interference event is described in detail with reference to the waveform diagram:

[0087] When the common-mode transient interference starts (transient shock): the secondary-side ground potential VEE suddenly rises relative to the primary-side ground GND. Due to the blocking of the isolation capacitor Ciso, the voltage of the input node IN+ cannot keep up with the change of VEE. A voltage difference is generated across the resistor Rin+, which generates a current to charge the high-voltage capacitor.

[0088] At this time, the voltage of the V+ node starts to drop relative to VEE. Due to the drop of V+, the tail current source source potential Vs of the pre-amplifier will also drop accordingly (because MA1 and MA3 form an approximate source follower structure). When V+ < Vb1−Vth, MN4 in the pull-up clamping circuit is turned on. MN4 draws current from the power supply to charge the V+ node (pull-up).

[0089] When the common-mode transient interference persists (steady-state maintenance): the charging current for the high-voltage capacitor is mainly provided by the resistor Rin+. The voltage of the IN+ node continues to drop, and the voltage of the V+ node starts to attempt to recover.

[0090] At this time, MN4 in the pull-up circuit may still be in a weakly conducting or off state, and the circuit mainly relies on the charging and discharging characteristics of Rin and Cin to maintain energy balance.

[0091] When the common-mode transient interference ends (reverse overshoot): the current charging the high-voltage capacitor decreases to 0, but the IN+ node voltage has not fully recovered. At this time, the current through Rin+ changes direction and begins to charge the capacitor Cin+.

[0092] The voltages at the IN+ and V+ nodes rise instantaneously (overshoot). The rise in V+ causes Vs to rise accordingly. The overshoot voltage of V+ makes V+ > Vb1 + Vth, turning on MP3 in the pull-down clamping circuit. Current flows through MP3 and R5. The current flowing through MP3 creates a voltage drop across R5, raising the gate potential of MN6 and turning it on. Once MN6 is on, it discharges Vs to ground. On one hand, MP3 clamps the overshoot of V+; on the other hand, MN6 clamps the potential of Vs. This bidirectional clamping ensures that the input transistor and tail current source transistor of the preamplifier always operate in the saturation region, maintaining the linearity of the circuit.

[0093] In summary, by working in concert with the voltage bias circuit and the active clamping circuit, this invention effectively solves the problem of input common-mode level drift caused by common-mode transient interference in the prior art, and significantly improves the anti-interference capability of the capacitive isolation driver chip.

[0094] The present invention also provides a capacitive isolation driver chip, which internally includes a dynamic level clamping circuit and a preamplifier as described in the above embodiments to improve CMTI, wherein the dynamic level clamping circuit dynamically clamps at least the input of the preamplifier.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A dynamic level clamping circuit for improving CMTI, applied to the clamping protection of the preamplifier in a capacitive isolation driver IC, characterized in that: Includes voltage biasing circuit and active clamping circuit, wherein: The active clamping circuit includes a first clamping unit and a second clamping unit, both of which include a pull-up clamping circuit and a pull-down clamping circuit; The voltage bias circuit includes a reference bias branch, a reference level branch, and a high-pass filter module. The reference bias branch provides bias voltage to the pull-up clamping circuit and the pull-down clamping circuit in the first clamping unit and the second clamping unit. The bias voltage is used to control the clamping state switching of the pull-up clamping circuit and the pull-down clamping circuit. The reference level branch is used to generate a common-mode reference level that matches the bias voltage and provides it to the differential input of the preamplifier; The high-pass filter module is used to filter out low-frequency components in the signal transmitted to the input of the preamplifier and to superimpose the filtered signal with the common-mode reference level. The superimposed level provides bias for the pull-up clamping circuit and the pull-down clamping circuit in the first clamping unit and the second clamping unit, so that the first clamping unit and the second clamping unit do not enter the clamping state when there is no transient interference; when there is transient interference, the pull-up clamping circuit and the pull-down clamping circuit in the first clamping unit and the second clamping unit switch to enter the pull-up or pull-down clamping state. Both the first and second clamping units include a first pull-down clamping branch and a second pull-down clamping branch. The first pull-down clamping branch is used to pull down and clamp to protect the input terminal of the preamplifier, and the second pull-down clamping branch is used to pull down and clamp the far point of the common resistor or common equivalent resistor of the differential circuit in the preamplifier. When the first pull-down clamping branch pulls down and clamps, it triggers the clamping action of the second pull-down clamping branch, wherein: The first pull-down clamping branch includes a first pull-down MOSFET and a first pull-down resistor. The reference bias branch provides a gate bias voltage for the first pull-down MOSFET. The source of the first pull-down MOSFET is connected to the input terminal of the preamplifier, and the drain is connected to one end of the first pull-down resistor. The other end of the first pull-down resistor is grounded. The second pull-down clamping branch includes a second pull-down MOS transistor and a third pull-down MOS transistor. The source of the third pull-down MOS transistor is grounded, its gate is connected to the drain of the first pull-down MOS transistor, and its drain is connected to the source of the second pull-down MOS transistor and the source of the preamplifier tail current source transistor. The gate and source of the second pull-down MOSFET are shorted, and the drain is connected to the input of the preamplifier.

2. The dynamic level clamping circuit for improving CMTI as described in claim 1, characterized in that: The pull-up clamping circuit includes a first pull-up MOSFET and a second pull-up MOSFET; The reference bias branch provides a gate bias voltage for the second pull-up MOS transistor. The drain of the second pull-up MOS transistor is connected to the source of the first pull-up MOS transistor, and the source is connected to the source of the first pull-down MOS transistor, and they are all connected to the input terminal of the preamplifier. The drain of the first pull-up MOSFET is connected to the second power supply, and the gate is connected to the first power supply.

3. The dynamic level clamping circuit for improving CMTI as described in claim 1, characterized in that: The reference bias branch includes a first bias MOSFET, a second bias MOSFET, a first bias resistor, and a second bias resistor; The gate and drain of the first biased MOS transistor are connected, and the source is connected to the source of the second biased MOS transistor. The gate and drain of the second biased MOS transistor are connected, forming a diode connection structure. The first bias resistor is connected in series between the drain of the first bias MOSFET and the first power supply, and the second bias resistor is connected in series between the drain of the second bias MOSFET and the ground terminal.

4. The dynamic level clamping circuit for improving CMTI as described in claim 1, characterized in that: The reference bias branch provides a gate bias voltage for the reference level branch, and the reference level branch includes a first reference MOS transistor and a second reference MOS transistor; The source of the first reference MOSFET is connected to the source of the second reference MOSFET, the drain of the first reference MOSFET is connected to the first power supply, and the drain of the second reference MOSFET is grounded.

5. A dynamic level clamping circuit for improving CMTI as described in claim 3 or 4, characterized in that: The reference bias branch and the reference level branch also include a first capacitor and a second capacitor. The first capacitor is connected in parallel between the source of the first bias MOSFET and the ground line, and the second capacitor is connected in parallel between the source of the second reference MOSFET and the ground line, for filtering out high-frequency noise in the bias voltage.

6. A dynamic level clamping circuit for improving CMTI as described in claim 3 or 4, characterized in that: The drain of the first bias MOSFET is connected to the gate of the first reference MOSFET, and the drain of the second bias MOSFET is connected to the gate of the second reference MOSFET, providing gate bias voltage for the first reference MOSFET and the second reference MOSFET. Furthermore, the total channel width of the second bias MOSFET is set to twice the total channel width of the first bias MOSFET, and the total channel width of the second reference MOSFET is set to twice the total channel width of the first reference MOSFET, thereby making the common-mode reference level equal to the bias voltage and providing a stable DC operating point for the preamplifier.

7. The dynamic level clamping circuit for improving CMTI as described in claim 1, characterized in that: The high-pass filter module includes a first filter unit and a second filter unit with the same structure and symmetrical arrangement. Both the first filter unit and the second filter unit include a passive filter circuit. The passive filter circuit includes a high-pass filter capacitor, a first high-pass filter resistor, and a second high-pass filter resistor. The high-pass filter capacitor and the first high-pass filter resistor are connected in parallel. One end of the high-pass filter capacitor is connected to the pre-stage isolation capacitor to receive the first AC input signal, and the other end is connected to the input terminal of the preamplifier through the second high-pass filter resistor.

8. A capacitor-type isolated driver chip, characterized in that: The isolation driver chip internally includes a dynamic level clamping circuit and a preamplifier for improving CMTI as described in any one of claims 1-7, wherein the dynamic level clamping circuit dynamically clamps at least the input of the preamplifier.

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