An asynchronous reading circuit and method for ADC conversion results

Abstract

The application relates to the technical field of integrated circuit design, and particularly discloses an ADC conversion result asynchronous reading circuit and method, the reading circuit being one of structure one, structure two and structure three; the structure one shifts ADC data from an ADC clock domain to an interface clock domain through four groups of registers connected in sequence, and samples the ADC data in the interface clock domain multiple times; the structure two generates three different clocks by delaying the interface clock through three delay units, and drives three groups of parallel registers to delay sample the value in the ADC data latch; and the structure three generates two different clocks by delaying the interface clock through two delay units, drives two-stage series D flip-flops to sample an indication signal of the ADC data update, and synchronizes the indication signal to the interface clock domain. The application can read the value in the ADC data register through the interface at any time, and does not need to wait for an ADC data indication signal, thereby improving the data reading efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and specifically to an asynchronous reading circuit and method for ADC conversion results. Background Technology

[0002] An analog-to-digital converter (ADC) is an integrated circuit that quantizes continuous-time analog signals (such as voltage or current) into discrete digital codes (usually in binary form). As a crucial interface connecting the physical analog domain and the digital processing domain (such as MCUs, FPGAs, or processors), the ADC temporarily stores the conversion result in its internal data register after signal sampling and quantization. Digital master devices can access this register to read the converted data via a serial peripheral interface (such as SPI or I²C).

[0003] When the ADC chip finishes a conversion, it updates the data register with the new conversion result. The value in the data register remains unchanged until the next ADC conversion is completed. The register update process takes a very short time, typically on the order of sub-nanoseconds; during this period, the register output value is in an uncertain transient state.

[0004] Since the interface communication clock and the ADC internal sampling clock usually operate in the asynchronous clock domain, if a read operation is performed within the time window of the instant the ADC data register is updated, it may cause metastability problems, resulting in the interface capturing invalid or erroneous data.

[0005] The existing solution is to require a handshake or indication signal between the ADC and the digital interface to ensure stable reading of ADC data, which reduces the efficiency of data reading.

[0006] Based on this technical background, this invention studies an asynchronous reading circuit and method for ADC conversion results. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention proposes an asynchronous reading circuit and method for ADC conversion results. This reading circuit solves the problem of performing read operations at the instant the ADC data register is updated by storing and correcting multiple times. It can read the value in the ADC data register at any time through the interface without waiting for the ADC data indication signal, thus improving the efficiency of data reading.

[0008] To achieve the above objectives, the first aspect of the present invention provides an asynchronous reading circuit for ADC conversion results, wherein the reading circuit is any one of structure one, structure two, and structure three; The structure includes: an ADC data register, four sets of registers connected in series, a comparison and judgment unit, and a selector. The four sets of registers connected in series are used to shift the ADC data from the ADC clock domain to the interface clock domain and to sample the ADC data multiple times in the interface clock domain. The comparison and judgment unit is used to compare and determine which set of registers has collected the correct and latest ADC data. The selector is used to select the correct and latest ADC data for output based on the comparison and judgment result. The second structure includes: an ADC data register, an ADC data latch, three delay units, three sets of parallel registers, a comparison and judgment unit, and a selector. The three delay units are used to generate three different clocks for delaying the interface clock. The three different clocks are used to drive the three sets of parallel registers to perform delayed sampling of the values ​​in the ADC data latch. The comparison and judgment unit is used to compare and judge the values ​​of the three sets of parallel registers. The selector is used to select the ADC data output from the ADC data register or the ADC data latch based on the comparison and judgment result. The structure three includes: two sets of cascaded ADC data latches, two delay units, two stages of cascaded D flip-flops, a selector, and a TX register. The two delay units are used to delay the interface clock to generate two different clocks to drive the two stages of cascaded D flip-flops to sample the ADC data update indication signal, so that they are synchronized to the interface clock domain. The selector is used to select which set of ADC data latches to output data according to the signal issued by the subsequent D flip-flops. The TX register is used to latch the output data of the selector.

[0009] A second aspect of the present invention provides an asynchronous reading method for ADC conversion results performed in the above-described reading circuit, comprising: In Structure 1, four sets of registers connected in series are used to shift ADC data from the ADC clock domain to the interface clock domain, and the ADC data is sampled multiple times in the interface clock domain. After comparing and judging which set of registers has collected the correct and latest ADC data, the selector selects the output based on the comparison and judgment result. In structure two, three delay units are used to delay the interface clock to generate three different clocks. The three different clocks are used to drive three sets of parallel registers to delay the sampling of the values ​​in the ADC data latch. A comparison and judgment unit is used to compare and judge the values ​​of the three sets of parallel registers. The selector selects the output based on the comparison and judgment result. In structure 3, two delay units are used to delay the interface clock to generate two different clocks, which drive two cascaded D flip-flops to sample the ADC data update indication signal and synchronize it to the interface clock domain. The selector selects which ADC data latch to output based on the signal from the subsequent D flip-flop, and the selector output data is latched and output through the TX register.

[0010] The beneficial effects of this invention include: (1) The asynchronous reading circuit for ADC conversion results proposed in this invention solves the problem of performing a read operation at the moment the ADC data register is updated by storing and correcting multiple times. It can read the value in the ADC data register at any time through the interface without waiting for the ADC data indication signal, thus improving the efficiency of data reading.

[0011] (2) The asynchronous reading circuit for ADC conversion results proposed in this invention uses four sets of registers to shift and store ADC data in structure one. It determines which set of registers the correct ADC data is stored in based on the comparison results of the data in the second to fourth register sets. It adopts the classic multi-level register synchronization chain (synchronizer) structure to effectively suppress metastability propagation and capture stable data values.

[0012] (3) The asynchronous reading circuit for ADC conversion results proposed in this invention generates three clocks after the interface clock SCLK passes through three delay units in structure two: SCLK0, SCLK1, and SCLK2. The delayed clocks are used to drive the first register group, the second register group, and the third register group to sample the values ​​in the ADC latch register, which effectively improves the data reading efficiency and accuracy.

[0013] (4) The asynchronous reading circuit for ADC conversion results proposed in this invention uses two-stage ADC data latches in structure three. By setting a certain phase difference between the indicator signal and the first latch register and the second latch register, it is ensured that the indicator signal does not change at the same time as the first latch register and the second latch register. At the same time, the SCLK synchronous indicator signal generated by the delay is used to determine the latching object of the TX register, so that the interface latches ADC data to avoid the ADC data update time, thereby ensuring that the interface latches stable ADC data.

[0014] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0015] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0016] Figure 1 This is a schematic diagram of a specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0017] Figure 2 This is a schematic diagram of the overall timing of multiple samplings of ADC data in the interface clock domain in a specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0018] Figure 3 This is a timing diagram illustrating the first case of multiple sampling of ADC data in the interface clock domain in a specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0019] Figure 4 This is a timing diagram illustrating the second case of multiple sampling of ADC data in the interface clock domain, as a specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0020] Figure 5 This is a timing diagram illustrating the third case of multiple sampling of ADC data in the interface clock domain, as a specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0021] Figure 6 This is a timing diagram illustrating the fourth case of multiple sampling of ADC data in the interface clock domain, as part of a specific implementation of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0022] Figure 7 This is a schematic diagram of another specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0023] Figure 8 This is a timing diagram of ADC data reading in another specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0024] Figure 9 This is a schematic diagram of the third specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0025] Figure 10 This is a timing diagram of ADC data reading in the third specific embodiment of the asynchronous reading circuit for ADC conversion results proposed in this invention.

[0026] Explanation of reference numerals in the attached figures: ADC_DATA - ADC data, ADC_CLK - ADC clock, SCLK - interface clock, SCLK0, SCLK1 and SCLK2 - delay clock, ADC_DATA_UPT - indication signal for ADC data update, DATA_UPT_SCLK - indication signal for ADC data update in the interface clock domain, DATA n-1 - the (n-1)th data, DATA n - the nth data, DATA n+1 - the (n+1)th data, DATA n+2 - the (n+2)th data, DATA m - the mth data, DATA m+1 - the (m+1)th data, T1, T2 and T3 - sampling times. Detailed Implementation

[0027] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0028] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its normal operating state, while "inner" and "outer" refer to their position relative to the device's outline. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] This invention provides an asynchronous reading circuit for ADC conversion results, wherein the reading circuit is any one of structure one, structure two, and structure three; Structure 1 includes: an ADC data register, four sets of registers connected in series, a comparator and a selector. The four sets of registers connected in series are used to shift the ADC data from the ADC clock domain to the interface clock domain and to sample the ADC data multiple times in the interface clock domain. The comparator is used to compare and determine which set of registers has acquired the correct and latest ADC data. The selector is used to select the correct and latest ADC data for output based on the comparison result. Structure 2 includes: an ADC data register, an ADC data latch, three delay units, three sets of parallel registers, a comparator, and a selector. The three delay units are used to generate three different clocks for delaying the interface clock. The three different clocks are used to drive the three sets of parallel registers to perform delayed sampling of the values ​​in the ADC data latch. The comparator is used to compare and judge the values ​​of the three sets of parallel registers. The selector is used to select the ADC data output from the ADC data register or the ADC data latch based on the comparison and judgment result. Structure 3 includes: two sets of cascaded ADC data latches, two delay units, two stages of cascaded D flip-flops, a selector, and a TX register. The two delay units are used to delay the interface clock to generate two different clocks to drive the two stages of cascaded D flip-flops to sample the ADC data update indication signal, so that it is synchronized to the interface clock domain. The selector is used to select which set of ADC data latches to output data according to the signal issued by the subsequent D flip-flops. The TX register is used to latch the output data of the selector.

[0030] In this invention, the problem of performing a read operation at the instant of updating the ADC data register is solved by storing and correcting the data multiple times. This allows the value in the ADC data register to be read at any time through the interface without waiting for the ADC data indication signal, thus improving the efficiency of data reading.

[0031] According to the present invention, such as Figure 1 As shown, in structure one, the data input port of the ADC data register is electrically connected to the data output interface of the ADC, and the clock input port is electrically connected to the clock of the ADC. The four sets of registers connected in series include the first register set, the second register set, the third register set, and the fourth register set. The clock input ports of the first register set, the second register set, the third register set, and the fourth register set are simultaneously electrically connected to the interface clock. The data input port of the first register set is electrically connected to the data output interface of the ADC data register. The data output interface is sequentially electrically connected to the data input ports of the second register set, the third register set, and the fourth register set. The data output interfaces of the second register set, the third register set, and the fourth register set are simultaneously electrically connected to the data input ports of the comparator and the selector. The output port of the comparator is electrically connected to the selection input port of the selector.

[0032] According to the present invention, such as Figure 2-6 As shown, the ADC data reading process in Structure 1 includes: The ADC data is shifted from the first register group to the fourth register group using the interface clock. The data in the first register group is the first stage of cross-clock domain synchronization and is not used. The values ​​of the ADC data register at three different times are stored in the second to fourth register groups respectively. The corresponding times are denoted as T3, T2, and T1. The ADC data at time T3 is stored in the fourth register group, the ADC data at time T2 is stored in the third register group, and the ADC data at time T1 is stored in the second register group. If the ADC data does not change during the three shifts, the data in the second register group to the fourth register group is exactly the same and is all correct ADC data. Use the selector to select any set of data from the second register group to the fourth register group for output. When the ADC data is being updated at time T1, or when the ADC data is being updated between T2 and T1, if the data in the third and fourth register groups are equal after the shift, but not equal to the data in the second register group, then the data in the second register group is either incorrect or new ADC data, while the data in the third or fourth register group is correct ADC data. The selector is used to select data from the third or fourth register group for output. When the ADC data is updated at time T2, or when the ADC data is updated between T2 and T3, the data in the second, third, and fourth register groups are not equal after the shift. The data in the third register group is incorrect, while the data in the second and fourth register groups is correct. The data in the second register group is the latest ADC data. The selector is used to select the data in the second register group for output. When the ADC data is being updated at time T3, or when the ADC data is being updated between T3 and T2, if the data in the third register group and the second register group are equal after the shift, but not equal to the data in the fourth register group, then the data in the fourth register group is incorrect or old ADC data, while the data in the third register group and the second register group is correct and the latest ADC data. The selector is used to select data from the second register group or the third register group for output.

[0033] In this invention, four sets of registers are used in structure one to shift and store ADC data. The correct ADC data is stored in which register based on the comparison results of the data in the second to fourth register sets. The classic multi-level register synchronization chain (synchronizer) structure is adopted to effectively suppress metastability propagation and capture stable data values.

[0034] According to the present invention, such as Figure 7 As shown, in structure two, the clock input ports of the ADC data register and the ADC data latch are both electrically connected to the clock of the ADC, the data input port of the ADC data register is electrically connected to the data output interface of the ADC, and the data output port is electrically connected to the data input port of the ADC data latch. The three delay units include a first delay unit, a second delay unit, and a third delay unit, which are connected in series. The input port of the first delay unit is electrically connected to the interface clock. The three parallel register groups include a first register group, a second register group, and a third register group. The data input ports of the first register group, the second register group, and the third register group are all electrically connected to the data output ports of the ADC data latch. The data output ports are all electrically connected to the input ports of the comparator. The clock input port of the first register group is electrically connected to the output port of the first delay unit. The clock input port of the second register group is electrically connected to the output port of the second delay unit. The clock input port of the third register group is electrically connected to the output port of the third delay unit. The selector's data input ports are electrically connected to the data output ports of the ADC data register and the ADC data latch, respectively, and the selection input / output ports are electrically connected to the output port of the comparator.

[0035] According to the present invention, such as Figure 8 As shown, the ADC data reading process in Structure 2 includes: The interface clock generates three clocks: SCLK0, SCLK1, and SCLK2 after passing through the first delay unit, the second delay unit, and the third delay unit. SCLK0, SCLK1, and SCLK2 are used to drive the first register group, the second register group, and the third register group respectively to sample the values ​​in the ADC data latch; The values ​​of the first register group, the second register group, and the third register group are compared using a comparator; If the values ​​of the three registers are equal, the ADC data is in a stable state, and the value in the ADC data latch is selected for output. If the values ​​of the three registers are not equal, the ADC data is in an update state, and the value in the ADC register is selected for output.

[0036] In this invention, the interface clock SCLK in structure two generates three clocks after passing through three delay units: SCLK0, SCLK1, and SCLK2. The delayed clocks are used to drive the first register group, the second register group, and the third register group to sample the values ​​in the ADC latch register, which effectively improves the data reading efficiency and accuracy.

[0037] According to the present invention, such as Figure 9As shown, in structure three, the two sets of cascaded ADC data latches include a first ADC data latch and a second ADC data latch. The clock input ports of both the first and second ADC data latches are electrically connected to the clock of the ADC. The data input port of the first ADC data latch is electrically connected to the data output interface of the ADC, and the data output port is electrically connected to the data input port of the second ADC data latch. The two delay units include a first delay unit and a second delay unit, which are connected in series. The input port of the first delay unit is electrically connected to the interface clock. The two-stage cascaded D flip-flops include a first D flip-flop and a second D flip-flop. The data input port of the first D flip-flop is electrically connected to the indicator signal for ADC data update, and the clock input port is electrically connected to the interface clock. The data input port of the second D flip-flop is electrically connected to the data output port of the first D flip-flop, and the clock input port is electrically connected to the output port of the first delay unit. The selector's data input port is electrically connected to the data output ports of the first ADC data latch and the second ADC data latch, respectively, and the select input port is electrically connected to the data output port of the second D flip-flop. The data input port of the TX register is electrically connected to the data output port of the selector, and the clock input port is electrically connected to the output port of the second delay unit. like Figure 10 As shown, the ADC data reading process in Structure 3 includes: The ADC data is latched in two stages using the first ADC data latch and the second ADC data latch. The indicator signal for ADC data update is set to indicate the ADC data from the first ADC data latch to the second ADC data latch, and there is a phase difference between this indicator signal and the signal from the first ADC data latch to the second ADC data latch, so as to ensure that the indicator signal and the signal from the first ADC data latch to the second ADC data latch do not change at the same time. The interface clock generates two clocks, SCLK0 and SCLK1, after passing through the first and second delay units. The ADC data update indication signal is generated in the interface clock domain after being synchronized with SCLK and SCLK0. The TX register selects the latched ADC data based on the indicator signal of ADC data update in the interface clock domain. If it is high, it latches the data output in the first ADC data latch; otherwise, it selects the data output in the second ADC data latch. By using two-level ADC data latching and update indicators, the interface latches ADC data to avoid the ADC data update time, thereby ensuring that the interface latches stable ADC data.

[0038] In this invention, a two-stage ADC data latch is used in structure three. By setting a certain phase difference between the indicator signal and both the first latch register and the second latch register, it is ensured that the indicator signal does not change at the same time as the first latch register and the second latch register. At the same time, the SCLK synchronous indicator signal generated by the delay is used to determine the latching object of the TX register, so that the interface latches ADC data to avoid the ADC data update time, thereby ensuring that the interface latches stable ADC data.

[0039] The present invention also provides an asynchronous reading method for ADC conversion results performed in the above-described reading circuit, comprising: In Structure 1, four sets of registers connected in series are used to shift ADC data from the ADC clock domain to the interface clock domain, and the ADC data is sampled multiple times in the interface clock domain. After comparing and judging which set of registers has collected the correct and latest ADC data, the selector selects the output based on the comparison and judgment result. In structure two, three delay units are used to delay the interface clock to generate three different clocks. The three different clocks are used to drive three sets of parallel registers to delay the sampling of the values ​​in the ADC data latch. A comparison and judgment unit is used to compare and judge the values ​​of the three sets of parallel registers. The selector selects the output based on the comparison and judgment result. In structure 3, two delay units are used to delay the interface clock to generate two different clocks, which drive two cascaded D flip-flops to sample the ADC data update indication signal and synchronize it to the interface clock domain. The selector selects which ADC data latch to output based on the signal from the subsequent D flip-flop, and the selector output data is latched and output through the TX register.

[0040] According to the present invention, in structure one, four sets of registers connected in series are used to shift ADC data from the ADC clock domain to the interface clock domain, and the ADC data is sampled multiple times in the interface clock domain. After comparing and determining which set of registers has acquired the correct and latest ADC data, the selector selects the output based on the comparison result, including: The ADC data is shifted from the first register group to the fourth register group using the interface clock. The data in the first register group is the first stage of cross-clock domain synchronization and is not used. The values ​​of the ADC data register at three different times are stored in the second to fourth register groups respectively. The corresponding times are denoted as T3, T2, and T1. The ADC data at time T3 is stored in the fourth register group, the ADC data at time T2 is stored in the third register group, and the ADC data at time T1 is stored in the second register group. If the ADC data does not change during the three shifts, the data in the second register group to the fourth register group is exactly the same and is all correct ADC data. Use the selector to select any set of data from the second register group to the fourth register group for output. When the ADC data is being updated at time T1, or when the ADC data is being updated between T2 and T1, if the data in the third and fourth register groups are equal after the shift, but not equal to the data in the second register group, then the data in the second register group is either incorrect or new ADC data, while the data in the third or fourth register group is correct ADC data. The selector is used to select data from the third or fourth register group for output. When the ADC data is updated at time T2, or when the ADC data is updated between T2 and T3, the data in the second, third, and fourth register groups are not equal after the shift. The data in the third register group is incorrect, while the data in the second and fourth register groups is correct. The data in the second register group is the latest ADC data. The selector is used to select the data in the second register group for output. When the ADC data is being updated at time T3, or when the ADC data is being updated between T3 and T2, if the data in the third register group and the second register group are equal after the shift, but not equal to the data in the fourth register group, then the data in the fourth register group is incorrect or old ADC data, while the data in the third register group and the second register group is correct and the latest ADC data. The selector is used to select data from the second register group or the third register group for output.

[0041] According to the present invention, in structure two, three delay units are used to generate three different clocks for delaying the interface clock. These three different clocks are used to drive three sets of parallel registers to perform delayed sampling of the values ​​in the ADC data latch. A comparison and judgment unit compares and judges the values ​​of the three sets of parallel registers, and a selector selects the output based on the comparison and judgment result. The interface clock generates three clocks: SCLK0, SCLK1, and SCLK2 after passing through the first delay unit, the second delay unit, and the third delay unit. SCLK0, SCLK1, and SCLK2 are used to drive the first register group, the second register group, and the third register group respectively to sample the values ​​in the ADC data latch; The values ​​of the first register group, the second register group, and the third register group are compared using a comparator; If the values ​​of the three registers are equal, the ADC data is in a stable state, and the value in the ADC data latch is selected for output. If the values ​​of the three registers are not equal, the ADC data is in an update state, and the value in the ADC register is selected for output.

[0042] According to the present invention, in structure three, two delay units are used to delay the interface clock to generate two different clocks, which respectively drive two cascaded D flip-flops to sample the ADC data update indication signal, synchronizing it to the interface clock domain. A selector selects which ADC data latch to output based on the signal from the subsequent D flip-flop, and the selector output data is latched and output through the TX register, including: The ADC data is latched in two stages using the first ADC data latch and the second ADC data latch. The indicator signal for ADC data update is set to indicate the ADC data from the first ADC data latch to the second ADC data latch, and there is a phase difference between this indicator signal and the signal from the first ADC data latch to the second ADC data latch, so as to ensure that the indicator signal and the signal from the first ADC data latch to the second ADC data latch do not change at the same time. The interface clock generates two clocks, SCLK0 and SCLK1, after passing through the first and second delay units. The ADC data update indication signal is generated in the interface clock domain after being synchronized with SCLK and SCLK0. The TX register selects the latched ADC data based on the indicator signal of ADC data update in the interface clock domain. If it is high, it latches the data output in the first ADC data latch; otherwise, it selects the data output in the second ADC data latch. By using two-level ADC data latching and update indicators, the interface latches ADC data to avoid the ADC data update time, thereby ensuring that the interface latches stable ADC data.

[0043] The present invention will now be described in more detail through specific embodiments.

[0044] Example 1

[0045] like Figure 1As shown, this embodiment provides an asynchronous reading circuit for ADC conversion results. The basic circuit structure includes a first register group, a second register group, a third register group, a fourth register group, a comparator, and a selector. The first to fourth register groups realize the transfer and shifting of ADC data from the ADC clock domain (ADC CLK) to the interface clock domain (SCLK), enabling multiple sampling of ADC data in the interface clock domain (SCLK). The comparator determines which register group contains the correct and latest ADC data by comparing the data stored in the second to fourth register groups. The selector selects the correct and latest ADC data for output based on the comparison result.

[0046] This embodiment provides a method for asynchronously reading ADC conversion results, the specific principle of which includes: When the ADC chip finishes conversion, it updates the ADC data register with the new conversion result. The value in the ADC data register remains unchanged until the next ADC conversion is completed. The ADC register update process is extremely short, typically on the order of sub-nanoseconds. During this period, the ADC register output value is in an uncertain transient state. If the interface performs a read operation within this time window, it may latch an incorrect value. This embodiment employs a multi-cycle sampling and value comparison mechanism, continuously reading the ADC data register multiple times through the interface and performing consistency checks on the continuous read results. This ensures that the obtained data is both a valid stable value and the latest conversion result. This method aims to mitigate the metastability risk caused by asynchronous reading across clock domains from a hardware perspective, ensuring the reliability of data transmission. In this embodiment, to safely read the ADC data register under the asynchronous clock domain, a classic multi-level register synchronization chain (synchronizer) structure is adopted to suppress metastability propagation and capture stable data values. When the interface reads ADC data, it uses the interface's clock to sample the ADC data register four times and shifts the data sequentially into the interface register group; for example... Figure 1 As shown, the interface clock is used to shift the ADC data into the first register group to the fourth register group. The data in the first register group is the first stage of cross-clock domain synchronization and cannot be directly used. The second to fourth register groups store the values ​​of the ADC data registers at three different times, denoted as T3, T2, and T1 respectively. The ADC data at time T3 is ultimately stored in the fourth register group, the ADC data at time T2 is ultimately stored in the third register group, and the ADC data at time T1 is ultimately stored in the second register group. Figure 2 As shown; When reading data at times T3, T2, and T1, the following situations may occur: Scenario 1: If the ADC data remains unchanged during the three shifts, then the data in the second to fourth register groups are exactly the same, all being correct ADC data. The selector then selects any one set of data from the second to fourth register groups for output, such as... Figure 3 As shown; Scenario 2: At time T1, the ADC data is being updated, or the ADC data is being updated between T2 and T1; after the shift, the data in the third and fourth register groups are equal, but not equal to the data in the second register group; the second register group contains incorrect data, or new ADC data, while the third or fourth register group contains correct ADC data; in this case, data is selected from the third or fourth register group for output, such as... Figure 4 As shown; Scenario 3: The ADC data is updated at time T2, or between T2 and T3. After the shift, the data in the second, third, and fourth register groups are equal, the third register group contains incorrect data, and the second and third register groups contain correct ADC data, but the second register group contains the latest ADC data. In this case, the data from the second register group is selected for output, such as... Figure 5 As shown; Scenario 4: The ADC updates data at time T3, or between T3 and T2. After the shift, the data in the third and second register groups are equal, but not equal to the data in the fourth register group. The fourth register group contains incorrect or old ADC data, while the data in the third and second register groups is the correct and latest ADC data. In this case, data is selected from the second register group for output, such as... Figure 6 As shown.

[0047] Example 2

[0048] like Figure 7 As shown, this embodiment provides an asynchronous reading circuit for ADC conversion results, including: an ADC data register, an ADC data latch, three delay units, three sets of parallel registers, a comparison and judgment unit, and a selector; The clock input ports of the ADC data register and the ADC data latch are both electrically connected to the ADC clock. The data input port of the ADC data register is electrically connected to the ADC data output interface, and the data output port is electrically connected to the data input port of the ADC data latch. The three delay units include a first delay unit, a second delay unit, and a third delay unit, which are connected in series. The input port of the first delay unit is electrically connected to the interface clock. The three parallel register groups include a first register group, a second register group, and a third register group. The data input ports of the first register group, the second register group, and the third register group are all electrically connected to the data output ports of the ADC data latch. The data output ports are all electrically connected to the input ports of the comparator. The clock input port of the first register group is electrically connected to the output port of the first delay unit. The clock input port of the second register group is electrically connected to the output port of the second delay unit. The clock input port of the third register group is electrically connected to the output port of the third delay unit. The selector's data input ports are electrically connected to the data output ports of the ADC data register and the ADC data latch, respectively, and the selection input / output ports are electrically connected to the output port of the comparator.

[0049] This embodiment provides a method for asynchronously reading ADC conversion results, specifically including: The interface clock SCLK generates three clocks after three delay units: SCLK0, SCLK1, and SCLK2. These delayed clocks drive the first, second, and third register groups respectively to sample the values ​​in the ADC latch register. The comparator compares the values ​​in the first, second, and third register groups. If the values ​​in the three register groups are equal, it indicates that the ADC data is in a stable state and can be used, and the value in the ADC data latch is selected for output. If the values ​​in the three register groups are not equal, it indicates that the ADC data is in an update state, and the value in the ADC register is selected for output. like Figure 8 As shown, when SCLK0 drives the first register group for sampling, the value in the ADC data latch has not yet changed, and the first register group samples the result of the nth conversion. When SCLK1 drives the second register group for sampling, the value in the ADC data latch is changing, and the second register group samples abnormal data. When SCLK2 drives the third register group for sampling, the value in the ADC data latch has been updated to the new data and has been documented, showing the result of the (n+1)th conversion of the register group. The comparator comparison results show that the values ​​in the first, second, and third register groups are different, so the value in the ADC data register is selected for output.

[0050] Example 3

[0051] like Figure 9 As shown, this embodiment provides an asynchronous reading circuit for ADC conversion results, including: two sets of cascaded ADC data latches, two delay units, two stages of cascaded D flip-flops, a selector, and a TX register; The two sets of cascaded ADC data latches include a first ADC data latch and a second ADC data latch. The clock input ports of both the first and second ADC data latches are electrically connected to the clock of the ADC. The data input port of the first ADC data latch is electrically connected to the data output interface of the ADC, and the data output port is electrically connected to the data input port of the second ADC data latch. The two delay units include a first delay unit and a second delay unit, which are connected in series. The input port of the first delay unit is electrically connected to the interface clock. The two-stage cascaded D flip-flops include a first D flip-flop and a second D flip-flop. The data input port of the first D flip-flop is electrically connected to the indicator signal for ADC data update, and the clock input port is electrically connected to the interface clock. The data input port of the second D flip-flop is electrically connected to the data output port of the first D flip-flop, and the clock input port is electrically connected to the output port of the first delay unit. The selector's data input port is electrically connected to the data output ports of the first ADC data latch and the second ADC data latch, respectively, and the select input port is electrically connected to the data output port of the second D flip-flop. The data input port of the TX register is electrically connected to the data output port of the selector, and the clock input port is electrically connected to the output port of the second delay unit.

[0052] This embodiment provides a method for asynchronously reading ADC conversion results, specifically including: The interface clock SCLK generates two clocks, SCLK1 and SCLK2, after passing through two delay units. SCLK and SCLK1 respectively drive two-stage D flip-flops in series to sample the ADC DATA update indication signal (ADC_DATA_UPT), synchronizing it to the SCLK clock domain. The transmit register (TX register) latches the first latched data of the ADC according to the synchronized ADC DATA update indication signal. like Figure 10As shown, the first and second ADC data latches are ADC clock domain registers, representing the result of two latching operations on the ADC data. ADC_DATA_UPT is an indication signal indicating that the ADC data is being latched from the first ADC data latch to the second ADC data latch. This indication signal has a certain phase difference with both the first and second ADC data latches to ensure that they do not change at the same time. After synchronization with SCLK and SCLK0, the indication signal generates the DATA_UPT_SCLK signal in the SCLK clock domain. The TX register selects the ADC data to latch based on DATA_UPT_SCLK. If DATA_UPT_SCLK is high, the data from the first ADC data latch is latched and output; otherwise, the value from the second ADC data latch is selected and output. This two-stage latching and update indication of the ADC data ensures that the interface latches stable ADC data, avoiding the ADC data update time.

[0053] The asynchronous reading circuit for ADC conversion results proposed in the embodiments of the present invention solves the problem of performing a read operation at the moment the ADC data register is updated by storing and correcting multiple times. It can read the value in the ADC data register at any time through the interface without waiting for the ADC data indication signal, thus improving the efficiency of data reading.

[0054] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. An asynchronous reading circuit for ADC conversion results, characterized in that, The reading circuit can be any one of structure one, structure two, and structure three; The structure includes: an ADC data register, four sets of registers connected in series, a comparison and judgment unit, and a selector. The four sets of registers connected in series are used to shift the ADC data from the ADC clock domain to the interface clock domain and to sample the ADC data multiple times in the interface clock domain. The comparison and judgment unit is used to compare and determine which set of registers has collected the correct and latest ADC data. The selector is used to select the correct and latest ADC data for output based on the comparison and judgment result. The second structure includes: an ADC data register, an ADC data latch, three delay units, three sets of parallel registers, a comparison and judgment unit, and a selector. The three delay units are used to generate three different clocks for delaying the interface clock. The three different clocks are used to drive the three sets of parallel registers to perform delayed sampling of the values ​​in the ADC data latch. The comparison and judgment unit is used to compare and judge the values ​​of the three sets of parallel registers. The selector is used to select the ADC data output from the ADC data register or the ADC data latch based on the comparison and judgment result. The structure three includes: two sets of cascaded ADC data latches, two delay units, two stages of cascaded D flip-flops, a selector, and a TX register. The two delay units are used to delay the interface clock to generate two different clocks to drive the two stages of cascaded D flip-flops to sample the ADC data update indication signal, so that they are synchronized to the interface clock domain. The selector is used to select which set of ADC data latches to output data according to the signal issued by the subsequent D flip-flop. The TX register is used to latch the output data of the selector. In the first structure, the data input port of the ADC data register is electrically connected to the data output interface of the ADC, and the clock input port is electrically connected to the clock of the ADC. The four sets of registers connected in series include a first register set, a second register set, a third register set, and a fourth register set. The clock input ports of the first register set, the second register set, the third register set, and the fourth register set are simultaneously electrically connected to the interface clock. The data input port of the first register set is electrically connected to the data output interface of the ADC data register. The data output interface is sequentially electrically connected to the data input ports of the second register set, the third register set, and the fourth register set. The data output interfaces of the second register set, the third register set, and the fourth register set are simultaneously electrically connected to the data input ports of the comparator and the selector. The output port of the comparator is electrically connected to the selection input port of the selector. In the second structure, the clock input ports of the ADC data register and the ADC data latch are both electrically connected to the clock of the ADC, the data input port of the ADC data register is electrically connected to the data output interface of the ADC, and the data output port is electrically connected to the data input port of the ADC data latch. The three delay units include a first delay unit, a second delay unit, and a third delay unit, which are connected in series. The input port of the first delay unit is electrically connected to the interface clock. The three sets of parallel registers include a first register set, a second register set, and a third register set. The data input ports of the first register set, the second register set, and the third register set are all electrically connected to the data output port of the ADC data latch, and the data output ports are all electrically connected to the input port of the comparator. The clock input port of the first register set is electrically connected to the output port of the first delay unit, the clock input port of the second register set is electrically connected to the output port of the second delay unit, and the clock input port of the third register set is electrically connected to the output port of the third delay unit. The data input port of the selector is electrically connected to the data output ports of the ADC data register and the ADC data latch, respectively, and the selection input / output port is electrically connected to the output port of the comparison and judgment unit. In the third structure, the two sets of cascaded ADC data latches include a first ADC data latch and a second ADC data latch. The clock input ports of the first ADC data latch and the second ADC data latch are both electrically connected to the clock of the ADC. The data input port of the first ADC data latch is electrically connected to the data output interface of the ADC, and the data output port is electrically connected to the data input port of the second ADC data latch. The two delay units include a first delay unit and a second delay unit, which are connected in series. The input port of the first delay unit is electrically connected to the interface clock. The two-stage cascaded D flip-flops include a first D flip-flop and a second D flip-flop. The data input port of the first D flip-flop is electrically connected to the indicator signal for ADC data update, and the clock input port is electrically connected to the interface clock. The data input port of the second D flip-flop is electrically connected to the data output port of the first D flip-flop, and the clock input port is electrically connected to the output port of the first delay unit. The data input port of the selector is electrically connected to the data output ports of the first ADC data latch and the second ADC data latch, respectively, and the selection input port is electrically connected to the data output port of the second D flip-flop. The data input port of the TX register is electrically connected to the data output port of the selector, and the clock input port is electrically connected to the output port of the second delay unit.

2. The reading circuit according to claim 1, characterized in that, The ADC data reading process in Structure 1 includes: The ADC data is shifted from the first register group to the fourth register group using the interface clock. The data in the first register group is the first stage of cross-clock domain synchronization and is not used. The values ​​of the ADC data register at three different times are stored in the second to fourth register groups respectively. The corresponding times are denoted as T3, T2, and T1. The ADC data at time T3 is stored in the fourth register group, the ADC data at time T2 is stored in the third register group, and the ADC data at time T1 is stored in the second register group. If the ADC data does not change during the three shifts, the data in the second register group to the fourth register group is exactly the same and is all correct ADC data. The selector can be used to select any set of data from the second register group to the fourth register group for output. When the ADC data is being updated at time T1, or when the ADC data is being updated between T2 and T1, if the data in the third and fourth register groups are equal after shifting, but not equal to the data in the second register group, then the data in the second register group is either incorrect or new ADC data, and the data in the third or fourth register group is correct ADC data. The selector is used to select data from the third or fourth register group for output. When the ADC data is updated at time T2, or when the ADC data is updated between T2 and T3, the data in the second, third, and fourth register groups are not equal after the shift. In this case, the data in the third register group is incorrect, while the data in the second and fourth register groups is correct. The data in the second register group is the latest ADC data. The selector is used to select the data in the second register group for output. When the ADC data is being updated at time T3, or when the ADC data is being updated between T3 and T2, if the data in the third register group and the second register group are equal after shifting, but not equal to the data in the fourth register group, then the data in the fourth register group is incorrect or old ADC data, and the data in the third register group and the second register group is correct and the latest ADC data. The selector is used to select data from the second register group or the third register group for output.

3. The reading circuit according to claim 1, characterized in that, The ADC data reading process in Structure 2 includes: The interface clock generates three clocks: SCLK0, SCLK1, and SCLK2 after passing through the first delay unit, the second delay unit, and the third delay unit. SCLK0, SCLK1, and SCLK2 are used to drive the first register group, the second register group, and the third register group respectively to sample the values ​​in the ADC data latch; The values ​​of the first register group, the second register group, and the third register group are compared using a comparator; If the values ​​of the three registers are equal, the ADC data is in a stable state, and the value in the ADC data latch is selected for output. If the values ​​of the three registers are not equal, the ADC data is in an update state, and the value in the ADC register is selected for output.

4. The reading circuit according to claim 1, characterized in that, The ADC data reading process in Structure 3 includes: The ADC data is latched in two stages using the first ADC data latch and the second ADC data latch. The indicator signal for ADC data update is set as the indicator signal for ADC data from the first ADC data latch to the second ADC data latch, and there is a phase difference between the indicator signal and the signal from the first ADC data latch to the second ADC data latch, so as to ensure that the indicator signal and the signal from the first ADC data latch to the second ADC data latch do not change at the same time. The interface clock generates two clocks, SCLK0 and SCLK1, through the first delay unit and the second delay unit; The ADC data update indication signal is generated in the interface clock domain after being synchronized with SCLK and SCLK0. The TX register selects the latched ADC data according to the indication signal of ADC data update in the interface clock domain. If it is high, the data output in the first ADC data latch is latched; otherwise, the data output of the second ADC data latch is selected. By using two-level ADC data latching and update indicators, the interface latches ADC data to avoid the ADC data update time, thereby ensuring that the interface latches stable ADC data.

5. An asynchronous reading method for ADC conversion results performed in the reading circuit according to any one of claims 1-4, characterized in that, include: In Structure 1, four sets of registers connected in series are used to shift ADC data from the ADC clock domain to the interface clock domain, and the ADC data is sampled multiple times in the interface clock domain. After comparing and judging which set of registers has collected the correct and latest ADC data, the selector selects the output based on the comparison and judgment result. In structure two, three delay units are used to delay the interface clock to generate three different clocks. The three different clocks are used to drive three sets of parallel registers to delay the sampling of the values ​​in the ADC data latch. A comparison and judgment unit is used to compare and judge the values ​​of the three sets of parallel registers. The selector selects the output based on the comparison and judgment result. In structure 3, two delay units are used to delay the interface clock to generate two different clocks, which drive two cascaded D flip-flops to sample the ADC data update indication signal and synchronize it to the interface clock domain. The selector selects which ADC data latch to output based on the signal from the subsequent D flip-flop, and the selector output data is latched and output through the TX register.

6. The reading method according to claim 5, characterized in that, In Structure 1, four sets of registers connected in series are used to shift ADC data from the ADC clock domain to the interface clock domain. Multiple samples of the ADC data are taken in the interface clock domain. A comparator determines which set of registers has acquired the correct and latest ADC data. A selector then selects the output based on the comparison result, including: The ADC data is shifted from the first register group to the fourth register group using the interface clock. The data in the first register group is the first stage of cross-clock domain synchronization and is not used. The values ​​of the ADC data register at three different times are stored in the second to fourth register groups respectively. The corresponding times are denoted as T3, T2, and T1. The ADC data at time T3 is stored in the fourth register group, the ADC data at time T2 is stored in the third register group, and the ADC data at time T1 is stored in the second register group. If the ADC data does not change during the three shifts, the data in the second register group to the fourth register group is exactly the same and is all correct ADC data. The selector can be used to select any set of data from the second register group to the fourth register group for output. When the ADC data is being updated at time T1, or when the ADC data is being updated between T2 and T1, if the data in the third and fourth register groups are equal after shifting, but not equal to the data in the second register group, then the data in the second register group is either incorrect or new ADC data, and the data in the third or fourth register group is correct ADC data. The selector is used to select data from the third or fourth register group for output. When the ADC data is updated at time T2, or when the ADC data is updated between T2 and T3, the data in the second, third, and fourth register groups are not equal after the shift. In this case, the data in the third register group is incorrect, while the data in the second and fourth register groups is correct. The data in the second register group is the latest ADC data. The selector is used to select the data in the second register group for output. When the ADC data is being updated at time T3, or when the ADC data is being updated between T3 and T2, if the data in the third register group and the second register group are equal after shifting, but not equal to the data in the fourth register group, then the data in the fourth register group is incorrect or old ADC data, and the data in the third register group and the second register group is correct and the latest ADC data. The selector is used to select data from the second register group or the third register group for output.

7. The reading method according to claim 5, characterized in that, In Structure 2, three delay units are used to generate three different clocks by delaying the interface clock. These three different clocks drive three sets of parallel registers to perform delayed sampling of the values ​​in the ADC data latch. A comparator compares the values ​​of the three sets of parallel registers, and a selector selects the output based on the comparison result. The interface clock generates three clocks: SCLK0, SCLK1, and SCLK2 after passing through the first delay unit, the second delay unit, and the third delay unit. SCLK0, SCLK1, and SCLK2 are used to drive the first register group, the second register group, and the third register group respectively to sample the values ​​in the ADC data latch; The values ​​of the first register group, the second register group, and the third register group are compared using a comparator; If the values ​​of the three registers are equal, the ADC data is in a stable state, and the value in the ADC data latch is selected for output. If the values ​​of the three registers are not equal, the ADC data is in an update state, and the value in the ADC register is selected for output.

8. The reading method according to claim 5, characterized in that, In structure three, two delay units delay the interface clock to generate two different clocks, which respectively drive two cascaded D flip-flops to sample the ADC data update indication signal, synchronizing it to the interface clock domain. A selector selects which ADC data latch to output based on the signal from the subsequent D flip-flop. The selector output data is latched and output through the TX register, including: The ADC data is latched in two stages using the first ADC data latch and the second ADC data latch. The indicator signal for ADC data update is set as the indicator signal for ADC data from the first ADC data latch to the second ADC data latch, and there is a phase difference between the indicator signal and the signal from the first ADC data latch to the second ADC data latch, so as to ensure that the indicator signal and the signal from the first ADC data latch to the second ADC data latch do not change at the same time. The interface clock generates two clocks, SCLK0 and SCLK1, through the first delay unit and the second delay unit; The ADC data update indication signal is generated in the interface clock domain after being synchronized with SCLK and SCLK0. The TX register selects the latched ADC data according to the indication signal of ADC data update in the interface clock domain. If it is high, the data output in the first ADC data latch is latched; otherwise, the data output of the second ADC data latch is selected. By using two-level ADC data latching and update indicators, the interface latches ADC data to avoid the ADC data update time, thereby ensuring that the interface latches stable ADC data.

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