A method and system for storing and preventing frame loss of a store-and-forward satellite TT&C integrated machine

Abstract

The application relates to a storage anti-loss frame method and system of a store-and-forward satellite measurement and control integrated machine, and the method comprises the following steps: real-time monitoring of a storage state parameter and equipment reset condition of the measurement and control integrated machine, wherein the storage state parameter comprises a storage residual space, a bad block quantity, an ECC error correction frequency and a writing speed; when it is monitored that the equipment is reset, whether the current data is the last frame or half frame data is judged according to the address and data length of the last writing operation before the reset, and abnormal data frames are marked; an anti-loss frame control strategy is dynamically generated according to the storage state parameter and the marking result of the abnormal data frames; the anti-loss frame control strategy is executed to perform a completion, copying or address locking operation on the abnormal data frames. Through state monitoring, abnormal identification, strategy generation and execution recovery, the application realizes accurate identification and protection of the last frame data, ensures data continuity and integrity, and improves the reliability of a satellite communication system in a space radiation environment.

Description

Technical Field

[0001] This application relates to the field of satellite communication technology, and in particular to a fixed-frame-loss prevention method and system for a store-and-forward integrated satellite telemetry and control system. Background Technology

[0002] Satellite communication, as a key component of integrated space-ground information networks, plays an irreplaceable role in areas such as wide-area IoT coverage, data collection in remote areas, and emergency communications. Among these, store-and-forward satellites, with their advantages of low cost, wide coverage, and lightweight deployment, have become the mainstream technology for low-Earth orbit IoT satellite systems. Their typical operating mode is as follows: ground terminals upload collected service data to the onboard payload, where it is temporarily stored and carried by the onboard solid-state storage (SSD); when the satellite passes within the line of sight of a ground gateway station, it then transmits the onboard user data and onboard telemetry data back to the ground receiving system via a data transmission channel, completing the entire data storage and forwarding process.

[0003] As the core payload equipment of a store-and-forward satellite, the telemetry, tracking, and command (TT&C) unit integrates functions such as TT&C, data transmission, and data storage. It is responsible for receiving, buffering, writing to fixed storage, and controlling downlink of onboard data, and is the core unit ensuring reliable data transmission between space and ground. In actual on-orbit operation, onboard fixed storage typically employs non-volatile memory arrays such as NAND Flash, in conjunction with an FPGA to achieve high-speed data read / write and storage management.

[0004] However, satellites operate in a complex space environment, and single-event events (high-energy charged particle impacts) can easily cause logic malfunctions, resets, or restarts in core control units such as onboard FPGAs, becoming a major factor affecting data storage reliability. When a single-event event triggers a sudden reset of the telemetry and control system, if the reset occurs at the end of a data frame write, when the memory is about to be full, or during the writing of the last frame / half frame, it will directly interrupt the current write operation, and the already written data cannot complete frame alignment and verification loop closure. Traditional storage management mechanisms do not have end-frame protection mechanisms designed for such sudden reset scenarios. When the system restarts after a reset, new data packets will directly overwrite the last frame or half frame data that has not been written, resulting in the permanent loss of the last frame data.

[0005] Therefore, existing technologies cannot effectively prevent the loss of the last frame / half frame of data in scenarios where the telemetry and control system is reset due to a single-event effect. This makes it difficult to meet the engineering requirements of store-and-forward IoT satellites for high data reliability, no frame loss, and continuous transmission, thus restricting the data security capabilities and on-orbit service stability of satellite communication systems. Summary of the Invention

[0006] In view of this, this application provides a fixed-frame anti-loss method and system for a store-and-forward satellite telemetry and control integrated machine. Through status monitoring, anomaly identification, strategy generation and execution recovery, it can accurately identify and protect the last frame of data, ensure data continuity and integrity, and improve the reliability of satellite communication system in space radiation environment.

[0007] To achieve the above objectives, the first aspect of this application provides a method for preventing frame loss in a store-and-forward satellite telemetry and control integrated machine, comprising the following steps: The solid memory status parameters and device reset status of the integrated monitoring and control unit are monitored in real time. The solid memory status parameters include the remaining solid memory space, the number of bad blocks, the number of ECC error corrections, and the write speed. When a device reset is detected, the system determines whether the current data is the last frame or half frame of data based on the address and data length of the last write operation before the reset, and marks the abnormal data frames. Based on the stored state parameters and the marking results of the abnormal data frames, a frame loss prevention control strategy is dynamically generated. The frame loss prevention control strategy is executed to perform completion, copying, or address locking operations on abnormal data frames.

[0008] As one possible implementation of the first aspect, the specific method for determining whether the current data is the last frame or half a frame of data is as follows: If the length of the current data is less than the preset full frame length, it is determined to be half frame data and marked as a frame to be processed; If the length of the current data is the length of a complete frame but the writing process is interrupted by a reset, it is determined to be the last frame of data and marked as a frame to be protected.

[0009] As one possible implementation of the first aspect, the dynamically generated anti-frame loss control strategy includes at least one of the following: If it is the last frame or half frame of data, the data of that frame will be temporarily stored in the buffer and the remaining part will be filled with the preset padding data. If the solid storage is about to be full, the write separation mechanism will be activated to temporarily transfer the newly written data to the backup storage block. If the number of bad blocks increases beyond a preset threshold, the write rate will be reduced and a low-priority data discarding strategy will be initiated to prioritize the protection of critical telemetry data. If the number of ECC error corrections increases abnormally, switch to redundant storage mode or adjust the data compression ratio.

[0010] As one possible implementation of the first aspect, the execution of the anti-frame loss control strategy includes at least one of the following operations: Execute a copy command on data marked as frames to be processed or frames to be protected, and write them completely into a new storage block; Lock the current write address to prevent subsequent data from being overwritten; Start / stop recording mechanism to ensure data continuity and address alignment; Record recovery logs for use in ground telemetry analysis.

[0011] As one possible implementation of the first aspect, it also includes: recording abnormal events and recovery process data, and dynamically adjusting the parameters of the anti-frame loss control strategy.

[0012] As one possible implementation of the first aspect, the specific method for recording abnormal events and recovery process data, and dynamically adjusting the parameters of the anti-frame loss control strategy is as follows: The reset reason, recovery result, ECC error correction count, and bad block change data are stored in the feedback log. The parameters of the anti-frame loss control strategy, including buffer size, data compression rate, and priority threshold, are dynamically adjusted through on-board or ground-based analysis systems.

[0013] The second aspect of this application provides a fixed-frame-loss prevention system for a store-and-forward satellite telemetry and control integrated machine, comprising: The monitoring module is used to monitor the solid memory status parameters and device reset status of the integrated measurement and control unit in real time. The solid memory status parameters include the remaining solid memory space, the number of bad blocks, the number of ECC error corrections, and the write speed. The identification module is used to determine whether the current data is the last frame or half frame of data based on the address and data length of the last write operation before the reset when the device is detected to have been reset, and to mark abnormal data frames. The decision module is used to dynamically generate a frame loss prevention control strategy based on the fixed state parameters and the marking results of the abnormal data frames. The execution module is used to execute the frame loss prevention control strategy and perform completion, copying, or address locking operations on abnormal data frames.

[0014] As a possible implementation of the second aspect, it also includes: a feedback learning module, used to record abnormal events and recovery process data, and dynamically adjust the parameters of the anti-frame loss control strategy.

[0015] A third aspect of this application provides a computing device, including a processor and a memory storing program instructions thereon, wherein when executed by the processor, the program instructions cause the processor to perform the aforementioned fixed-storage anti-frame-loss method for a store-and-forward satellite telemetry and control integrated machine.

[0016] The fourth aspect of this application provides a computer-readable storage medium having program instructions stored thereon, which, when executed by a computer, cause the computer to perform the above-described method for preventing frame loss in a store-and-forward satellite telemetry and control integrated machine.

[0017] Compared with the prior art, this application has the following beneficial effects: This application provides a fixed-frame anti-loss method and system for a store-and-forward satellite telemetry and control integrated machine. By monitoring the fixed-frame status parameters and device reset status in real time, it accurately identifies and marks the last frame or half-frame of abnormal data. Based on the fixed-frame health status, it dynamically generates differentiated anti-loss control strategies and performs protection operations such as data completion, copying, or address locking. At the same time, it continuously optimizes strategy parameters by combining a feedback learning mechanism. This effectively solves the key problem of data loss of the last frame during reset due to single-event effects during satellite operation in orbit. It significantly improves the data integrity and system reliability of the store-and-forward satellite telemetry and control integrated machine. Meanwhile, through intelligent resource allocation strategies, it avoids the waste of storage resources caused by traditional full backup, and maximizes data protection efficiency under limited onboard resources. Attached Figure Description

[0018] Figure 1 A flowchart illustrating a fixed-frame-loss prevention method for a store-and-forward integrated satellite telemetry and control system provided in this application embodiment.

[0019] Figure 2 This is a structural diagram of a fixed-frame-loss prevention system for a store-and-forward integrated satellite telemetry and control unit provided in an embodiment of this application.

[0020] Figure 3 This is a structural diagram of a computing device provided in an embodiment of this application.

[0021] It should be understood that the dimensions and shapes of the block diagrams in the above structural diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of this application. The relative positions and inclusion relationships between the block diagrams presented in the structural diagrams are only schematic representations of the structural relationships between the block diagrams, and are not intended to limit the physical connection methods of the embodiments of this application. Detailed Implementation

[0022] To make this application easier to understand, specific embodiments are described below to further illustrate this application. The technical solutions provided by this application are further explained below with reference to the accompanying drawings and examples. It should be understood that the system architecture and business scenarios provided in the embodiments of this application are mainly for illustrating possible implementations of the technical solutions of this application and should not be construed as the sole limitation on the technical solutions of this application. Those skilled in the art will recognize that, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided by this application are equally applicable to similar technical problems.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of any inconsistency, the meaning set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.

[0024] The solutions provided in this application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] This application proposes a method and system for preventing frame loss in a store-and-forward satellite telemetry, tracking, and command (TT&C) system. Through five stages—state monitoring, anomaly identification, strategy generation, execution recovery, and feedback learning—a dynamic, intelligent, and adaptive data protection mechanism is constructed. This mechanism can accurately identify and protect the last frame of data when a single-event event causes a reset, ensuring no data loss and guaranteeing the reliability of the satellite communication system. This application is applicable to spacecraft relying on store-and-forward mechanisms, such as low-Earth orbit IoT satellites, remote sensing satellites, and data relay satellites, and has high engineering practical value and promising application prospects.

[0026] Figure 1 The diagram shows a flowchart of a fixed-storage anti-frame-loss method for a store-and-forward satellite telemetry and control integrated machine according to an embodiment of this application. This method uses a low-Earth orbit store-and-forward IoT satellite as the application carrier, with an orbital altitude of 900km. The satellite carries a telemetry and control integrated machine equipped with an FPGA control unit and a NAND Flash storage array, with a total fixed-storage capacity of 256GB. Ground terminals upload data to the satellite via LoRa modulation, and the satellite receives the data and writes it to the fixed-storage memory in real time. When the satellite passes over a gateway station, it reads data from the fixed-storage memory and transmits it down through the data transmission channel. (Refer to...) Figure 1 As shown, the method includes the following steps: S110: Real-time monitoring of the fixed status parameters of the integrated measurement and control unit and the equipment reset status.

[0027] In this step, after the integrated measurement and control unit is powered on, it starts a background monitoring task to read the following status parameters at fixed intervals (e.g., 1 second): Remaining storage space: Obtain the currently unused storage capacity through the NAND Flash controller.

[0028] Number of bad blocks: Read the factory bad block table of the fixed memory and the record of bad blocks added during operation.

[0029] ECC Error Correction Count: Counts the number of bit errors corrected by the ECC module each time data is read.

[0030] Write speed: Calculate the total amount of data written to solid memory in the most recent monitoring period and divide by the period time.

[0031] Reset flag bit: Read the reset reason field in the FPGA internal register. If the field is non-zero, it indicates that the device has undergone a reset (including power-on reset, watchdog reset, single event latch-up reset, etc.).

[0032] S120: When a reset of the device is detected, it is determined whether the current data is the last frame or a half frame of data according to the address and data length of the last write operation before the reset, and the abnormal data frame is marked.

[0033] When it is detected that the reset flag bit is 1, the system enters an exception recovery process, which specifically includes the following sub-steps: Read the write status before reset: Read the start address start_addr of the last write operation before reset and the length of written data write_len (unit: byte) from the non-volatile register; Determine the type of data frame: Set the preset complete frame length as FRAME_LEN (for example, 512 bytes); If write_len < FRAME_LEN, it is determined that the current data is a half frame of data, and it is marked as a to-be-processed frame; If write_len = FRAME_LEN, but the writing process is interrupted by a reset (that is, the reset occurs exactly after the writing of this frame is completed and before the start of the next frame), it is determined as the last frame of data, and it is marked as a to-be-protected frame; If write_len = FRAME_LEN and the reset occurs in the frame gap, the frame is regarded as a normal frame and no special processing is required.

[0034] Mark the abnormal data frame: Store the start address start_addr, the length write_len and the mark type of the abnormal data frame into a temporary buffer for subsequent strategy generation.

[0035] S130: Dynamically generate an anti-frame-loss control strategy according to the non-volatile memory state parameter and the marking result of the abnormal data frame.

[0036] According to the non-volatile memory state parameter monitored in step S110 and the abnormal data frame mark generated in step S120, one or more anti-frame-loss strategies are dynamically selected according to the following rules: Strategy A (for the last frame / half frame data): If there is data marked as a to-be-processed frame or a to-be-protected frame, read the frame data from the non-volatile memory and temporarily store it in the FPGA internal buffer, and fill the remaining part (FRAME_LEN - write_len bytes) with the preset padding data 0xAA to form a complete frame.

[0037] Strategy B (for solid memory that is about to be full): If the remaining space in solid memory is less than the threshold (e.g., 5% of the total capacity), the write separation mechanism is activated to temporarily transfer the newly written data to the backup storage block (e.g., the emergency area reserved in solid memory or another independent Flash chip).

[0038] Strategy C (for excessively rapid bad block growth): If the number of new bad blocks in the last hour exceeds the preset threshold (e.g., 3), the write rate will be reduced to 50% of the normal value (achieved by increasing the write interval), and a low-priority data discarding strategy will be activated. Non-critical fields in the data packet (such as redundancy check and padding bytes) will not be written, and only critical telemetry data will be written.

[0039] Strategy D (for abnormally high ECC error correction counts): If the number of ECC error corrections exceeds the threshold (e.g., 100 times) in the last 10 minutes, switch to redundant storage mode, write each frame of data to two different physical blocks, or adjust the data compression ratio (e.g., change from 2:1 compression to no compression) to improve the ability to resist bit flips.

[0040] In this embodiment, if multiple policy conditions are met simultaneously, they are executed according to priority: Policy A > Policy D > Policy C > Policy B. The priority can be dynamically adjusted by ground commands.

[0041] S140: Execute the frame loss prevention control strategy to perform completion, copying, or address locking operations on abnormal data frames.

[0042] Based on the strategy generated in step S130, the system performs the corresponding hardware / software operations: Execution of strategy A: Data copy: The copy instruction is executed on the frame to be processed and the frame to be protected to write the complete data into the new fixed storage block, avoiding bad blocks and the original interrupt address; Address locking: The address last written before reset is added to the write lock set, and the hardware level prohibits subsequent data from being written to this address, preventing valid data from being overwritten; Address calibration: Initiates the stop / start recording mechanism to recalibrate the data write address, ensuring frame alignment and data continuity; Log recording: Generates data recovery logs, recording reset time, frame type, policy execution steps, and address lock information for use in ground telemetry analysis.

[0043] For the execution of strategy B: Modify the address mapping table of the fixed storage controller, redirect the current write logical address to the physical address of the spare block, and record the mapping relationship.

[0044] For the execution of strategy C: By adjusting the data flow control state machine inside the FPGA, an extra wait cycle is inserted between every two write operations, and a priority filter is configured to allow only fields marked as "high priority" in the data packet to pass through.

[0045] For strategy D: Set the NAND Flash controller to redundant write mode (operating on two target pages simultaneously for each write), or modify the compression ratio parameter by reconfiguring the compression IP core.

[0046] In some embodiments, the method further includes an adaptive optimization process, in which the system stores each abnormal event and recovery process data in a feedback log, specifically including: reset reason (provided by the FPGA reset register), recovery result (success / failure, failure reason code), ECC error correction count (statistical value within 1 minute before and after the event), change in the number of bad blocks (new bad block number and location), and the combination of anti-frame loss control strategies and execution time.

[0047] After completing the above log storage, at regular intervals (e.g., after each transit gateway), the satellite transmits the feedback logs to the ground analysis system via the data transmission channel. The ground system analyzes the logs using offline machine learning models (such as decision trees or Bayesian classifiers) to generate an optimized set of policy parameters, including: cache size (e.g., adjusted from the default 4KB to 8KB), data compression ratio (e.g., adjusted from 2:1 to 1.5:1), and priority threshold (e.g., adjusting the priority of telemetry data from 7 to 9, and non-critical data from 3 to 1). The optimized parameters are sent to the satellite via uplink injection commands. After receiving the commands, the onboard system updates the policy configuration table, achieving adaptive closed-loop optimization.

[0048] In summary, the fixed-storage anti-frame-loss method for a store-and-forward satellite telemetry and control integrated machine provided in this application, by real-time monitoring of the fixed-storage status and device reset status and accurately identifying and marking the last frame and half-frame abnormal data frames, can dynamically adapt to different storage anomaly scenarios to generate corresponding anti-frame-loss strategies. After data completion, copying, address locking, and start / stop recording are executed, it can effectively prevent on-board fixed-storage data from being overwritten or lost due to device reset, ensuring the continuity and integrity of data transmission. At the same time, it can prioritize the protection of critical telemetry data, reasonably optimize the utilization of storage resources, and further improve the system's adaptive optimization capability and on-orbit operational stability by recording abnormal and recovered data and dynamically adjusting strategy parameters.

[0049] like Figure 2As shown, this application also provides a fixed-storage anti-frame-loss system for a store-and-forward satellite telemetry and control integrated machine. This system can be applied to the telemetry and control integrated machine carried by a store-and-forward IoT satellite, and can be used to implement any step of the above-mentioned fixed-storage anti-frame-loss method for a store-and-forward satellite telemetry and control integrated machine and its optional embodiments, as shown in the attached document. Figure 2 As shown, the system includes a monitoring module 210, an identification module 220, a decision-making module 230, and an execution module 240.

[0050] The monitoring module 210 is used to monitor the solid memory status parameters and device reset status of the integrated measurement and control unit in real time. The solid memory status parameters include the remaining solid memory space, the number of bad blocks, the number of ECC error corrections, and the write speed. The identification module 220 is used to determine whether the current data is the last frame or half frame of data based on the address and data length of the last write operation before the reset when the device is detected to have reset, and to mark the abnormal data frames. The decision module 230 is used to dynamically generate an anti-frame loss control strategy based on the solid memory status parameters and the marking results of the abnormal data frames. The execution module 240 is used to execute the anti-frame loss control strategy and perform completion, copying, or address locking operations on the abnormal data frames.

[0051] In some embodiments, the system further includes a feedback learning module for recording abnormal events and recovery process data, and dynamically adjusting the parameters of the anti-frame loss control strategy, thereby achieving adaptive closed-loop optimization of the system.

[0052] It should be understood that the systems or modules in the embodiments of this application can be implemented by software, for example, by computer programs or instructions having the above-described functions. The corresponding computer programs or instructions can be stored in the internal memory of the terminal, and the processor reads the corresponding computer programs or instructions from the memory to implement the above functions. Alternatively, the systems or modules in the embodiments of this application can also be implemented by hardware. Or, the systems or modules in the embodiments of this application can also be implemented by a combination of a processor and software modules.

[0053] It should be understood that the processing details of the system or module in the embodiments of this application can be found by referring to... Figure 1 The descriptions of the embodiments and related extended embodiments shown will not be repeated in this application.

[0054] Figure 3 This is a schematic structural diagram of a computing device 1000 provided in an embodiment of this application. This computing device can execute or implement various optional embodiments of the above-described methods. The computing device can be a terminal, or a chip or chip system within the terminal. Figure 3 As shown, the computing device 1000 includes: a processor 1010, a memory 1020, and a communication interface 1030.

[0055] It should be understood that Figure 3 The communication interface 1030 in the computing device 1000 shown can be used to communicate with other devices, and may specifically include one or more transceiver circuits or interface circuits.

[0056] The processor 1010 can be connected to the memory 1020. The memory 1020 can be used to store the program code and data. Therefore, the memory 1020 can be a storage unit inside the processor 1010, an external storage unit independent of the processor 1010, or a component that includes both the storage unit inside the processor 1010 and the external storage unit independent of the processor 1010.

[0057] Optionally, the computing device 1000 may also include a bus. The memory 1020 and communication interface 1030 can be connected to the processor 1010 via the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The symbol is represented by a line without an arrow, but this does not mean that there is only one bus or one type of bus.

[0058] It should be understood that in the embodiments of this application, the processor 1010 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Alternatively, the processor 1010 may employ one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0059] The memory 1020 may include read-only memory and random access memory, and provides instructions and data to the processor 1010. A portion of the processor 1010 may also include non-volatile random access memory. For example, the processor 1010 may also store device type information.

[0060] When the computing device 1000 is running, the processor 1010 executes computer execution instructions stored in the memory 1020 to perform any of the operation steps of the above method and any of the optional embodiments thereof.

[0061] It should be understood that the computing device 1000 according to the embodiments of this application can correspond to the corresponding subject in executing the methods according to the various embodiments of this application, and the above and other operations and / or functions of each module in the computing device 1000 are respectively for implementing the corresponding processes of the methods of this embodiment. For the sake of brevity, they will not be described in detail here.

[0062] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0063] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0064] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0065] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0066] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0067] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0068] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is used to perform the above-described method, which includes at least one of the schemes described in the above embodiments.

[0069] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0070] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0071] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0072] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0073] Furthermore, the terms "first, second, third, etc." or similar terms such as module A, module B, and module C used in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that, where permissible, a specific order or sequence may be interchanged so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0074] In the above description, the labels of the steps involved, such as S110, S120, etc., do not mean that the steps will necessarily be executed. The order of the steps can be interchanged or executed simultaneously if permitted.

[0075] The term "comprising" as used in the specification and claims should not be construed as limiting itself to what follows; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or groups thereof. Thus, the statement "device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0076] The terms "an embodiment" or "an embodiment" as used in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of this application. Therefore, the terms "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics can be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure.

[0077] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, all of which fall within the scope of protection of this application.

Claims

1. A method for preventing frame loss in a store-and-forward satellite telemetry and control integrated machine, characterized in that, include: The solid memory status parameters and device reset status of the integrated monitoring and control unit are monitored in real time. The solid memory status parameters include the remaining solid memory space, the number of bad blocks, the number of ECC error corrections, and the write speed. When a device reset is detected, the system determines whether the current data is the last frame or half-frame based on the starting address of the last write operation before the reset and the length of the written data read from the non-volatile register, and marks abnormal data frames accordingly. The specific method for determining whether the current data is the last frame or half-frame is as follows: if the length of the current data is less than the preset full frame length, the current data is determined to be half-frame data and marked as a frame to be processed; if the length of the current data is equal to the full frame length but the write process is interrupted by a reset, the current data is determined to be the last frame data and marked as a frame to be protected. Based on the stored state parameters and the marking results of abnormal data frames, a frame loss prevention control strategy is dynamically generated; the dynamically generated frame loss prevention control strategy includes at least one of the following: Strategy A: If there is data marked as a frame to be processed or a frame to be protected, the frame data is read from the fixed memory and temporarily stored in the FPGA's internal buffer, and the remaining part of the frame to be processed is filled with preset filling data. Strategy B: If the remaining solid storage space is less than the threshold, the write separation mechanism will be activated to temporarily transfer the newly written data to the standby storage block; Strategy C: If the number of newly added bad blocks within the first preset time period exceeds the first preset threshold, the write rate will be reduced and a low-priority data discarding strategy will be activated. Non-critical fields in the data packet will not be written, and only critical telemetry data will be written. The non-critical fields include redundancy check and padding bytes. Strategy D: If the number of ECC error corrections within the second preset time exceeds the second preset threshold, switch to redundant storage mode, write each frame of data to two different physical blocks, or adjust the data compression rate. The frame loss prevention control strategy is executed to perform completion, copying, and address locking operations on abnormal data frames; The execution of the frame loss prevention control strategy includes: For Strategy A: Execute a copy command on data marked as frames to be processed or frames to be protected, and write the complete data to a new fixed storage block; add the address last written before reset to the write lock set to prevent valid data from being overwritten; start the start recording mechanism to recalibrate the data write address; record the recovery log for use in ground telemetry analysis; For strategy B: Modify the address mapping table of the fixed storage controller to redirect the current write address to the physical address of the spare storage block and record the mapping relationship; For strategy C: By adjusting the data flow control state machine inside the FPGA, an extra wait cycle is inserted between every two write operations, and a priority filter is configured to allow only fields marked as high priority in the data packet to pass through; For strategy D: Set the NAND Flash controller to redundant write mode, or modify the compression ratio parameter by reconfiguring the compression IP core; If multiple policy conditions are met simultaneously, they are executed in order of priority: Policy A > Policy D > Policy C > Policy B.

2. The method according to claim 1, characterized in that, Also includes: Record abnormal events and recovery process data, and dynamically adjust the parameters of the anti-frame loss control strategy.

3. The method according to claim 2, characterized in that, The specific method for recording abnormal events and recovery process data, and dynamically adjusting the parameters of the anti-frame loss control strategy is as follows: The reset reason, recovery result, ECC error correction count, and bad block change data are stored in the feedback log. The parameters of the anti-frame loss control strategy, including buffer size, data compression rate, and priority threshold, are dynamically adjusted through on-board or ground-based analysis systems.

4. A fixed-frame-loss prevention system for a store-and-forward satellite telemetry and control integrated machine, characterized in that, include: The monitoring module is used to monitor the solid memory status parameters and device reset status of the integrated measurement and control unit in real time. The solid memory status parameters include the remaining solid memory space, the number of bad blocks, the number of ECC error corrections, and the write speed. The identification module is used to determine whether the current data is the last frame or half frame of data when a device reset is detected, based on the starting address of the last write operation before the reset and the length of the written data read from the non-volatile register, and to mark abnormal data frames. The specific method for determining whether the current data is the last frame or half frame of data is as follows: if the length of the current data is less than the preset full frame length, the current data is determined to be half frame data and marked as a frame to be processed; if the length of the current data is equal to the full frame length but the write process is interrupted by a reset, the current data is determined to be the last frame of data and marked as a frame to be protected. The decision module is used to dynamically generate a frame loss prevention control strategy based on the fixed state parameters and the marking results of abnormal data frames; the dynamically generated frame loss prevention control strategy includes at least one of the following: Strategy A: If there is data marked as a frame to be processed or a frame to be protected, the frame data is read from the fixed memory and temporarily stored in the FPGA's internal buffer, and the remaining part of the frame to be processed is filled with preset filling data. Strategy B: If the remaining solid storage space is less than the threshold, the write separation mechanism will be activated to temporarily transfer the newly written data to the standby storage block; Strategy C: If the number of newly added bad blocks within the first preset time period exceeds the first preset threshold, the write rate will be reduced and a low-priority data discarding strategy will be activated. Non-critical fields in the data packet will not be written, and only critical telemetry data will be written. The non-critical fields include redundancy check and padding bytes. Strategy D: If the number of ECC error corrections within the second preset time exceeds the second preset threshold, switch to redundant storage mode, write each frame of data to two different physical blocks, or adjust the data compression rate. The execution module is used to execute the frame loss prevention control strategy, and to perform completion, copying and address locking operations on abnormal data frames; The execution of the frame loss prevention control strategy includes: For Strategy A: Execute a copy command on data marked as frames to be processed or frames to be protected, and write the complete data to a new fixed storage block; add the address last written before reset to the write lock set to prevent valid data from being overwritten; start the start recording mechanism to recalibrate the data write address; record the recovery log for use in ground telemetry analysis; For strategy B: Modify the address mapping table of the fixed storage controller to redirect the current write address to the physical address of the spare storage block and record the mapping relationship; For strategy C: By adjusting the data flow control state machine inside the FPGA, an extra wait cycle is inserted between every two write operations, and a priority filter is configured to allow only fields marked as high priority in the data packet to pass through; For strategy D: Set the NAND Flash controller to redundant write mode, or modify the compression ratio parameter by reconfiguring the compression IP core; If multiple policy conditions are met simultaneously, they are executed in order of priority: Policy A > Policy D > Policy C > Policy B.

5. The system according to claim 4, characterized in that, Also includes: The feedback learning module is used to record abnormal events and recovery process data, and dynamically adjust the parameters of the anti-frame loss control strategy.

6. A computing device, characterized in that, include: processor, and A memory having stored program instructions that, when executed by the processor, cause the processor to perform the method according to any one of claims 1 to 3.

7. A computer-readable storage medium, characterized in that, It stores program instructions that, when executed by a computer, cause the computer to perform the method described in any one of claims 1 to 3.

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