A received signal strength indication operation circuit for a power grid dual-mode communication unit

Abstract

The application provides a received signal strength indication operation circuit for a power grid dual-mode communication unit, and belongs to the technical field of integrated circuits. The circuit comprises an analog module and a digital module. A signal processing link of the digital module comprises a clock control unit, a cascaded half-frequency reverse integration unit and an overflow detection unit. The analog module is used for comparing a measured signal with a reference voltage to generate a plurality of digital signals. The clock control unit is used for transmitting a clock signal to the cascaded half-frequency reverse integration unit according to a digital signal and a feedback signal output by an inverting output end. The cascaded half-frequency reverse integration unit is used for performing an integration operation according to a preset comparison threshold within a preset time window to output a target integral value. The overflow detection unit is used for performing signal inversion according to the target integral value to output different bit positions of a received signal strength indication and generating a feedback signal according to the target integral value. The application can reduce circuit area overhead and reduce circuit operation power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a received signal strength indication calculation circuit for a dual-mode communication unit for power grids. Background Technology

[0002] RSSI (Received Signal Strength Indication) is a crucial parameter in the communications field, directly reflecting the signal strength of the current communication link and serving as an important indicator for evaluating link quality. It plays a particularly important role in State Grid's dual-mode communication services. Firstly, terminal communication units can intelligently select the link with better signal quality for communication by comparing the RSSI values ​​on the HPLC (wired) and HRF (wireless) links in real time. Secondly, in specific communication links, the modulation scheme can be dynamically adjusted based on the RSSI results to increase communication robustness.

[0003] In related technologies, the digital section of the RSSI calculation circuit consists of an N-bit accumulator, an N-bit comparator, and N DFF flip-flops. During the integration and summation operation within the time window, all N DFF flip-flops operate at the same clock (frequency) clk(F). The digital section of the RSSI calculation circuit includes multi-bit registers, multi-bit adders, and multi-bit comparators, occupying a large circuit area. During the integration and summation operation, the registers and adders operate at high clock frequencies, resulting in high circuit power consumption.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a signal strength indication and calculation circuit for a dual-mode communication unit in a power grid, which can reduce circuit area overhead and lower circuit power consumption.

[0006] To achieve the above objectives, one aspect of this application proposes a received signal strength indication calculation circuit for a dual-mode communication unit in a power grid. The circuit includes an analog module and a digital module. The digital module includes multiple signal processing links. Each signal processing link includes a clock control unit, a cascaded frequency divider inverse integration unit, and an overflow detection unit. The analog module is connected to the first input terminal of the clock control unit. The output terminal of the clock control unit is connected to the input terminal of the cascaded frequency divider inverse integration unit. The output terminal of the cascaded frequency divider inverse integration unit is connected to the input terminal of the overflow detection unit. The inverted output terminal of the overflow detection unit is connected to the second input terminal of the clock control unit. The analog module is used to compare the measured signal with a reference voltage and generate multiple digital signals. The clock control unit is used to transmit a clock signal to the cascaded divide-by-two inverse integrator unit based on the digital signal and the feedback signal output from the inverting output terminal. The cascaded frequency divider inverse integration unit is used to perform integration calculations within a preset time window according to a preset comparison threshold, and output the target integration value. The overflow detection unit is used to flip the signal according to the target integral value, output different bits indicating the received signal strength, and generate the feedback signal according to the target integral value.

[0007] In some embodiments, the analog module includes a power supply, multiple resistors, and multiple comparators. The multiple resistors are connected in series to form a voltage divider branch. The starting end of the voltage divider branch is connected to the power supply, and the ending end of the voltage divider branch is connected to ground. The non-inverting input of the comparator receives the measured signal, and the inverting inputs of different comparators are connected to different voltage nodes of the voltage divider branch. The voltage divider branch is used to divide the output voltage of the power supply into multiple reference voltages with equal step sizes. The comparator is used to compare the measured signal with the reference voltage to generate the digital signal.

[0008] In some embodiments, different signal processing links are connected to different outputs of the comparator.

[0009] In some embodiments, the clock control unit includes a two-input AND gate and a clock gating unit. The input terminals of the two-input AND gate serve as the first input terminal and the second input terminal. The output terminal of the two-input AND gate is connected to the control terminal of the clock gating unit. The clock input terminal of the clock gating unit receives a clock signal, and the output terminal of the clock gating unit serves as the output terminal of the clock control unit. The two-input AND gate is used to generate a clock control signal based on the digital signal and the feedback signal; The clock gating unit is used to control the output of the clock signal according to the clock control signal.

[0010] In some embodiments, the cascaded frequency divider inverse integration unit includes multiple frequency divider units, which form a cascaded structure, and the input terminal of the first-stage frequency divider unit receives the clock signal. The frequency divider unit is used to divide the received signal by two according to the comparison threshold.

[0011] In some embodiments, the frequency divider unit includes a D flip-flop and a two-input data selector; The clock input of the D flip-flop is connected to the output of the two-input data selector of the previous stage divider unit. The data input of the D flip-flop is connected to the inverted output of the same D flip-flop. The inverted output is connected to the first input of the two-input data selector. The non-inverted output of the D flip-flop is connected to the zero input of the two-input data selector. The selection terminal of the two-input data selector receives different bits of the comparison threshold.

[0012] In some embodiments, the overflow detection unit includes a D flip-flop, the clock input of which is connected to the output of the cascaded divide-by-two inverse integrator unit, the non-inverting output of which outputs different bits of the received signal strength indication, and the inverting output of which is connected to the data input of the same D flip-flop and the second input of the clock control unit.

[0013] In some embodiments, the power supply is a low-dropout linear regulator.

[0014] In some embodiments, the reset ports of the plurality of D flip-flops are connected to a reset control bus.

[0015] To achieve the above objectives, another aspect of the embodiments of this application proposes a received signal strength indication calculation device for a dual-mode communication unit for power grids, the device including the circuit described in the above embodiments.

[0016] The embodiments of this application include at least the following beneficial effects: This application provides a received signal strength indication operation circuit for a dual-mode communication unit in the power grid. This scheme does not require the use of multi-bit wide adders and multi-bit wide comparators, thus reducing circuit area overhead; the operating clock frequency of the cascaded divider inverse integrator is exponentially reduced, which can reduce the circuit operating power consumption. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the received signal strength indication calculation circuit for a dual-mode communication unit for power grids provided in this application embodiment; Figure 2 This is a schematic diagram of the structure of the digital module provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the clock control unit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the frequency divider unit provided in the embodiment of this application; Figure 5 This is a schematic diagram of the overflow detection unit provided in the embodiments of this application; Figure 6 This is another structural schematic diagram of the frequency divider unit provided in the embodiments of this application; Figure 7 This is a schematic diagram illustrating the principle of the received signal strength indication calculation process in the related technology provided in the embodiments of this application; Figure 8 This is provided by the embodiments of this application. Figure 7 A schematic diagram of the structure of the digital processing section. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] RSSI (Received Signal Strength Indication) is a crucial parameter in the communications field, directly reflecting the signal strength of the current communication link and serving as an important indicator for evaluating link quality. It plays a particularly important role in State Grid's dual-mode communication services. Firstly, terminal communication units can intelligently select the link with better signal quality for communication by comparing the RSSI values ​​on the HPLC (wired) and HRF (wireless) links in real time. Secondly, in specific communication links, the modulation scheme can be dynamically adjusted based on the RSSI results to increase communication robustness.

[0021] In related technologies, such as Figure 7 and Figure 8As shown, the analog section of the RSSI calculation circuit includes multiple comparators, the digital section consists of an N-bit accumulator, an N-bit comparator, and N DFF flip-flops, and the integrator includes multiple accumulators and DFF flip-flops. During the integration and summation operation within the time window, all N DFF flip-flops operate at the same clock frequency (clk(F)). The digital section of the RSSI calculation circuit contains multi-bit registers, multi-bit adders, and multi-bit comparators, occupying a large circuit area. During the integration and summation operation, the registers and adders operate at high clock frequencies, resulting in high circuit power consumption.

[0022] In summary, the technical problems existing in the relevant technologies need to be improved.

[0023] Figure 1 This is an optional structural diagram of the received signal strength indication calculation circuit for a dual-mode communication unit for a power grid provided in this application embodiment. The circuit includes an analog module and a digital module. The digital module includes multiple signal processing links. Each signal processing link includes a clock control unit, a cascaded frequency divider inverse integration unit, and an overflow detection unit. The analog module is connected to the first input terminal of the clock control unit. The output terminal of the clock control unit is connected to the input terminal of the cascaded frequency divider inverse integration unit. The output terminal of the cascaded frequency divider inverse integration unit is connected to the input terminal of the overflow detection unit. The inverted output terminal of the overflow detection unit is connected to the second input terminal of the clock control unit. The analog module is used to compare the measured signal with a reference voltage and generate multiple digital signals; The clock control unit is used to transmit clock signals to the cascaded divide-by-two inverse integrator unit based on the digital signal and the feedback signal output from the inverting output terminal; The cascaded frequency divider inverse integration unit is used to perform integration operations within a preset time window according to a preset comparison threshold and output the target integral value. The overflow detection unit is used to flip the signal according to the target integral value, output different bits indicating the received signal strength, and generate a feedback signal according to the target integral value.

[0024] like Figure 2 As shown, the circuit provided in this embodiment does not require the use of multi-bit wide adders and multi-bit wide comparators, reducing circuit area overhead; the operating clock frequency of the cascaded divide-by-two inverse integrator is exponentially reduced, which can reduce circuit power consumption. When the value of the received signal strength indication is determined, a feedback signal is generated by the overflow detection unit to control the clock control unit to interrupt the clock signal transmission in advance, thereby saving power consumption.

[0025] In some embodiments, the analog module includes a power supply, multiple resistors and multiple comparators. The multiple resistors are connected in series to form a voltage divider branch. The start end of the voltage divider branch is connected to the power supply, and the end end of the voltage divider branch is connected to ground. The non-inverting input of the comparator receives the signal under test, and the inverting inputs of different comparators are connected to different voltage nodes of the voltage divider branch. The voltage divider branch is used to divide the output voltage of the power supply into multiple reference voltages with equal step sizes. A comparator is used to compare the measured signal with a reference voltage to generate a digital signal.

[0026] Specifically, the analog module averages the power supply output voltage to generate a reference voltage Vref[n-1:0] with equal steps, which is connected to the reference terminal of the analog comparator. VIN is the analog signal of the measurement root node, which is input to the signal terminal of each stage of the analog comparator. The output of each analog comparator is: When VIN > Vref[n], Vrssi[n] = VDD; when VIN > Vref[n], Vrssi[n] = VDD. <Vref[n],Vrssi[n]=VSS; Then it is converted from a modulus to a digital form (1 / 0) and output to the digital module.

[0027] In some embodiments, the power supply is a low dropout regulator (LDO), which can provide clean DC power, suppress power ripple, and improve the accuracy of the frequency division clock.

[0028] In some embodiments, different signal processing links are connected to different outputs of the comparator to calculate different bits of the received signal strength indication.

[0029] In some embodiments, the clock control unit includes a two-input AND gate and a clock gating unit. The input terminals of the two-input AND gate serve as the first input terminal and the second input terminal. The output terminal of the two-input AND gate is connected to the control terminal of the clock gating unit. The clock input terminal of the clock gating unit receives the clock signal, and the output terminal of the clock gating unit serves as the output terminal of the clock control unit. A two-input AND gate is used to generate a clock control signal based on digital signals and feedback signals; The clock gating unit is used to control the output of the clock signal according to the clock control signal.

[0030] Specifically, please refer to Figure 3 The clock control unit includes a two-input AND gate and a clock gating unit. Clk is the main input clock for the module's operation, with a frequency of F, and is connected to the clock input terminal of the clock gating unit ICG. Vrssi[i] is a digital signal, and the integration unit counts the number of times it is 1 (high) within the time window, connected to the two-input AND gate in1 (first input terminal); the overflow detection unit... The output terminal (inverting output terminal) is connected to the two-input AND gate in2 (second input terminal). When When the output is 0 (low level), it means that the count value of the integration unit is greater than the comparison threshold TH[N-1:0] within the time window. At this time, the clock gating unit can be turned off to reduce the power consumption of the circuit.

[0031] When Vrssi[i] is high and overflow detection unit When the output is high, i.e., when the output of the two-input AND gate is 1, the clock gating unit ICG is in the open state, and the ICG outputs a valid clock signal with a frequency of F; when the output of the two-input AND gate is 0, the clock gating unit ICG is in the closed state, and its output remains 0.

[0032] In some embodiments, the cascaded frequency divider inverse integration unit includes multiple frequency divider units, which form a cascaded structure, and the input terminal of the first-stage frequency divider unit receives a clock signal. The frequency divider unit is used to divide the received signal by two according to a comparison threshold.

[0033] Specifically, the N-stage cascaded divide-by-two inverse integrator unit comprises N divide-by-two units. The output 'out' of the clock control unit ICG is connected to the clock input 'clk' of the first-stage divide-by-two unit within the N-stage cascaded divide-by-two inverse integrator unit. The output 'out' of the first-stage divide-by-two unit is connected to the clock input 'clk' of the second-stage divide-by-two unit, and so on. The output 'out' of the (N-1)th stage divide-by-two unit is connected to the clock input 'clk' of the overflow detection unit. The operating clock frequency of the first-stage divide-by-two unit is F, the operating clock frequency of the second-stage divide-by-two unit is F / 2, and the operating clock frequency of the (N-1)th stage divide-by-two unit is F / 2. N-1 .

[0034] In some embodiments, the divide-by-two unit includes a D flip-flop and a two-input data selector; The clock input of the D flip-flop is connected to the output of the two-input data selector of the previous stage divider unit. The data input of the D flip-flop is connected to the inverted output of the same D flip-flop. The inverted output is connected to the first input of the two-input data selector. The non-inverted output of the D flip-flop is connected to the zero input of the two-input data selector. The selection terminal of the two-input data selector receives different bits of the comparison threshold.

[0035] Specifically, please refer to Figure 4 The divide-by-two unit consists of one asynchronous reset DFF flip-flop (D flip-flop) and one two-input MUX. In the power-on reset state, the Q output of the DFF flip-flop is 0. The output is 1, and the data input to the DFF trigger comes from the DFF trigger's... Output. When the MUX selection terminal is 1, the DFF trigger is activated. The output is selected by activating input terminal 1. When the MUX selection terminal is 0, the Q output of the DFF flip-flop is activated, which means the zero input terminal is activated for output. Overall, the divide-by-two unit implements the divide-by-two logic function that supports preset values. The MUX selection terminal of the first-stage divide-by-two unit is connected to the comparison threshold TH[0], the MUX selection terminal of the second-stage divide-by-two unit is connected to the comparison threshold TH[1], and the MUX selection terminal of the (N-1)th-stage divide-by-two unit is connected to the comparison threshold TH[N-1].

[0036] In some embodiments, the reset ports of multiple D flip-flops are connected to a reset control bus.

[0037] After power-on reset and configuration of the comparison threshold TH[N-1:0], the integral value acc[N-1:0] of the inverse integration unit is initialized to TH[N-1:0]. Whenever Vrssi[n] is high, the clock control unit ICG is turned on, and acc[N-1:0] is decremented by one; whenever Vrssi[n] is low, the clock control unit ICG is turned off, and acc[n-1:0] remains unchanged. When acc[N-1:0] decrements to 0, it means that the number of times Vrssi[n] is high is equal to the threshold TH[N-1:0].

[0038] In some embodiments, please refer to Figure 6 The frequency divider unit consists of two asynchronous reset DFF flip-flops and a two-input MUX. In the power-on reset state, the Q output of the DFFA flip-flop is 0. Output 1), the Q output of the DFFB flip-flop is 1 ( The output is 0), the two D flip-flops share the same input clock, and the data input comes from the MUX output. The two inputs are the MUX selection terminals. When the MUX selection terminal is 1, the DFFA flip-flops are activated. The output, when the MUX selection terminal is 0, selects the DFFB flip-flop. The output, this divide-by-two unit can also perform the divide-by-two function, which can effectively reduce area and power consumption when the time window is large.

[0039] In some embodiments, the overflow detection unit includes a D flip-flop, the clock input of which is connected to the output of a cascaded divide-by-two inverse integrator, the non-inverting output of which outputs different bits indicating the received signal strength, and the inverting output of which is connected to the data input of the same D flip-flop and the second input of the clock control unit.

[0040] Please refer to Figure 5, the overflow detection unit comprises a DFF flip-flop, whose clock input terminal is connected to the output acc[N-1] of the N-stage cascaded frequency-divide-by-two reverse integration unit, and whose data input terminal D is connected to the output terminal, and the output terminal Q of the DFF is RSSI[i] (one bit of the Received Signal Strength Indication).

[0041] After power-on reset, RSSI[i] is 0. When the number of high-level Vrssi[i] is greater than the comparison threshold TH[N-1:0], the output acc[N-1] of the preceding stage reverse integration unit will change from 0 to 1, completing a flip. Since acc[N-1] is connected to the clock terminal clk of the overflow detection unit, it will also cause the output Q of the DFF flip-flop in the overflow detection unit to complete a 0-to-1 flip operation, that is, RSSI[i] becomes 1.

[0042] The clock control unit, the N-stage cascaded frequency-divide-by-two reverse integration unit and the overflow detection unit equivalently implement the functions of integration, comparison and result storage as a whole.

[0043] The statistical calculation of the RSSI[i] value is performed within a configured time window. The conventional statistical method is to perform overall statistics on Vrssi[i] throughout the entire time window, and then perform result comparison. This method usually causes waste of partial invalid power consumption when the final value of RSSI[i] is 1. Assuming that the statistical window is Win and the comparison threshold is TH, since the value of Vrssi[i] is random, there is a probability that at the w-th (w<=Win) point in the Win window, acc [N-1:0]>TH is satisfied, and at this time, the result of RSSI[i] can already be judged as 1, that is, the Vrssi[i] values of the remaining Win-w points in the window will not affect the final RSSI[i] result. At this time, the ICG of the clock control unit can be actively turned off to save power consumption, that is, the Q output terminal of a DFF flip-flop in the overflow detection unit is connected to the input2 terminal of the two-input AND gate in the clock control unit.

[0044] In addition, when the final value of RSSI[i] is 0, that is, acc [N-1:0]<TH, it indicates that the number of cases where Vrssi[i] is 1 in the Win window is small, so the ICG of the clock control unit is turned on less frequently, and the DFF flip-flops in the subsequent N-stage cascaded frequency-divide-by-two reverse integration unit flip less, so the power consumption of this embodiment in this case is also low.

[0045] To achieve the above objectives, another aspect of this application provides a received signal strength indication calculation device for a dual-mode communication unit in a power grid, the device comprising the circuit described in the above embodiments. It is understood that the content of the above circuit embodiments is applicable to this device embodiment, and the specific functions implemented in this device embodiment are the same as those in the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved in the above circuit embodiments.

[0046] The received signal strength indication operation circuit for a dual-mode communication unit in the power grid provided in this application, for an integrator with a bit width of w, only requires one clock gate unit and 2N+1 registers in terms of circuit configuration for optimized integration and comparison operation structure. Compared with the traditional integration and comparison operation structure, which requires an N-bit wide adder and an N-bit wide comparator, the area overhead is greatly reduced, especially in application scenarios where N is large.

[0047] For an integrator with a bit width of w, the optimized integrator structure uses the lowest bit register operating at the highest master clock frequency, the second lowest bit register operating at half its frequency, and so on, with the highest bit register operating at F / 2. N-1 According to the formula for calculating dynamic power consumption of digital circuits: P switch =VDD 2 *Cload*f; Where VDD represents the operating voltage, Cload represents the load capacitance, and f can be represented as the sum of the operating frequencies of multiple registers. The power consumption is directly proportional to the clock operating frequency f. The dynamic operating power consumption of the cascaded divider inverse integrator unit will be greatly reduced.

[0048] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of this application, and do not constitute a limitation on the technical solutions provided in this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in this application are also applicable to similar technical problems.

[0049] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0050] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0051] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0052] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0054] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0055] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0056] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0057] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0058] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A received signal strength indication and operational circuit for a dual-mode communication unit in a power grid, characterized in that, The circuit includes an analog module and a digital module. The digital module includes multiple signal processing links. Each signal processing link includes a clock control unit, a cascaded divide-by-two inverse integration unit, and an overflow detection unit. The analog module is connected to the first input terminal of the clock control unit. The output terminal of the clock control unit is connected to the input terminal of the cascaded divide-by-two inverse integration unit. The output terminal of the cascaded divide-by-two inverse integration unit is connected to the input terminal of the overflow detection unit. The inverted output terminal of the overflow detection unit is connected to the second input terminal of the clock control unit. The analog module is used to compare the measured signal with a reference voltage and generate multiple digital signals. The clock control unit is used to transmit a clock signal to the cascaded divide-by-two inverse integrator unit based on the digital signal and the feedback signal output from the inverting output terminal. The cascaded frequency divider inverse integration unit is used to perform integration calculations within a preset time window according to a preset comparison threshold, and output the target integration value. The overflow detection unit is used to flip the signal according to the target integral value, output different bits indicating the received signal strength, and generate the feedback signal according to the target integral value. The cascaded frequency divider inverse integration unit includes multiple frequency divider units, which form a cascaded structure. The input terminal of the first-stage frequency divider unit receives the clock signal. The frequency division unit is used to divide the received signal by two according to the comparison threshold. The frequency divider unit includes a D flip-flop and a two-input data selector; The clock input of the D flip-flop is connected to the output of the two-input data selector of the previous stage divider unit. The data input of the D flip-flop is connected to the inverted output of the same D flip-flop. The inverted output is connected to the first input of the two-input data selector. The non-inverted output of the D flip-flop is connected to the zero input of the two-input data selector. The selection terminal of the two-input data selector receives different bits of the comparison threshold.

2. The circuit according to claim 1, characterized in that, The analog module includes a power supply, multiple resistors, and multiple comparators. The multiple resistors are connected in series to form a voltage divider branch. The starting end of the voltage divider branch is connected to the power supply, and the ending end of the voltage divider branch is connected to ground. The non-inverting input of the comparator receives the measured signal, and the inverting inputs of different comparators are connected to different voltage nodes of the voltage divider branch. The voltage divider branch is used to divide the output voltage of the power supply into multiple reference voltages with equal step sizes. The comparator is used to compare the measured signal with the reference voltage to generate the digital signal.

3. The circuit according to claim 2, characterized in that, The different signal processing links are respectively connected to different outputs of the comparator.

4. The circuit according to claim 1, characterized in that, The clock control unit includes a two-input AND gate and a clock gating unit. The input terminals of the two-input AND gate serve as the first input terminal and the second input terminal. The output terminal of the two-input AND gate is connected to the control terminal of the clock gating unit. The clock input terminal of the clock gating unit receives a clock signal, and the output terminal of the clock gating unit serves as the output terminal of the clock control unit. The two-input AND gate is used to generate a clock control signal based on the digital signal and the feedback signal; The clock gating unit is used to control the output of the clock signal according to the clock control signal.

5. The circuit according to claim 1, characterized in that, The overflow detection unit includes a D flip-flop, the clock input of which is connected to the output of the cascaded divide-by-two inverse integrator unit, the non-inverting output of which outputs different bits of the received signal strength indication, the inverting output of which is connected to the data input of the same D flip-flop, and the inverting output of which is connected to the second input of the clock control unit.

6. The circuit according to claim 2, characterized in that, The power supply is a low-dropout linear regulator.

7. The circuit according to claim 1 or 5, characterized in that, The reset ports of the multiple D flip-flops are connected to the reset control bus.

8. A receiving signal strength indication and calculation device for a dual-mode communication unit in a power grid, characterized in that, The device includes the circuitry as described in any one of claims 1 to 7.

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