Accelerator high-frequency power loading control method and system

Abstract

The application provides an accelerator high-frequency power loading control method and system, and relates to the technical field of accelerator control. The method comprises the following steps: setting the amplitude value of an initial intermediate-frequency excitation signal as a normal working voltage value, and setting an initial pulse signal as a narrow pulse; demodulating an intermediate-frequency sampling signal of a high-frequency cavity to obtain in-phase components and quadrature components; performing linear fitting on multiple phase data points of the intermediate-frequency sampling signal at a pulse falling edge to calculate a detuning frequency; adjusting the frequency of the intermediate-frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high-frequency cavity; maintaining the tuning mechanism of the high-frequency cavity in a stationary state, gradually increasing the pulse width and repetition frequency of the pulse excitation signal, performing frequency compensation again after each increase, and stopping until a target value is reached; and switching the excitation signals of the cavities to a unified reference frequency, and starting the tuning mechanism to track the reference frequency. The application solves the mechanical fatigue and failure problems caused by frequent operation of the tuning mechanism.

Description

Technical Field

[0001] This invention relates to the field of accelerator control technology, and in particular to a method and system for controlling high-frequency power loading in accelerators. Background Technology

[0002] Heavy ion linear accelerators are core devices in fields such as fundamental nuclear physics research, nuclear medicine, and aerospace science. The low-level control system, as a crucial component, is responsible for real-time adjustment of the resonant cavity's dynamic characteristics to ensure the stable establishment of the electric field. During the accelerator's initial startup or fault recovery process, the control system must automatically apply power from zero to the set value of the high-frequency electric field. This process is essential for meeting beam acceleration requirements and ensuring the accelerator's long-term stable operation.

[0003] Existing technologies typically employ a phased voltage increase strategy combined with amplitude feedback during power loading. This involves real-time monitoring of the amplitude of the cavity sampling signal to determine the cavity's detuning state. To compensate for the cavity's thermal detuning caused by increased power, the system often requires a drive motor to power a fine-tuning ring or other mechanical structures, or to physically alter the cavity frequency by adjusting the cooling water temperature, thereby ensuring that the resonant frequency matches the RF operating frequency.

[0004] However, in pulsed operation mode, the leading edge overshoot of the cavity sampling signal severely interferes with the accurate determination of voltage amplitude. Furthermore, existing technologies rely entirely on slow-responding mechanical tuning mechanisms to track frequency shifts in real time during the dynamic power loading process. This approach not only results in a long and inefficient power loading process, but also makes the frequent, high-frequency, iterative adjustments of the mechanical mechanism during this stage highly susceptible to hardware wear and fatigue failure, severely impacting the operational reliability of the entire accelerator system. Summary of the Invention

[0005] This invention provides a high-frequency power loading control method and system for accelerators, which solves the defects in the prior art of power loading control of multiple high-frequency cavities in heavy ion accelerators, such as slow power loading speed due to reliance on mechanical tuning, easy wear of tuning mechanism, and voltage failure caused by electron multiplication effect. It achieves fast, highly reliable and mechanically lossless automatic power loading.

[0006] This invention provides a high-frequency power loading control method for accelerators, used for power loading control of multiple high-frequency cavities in a heavy ion accelerator. The method includes the following steps: S1. Set the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and set the initial pulse signal to a narrow pulse to generate a pulse excitation signal; S2. Acquire the intermediate frequency sampling signal of the high frequency cavity, and demodulate the intermediate frequency sampling signal to obtain its in-phase component and quadrature component; S3. Based on the in-phase component and quadrature component, extract multiple phase data points of the intermediate frequency sampling signal at the falling edge of the pulse and perform linear fitting to calculate the detuning frequency; S4. Adjust the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high frequency cavity; S5. While keeping the tuning mechanism of the high-frequency cavity in a static state, gradually increase the pulse width and repetition frequency of the pulse excitation signal, and after each increase, execute steps S2 to S4 again to perform frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency respectively, and complete the high-frequency power loading of each high-frequency cavity. S6. Switch the pulse excitation signal of each high-frequency cavity to the reference frequency, and use the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency.

[0007] According to the accelerator high-frequency power loading control method provided by the present invention, the step of demodulating the intermediate frequency sampling signal to obtain its in-phase and quadrature components includes: Two orthogonal signals with the same frequency as the intermediate frequency sampled signal are generated using a direct digital frequency synthesizer module. The intermediate frequency sampled signal is multiplied by the two quadrature signals respectively, and then filtered out by a low-pass filter to obtain the in-phase component and the quadrature component.

[0008] According to the accelerator high-frequency power loading control method provided by the present invention, the step of extracting multiple phase data points of the intermediate frequency sampling signal at the falling edge of the pulse based on the in-phase component and the quadrature component and performing linear fitting includes: The real-time phase value of the intermediate frequency sampled signal is calculated using the in-phase component and the quadrature component. After the pulse excitation is turned off, multiple phase values ​​within the pulse falling edge time period are extracted from the real-time phase value as multiple phase data points, and linear fitting is performed on the multiple phase data points to obtain the detuning frequency.

[0009] According to the accelerator high-frequency power loading control method provided by the present invention, the step of linearly fitting the plurality of phase data points includes: The least squares method is used to perform linear fitting on the multiple phase data points to calculate the rate of change of the phase value over time.

[0010] According to the accelerator high-frequency power loading control method provided by the present invention, the step of adjusting the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency includes: The frequency setting word of the direct digital frequency synthesizer is modified according to the detuning frequency, and the detuning frequency is used as a frequency offset to compensate the current frequency of the excitation signal, so that the frequency of the excitation signal dynamically tracks the real-time resonant frequency of the high-frequency cavity.

[0011] According to the accelerator high-frequency power loading control method provided by the present invention, the step of gradually increasing the pulse width and repetition frequency of the pulse excitation signal includes: The duty cycle and repetition frequency of the trigger are gradually increased by preset step values, and after each increase, steps S2 to S4 are executed again to perform frequency compensation.

[0012] According to the accelerator high-frequency power loading control method provided by the present invention, the intermediate frequency sampling signal is obtained by down-converting the radio frequency signal in the high-frequency cavity; wherein, the sampling clock of the intermediate frequency sampling signal, the operating clock of the direct digital frequency synthesizer, and the reference clock signal are kept in the same source and synchronized.

[0013] According to the accelerator high-frequency power loading control method provided by the present invention, the step of setting the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value includes: Obtain the upper limit of the threshold region for the electron multiplication effect generated by the high-frequency cavity; set the normal operating voltage value to be greater than the upper limit of the threshold region so that the radio frequency field strength in the high-frequency cavity directly crosses the threshold region of the electron multiplication effect.

[0014] The present invention also provides a high-frequency power loading control system for an accelerator, used for power loading control of multiple high-frequency cavities in a heavy ion accelerator, the system comprising the following modules: The modulation module is used to set the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and to set the initial pulse signal to a narrow pulse to generate a pulse excitation signal; The demodulation module is used to acquire the intermediate frequency sampling signal of the high frequency cavity and demodulate the intermediate frequency sampling signal to obtain its in-phase component and quadrature component. The calculation module is used to extract multiple phase data points of the intermediate frequency sampled signal at the falling edge of the pulse based on the in-phase component and the quadrature component, and perform linear fitting to calculate the detuning frequency; The control module is used to adjust the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high-frequency cavity. While keeping the tuning mechanism of the high-frequency cavity in a static state, it controls the modulation module to gradually increase the pulse width and repetition frequency of the pulse excitation signal. After each increase, it calls the demodulation module and calculation module again to perform frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency, respectively, thus completing the high-frequency power loading of each high-frequency cavity. After completing the high-frequency power loading, it is also used to switch the pulse excitation signal of each high-frequency cavity to the reference frequency and control the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency.

[0015] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the accelerator high-frequency power loading control method as described above.

[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the accelerator high-frequency power loading control method as described above.

[0017] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the accelerator high-frequency power loading control method as described above.

[0018] This invention provides a high-frequency power loading control method and system for accelerators. During the dynamic power build-up phase from zero to the rated value, by setting the amplitude of the initial intermediate frequency excitation signal to the normal operating voltage value and coordinating with a narrow pulse start-up, the radio frequency field strength within the high-frequency cavity can directly cross the threshold region of the electron multiplication effect, fundamentally suppressing the electron multiplication phenomenon during power loading. Cavity detuning detection is performed using the phase value of the pulse falling edge, effectively avoiding interference from pulse leading-edge overshoot on the sampling signal determination, ensuring the accuracy and robustness of detuning frequency calculation. By adjusting the excitation signal frequency in real time to track the cavity resonant frequency and maintaining the cavity tuning mechanism in a stationary state throughout the power loading process, a fast-response digital frequency compensation technology is used to replace the traditional slow mechanical displacement tuning. This not only significantly shortens the power build-up time and significantly improves loading efficiency but also completely solves the mechanical fatigue and failure problems caused by frequent tuning mechanism movements. During the system frequency alignment phase after power stabilization, the mechanical tuning mechanism is rationally activated, utilizing its high precision to accurately lock the frequencies of multiple cavities to a unified reference frequency, greatly enhancing the operational stability and lifespan of the accelerator system. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the high-frequency power loading control method for accelerators provided by the present invention.

[0020] Figure 2 This is a schematic diagram of the structure of a digital low-level control system provided by the present invention.

[0021] Figure 3 This is a schematic diagram of the modulation unit in the digital low-level control system provided by the present invention.

[0022] Figure 4 This is a schematic diagram of the demodulation unit in the digital low-level control system provided by the present invention.

[0023] Figure 5 This is a schematic diagram of the structure of the accelerator high-frequency power loading control system provided in an embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0025] The technical solutions of the present invention will now be described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0026] Hereinafter, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. For example, a plurality of processing units refers to two or more processing units.

[0027] Furthermore, in this embodiment of the invention, "upper," "lower," "left," and "right" are not limited to the orientation relative to the schematic placement of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings. In the accompanying drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the drawings do not reflect the actual dimensional proportions.

[0028] In this embodiment of the invention, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0029] In this embodiment of the invention, the term "module" typically refers to a logically divided functional structure. This "module" can be implemented purely in hardware, or a combination of hardware and software. In this embodiment of the invention, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, or both A and B existing simultaneously.

[0030] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this embodiment of the invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0031] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0032] First, let's explain the English abbreviations that appear in the text or accompanying images: FPGA: Field Programmable Gate Array; CPU: Central Processing Unit; PLC stands for Programmable Logic Controller. ADC: Analog-to-Digital Converter; DAC: Digital-to-Analog Converter; DDS: Direct Digital Synthesizer; DDC: Digital Down Converter; CPCI, CompactPCI, is a high-performance industrial-grade bus interface. PCI / PCIe: Peripheral Component Interconnect / Express, a system bus for interconnecting peripheral components; SPI: Serial Peripheral Interface, a serial peripheral interface bus; PC: Personal Computer, host computer; MSPS: Mega Samples Per Second.

[0033] A heavy-ion linear accelerator is a device that uses a high-frequency electric field in a resonant cavity to accelerate charged heavy ions along a linear trajectory. It is typically used to accelerate heavier ions than their weight. Heavy ions can sometimes be used to accelerate protons. Heavy ion linear accelerators can operate independently or as injectors in synchrotron accelerators, offering advantages such as easy injection and extraction, high transmission efficiency, high beam intensity and quality, and progressively increasing energy. Using heavy ion linear accelerators to artificially generate heavy ion beams of a certain energy and quality can be used for fundamental research in nuclear physics and has broad application prospects in materials science, nuclear medicine, radiobiology, aerospace, cancer treatment and diagnosis.

[0034] The low-level control system is an important component of the heavy-ion linear accelerator. Its main function is to adjust the dynamic characteristics of the resonant cavity, so that the cavity resonant frequency is consistent with the radio frequency operating frequency, and to dynamically adjust the output of the power source to realize the establishment, stabilization, regulation and protection functions of the accelerating electric field in the high-frequency cavity, so as to meet the beam acceleration requirements and the normal operation of the accelerator.

[0035] When the accelerator is first powered on, or after the high-frequency electric field protection drops to zero during equipment operation, it is necessary to control the high-frequency electric field to automatically load from zero to the set value. During the automatic power loading process, the low-level radio frequency excitation signal is amplified by the power source and fed to the high-frequency cavity to establish the electric field. This process mainly faces two challenges: (1) Cavity detuning detection and tuning control: On the one hand, when the device is first powered on, the cavity resonant frequency is far from the high-frequency operating frequency, and the cavity will reflect the input RF power; on the other hand, during the power loading process, as the input power increases, the temperature change caused by the cavity power loss will cause the cavity resonant frequency to shift. Therefore, in the automatic loading control process, cavity detuning detection and tuning control need to be performed in real time to make the RF operating frequency and the high-frequency cavity resonant frequency basically consistent.

[0036] (2) Electron multiplication effect: Once an RF electric field exists within the RF cavity, some electrons will detach from the cavity wall surface and be accelerated by the RF field. If the electrons are sufficiently accelerated, they may collide with another surface of the RF cavity, releasing several secondary electrons. When the field polarity changes, these secondary electrons can be accelerated again by the RF field. When the intensity and frequency of the RF field and the distance between the surfaces of the RF cavity are appropriate, a positive feedback effect may be triggered, a phenomenon known as the electron multiplication effect. When this phenomenon occurs, the electrons shuttling back and forth between the relative surfaces of the RF cavity may form a sufficiently strong current, causing the RF voltage to fail to reach the set value. Given the relative surface spacing and RF frequency, the electron multiplication effect will only occur at a specific RF voltage value or in the threshold region. When the RF system is running, if the RF voltage used to accelerate the beam is too high, this effect cannot be triggered. However, when the RF power is automatically loaded, the RF voltage gradually rises from zero to the voltage required for beam acceleration, at which point the electron multiplication effect may occur.

[0037] Currently, high-frequency low-level control systems in ambient-temperature linear accelerators commonly employ a phased approach to increasing power or voltage values ​​during power loading. Under this conventional logic, operators or control programs typically set a low initial voltage value in pulse mode and monitor the amplitude of the cavity's radio frequency sampling signal in real time. When the system detects an amplitude deviation, it uses logical judgment to control the mechanical tuning mechanism, such as driving a motor to physically displace the fine-tuning ring or adjusting the cavity's cooling water temperature to change its volume, thereby forcibly pulling the cavity's resonant frequency back to the operating frequency. This method often requires frequent switching between pulse and continuous wave modes when crossing the threshold region caused by the electron multiplication effect and is highly dependent on manual judgment. However, since cavity tuning is essentially a mechanical or thermodynamic process, its response speed exhibits significant lag, and the frequent reciprocating motion during high-frequency loading leads to severe wear and fatigue of the mechanical structure. Especially when processing pulse mode signals, the overshoot of the leading edge of the cavity sampling signal can seriously interfere with the accurate reading of the sampling voltage amplitude, causing the system to misjudge the detuning, which in turn leads to loading failure or equipment interlock protection.

[0038] In view of the bottlenecks of the above-mentioned prior art in terms of response speed, mechanical life and pulse signal processing accuracy, the present application provides a high-frequency power loading control scheme for pulsed-mode heavy ion linear accelerators. The scheme adopts digital frequency tracking technology, directly sets the initial excitation signal to the normal operating voltage and cooperates with the narrow pulse mode, and uses the phase linear fitting algorithm of the pulse falling edge to accurately extract the detuning frequency, so that the frequency of the excitation signal dynamically tracks the change of the cavity resonant frequency in the digital domain. This method ensures that the mechanical tuning mechanism of the cavity remains stationary throughout the power loading process, effectively suppresses the multipacting effect, eliminates the influence of pulse leading-edge overshoot on control accuracy, and realizes automatic power loading with high establishment speed and low hardware loss.

[0039] The accelerator high-frequency power loading control method provided by the embodiment of the present invention can be applied to radio frequency control scenarios in heavy ion linear accelerator systems, for example, radio frequency power loading control, radio frequency system start-up control and cavity resonance state tracking control for normal-temperature heavy ion linear accelerators and other application scenarios. In addition, the method provided by the embodiment of the present invention can also be applied to other systems that use radio frequency cavities for particle acceleration, for example, the radio frequency control link in proton accelerators or other types of linear accelerator systems. It can be understood that, in practical applications, the execution subject of the method may be the low-level radio frequency control system in the accelerator system, or a radio frequency control device composed of field programmable gate array (FPGA), digital signal processor or other controllers; in some implementation modes, the relevant control functions can also be implemented cooperatively by the upper computer and low-level radio frequency control hardware.

[0040] The embodiment of the present invention provides an accelerator high-frequency power loading control method, which is used for power loading control of multiple high-frequency cavities in a heavy ion accelerator, see Figure 1 , the method includes the following steps: S1, setting the amplitude value of the initial intermediate-frequency excitation signal as the normal operating voltage value, and setting the initial pulse signal as a narrow pulse to generate a pulse excitation signal; S2, acquiring an intermediate-frequency sampling signal of the high-frequency cavity, and performing demodulation processing on the intermediate-frequency sampling signal to obtain its in-phase component and quadrature component; S3, extracting a plurality of phase data points of the intermediate-frequency sampling signal at the falling edge of the pulse and performing linear fitting according to the in-phase component and quadrature component, and calculating the detuning frequency; S4, adjusting the frequency of the intermediate-frequency excitation signal in real time according to the detuning frequency, so as to track the resonant frequency of the high-frequency cavity; S5. While keeping the tuning mechanism of the high-frequency cavity in a static state, gradually increase the pulse width and repetition frequency of the pulse excitation signal, and after each increase, execute steps S2 to S4 again to perform frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency respectively, and complete the high-frequency power loading of each high-frequency cavity. S6. Switch the pulse excitation signal of each high-frequency cavity to the reference frequency, and use the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency.

[0041] It is worth noting that existing accelerator high-frequency power loading control schemes use the sampled signal amplitude as the basis for detuning detection, monitor the cavity RF sampling voltage in real time, set reasonable tuning logic to control the tuning mechanism, and use tuning structures such as fine-tuning loops or cooling water temperature to change the cavity resonant frequency to match the operating frequency. Since cavity tuning is usually achieved by a motor driving a mechanical tuning structure or controlling the cavity cooling water temperature, it suffers from slow tuning speed, frequent wear and tear on the tuning mechanism, resulting in long power loading processes and susceptibility to failure. Furthermore, relying on empirical values ​​or manual methods to determine the threshold voltage, especially for cavities with high threshold voltages, may induce electron multiplication. Finally, this scheme is applied to accelerators operating in continuous wave mode. For pulsed mode accelerators, the cavity RF sampling signal is a pulse waveform, and overshoot at the pulse leading edge can affect the determination of the sampling amplitude.

[0042] Therefore, this invention proposes a high-frequency power loading control method for heavy-ion linear accelerators operating in pulse mode. It employs a method of setting the required voltage in a narrow pulse mode to suppress the electron multiplication effect, eliminating the need for segmented voltage increases. During loading, cavity detuning is detected based on the phase value of the falling edge of the sampling signal pulse. By adjusting the excitation signal frequency while keeping the cavity tuning mechanism stationary, the excitation signal frequency tracks the cavity resonant frequency, achieving tuning control without frequent movement of the tuning mechanism.

[0043] In some specific embodiments of the present invention, the main body of the method for implementing the embodiments of the present invention is based on a digital low-level control system, which achieves precise loading of high-frequency power of the accelerator through the coordinated cooperation of hardware circuits and software algorithms.

[0044] The method in this embodiment of the invention is mainly executed by a digital controller, which is logically divided into a real-time processing layer and a strategy calculation layer: Real-time processing layer (can be implemented using FPGA): As the underlying execution core, it is responsible for performing highly deterministic signal processing tasks. Specifically, this includes: generating pulse-modulated excitation signals through a direct digital frequency synthesizer; demodulating the feedback intermediate frequency sampled signal using digital down-conversion technology to separate the in-phase component I and the quadrature component Q; and adjusting the output frequency according to the frequency word issued by the strategy calculation layer.

[0045] Strategy computation layer (can be implemented by a host PC / CPU): As the core of logical decision-making, it is responsible for executing complex mathematical operations and process control. Specifically, this includes: reading component data demodulated from the FPGA via an industrial-grade bus interface (such as CPCI or PCIe); processing the falling edge phase value of the pulse using a linear fitting algorithm to calculate the detuning frequency. Dynamically update pulse width, repetition frequency, and frequency offset instructions, and send the updated parameters to the FPGA.

[0046] The executing entity completes closed-loop control through the following hardware links: Signal conversion link: The intermediate frequency sampling signal of the high-frequency cavity is digitized by the analog-to-digital converter (ADC) and sent to the FPGA. The digital excitation signal generated by the FPGA is restored to an analog signal by the digital-to-analog converter (DAC) and sent to the power source.

[0047] Clock synchronization link: The clock reference unit provides a unified reference signal and local oscillator signal to ensure that the sampling clock, working clock and radio frequency signal in the system are strictly synchronized from the same source. This is the physical basis for ensuring the accuracy of phase detection.

[0048] External interaction link: The status of the cavity tuner is monitored through a PLC (Programmable Logic Controller) to ensure that the mechanical tuning mechanism remains in a fixed position during power loading and does not participate in real-time frequency compensation.

[0049] In actual operation, the execution unit first sets the target voltage and narrow pulse width parameters on the host PC and writes them to the FPGA registers via the CPCI bus. The FPGA generates timing-triggered excitation pulses based on the register values ​​to drive the high-frequency cavity. Subsequently, the FPGA acquires cavity feedback in real time and demodulates the I / Q data back to the PC. The PC uses mathematical software or a pre-compiled algorithm to analyze the falling edge phase value, dynamically calculates the frequency deviation, and corrects the frequency control word of the FPGA's internal Direct Digital Synthesizer (DDS). Finally, power loading is smoothly completed without manual intervention and with the mechanical tuner stationary.

[0050] The present invention will be described in detail below through specific embodiments.

[0051] The hardware architecture of the digital low-level control system is as follows: Figure 2As shown, the system includes a clock reference unit, a digital controller, an analog front-end, an amplifier, a high-frequency cavity, a tuner, a driver circuit, and a programmable logic controller. The clock reference unit includes a master oscillator and a local oscillator, providing a high-frequency operating reference signal and a local oscillator signal. The analog front-end includes a mixer and a bandpass filter, using the local oscillator signal for up-conversion and down-conversion, mixing the feedback signal and RF signal with the local oscillator signal to generate an intermediate frequency (IF) signal. The digital controller includes a DAC, an ADC, an FPGA, a CPU (central processing unit) in a PC, and a clock. The CPU and FPGA are connected via a high-performance industrial-grade bus interface technology (CompactPCI, CPCI). After generating the IF signal, the analog front-end inputs the IF signal to the FPGA for digital signal processing, and the DAC outputs the RF excitation signal corresponding to the IF sampling signal, which is then sent to the power source.

[0052] In this embodiment, high-frequency power loading control is implemented in an FPGA and a PC. The FPGA is configured with a modulation unit and a demodulation unit. The specific implementation steps include: Step 1, such as Figure 3 As shown, the modulation unit function is implemented in the FPGA. Modulation is mainly achieved through a DDS, a trigger module, a multiplier, and a limiter. The trigger module generates a narrow pulse signal with a specific frequency and pulse width based on the repetition frequency R and duty cycle D set by the host computer. The initial pulse width is set to a narrow pulse, such as 200µs. The DDS generates a sine or cosine signal with a specific frequency based on the frequency word F set by the host computer. This signal is multiplied by the amplitude value A set by the host computer, modulated by the pulse signal generated by the trigger module, and then output through a DAC to generate an analog intermediate frequency excitation signal. Unlike the segmented voltage increase method, here the amplitude value is directly set to the normal operating voltage value.

[0053] Step 2: The cavity samples the intermediate frequency signal, and the demodulation unit functions through digital down-conversion (DDC). For example... Figure 4 As shown, after being acquired and digitized by the ADC, the data is sent to the DDC in the FPGA for demodulation to obtain the I and Q components, and then transmitted to the host computer PC via the system bus (PCI or PCIe).

[0054] The intermediate frequency sampled signal can be represented as: (1), in, This is an intermediate frequency sampling voltage signal. Let A be the intermediate frequency sampling signal frequency, t be the time, and A be the frequency of the sampling signal. Let the amplitude and phase of the intermediate frequency sampled signal be respectively. Equation (1) can be expanded to obtain: (2), in, and They are respectively The I and Q components.

[0055] This embodiment utilizes the DDC demodulation algorithm, which uses DDS to generate two orthogonal signals with the same frequency as the sampled signal. and Then, multiply the sampled signal by the given information, and pass the result through a low-pass filter to remove high-frequency terms, thus obtaining the I and Q components. In the following formulas, the symbols... This represents a low-pass filter operation, and the calculation formula is: (3); (4).

[0056] Step 3: Calculate the amplitude of the intermediate frequency sampled signal on the host computer (PC). and phase value : (5), (6).

[0057] Within the pulse width, the cavity sampling signal and the excitation signal have the same frequency. After the pulse excitation is turned off, the cavity electric field gradually decays at the cavity resonant frequency, and the difference between the two is the detuning frequency. f is characterized by a linear decrease in the falling edge of the phase waveform of the intermediate frequency sampled signal; conversely, the detuning frequency can be obtained by linearly fitting the phase value of the falling edge of the pulse. f The host computer uses the detuning frequency as a reference. f The value is adjusted by modifying the DDS frequency setting word F to make the excitation signal frequency basically consistent with the cavity resonant frequency.

[0058] Step 4: Repeat steps 1 to 3, with the host computer controlling the trigger to gradually increase the pulse width and repetition frequency to the working value.

[0059] The technical solution of this invention has the advantages of high speed and high reliability, and is easy to integrate into existing low-level control systems without the need for additional hardware modules.

[0060] The following describes another specific embodiment. Figure 1 The execution process of each step is explained in detail.

[0061] This embodiment uses a 162.5MHz room-temperature linear accelerator as an example. The digital low-level control system of this accelerator operates normally in pulse mode with a repetition frequency of 10Hz, a duty cycle of 1%, and a rated operating voltage of 70kV. The specific structure of this system is still referred to Figure 2The clock unit uses the AD9516 clock chip, which includes a configurable analog phase-locked loop. The analog-to-digital converter (ADC) uses the AD9268 with a maximum sampling rate of 125 MSPS. The digital-to-analog converter (DAC) uses the AD9766 with a sampling rate of 200 MSPS. The FPGA is a Xilinx V5. A standard CPCI interface is used between the FPGA and the CPU.

[0062] The clock reference unit provides a 162.5MHz reference signal and a 150MHz local oscillator signal with a signal amplitude of 7dBm.

[0063] The FPGA configures the AD9516 via the SPI bus, using a 162.5MHz reference clock to multiply or divide the 162.5MHz reference signal, generating a 100MHz sampling clock which is sent to the analog-to-digital converter AD9268. A 200MHz DAC clock is generated and sent to the digital-to-analog converter AD9766, and a 200MHz operating clock is generated and sent to the digital controller FPGA. This design ensures that the sampling clock, the direct digital frequency synthesizer (DDS) clock, and the reference signal are synchronized, eliminating random phase jitter introduced by asynchronous clocks and providing a physical basis for high-precision phase measurement.

[0064] S1. Set the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and set the initial pulse signal to a narrow pulse to generate a pulse excitation signal; At the initial stage of power loading, initialization settings are performed first. For a 162.5MHz room-temperature linear accelerator system, its normal operation is in pulse mode with a repetition frequency of 10Hz, a duty cycle of 1%, and a rated operating voltage of 70kV. In this embodiment, the amplitude of the initial intermediate frequency excitation signal is directly set to the normal operating voltage value (i.e., the level corresponding to 70kV), and the initial pulse signal is set to a narrow pulse (e.g., 200μs). By directly applying the rated voltage, the radio frequency field strength in the high-frequency cavity can directly cross the threshold region of the electron multiplication effect, thus physically suppressing the positive feedback current caused by the electron multiplication phenomenon. Due to the use of the narrow pulse mode, even under high voltage conditions, the temperature rise caused by cavity power loss is within a safe and controllable range, avoiding damage to the hardware.

[0065] S2. Acquire the intermediate frequency sampling signal of the high frequency cavity, and demodulate the intermediate frequency sampling signal to obtain its in-phase component and quadrature component; The system then enters the signal acquisition and processing stage, where it acquires the feedback signal from the high-frequency cavity through a digital controller. To ensure measurement accuracy, the clock reference unit uses the AD9516 clock chip to generate a synchronous sampling clock and operating clock.

[0066] Specifically, the system uses a 162.5MHz reference clock to generate a 100MHz sampling clock, which is fed into the AD9268 analog-to-digital converter (ADC), and generates a 200MHz DAC clock, which is fed into the AD9766 digital-to-analog converter (DAC). The 162.5MHz RF sampling signal is down-converted to a 12.5MHz intermediate frequency (IF) signal by the analog front-end, then digitized by the ADC and sent to the FPGA for digital down-conversion demodulation. The FPGA uses a 200MHz clock to perform DDC demodulation on the AD9268 sampling data and modulates the DDS output. Inside the FPGA, the DDS generates a quadrature signal with the same frequency, which is multiplied by the sampling signal and filtered by a low-pass filter to remove high-frequency terms, yielding the in-phase component (I) and the quadrature component (Q).

[0067] These component data are transmitted to the host computer CPU in real time via the CPCI high-performance bus.

[0068] S3. Based on the in-phase component and quadrature component, extract multiple phase data points of the intermediate frequency sampling signal at the falling edge of the pulse and perform linear fitting to calculate the detuning frequency; After acquiring the I and Q components, detuning detection is performed. The host computer calculates the amplitude and phase of the intermediate frequency sampling signal according to formulas (5) and (6). In this embodiment, the frequency deviation is obtained by linearly fitting the phase value of the falling edge of the pulse. After the narrow pulse excitation is turned off, the cavity electric field decays at its inherent resonant frequency, and the difference between this frequency and the excitation frequency is expressed as the linear slope of the falling edge phase value. Within a preset time window after the pulse excitation signal is turned off, the system extracts phase data points and uses the least squares method to fit and calculate the rate of change of phase with time, thereby accurately obtaining the detuning frequency. This method completely avoids the interference of pulse leading-edge overshoot on amplitude judgment, significantly improving the robustness of detuning detection.

[0069] S4. Adjust the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high frequency cavity; Next, frequency feedback compensation is implemented. The host computer modifies the frequency setting word F in the DDS of the FPGA based on the calculated detuning frequency. In practice, the detuning frequency is used as a frequency offset to compensate for the current frequency of the excitation signal. Through this digital frequency correction, the frequency of the output excitation signal tracks the resonant frequency of the cavity in real time, maintaining a basic consistency between the two. This process achieves dynamic tuning of the excitation source to follow the cavity frequency.

[0070] S5. While keeping the tuning mechanism of the high-frequency cavity in a static state, gradually increase the pulse width and repetition frequency of the pulse excitation signal, and after each increase, execute steps S2 to S4 again to perform frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency respectively, thus completing the high-frequency power loading of each high-frequency cavity.

[0071] Finally, the entire power loading process is executed. Throughout the automatic loading cycle, the host computer controls the PLC to keep the cavity tuning mechanism (such as the fine-tuning ring or cooling water temperature control) in a static state, without any mechanical displacement. In this state, the control trigger gradually increases the pulse width and repetition frequency in preset step values ​​(e.g., gradually increasing from 200μs, 1Hz to the rated value), and the system cyclically executes the detection and compensation logic from S2 to S4. After each step is completed, the system performs a real-time frequency calibration until the pulse width and repetition frequency reach the preset target pulse width and target repetition frequency, respectively. This method replaces mechanical tuning actions with algorithmic compensation, eliminating wear on the tuning mechanism.

[0072] The accelerator power loading control method provided by this invention directly sets the full operating voltage and uses a narrow pulse to allow the radio frequency field strength to directly cross the electric threshold region, thus suppressing the electron multiplication effect at its source. During the loading process, digital frequency tracking technology replaces mechanical physical tuning, keeping the tuning mechanism stationary, eliminating hardware wear, and improving system reliability. The detuning frequency is extracted using linear phase fitting of the pulse falling edge, effectively avoiding interference from pulse leading-edge overshoot on amplitude detection and significantly improving detection accuracy.

[0073] S6. Switch the pulse excitation signal of each high-frequency cavity to the reference frequency, and use the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency.

[0074] Specifically, after all the high-frequency cavities requiring power loading in the heavy ion accelerator have undergone rapid and lossless power loading through steps S1 to S5, the entire multi-cavity system enters the final stage of beam acceleration preparation. At this point, the control system switches the pulse excitation signals of each high-frequency cavity from their respective dynamically tracked frequencies to a common, preset reference frequency.

[0075] Subsequently, the control system activates the tuning mechanisms of each high-frequency cavity, which had previously been stationary (e.g., by controlling a motor to drive a fine-tuning ring via a PLC). Through physical adjustment, the resonant frequency of each cavity is precisely adjusted to match the reference frequency. After this step, all high-frequency cavities not only reach their rated power, but their operating frequencies and phases are also unified, and the entire accelerator system enters a ready state to introduce a beam for acceleration at any time.

[0076] This invention also provides an accelerator high-frequency power loading control system for power loading control of multiple high-frequency cavities in a heavy ion accelerator. The system is used to implement the accelerator power loading control method described in the above embodiments, such as... Figure 5 As shown, the system includes: modulation module 10, demodulation module 20, calculation module 30 and control module 40.

[0077] The modulation module 10 is used to set the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and to set the initial pulse signal to a narrow pulse to generate a pulse excitation signal. The demodulation module 20 is used to acquire the intermediate frequency sampling signal of the high frequency cavity and demodulate the intermediate frequency sampling signal to obtain its in-phase component and quadrature component. The calculation module 30 is used to extract multiple phase data points of the intermediate frequency sampling signal at the falling edge of the pulse based on the in-phase component and the quadrature component, and perform linear fitting to calculate the detuning frequency; The control module 40 is used to adjust the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high-frequency cavity. While keeping the tuning mechanism of the high-frequency cavity in a static state, it controls the modulation module 10 to gradually increase the pulse width and repetition frequency of the pulse excitation signal. After each increase, it calls the demodulation module 20 and the calculation module 30 again to perform frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and the preset target repetition frequency, respectively, thus completing the high-frequency power loading of each high-frequency cavity. After completing the high-frequency power loading, it is also used to switch the pulse excitation signal of each high-frequency cavity to the reference frequency and control the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency.

[0078] The internal logic of the accelerator high-frequency power loading control system corresponds to the accelerator high-frequency power loading control method described above, and will not be repeated here.

[0079] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other through the communication bus 640. The processor 610 can call logic instructions in the memory 630 to execute an accelerator high-frequency power loading control method, which includes: S1, setting the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and setting the initial pulse signal to a narrow pulse to generate a pulse excitation signal; S2, acquiring the intermediate frequency sampling signal of the high-frequency cavity, and demodulating the intermediate frequency sampling signal to obtain its in-phase component and quadrature component; S3, extracting multiple phase data points of the intermediate frequency sampling signal at the falling edge of the pulse based on the in-phase component and quadrature component, and performing linear fitting to calculate the detuning frequency; S4, calculating the detuning frequency based on the detuning frequency. S5. While keeping the tuning mechanism of the high-frequency cavity in a static state, gradually increase the pulse width and repetition frequency of the pulse excitation signal, and after each increase, execute steps S2 to S4 again for frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency, respectively, to complete the high-frequency power loading of each high-frequency cavity; S6. Switch the pulse excitation signal of each high-frequency cavity to the reference frequency, and use the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency. In addition, the logic instructions in the memory 630 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage media include: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media that can store program code.

[0080] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the accelerator high-frequency power loading control method provided by the above methods. The method includes: S1, setting the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and setting the initial pulse signal to a narrow pulse to generate a pulse excitation signal; S2, acquiring the intermediate frequency sampling signal of the high-frequency cavity, and demodulating the intermediate frequency sampling signal to obtain its in-phase component and quadrature component; S3, extracting the multiple components of the intermediate frequency sampling signal at the falling edge of the pulse based on the in-phase component and quadrature component. S4. The frequency of the intermediate frequency excitation signal is adjusted in real time according to the detuning frequency to track the resonant frequency of the high-frequency cavity. S5. While keeping the tuning mechanism of the high-frequency cavity in a static state, the pulse width and repetition frequency of the pulse excitation signal are gradually increased, and after each increase, steps S2 to S4 are executed again for frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency, respectively, to complete the high-frequency power loading of each high-frequency cavity. S6. The pulse excitation signals of each high-frequency cavity are uniformly switched to the reference frequency, and the resonant frequency of each high-frequency cavity is tracked by the tuning mechanism of the high-frequency cavity to the reference frequency.

[0081] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the accelerator high-frequency power loading control method provided by the above methods. The method includes: S1, setting the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and setting the initial pulse signal to a narrow pulse to generate a pulse excitation signal; S2, acquiring the intermediate frequency sampling signal of the high-frequency cavity, and demodulating the intermediate frequency sampling signal to obtain its in-phase and quadrature components; S3, based on the in-phase and quadrature components, extracting multiple phase data points of the intermediate frequency sampling signal at the falling edge of the pulse and performing linear fitting, and calculating... S4. Calculate the detuning frequency; S5. Adjust the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high-frequency cavity; S6. While keeping the tuning mechanism of the high-frequency cavity in a static state, gradually increase the pulse width and repetition frequency of the pulse excitation signal, and after each increase, execute steps S2 to S4 again for frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency, respectively, to complete the high-frequency power loading of each high-frequency cavity; S7. Switch the pulse excitation signal of each high-frequency cavity to the reference frequency, and track the resonant frequency of each high-frequency cavity to the reference frequency through the tuning mechanism of the high-frequency cavity.

[0082] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0083] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features in the formula. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling high-frequency power loading in an accelerator, characterized in that, The method for power loading control of multiple high-frequency cavities in a heavy ion accelerator includes: S1. Set the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and set the initial pulse signal to a narrow pulse to generate a pulse excitation signal; S2. Acquire the intermediate frequency sampling signal of the high frequency cavity, and demodulate the intermediate frequency sampling signal to obtain its in-phase component and quadrature component; S3. Based on the in-phase component and quadrature component, extract multiple phase data points of the intermediate frequency sampling signal at the falling edge of the pulse and perform linear fitting to calculate the detuning frequency; S4. Adjust the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high frequency cavity; S5. While keeping the tuning mechanism of the high-frequency cavity in a static state, gradually increase the pulse width and repetition frequency of the pulse excitation signal, and after each increase, execute steps S2 to S4 again to perform frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency respectively, and complete the high-frequency power loading of each high-frequency cavity. S6. Switch the pulse excitation signal of each high-frequency cavity to the reference frequency, and use the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency.

2. The accelerator high-frequency power loading control method according to claim 1, characterized in that, The step of demodulating the intermediate frequency sampled signal to obtain its in-phase and quadrature components includes: Two orthogonal signals with the same frequency as the intermediate frequency sampled signal are generated using a direct digital frequency synthesizer module. The intermediate frequency sampled signal is multiplied by the two quadrature signals respectively, and then filtered out by a low-pass filter to obtain the in-phase component and the quadrature component.

3. The accelerator high-frequency power loading control method according to claim 1, characterized in that, The step of extracting multiple phase data points of the intermediate frequency sampled signal at the falling edge of the pulse based on the in-phase component and the quadrature component, and performing linear fitting, includes: The real-time phase value of the intermediate frequency sampled signal is calculated using the in-phase component and the quadrature component. After the pulse excitation is turned off, multiple phase values ​​within the pulse falling edge time period are extracted from the real-time phase value as multiple phase data points, and linear fitting is performed on the multiple phase data points to obtain the detuning frequency.

4. The accelerator high-frequency power loading control method according to claim 3, characterized in that, The step of performing linear fitting on the plurality of phase data points includes: The least squares method is used to perform linear fitting on the multiple phase data points to calculate the rate of change of the phase value over time.

5. The accelerator high-frequency power loading control method according to claim 1, characterized in that, The step of adjusting the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency includes: The frequency setting word of the direct digital frequency synthesizer is modified according to the detuning frequency, and the detuning frequency is used as a frequency offset to compensate the current frequency of the excitation signal, so that the frequency of the excitation signal dynamically tracks the real-time resonant frequency of the high-frequency cavity.

6. The accelerator high-frequency power loading control method according to claim 1, characterized in that, The step of gradually increasing the pulse width and repetition frequency of the pulse excitation signal includes: The duty cycle and repetition frequency of the trigger are gradually increased by preset step values, and after each increase, steps S2 to S4 are executed again to perform frequency compensation.

7. The accelerator high-frequency power loading control method according to claim 1, characterized in that, The intermediate frequency sampling signal is obtained by down-converting the radio frequency signal in the high frequency cavity; wherein the sampling clock of the intermediate frequency sampling signal, the operating clock of the direct digital frequency synthesizer, and the reference clock signal are kept in the same source and synchronized.

8. The accelerator high-frequency power loading control method according to claim 1, characterized in that, The setting of the initial intermediate frequency excitation signal amplitude value to the normal operating voltage value includes: Obtain the upper limit of the threshold region for the electron multiplication effect generated by the high-frequency cavity; set the normal operating voltage value to be greater than the upper limit of the threshold region so that the radio frequency field strength in the high-frequency cavity directly crosses the threshold region of the electron multiplication effect.

9. A high-frequency power loading control system for an accelerator, characterized in that, The system is used for power loading control of multiple high-frequency cavities in a heavy ion accelerator, and includes: The modulation module is used to set the amplitude value of the initial intermediate frequency excitation signal to the normal operating voltage value, and to set the initial pulse signal to a narrow pulse to generate a pulse excitation signal; The demodulation module is used to acquire the intermediate frequency sampling signal of the high frequency cavity and demodulate the intermediate frequency sampling signal to obtain its in-phase component and quadrature component. The calculation module is used to extract multiple phase data points of the intermediate frequency sampled signal at the falling edge of the pulse based on the in-phase component and the quadrature component, and perform linear fitting to calculate the detuning frequency; The control module is used to adjust the frequency of the intermediate frequency excitation signal in real time according to the detuning frequency to track the resonant frequency of the high-frequency cavity. While keeping the tuning mechanism of the high-frequency cavity in a static state, it controls the modulation module to gradually increase the pulse width and repetition frequency of the pulse excitation signal. After each increase, it calls the demodulation module and calculation module again to perform frequency compensation until the pulse width and repetition frequency reach the preset target pulse width and preset target repetition frequency, respectively, thus completing the high-frequency power loading of each high-frequency cavity. After completing the high-frequency power loading, it is also used to switch the pulse excitation signal of each high-frequency cavity to the reference frequency and control the tuning mechanism of the high-frequency cavity to track the resonant frequency of each high-frequency cavity to the reference frequency.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, are used to implement the accelerator high-frequency power loading control method as described in any one of claims 1-8.

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