An IGBT device and method of manufacture

Abstract

The application discloses an IGBT device and a preparation method, and relates to the technical field of power semiconductor devices, and comprises a collector, a P-type collector, an N-type cutoff layer, an N-type drift region, an N-type current diffusion layer, a P-type body region, a P+ contact region, an N+ contact region, an emitter, a first SiO2 gate dielectric layer and a first polysilicon gate; the collector, the P-type collector, the N-type cutoff layer, the N-type drift region, the N-type current diffusion layer and the P-type body region are sequentially arranged; the P+ contact region and the N+ contact region are arranged side by side on one side of the P-type body region, and the emitter is arranged on one side of the P+ contact region and the N+ contact region; a high dielectric constant medium region and a P column are arranged on one side of the N-type cutoff layer and are oppositely arranged on both sides of the N-type drift region; the first polysilicon gate is arranged on one side of the high dielectric constant medium region and is separated from the N-type current diffusion layer, the P-type body region, the N+ contact region and the emitter through the first SiO2 gate dielectric layer. The application reduces the turn-off loss of the device.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to an IGBT device and a method for fabricating the IGBT device. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors) are the most widely used gate-controlled device structure in power devices. Because IGBTs operate on a bipolar transport mechanism, they exhibit conductivity modulation effects, resulting in lower on-state voltage drop and higher current density compared to unipolar devices. Furthermore, their gate voltage control and excellent switching characteristics make IGBTs a new generation of power devices that combine high voltage withstand capability with low loss. As a representative of key materials in integrated circuits, High-K materials (high dielectric constant materials) possess advantages such as higher dielectric constant, better gate control capability, wider bandgap, superior interface characteristics, and better thermal stability than traditional SiO2. They are ideal materials for fabricating gate dielectrics for semiconductor power devices and have broad application prospects in microelectronics fields such as very large-scale integrated circuits, low-power logic devices, and memory.

[0003] Switching losses are a core parameter for measuring the dynamic performance of power devices and directly affect system efficiency. In high-frequency switching scenarios, turn-off losses often become the main source of switching losses. For bipolar devices, due to the minority carrier storage effect, a longer reverse recovery process is required during turn-off, resulting in a significant increase in turn-off losses. Summary of the Invention

[0004] The present invention aims to at least solve one of the aforementioned technical problems existing in the prior art. Therefore, the object of the present invention is to provide an IGBT device that facilitates optimized carrier distribution and extraction path, shortens reverse recovery time, reduces turn-off tail current, and lowers the turn-off loss of the IGBT device.

[0005] The present invention also provides a method for preparing the above-mentioned IGBT device.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An IGBT device, comprising: Collector, P-type collector, N-type cutoff layer, N-type drift region, N-type current diffusion layer, P-type body region, P+ contact region, N+ contact region, emitter, first SiO2 gate dielectric layer, first polysilicon gate; Along the thickness direction of the IGBT device, the collector, P-type collector, N-type cutoff layer, N-type drift region, N-type current diffusion layer and P-type body region are arranged sequentially. The P+ contact region and the N+ contact region are arranged side by side on the side of the P-type body region away from the N-type current diffusion layer, and the emitter is located on the side of the P+ contact region and the N+ contact region away from the P-type body region; A high dielectric constant dielectric region and a P-pillar are provided on the side of the N-type cutoff layer away from the P-type collector, and the high dielectric constant dielectric region and the P-pillar are arranged opposite each other on both sides of the N-type drift region. The first polysilicon gate is disposed on the side of the high dielectric constant dielectric region away from the N-type cutoff layer; wherein, the first polysilicon gate is separated from the N-type current diffusion layer, the P-type body region, the N+ contact region and the emitter stacked sequentially by the first SiO2 gate dielectric layer.

[0007] The beneficial effects of the IGBT device provided by this invention are at least as follows: This application adopts a structural design with alternating P-pillars, N-type drift regions, and high-dielectric-constant dielectric regions. By setting P-pillars and high-dielectric-constant dielectric regions in the N-type drift region, the N-type drift region can use a higher doping concentration and a thinner thickness at the same voltage rating, thereby significantly reducing the resistance of the N-type drift region. This design reduces the number of stored charge carriers, and combined with the P-type hole channel formed between the first polysilicon gate and the N-type current diffusion layer, effectively shortens the reverse recovery time, reduces the turn-off loss of the IGBT device, and improves its performance. Simultaneously, the high-dielectric-constant dielectric provides superior gate control capability, helping to improve the gate's control efficiency over the channel region, thereby reducing Miller capacitance and gate charge during switching, and decreasing switching losses. Furthermore, the alternating arrangement of the P-pillar, N-type drift region, and high-dielectric-constant dielectric region enhances the lateral electric field strength of the N-type drift region, allowing for more complete depletion of the stored charge carriers, eliminating the risk of local breakdown, and improving the IGBT device's breakdown voltage. In addition, the sequentially arranged N-type current diffusion layer, P-type body region, and the parallel P+ and N+ contact regions on the side of the P-type body region away from the N-type current diffusion layer optimize carrier distribution and extraction paths, further shortening the reverse recovery time, reducing the turn-off tail current, and further lowering the IGBT device's turn-off loss.

[0008] The IGBT device described above further includes: an N+ short-circuit region, wherein the N+ short-circuit region and the P-type collector are disposed side by side on the collector; wherein the N+ short-circuit region is embedded in the P-type collector along the width direction of the IGBT device for reverse conduction of current.

[0009] In the IGBT device described above, the cross-sectional area of ​​the P-type collector along the thickness direction of the IGBT device is greater than the cross-sectional area of ​​the N+ short-circuit region along the thickness direction of the IGBT device.

[0010] The IGBT device described above further includes: a second SiO2 gate dielectric layer and a second polysilicon gate; The second polysilicon gate is disposed on the side of the P-pillar away from the N-type cutoff layer. The second polysilicon gate is separated from the P-pillar, N-type current diffusion layer, P-type body region and P+ contact region stacked sequentially by the second SiO2 gate dielectric layer.

[0011] As described above, in an IGBT device, the second SiO2 gate dielectric layer includes a first separation structure and a second separation structure. Along the width direction of the IGBT device, the second polysilicon gate is separated from the sequentially stacked N-type current diffusion layer, P-type body region, and P+ contact region by the first separation structure. Along the thickness direction of the IGBT device, the second separation structure embeds a P-pillar and separates the P-pillar from the second polysilicon gate.

[0012] As described above, in an IGBT device, the first SiO2 gate dielectric layer includes a third separation structure and a fourth separation structure; along the width direction of the IGBT device, the first polysilicon gate is separated from the sequentially stacked N-type current diffusion layer, P-type body region, and P+ contact region by the third separation structure; along the thickness direction of the IGBT device, the fourth separation structure is embedded in the emitter and separates the emitter from the first polysilicon gate.

[0013] In the IGBT device described above, the material of the high dielectric constant dielectric region is any one of hafnium oxide, aluminum oxide, silicon nitride, and barium titanate.

[0014] The IGBT device described above is made of silicon carbide.

[0015] This invention also provides a method for fabricating an IGBT device, which includes the following steps: Substrate preparation: Select materials to prepare the N-type cutoff layer; First epitaxial layer growth: Along the thickness direction of the IGBT device, an N-type drift region is prepared on the surface of the N-type cutoff layer; First etching: The first and second trenches are formed in the N-type drift region (13) by using a dry etching process; Filling: P-pillars and high dielectric constant dielectric regions are formed in the first and second trenches respectively by filling materials; Secondary epitaxial layer growth: An N-type current diffusion layer is prepared on the surface of the N-type drift region far from the N-type cutoff layer; Three-stage epitaxial layer growth: A P-type bulk region is prepared on the surface of the N-type current diffusion layer far from the N-type drift region; Secondary etching: Along the width direction of the IGBT device, a third trench is formed on the same side of the N-type current diffusion layer and the P-type body region. Trench gate formation: The first SiO2 gate dielectric layer is formed in the third trench by dry oxidation process, and the first polysilicon gate is formed in the first SiO2 gate dielectric layer by photolithography and dry etching process. Emitter ion implantation: Ions are implanted into the surface of the P-type body region away from the N-type current diffusion layer to form N+ contact region and P+ contact region through ion implantation process; Collector ion implantation: Ions are implanted into the surface of the N-type cutoff layer away from the N-type drift region to form a P-type collector; Metallization: Emitters are formed on the surfaces of the P+ and N+ contact regions away from the P-type body region using sputtering or evaporation processes, and collectors are formed on the side of the P-type collector away from the N-type cutoff layer using sputtering processes, in order to fabricate IGBT devices.

[0016] The method for fabricating an IGBT device as described above employs an inductively coupled plasma dry etching process.

[0017] The beneficial effects of the fabrication method for the aforementioned IGBT device provided by this invention are at least as follows: First, by filling materials in the first and second trenches after a single etching step, a superjunction P-pillar and a high-dielectric-constant dielectric region are simultaneously formed, thereby integrating the fabrication process of the superjunction structure and the high-gate-control capability dielectric layer, simplifying the process flow, reducing the number of etching steps, and lowering manufacturing costs and process complexity. Second, this method sequentially grows an N-type current diffusion layer and a P-type body region before the subsequent trench gate formation, optimizing carrier distribution and extraction paths, avoiding the adverse effects of additional high-temperature processes on the high-dielectric-constant dielectric region, and exhibiting good process compatibility. Third, the IGBT device fabricated using this method not only possesses the advantages of high voltage withstand and low on-resistance of the superjunction structure, but also enhances gate control capability through the high-dielectric-constant dielectric region, effectively suppressing the Miller effect and minority carrier storage effect under high-frequency switching, effectively reducing turn-off losses and switching losses, and improving the overall performance of the IGBT device in high-frequency power conversion systems.

[0018] The method for fabricating an IGBT device as described above uses an inductively coupled plasma dry etching process. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a traditional IGBT device; Figure 2 This is a schematic diagram of the structure of the IGBT device according to an embodiment of the present invention; Figure 3 A process flow diagram for fabricating the IGBT device according to an embodiment of the present invention.

[0020] Reference numerals: 11-N+ contact region; 12-N-type current diffusion layer; 13-N-type drift region; 14-N-type cutoff layer; 15-N+ short-circuit region; 21-P+ contact region; 22-P-type body region; 23-P-pillar; 24-P-type collector; 31-emitter; 32-first polysilicon gate; 33-second polysilicon gate; 34-collector; 41-first SiO2 gate dielectric layer; 411-third separator structure; 412-fourth separator structure; 42-second SiO2 gate dielectric layer; 421-first separator structure; 422-second separator structure; 43-high dielectric region. Detailed Implementation

[0021] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0022] In the description of this application, it should be understood that if directional descriptions are involved, such as up, down, front, back, left, right, etc., indicating the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0023] In the description of this application, if words such as several, greater than, less than, exceeding, above, below, or within appear, "several" means one or more, "more than" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the number itself, and "above," "below," "within," etc. are understood to include the number itself.

[0024] In the description of this application, the use of terms such as "first" and "second" is for the purpose of distinguishing technical features only, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0025] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0026] like Figures 2-3 As shown, an IGBT device provided in an embodiment of the present invention includes: The IGBT device comprises a collector 34, a P-type collector 24, an N-type cutoff layer 14, an N-type drift region 13, an N-type current diffusion layer 12, a P-type body region 22, a P+ contact region 21, an N+ contact region 11, an emitter 31, a first SiO2 gate dielectric layer 41, and a first polysilicon gate 32. Along the thickness direction of the IGBT device, the collector 34, P-type collector 24, N-type cutoff layer 14, N-type drift region 13, N-type current diffusion layer 12, and P-type body region 22 are sequentially arranged. The P+ contact region 21 and N+ contact region 11 are arranged side-by-side on the side of the P-type body region 22 away from the N-type current diffusion layer 12. The emitter 31 is disposed on the side of the P+ contact region 21 and the N+ contact region 11 away from the P-type body region 22; a high dielectric constant dielectric region 43 and a P-pillar 23 are disposed on the side of the N-type cutoff layer 14 away from the P-type collector 24, and the high dielectric constant dielectric region 43 and the P-pillar 23 are disposed opposite to each other on both sides of the N-type drift region 13; the first polysilicon gate 32 is disposed on the side of the high dielectric constant dielectric region 43 away from the N-type cutoff layer 14; wherein, the first polysilicon gate 32 is separated from the N-type current diffusion layer 12, the P-type body region 22, the N+ contact region 11 and the emitter 31 stacked sequentially by the first SiO2 gate dielectric layer 41.

[0027] Specifically, the collector 34 and emitter 31 are used to form ohmic contacts with the external circuit; the collector 34 is connected to the high voltage terminal (positive terminal) of the external circuit, and the emitter 31 is connected to the low voltage terminal (negative terminal / ground) of the external circuit. The first polysilicon gate 32 is used to receive the switching signal and induce a MOS channel on the surface of the P-type body region 22 through the first SiO2 gate dielectric layer 41 to control the injection of electrons into the N-type drift region 13, thereby triggering the device to turn on or off.

[0028] Specifically, one end of the P-type collector 24 is connected to the collector 34, and the other end is connected to the N-type cutoff layer 14, which is used to inject a large number of holes (carriers) into the N-type drift region 13 when the IGBT device is turned on.

[0029] Specifically, the N-type cutoff layer 14 is connected to the P-type collector 24 at one end and to the N-type drift region 13 at the other end. It is used to prevent the depletion layer from extending to the P-type collector 24 when the IGBT device is turned off, thereby reducing turn-off losses and improving breakdown voltage. The depletion layer is a high-resistivity space charge region with no free carriers, composed of immobile ionic charges, when the PN junction interface between the P-type body region 22 and the N-type drift region 13 is reverse biased. It then extends towards the less doped side (mainly the N-type drift region 13) as the voltage increases. If the depletion layer extends excessively into the P-type collector 24, it will carry away a large number of holes from the P-type collector 24, exacerbating the turn-off tail current and increasing the turn-off loss, thereby causing PN junction interface punch-through breakdown. Therefore, by setting the N-type cutoff layer 14, the extension of the depletion layer can be effectively prevented, the turn-off loss can be reduced, and the breakdown voltage can be improved.

[0030] Specifically, one end of the N-type drift region 13 is connected to the N-type current diffusion layer 12, and the other end is connected to the N-type cutoff layer 14, which is used to withstand most of the reverse voltage when the IGBT device is turned off; when the IGBT device is turned on, the interior of the N-type drift region 13 is filled with electrons and holes, resulting in conductivity modulation and exhibiting a low resistance state.

[0031] Specifically, one end of the N-type current diffusion layer 12 is connected to the P-type body region 22, and the other end is connected to the N-type drift region 13, so that electrons flowing out of the MOS channel enter the N-type drift region 13 more evenly. When the IGBT device is turned on, the N-type current diffusion layer 12 forms a potential barrier for holes, confining the holes in the N-type drift region 13 to enhance conductivity modulation. When a voltage is applied to the first SiO2 gate dielectric layer 41, the N+ contact region 11 is connected to the N-type current diffusion layer 12 through the MOS channel, so that electrons enter the N-type current diffusion layer 12 from the N+ contact region 11, thereby triggering the P-type collector 24 to inject a large number of holes into the N-type drift region 13, inducing the conductivity modulation effect of the N-type drift region 13, thereby significantly reducing the resistance of the N-type drift region 13 and obtaining a low on-state voltage drop, so that the IGBT device can conduct a large current with an extremely low on-state voltage drop.

[0032] Specifically, one end of the P-type body region 22 is connected to the P+ contact region 21, and the other end is connected to the N-type current diffusion layer 12, serving as the carrier of the MOS channel. Under the control of the first polysilicon gate 32, the surface of the P-type body region 22 forms an N-type inversion layer (i.e., the MOS channel) that blocks / turns off electron flow.

[0033] Specifically, the first SiO2 gate dielectric layer 41 is disposed between the first polysilicon gate 32 and the P-type body region 22 and the N-type current diffusion layer 12, isolating the first polysilicon gate 32 from other regions, while allowing the electric field generated by the electrode voltage of the first polysilicon gate 32 to penetrate, so as to control the formation of the MOS channel.

[0034] Specifically, the first SiO2 gate dielectric layer 41 separates the first polysilicon gate 32 from the N-type current diffusion layer 12, forming a P-type hole channel between the first polysilicon gate 32 and the N-type current diffusion layer 12. During the IGBT device's turn-on period, the holes injected from the collector 34 first pass through the N-type drift region 13 and then diffuse towards the emitter 31. During this process, the hole concentration gradually decreases from the collector 34 side to the emitter 31 side, forming a potential barrier in the N-type current diffusion layer 12, suppressing the extraction of holes by the P-pillar 23, thereby enhancing the conductance modulation of the IGBT device and reducing the on-state voltage drop. During the turn-off transient period, as the potential of the P-pillar 23 increases, the P-type hole channel opens, rapidly extracting holes from the N-type drift region 13, thereby shortening the turn-off time and reducing turn-off losses.

[0035] Specifically, this application employs a structural design with alternating P-pillars 23, N-type drift regions 13, and high-dielectric-constant dielectric regions 43. The introduction of P-pillars 23 and high-dielectric-constant dielectric regions 43 into the N-type drift region 13 allows for higher doping concentrations and thinner thicknesses within the same voltage rating, thereby significantly reducing the resistance of the N-type drift region 13. This design reduces the number of stored charge carriers. Combined with the P-type hole channel formed between the first polysilicon gate 32 and the N-type current diffusion layer 12, it effectively shortens the reverse recovery time, reduces the turn-off loss of the IGBT device, and improves the performance of the IGBT device. At the same time, the high dielectric constant dielectric has better gate control capability, which helps to improve the gate's control efficiency over the channel region, thereby reducing Miller capacitance and gate charge during the switching process and reducing switching losses. Furthermore, the alternating arrangement of the P-pillar 23, the N-type drift region 13, and the high dielectric constant dielectric region 43 enhances the lateral electric field strength of the N-type drift region 13, allowing the charge carriers stored in the N-type drift region 13 to be more completely depleted, eliminating the risk of local breakdown and improving the breakdown voltage of the IGBT device. In addition, the sequential arrangement of the N-type current diffusion layer 12, the P-type body region 22, and the P+ contact region 21 and N+ contact region 11 helps to optimize the carrier distribution and extraction path, further shortening the reverse recovery time, reducing the turn-off tail current, and further reducing the turn-off loss of the IGBT device.

[0036] In some embodiments, the device further includes: an N+ short-circuit region 15, wherein the N+ short-circuit region 15 and the P-type collector 24 are disposed side by side on the collector 34; wherein the N+ short-circuit region 15 is embedded in the P-type collector 24 along the width direction of the IGBT device for reverse conduction of current.

[0037] Specifically, the N+ short-circuit region 15 is located within the P-type collector 24 and does not extend beyond the surface of the P-type collector 24 facing the N-type cutoff layer 14. Therefore, the N+ short-circuit region 15 is not directly connected to the N-type cutoff layer 14, but forms a PIN diode in reverse parallel with the P-type body region 22 and the N-type drift region 13 through the P-type collector 24. The diode 1 is configured as follows: emitter 31 → P+ contact region 21 → P-type body region 22 → N-type current diffusion layer 12 → N-type drift region 13. 3 → N-type cutoff layer 14 → P-type collector 24 → collector 34; Diode 2 is: emitter 31 → P+ contact region 21 → P-type body region 22 → N-type current diffusion layer 12 → N-type drift region 13 → N-type cutoff layer 14 → P-type collector 24 → N+ short-circuit region 15 (in this embodiment, it passes laterally) → collector 34; When the voltage is forward biased (emitter 31 potential < collector 34 potential), the current of diode 1 is forward-conducting, and the current path... The path is: emitter 31 → P+ contact region 21 → P-type body region 22 → N-type current diffusion layer 12 → N-type drift region 13 → N-type cutoff layer 14 → P-type collector 24 → collector 34. When the voltage is reverse biased (emitter 31 potential > collector 34 potential), diode 2 conducts in reverse, collector 34 → N+ short circuit region 15 → P-type collector 24 → N-type cutoff layer 14 → N-type drift region 13 → N-type current diffusion layer 12 → P-type body region 22 → P+ contact region 21 → emitter 31, thus enabling the IGBT device to have bidirectional conduction function, eliminating the need for the external PIN diode in the traditional method and reducing the overall size of the IGBT device. At the same time, when the IGBT device is turned off, some holes in the N-type drift region 13 can flow laterally and be extracted by the collector 34 through the interface of the P-type collector 24 or the N+ short circuit region 15, accelerating the disappearance process of holes in the N-type drift region 13 and effectively reducing turn-off losses.

[0038] In some embodiments, the cross-sectional area of ​​the P-type collector 24 along the thickness direction of the IGBT device is greater than the cross-sectional area of ​​the N+ short-circuit region 15 along the thickness direction of the IGBT device.

[0039] Specifically, along the thickness direction of the IGBT device, the ratio of the cross-sectional area of ​​the P-type collector 24 to the cross-sectional area of ​​the N+ short-circuit region 15 is 3:1 to 9:1, and this ratio increases with the increase of the withstand voltage level of the IGBT device, so as to balance the on-state voltage drop and the turn-off loss, ensuring sufficient hole injection during forward conduction and obtaining a low on-state voltage drop. When the ratio is close to 3:1, the cross-sectional area of ​​the N+ short-circuit region 15 is larger than that of the P-type collector 24, providing a more efficient electronic path and reducing the on-state voltage drop. It also provides a faster extraction path for holes during turn-off, effectively reducing turn-off losses. However, insufficient hole injection can easily lead to a slight increase in the on-state voltage drop. When the ratio is close to 9:1, the cross-sectional area of ​​the P-type collector 24 is larger than that of the N+ short-circuit region 15, meaning that the ability to inject holes from the collector 34 into the N-type drift region 13 is stronger, forming a strong conductivity modulation effect, thereby reducing the on-state voltage drop. However, this can easily lead to more holes (excess carriers) needing to be extracted during turn-off, resulting in increased turn-off losses. Furthermore, the upper limit of 9:1 ensures that even if the cross-sectional area of ​​the P-type collector 24 is large, the N+ short-circuit region 15 still has sufficient cross-sectional area to provide a low-resistance freewheeling path, enabling the IGBT device to effectively replace the external freewheeling diode, thereby improving the reliability of the IGBT device.

[0040] In some embodiments, the system further includes: a second SiO2 gate dielectric layer 42 and a second polysilicon gate 33; wherein the second polysilicon gate 33 is disposed on the side of the P-pillar 23 away from the N-type cutoff layer 14, and the second polysilicon gate 33 is separated from the sequentially stacked P-pillar 23, N-type current diffusion layer 12, P-type body region 22 and P+ contact region 21 by the second SiO2 gate dielectric layer 42.

[0041] Specifically, the second polysilicon gate 33 is directly connected to the emitter 31. Since the emitter 31 is at a low potential, the second polysilicon gate 33 can effectively shield the direct electric field coupling between the first polysilicon gate 32 and the collector 34, thereby significantly reducing the effective Miller capacitance of the first polysilicon gate 32, preventing false turn-on under high voltage conditions, and improving the reliability and anti-interference capability of the IGBT device. At the same time, when the IGBT device is turned off, a large number of holes stored in the N-type drift region 13 need to be extracted. In the traditional structure, holes can only pass through the junction of the P-type body region 22. The current flows from the contact hole to the emitter 31, following a single path. However, after setting the second SiO2 gate dielectric layer 42 and the second polysilicon gate 33, by connecting the second polysilicon gate 33 to the emitter 31 (or applying a negative voltage), accumulated holes can be induced or an additional electric field can be formed in the P-pillar 23 (or P-type body region 22) on the sidewall of the second polysilicon gate 33. This provides an additional, low-impedance extraction path for the holes, allowing them to be quickly discharged along the channel on the sidewall of the second polysilicon gate 33. This effectively shortens the duration of the turn-off tail current, thereby significantly reducing the turn-off loss.

[0042] In some embodiments, the second SiO2 gate dielectric layer 42 includes a first separation structure 421 and a second separation structure 422; along the width direction of the IGBT device, the second polysilicon gate 33 is separated from the sequentially stacked N-type current diffusion layer 12, P-type body region 22 and P+ contact region 21 by the first separation structure 421; along the thickness direction of the IGBT device, the second separation structure 422 is embedded with P-pillar 23 and separates the P-pillar 23 from the second polysilicon gate 33.

[0043] Specifically, the first partition structure 421 and the second partition structure 422 are connected to form an L-shaped structure. The first partition structure 421 and the second partition structure 422 are integrally formed silicon dioxide layers, which are integrally formed by dry oxidation process, effectively reducing process steps and reducing manufacturing costs and cycle time. At the same time, the structural design of embedding the second partition structure 422 into the P-pillar 23 uses the second partition structure 422 as a dielectric barrier to isolate the P-pillar 23 from the second polysilicon gate 33, and guides the electric field to bypass the critical area of ​​the P-pillar 23, avoiding the surface or edge of the P-pillar 23 from being directly exposed to the high electric field, which could lead to avalanche breakdown or premature breakdown.

[0044] In some embodiments, the first SiO2 gate dielectric layer 41 includes a third separation structure 411 and a fourth separation structure 412. Along the width direction of the IGBT device, the first polysilicon gate 32 is separated from the N-type current diffusion layer 12, the P-type body region 22, and the P+ contact region 21 stacked sequentially by the third separation structure 411. Along the thickness direction of the IGBT device, the fourth separation structure 412 is embedded in the emitter 31 and separates the emitter 31 from the first polysilicon gate 32.

[0045] Specifically, the third partition structure 411 and the fourth partition structure 412 are connected to form an L-shaped structure. The third partition structure 411 and the fourth partition structure 412 are integrally formed silicon dioxide layers, which are integrally formed by dry oxidation process, effectively reducing process steps and reducing manufacturing costs and cycle time. At the same time, the design of embedding the emitter 31 into the fourth partition structure 412 forms a longitudinally extending dielectric isolation wall between the first polysilicon gate 32 and the emitter 31, thereby increasing the creepage distance between the first polysilicon gate 32 and the emitter 31, thereby suppressing leakage current under high temperature reverse bias conditions and extending the service life of IGBT devices.

[0046] In some embodiments, the material of the high dielectric constant dielectric region 43 is any one of hafnium oxide, aluminum oxide, silicon nitride, and barium titanate.

[0047] Specifically, the material of the high dielectric constant dielectric region 43 is preferably hafnium oxide to enhance the gate control capability of the high dielectric constant dielectric region 43 and reduce the equivalent oxide thickness, thereby reducing the switching loss and tail current of the IGBT. In addition, the material of the high dielectric constant dielectric region 43 can adopt a stacked structure composed of hafnium oxide and aluminum oxide to make up for the deficiencies of hafnium oxide by utilizing the interface characteristics of aluminum oxide, so as to achieve a balance between high gate control and high reliability of the IGBT device.

[0048] In some embodiments, the IGBT device is made of silicon carbide; wherein the IGBT device adopts 4H-SiC crystal form or 6H-SiC crystal form, preferably 4H-SiC crystal form, so as to effectively reduce the on-resistance of the IGBT device through the higher electron mobility and wider band gap of 4H-SiC crystal form, thereby reducing the on-voltage drop of the device and thus reducing the turn-off loss of the IGBT device.

[0049] like Figures 2-3 As shown in the figure, an embodiment of the present invention provides a method for fabricating an IGBT device, which is used to fabricate the aforementioned IGBT device, and includes the following steps: S100, Substrate preparation: N-type stop layer 14 is prepared by selecting N-type 4H-SiC single crystal.

[0050] Specifically, an N-type cutoff layer 14 is prepared using N-type 4H-SiC single crystal, which enables the N-type cutoff layer 14 to effectively withstand high voltage in the blocking state and prevent the electric field from penetrating to the collector 34 side, thereby improving the voltage withstand performance of the IGBT device.

[0051] S200, First epitaxial layer growth: Along the thickness direction of the IGBT device, an N-type drift region 13 is prepared on the surface of the N-type cutoff layer 14.

[0052] Specifically, along the thickness direction of the IGBT device, an N-type 4H-SiC single crystal is used to prepare an N-type drift region 13 on the surface of the N-type cutoff layer 14 through chemical vapor deposition. This achieves a uniform doping concentration distribution during the growth of the N-type drift region 13, avoiding the problem of local electric field concentration or increased on-resistance caused by uneven doping, and improving the stability of the IGBT device.

[0053] S300, First Etching: A dry etching process is used to etch the first and second trenches in the N-type drift region 13.

[0054] Specifically, an inductively coupled plasma dry etching process is used to etch the first and second trenches in the N-type drift region 13 to ensure that the bottom of the first and second trenches is flat and the sidewalls are smooth, thus ensuring the consistency of the electrical performance of the IGBT device.

[0055] S400, Filling: P-pillars 23 and high dielectric constant dielectric regions 43 are formed by filling materials in the first and second trenches, respectively.

[0056] Specifically, P-type 4H-SiC single crystals are filled into the first trench to form P-pillars 23, and hafnium oxide and aluminum oxide are filled into the second trench to form a high dielectric constant dielectric region 43, ensuring that the first and second trenches are completely filled from the bottom up to improve the stability of the IGBT device.

[0057] S500, Secondary epitaxial layer growth: An N-type current diffusion layer 12 is prepared on the surface of the N-type drift region 13 away from the N-type cutoff layer 14.

[0058] Specifically, an N-type 4H-SiC single crystal is used, and an N-type current diffusion layer 12 is prepared on the surface of the N-type drift region 13 away from the N-type cutoff layer 14 by chemical vapor deposition. This achieves a uniform doping concentration distribution during the growth of the N-type current diffusion layer 12, avoiding the problem of local electric field concentration or increased on-resistance caused by uneven doping, and improving the stability of the IGBT device.

[0059] S600, three-stage epitaxial layer growth: P-type body region 22 is prepared on the surface of N-type current diffusion layer 12 away from N-type drift region 13.

[0060] Specifically, a P-type 4H-SiC single crystal is used, and a P-type body region 22 is prepared on the surface of the N-type current diffusion layer 12 away from the N-type drift region 13 by chemical vapor deposition. This achieves a uniform doping concentration distribution during the growth of the P-type body region 22, avoiding the problem of local electric field concentration or increased on-resistance caused by uneven doping, and improving the stability of the IGBT device.

[0061] S700, Secondary Etching: In this embodiment of the invention, a second SiO2 gate dielectric layer 42 and a second polysilicon gate 33 are also provided. Therefore, along the width direction of the IGBT device, a third trench and a fourth trench are formed on both sides of the N-type current diffusion layer 12 and the P-type body region 22, respectively.

[0062] Specifically, along the width direction of the IGBT device, an inductively coupled plasma dry etching process is used to etch a third trench and a fourth trench on both sides of the N-type current diffusion layer 12 and the P-type body region 22, respectively, to ensure that the bottom of the third trench and the fourth trench are flat and the sidewalls are smooth, thus ensuring the consistency of the electrical performance of the IGBT device.

[0063] S800, Trench gate formation: A first SiO2 gate dielectric layer 41 is formed in the third trench through a dry oxidation process, and a first polysilicon gate 32 is formed in the first SiO2 gate dielectric layer 41 through a photolithography and dry etching process.

[0064] Specifically, SiO2 is used as the material, and a first SiO2 gate dielectric layer 41 and a second SiO2 gate dielectric layer 42 are formed in the third and fourth trenches respectively by dry oxygen oxidation process under high temperature oxygen of 1200°C~1250°C. Nitriding annealing is then used to obtain a gate dielectric with low interface state density, high breakdown electric field and high reliability, thereby meeting the gate insulation performance requirements of 4H-SiC IGBT devices. Then, photolithography and inductively coupled plasma dry etching process are used to form a first polysilicon gate 32 and a second polysilicon gate 33 in the first SiO2 gate dielectric layer 41 and the second SiO2 gate dielectric layer 42 respectively.

[0065] S900, Emitter Ion Implantation: Ions are implanted into the surface of the P-type body region 22 away from the N-type current diffusion layer 12 through ion implantation process to form N+ contact region 11 and P+ contact region 21 respectively.

[0066] Specifically, the ions forming the N+ contact region 11 are N... + or P + N is preferred + This reduces the interface state density, increases the channel electron mobility, and thus reduces the on-resistance of the IGBT device; the ions forming the P+ contact region 21 are Al + Or B + Al is preferred + Because aluminum has a lower acceptor activation energy (about 200 meV, while boron is about 300~350 meV) when it acts as an acceptor impurity in 4H-SiC, aluminum ions can achieve a higher activation rate after high-temperature annealing, thereby obtaining a higher hole concentration and a lower specific contact resistance, which is beneficial to reducing the on-resistance of IGBT devices. At the same time, in order to obtain a uniform N+ contact region 11 and P+ contact region 21 with sufficient thickness and high doping concentration, a multiple implantation scheme is adopted to ensure the doping uniformity of N+ contact region 11 and P+ contact region 21.

[0067] S1000, Collector ion implantation: Ions are implanted on the surface of the N-type cutoff layer 14 away from the N-type drift region 13 to form a P-type collector 24.

[0068] Specifically, the P-type collector 24 is formed as Al + Or B + Al is preferred + A multiple implantation scheme is adopted to ensure the doping uniformity of the P-type collector 24.

[0069] S1100, N+ Short Circuit Region Formation: Along the width direction of the IGBT device, N+ is injected into the P-type collector 24 near the P-pillar 23. + or P + N is preferred + N is injected with nitrogen ions in high doses.+ In conjunction with high-temperature annealing, a higher doping concentration is obtained, enabling the N+ short-circuit region 15 to form a low-resistance ohmic contact with the collector 34. At the same time, it is important to ensure that the implantation depth is controlled within the thickness of the P-type collector 24 to ensure that a PN junction is formed between the N+ short-circuit region 15 and the P-type collector 24, thereby realizing the freewheeling diode function during reverse conduction.

[0070] S1200, Metallization: Emitter 31 with low resistance ohmic contact is formed by front sputtering or evaporating Ni alloy on the surface of P+ contact region 21 and N+ contact region 11 away from P-type body region 22. Collector 34 is formed by sputtering Ti or Al metallization on the side of P-type collector 24 away from N-type cutoff layer 14. At the same time, gate metal interconnects are used to connect to the first polysilicon gate 32 and the second polysilicon gate 33 through gate contact holes provided on the first polysilicon gate 32 and the second polysilicon gate 33, respectively, to realize gate metallization of the first polysilicon gate 32 and the second polysilicon gate 33.

[0071] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. An IGBT device, characterized in that, include: Collector, P-type collector, N-type cutoff layer, N-type drift region, N-type current diffusion layer, P-type body region, P+ contact region, N+ contact region, emitter, first SiO2 gate dielectric layer, first polysilicon gate; Along the thickness direction of the IGBT device, the collector, the P-type collector, the N-type cutoff layer, the N-type drift region, the N-type current diffusion layer, and the P-type body region are arranged sequentially. The P+ contact region and the N+ contact region are arranged side by side on the side of the P-type body region away from the N-type current diffusion layer, and the emitter is located on the side of the P+ contact region and the N+ contact region away from the P-type body region; A high dielectric constant dielectric region and a P-pillar are provided on the side of the N-type cutoff layer away from the P-type collector, and the high dielectric constant dielectric region and the P-pillar are arranged opposite to each other on both sides of the N-type drift region; The first polysilicon gate is disposed on the side of the high dielectric constant dielectric region away from the N-type cutoff layer; wherein, the first polysilicon gate is separated from the N-type current diffusion layer, the P-type body region, the N+ contact region and the emitter stacked sequentially through the first SiO2 gate dielectric layer; The IGBT device further includes: a second SiO2 gate dielectric layer and a second polysilicon gate; The second polysilicon gate is disposed on the side of the P-pillar away from the N-type cutoff layer. The second polysilicon gate is separated from the P-pillar, the N-type current diffusion layer, the P-type body region and the P+ contact region stacked sequentially by the second SiO2 gate dielectric layer, and the second polysilicon gate is directly connected to the emitter.

2. The IGBT device according to claim 1, characterized in that, Also includes: The N+ short-circuit region and the P-type collector are arranged side by side on the collector; wherein the N+ short-circuit region is embedded in the P-type collector along the width direction of the IGBT device for reverse conduction of current.

3. An IGBT device according to claim 2, characterized in that, The cross-sectional area of ​​the P-type collector along the thickness direction of the IGBT device is greater than the cross-sectional area of ​​the N+ short-circuit region along the thickness direction of the IGBT device.

4. An IGBT device according to claim 1, characterized in that, The second SiO2 gate dielectric layer includes a first separation structure and a second separation structure; along the width direction of the IGBT device, the second polysilicon gate is separated from the N-type current diffusion layer, the P-type body region and the P+ contact region stacked sequentially by the first separation structure; along the thickness direction of the IGBT device, the second separation structure is embedded in the P-pillar and separates the P-pillar from the second polysilicon gate.

5. An IGBT device according to claim 1, characterized in that, The first SiO2 gate dielectric layer includes a third separation structure and a fourth separation structure; along the width direction of the IGBT device, the first polysilicon gate is separated from the N-type current diffusion layer, the P-type body region, and the P+ contact region stacked sequentially by the third separation structure; along the thickness direction of the IGBT device, the fourth separation structure is embedded in the emitter and separates the emitter from the first polysilicon gate.

6. An IGBT device according to claim 1, characterized in that, The material of the high dielectric constant dielectric region is any one of hafnium oxide, aluminum oxide, silicon nitride, and barium titanate.

7. An IGBT device according to claim 1, characterized in that, The IGBT device is made of silicon carbide.

8. A method for fabricating an IGBT device, used to fabricate an IGBT device as described in any one of claims 1-7, characterized in that, Includes the following steps: Substrate preparation: Select materials to prepare the N-type cutoff layer; First epitaxial layer growth: The N-type drift region is prepared on the surface of the N-type cutoff layer along the thickness direction of the IGBT device; First etching: A dry etching process is used to etch the first and second trenches in the N-type drift region; Filling: The P-pillar and the high dielectric constant dielectric region are respectively formed by filling materials in the first and second trenches; Secondary epitaxial layer growth: The N-type current diffusion layer is prepared on the surface of the N-type drift region away from the N-type cutoff layer; Three-stage epitaxial layer growth: The P-type body region is prepared on the surface of the N-type current diffusion layer away from the N-type drift region; Secondary etching: Along the width direction of the IGBT device, a third trench is etched on the same side of the N-type current diffusion layer and the P-type body region to form a third trench; Trench gate formation: The first SiO2 gate dielectric layer is formed in the third trench by dry oxidation process, and the first polysilicon gate is formed in the first SiO2 gate dielectric layer by photolithography and dry etching process. Emitter ion implantation: Ions are implanted into the surface of the P-type body region away from the N-type current diffusion layer to form the N+ contact region and the P+ contact region, respectively, through an ion implantation process. Ion implantation of the current collector: Ions are implanted into the surface of the N-type cutoff layer away from the N-type drift region to form the P-type current collector; Metallization: The emitter is formed on the surface of the P+ contact region and the N+ contact region away from the P-type body region by sputtering or evaporation process, and the collector is formed on the side of the P-type collector away from the N-type cutoff layer by sputtering process to obtain the IGBT device.

9. The method for fabricating an IGBT device according to claim 8, characterized in that, The dry etching process employs inductively coupled plasma dry etching.

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